INDEX
S. No
Topic
Week 1
Page No
1
Introduction
1
2
Transistor as a switch
16
3
Performance Issues and Introduction to TTL
33
4
Transistor Transistor Logic (TTL)
47
5
CMOS Logic
61
Week 2
6
Basic Gates and their representations
77
7
Fundamentals of Boolean Algebra
94
8
Boolean Function to Truth Table and Implementaion Issues
110
9
Truth Table to Boolean Function and Implementaion Issues
124
10
Karnugh Map and Digital Circuit Realization
141
Week 3
11
Karnaugh Map to Entered Variable Map
160
12
Quine - McClusky (QM) Algorithm
175
13
Cost Criteria and Minimization of Multiple Output Functions
189
14
Static 1 Hazard
204
15
Static 0 Hazard and Dynamic Hazard
217
Week 4
16
Multiplexer Part I
231
17
Multiplexer Part II
246
18
Demultiplexer / Decoder
261
19
Decoder with BCD Input and Encoder
277
20
Parity Generator and Checker
292
Week 5
21
Number System
307
22
Negative Number and 2’s Complement Arithmetic
323
23
Arithmetic Building Blocks - I
337
24
Arithmetic Building Blocks - II
351
25
Overflow Detection and BCD Arithmetic
367
Week 6
26
Magnitude Comparator
383
27
Arithmetic Logic Unit (ALU)
399
28
Unweighted Code
412
29
Error Detection and Correction Code
427
30
Multiplication and Division
439
Week 7
31
SR Latch and Introduction to Clocked Flip-Flop
453
32
Edge-Triggered Flip-Flop
468
33
Representations of Flip-Flops
483
34
Analysis of Sequential Logic Circuit
497
35
Conversion of Flip-Flops and Flip-Flop Timing Parameters
511
Week 8
36
Register and Shift Register PIPO and SISO
529
37
Shift Register SIPO, PISO and Universal Shift Register
544
38
Application of Shift Register
559
39
Linear Feedback Shift Register
572
40
Serial Addition, Multiplication and Division
587
Week 9
41
Asynchronous Counter
599
42
Decoding Logic and Synchronous Counter
614
43
Cascading Mod 2, 3, 5 to Mod 6, 10, 1000 Counter
630
44
Counter Design with Asynchronous Reset and Preset
643
45
Counter Design as Synthesis Problem and Few Other Uses of Counter
656
Week 10
46
Synthesis of Sequential Logic Circuit Moore Model and Mealy Model
671
47
Moore Model and Mealy Model Realization of Digital Logic Circuit
685
48
Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic
703
49
Circuit Realization from ASM Chart and State Minimization
715
50
State Minimization by Implication Table and Partitioning Method
731
Week 11
51
Digital to Analog Conversion - I
744
52
Digital to Analog Conversion - II
758
53
Analog to Digital Conversion - I
774
54
Analog to Digital Conversion - II
789
55
Certain Performance Issue of ADC and DAC
805
Week 12
56
Introduction to Memory
819
57
Static Random Access Memory (SRAM)
835
58
Dynamic RAM(DRAM) and Memory Expansion
852
59
Read Only Memory (ROM)
865
60
PAL, PLA, CPLD, FPGA
880
Digital Electronic Circuits
Prof. Goutam Saha
Department of E and EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 01
Introduction
Hello everybody, this is Goutam Saha. I am a Professor of Electronics and Communication
Engineering Department, IIT Kharagpur. I shall be working with you in this course Digital
Electronic Circuits. And there will be teaching assistants, all of them are PG students over
here. They will be also working together in this particular course. As you know, this course
is named Digital Electronic Circuits.
(Refer Slide Time: 00:45)
And in the introductory lecture we shall cover few basic things, why we are going for this
digital electronics or digital technology. And what we actually mean by digital.
Then we shall see; what is manipulation of digital signal, how it is done the basic
introductory part only, and importance of switching and logic operation in digital
manipulation. And finally, we will end up with one small circuit that is use of diode as a
switch.
1
(Refer Slide Time: 01:25)
Regarding why digital? You are associated, you are familiar with many terms like digital
clock, digital camera, digital money, digital media so and so forth that mean you can go
on increasing this list; we have digital thermometer, digital weighing machine. And when
we associate a term digital, with any particular entity what actually we mean that that entity
is associated with digital technology. And this digital technology is considered more
efficient, more efficient in terms of performance different kind of the performance metric,
quality and at a given cost - the cost is also very important, for which the digital technology
is so much prevalent, you know getting into any different aspects of our life.
And some of the features of this digital technology, if you look at it, they are easy to store,
they are easy to copy from one place to another. All of us are familiar with you know
copying a song from one device to another device. We can compress it, we can store the
information in the compressed manner and then we can decompress it. It shows immunity
to noise, different kind of interferences (in spite of) which retains the quality or enhances
the quality (by use) of different algorithms, by which you can enhance the quality.
It provides various transmission options. There are serial then parallel, many way you can
convert, transmit this signal from one place to another. There are options for the error
correction and the encryption. You know, you (can) send the signal from one place to
another in an encrypted manner. So, there anybody who intercept the signal may not be
able to make any meaning out of it. Only the person who knows how to decrypt it what
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was the initial encryption algorithm, they are the ones who can make a meaning as the
final recipient of that signal. It provides flexibility in processing. It is very, very important
the flexibility aspect, that the probability aspect, the same device we can use for many
different ways, the general purpose aspect of it. The data that we get, the digital data, we
can analyze it to, you know, extract many information out of it. And data analysis, data
analytics is, you know, kind of thing that we all are aware of, which is a very important
field and emerging field. All are happening - it is because of this I would say, the burst of
digital technology.
And, what comes at the end - this inexpensive building block. So, this is actually an
important thing; this inexpensive building block. This actually forms the core of this thing
– see, we can get lot of interesting features, but at the end that if it is very costly, if it burns
the pocket, then it really is not something which were looking for. This inexpensive
building block actually will take us to this particular course, that is, digital electronics
circuit. It is the electronic circuits which are there at its core for which we are able to get
whatever we are getting. Of course, there are many advanced algorithms so many other
developments around it, but this building blocks are the primary things which actually has
driven the digital technologies and digital transformations that we are seeing today.
(Refer Slide Time: 05:27)
Now coming to I mean, since the term is so much used, so often used that digital
everywhere we are seeing, what exactly we mean by digital? So, the first thing that you
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need to know is that what is a digital signal? So, digital signals represent only finite number
of discrete values. Finite means because ultimately we are associating we are talking about
a technology development. So, we are talking about certain number of bits or binary values
that will be associated with a particular signal and it is representation. So, that only offers
you a finite number of sets, finite number of representations.
So, that is why we are saying that this is a finite number of - and it has to be discrete, that
is one important part of it, that these are discrete values. And we are in this particular
context, when we discuss digital technology these discreet values are making a
presentation of itself by a 2 valued representation, which is binary. There could be
quaternary - 4 symbols can be associated and all, but we shall be restricting ourselves here
to two valued binary representation. And a group of binary values or bits can be used to
represent many different discreet levels. Now coming to the signal, the signal by itself can
be discrete in nature.
The examples are, I mean what about - like the marks that we get in our exam, a salary
that we get as a faculty member or all these things, I mean the most of these human
generated signals are discreet in nature. But if you look at the natural signal, signals
generated by the nature, that these they are mostly continuous in nature. Continuous in the
sense that the all source of values that can be associated with that particular signal; now
we need to analyze and process those signals as well - these signals that are coming from
nature. Now, to do that - what we need to do is to discretize these signals, these continuous
signals. So, for which we need something which is called analog to digital conversion.
And if you want to get back in the form of a continuous signal, then we need to do the
reverse of it. That is a process by which we shall get the digital signal converted to analog
form, that is called digital to analog conversion. And we can see one example where an
analog signal is converted to a digital signal in this particular figure; the figure that we see
here in the screen.
So, this is an analog signal what you see over here – right! And this signal can take any
value and we need to discretize it and for that what we are having here is different levels.
These are in the y axis - that you see the voltage, that you see at different levels to which
the analog signal need to be associated with. So, there are no other values available there.
So, either the value should be if the whole thing is normalized to say a specific one - V
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volt. So, this is 𝑉𝑉/8, 2𝑉𝑉/8, 3𝑉𝑉/8. so on and so forth up to 7𝑉𝑉/8. So, how many levels are
there discreet levels are there you can count you can see it is 8 levels are there – ok!
So, the analog signal when converted to discreet signal, it can take one of these 8 values
only – ok! And for that, what we will do, we shall associate when we look at a sample of
the signal at a specific discreet value which is the closest. So, that could be one particular
way of approximating the signal. And what we are doing? This is the time axis, x axis is
the time. So, we are measuring, having a measurement of the signal at different time
instances – ok! So, this is time instance 0, time instance 1, time instance 2 and so on and
so forth – right!
Now, there are concerns like how close these time samples will be to truthfully represent
the analog signal. One way of looking at it that we can we reconstruct we can get back the
analog signal in the form that we are having over here – ok! So, we can reconstruct by
interpolation of those samples. So, there is a specific rate that whatever is the frequency
content of the signal, analog signal in the first place, we have to sample it at a particular
rate, which is above twice the highest frequency content, if it is a band pass signal, then
there will be something else. So, there is a specific way, specific rate by which it needs to
be sampled, so that we can reconstruct the analog signal from the discreet samples. So,
these are the samples – ok! So, these are the time instances and at each sample point, at
simple value we can see the corresponding discreet value. So, at 0 we see the value is over
here. So, we associated the close value which is 2𝑉𝑉/8– ok!. At 1 again it is 2𝑉𝑉/8. At 2 we
see this is associated with 4𝑉𝑉/8. so and so forth.
Now, this is discreet level. Now as I said we are finally, representing it using binary codes
– right! So, 2 valued binary. So, there are 8 levels if you want to represent it using only
binary we need how many binary digits or bits, it is log2 𝑁𝑁– ok! That is the number that
will be required - that is. So, if it is 8. So, log 2 8 is 3. So, 3 such bits will be required.
And you see, 000, 001 - these are the corresponding representations. So, at first time
instant, what shall I get? I shall get 010, which is to be an approximation of 2 V by 8; 010
- I will again get at time instant 1. Time instant 2, I shall get 100 and so on and so forth.
So, that way it will continue – ok! So, of course, we can reduce the approximation error,
whatever error that you see, called quantization error, by reducing this gap, making it as
close as possible. So, that is possible when we have more number of bits, more number of
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bits. So, if you have instead of 3 bits, if you have got 4 bits we will be having 16 such
levels. So, approximation error will be less.
If we have 8 bits we will be having to 2 the power 8, 256 number of levels. So, that way
the approximation error or quantization will be reduced. So, this is - there is some initial
issues, when we get to know the error that we can see, from in the analog to digital
conversion. After that we shall see that the digital signal itself is more robust in presence
of noise and other things, processing aspect of it – ok! Now, if you look at digital systems.
What do they do? They represent and manipulate digital signals – ok!. So, the digital
signals that we see that would be, that are getting manipulated, that are getting processed
by the digital signals.
(Refer Slide Time: 13:55)
Now, we come to the manipulation of digital signals. As I said this is an introductory
lecture - we are looking at some example cases. So, first thing, that is very important thing
is that when we talk about manipulation of digital signal, switching is the key to it – ok!
By switching what we mean that we shall see little later. Switching is - the kind of switch
that we have seen in our household - like we switch on the fan – fan starts rotating. Then
you switch or switch it off - then it stops. So, it is basically again an on-off kind of thing.
A binary kind of activity that is associated with switching.
And just now we have seen the binary representations of digital signals in the form of 0s
and 1s, that is also can be you know in that sense associated with switching. So, one is.
6
OFF say associated with 0 and, ON with associated with 1. So, this is one way of
association there could be other way of association - is just its reverse. So, the standard
process, standard understanding is that OFF is associated with say, 0. And ON is associated
with 1 - so that that helps. So, this is one important aspect which we shall keep in our mind
– ok!
And so, we look at one example where the switching is important. So, this is a n to 1
multiplexer – ok! We will discuss the circuit what is there inside - that is a part of our
course, digital electronics circuit. So, we shall see what is this - it should not remain a
black box, but for the time being let us see what does it do. So, this particular block actually
takes any of the n inputs, which is present at this site at the input site and makes it available
to the output. So, at a given time only one of the input will be available at the output.
Now; that means, if I wish that this channel will go to the output, it will go. If I wish the
other channel will go to the output that will go. Now, who will decide that? Who will do,
who will make the decision? Of course, the circuit inside will make the decision, but based
on what? So, based on again another set of input this is called control input. So, this was
data which is going to the output. So, this control input will be deciding based on certain
combination over here, that who is going from here to the output –ok! So, if 1 and 2 and
m- 3 and 4 and up to say, m all are 0 say - 1 goes to the output.
If 1 and 2 and 3 and all of them are 0, up to m minus 1 and m is 1, then 2 goes to the output;
so in the statement itself - if you look at it the way I am phrasing it, that if A and B and C
and D are 1 something happens. If A and B and C and D are 0, A and B and C are 1 and
D is 0, something else happens. So, this involves a certain kind of a logical statement or
logical build-up which is associated with switching, which can be associated with
switching – ok!. So, this is one aspect of it. The other thing is the data that is storage the
storage of data that you have stored. So, this is what you can see that an 8 bit data storage
unit. It could be it made up of say, flip flops - what is that flip flop and all, those things,
we shall see later.
So, there are parallel data inputs and these are parallel data outputs. So, in the data will be
coming here that is decided by a specific logic and the how data will be stored. So, if you
look at the internal circuits of it there are switching activity that is happening inside – ok!
7
So, this is as I said is one of the core aspect of digital processing, digital manipulation,
when you look at it at the circuit level!
(Refer Slide Time: 18:43)
Right! So, now we look at the switching, the way we have already seen it, we have
understood it – ok! So, this is an example, where you see, there are 2 switches. This is one
switch and this is another switch right. And there is a 5 volt dc supply and this is the output
and this is connected to the ground – ok!
And when at the input, voltage is placed, I mean high voltage say 5 volt is placed. So, what
placed. So, what happens this switch closes and connects these 2 points, are getting shorted
- these 2 points get connected. So, these 2 points will get connected ok,. when this is high.
And if it is low that means, it is remaining the same. Similarly, for V2 – ok! Now let us
see how this particular circuit it is inputs side and outputs side will be related. So, when V
one is low; that means, this switch is this switch over here is this - is open right and this is
V2 is also low that means, this is also open. So, at that time what will be the value of the
output? The value of the output will be - this 5 volt cannot come to the output ok; so the
value of the output is low. Is it ok?
Now if you close one of them, say this is closed, but this remains open, still these situation
remains the same the condition remains, the same the output will remain, output will not
get the value - this 5 volt. So, any of them is low you see the output is low. Only when
both of them are both the both the switches are connected; that means, both of them are
8
high. So, this switch you know changes site from here and gets connected over there. Then
only the output of this 5 volt gets the path over here and you get you can see a high value
over there ok.
So, when we look at it from the logic circuit point of view, it is V1, V2, Vo. So, what kind
of logic do we see? That when both V1 and V2 are high, output Vo is high. That is how
we read it. Isn’t it? That is how we phrase it. And the table - the corresponding table is
what you see over here, ok! And this is nothing but what is known as AND logic - this is
your AND logic – ok! So, this AND logic when you know - represent in the form of a
symbol logic – symbol, this is how we represent it. And this is the AND symbol which we
shall be using in subsequent discussion – ok!
But still it is an electrical circuit - the electronic part and other things - that we shall discuss
little later.
(Refer Slide Time: 22:25)
Now, we will look at another such circuit, a switching circuit where these are - there you
can see there are 2 switches – ok! And – but, earlier they were connected in series, now
you can see they are connected in parallel – right! And what difference does it make? The
difference is, earlier both of them were to be closed. That means both the switches the
input side needed to be high. So, that the 5 volt gets a path to the output – ok!
9
In this case since they are parallel, any one of them high any one of them high, this one
switch gets closed and the path will be available - a 5 volt will get a path to the output and
Vo will be high – ok! So, that is what is happening. Only when both of them are low, only
when both of them are low - then only 5 volt does not get any path to the output. So, this
is the corresponding truth table that we can see. These are called truth table when you are
presenting in terms of low-high or true and false. So, False is associated with L - logic
low and H is associated with True – ok! So, then it becomes a truth table.
So, this is another way we can say that - a representation of truth table, where this FalseFalse gives you False; True-False gives you True; False-True gives you True and True
give you True. And this is nothing but OR representation, OR logic – ok! And what is the
corresponding symbol? So, this is the corresponding symbol that you see over here. Is it
clear? Ok!
(Refer Slide Time: 24:59)
Now, we look at the other one which is NOT – ok! So, look at this particular switch this
is another logic operation. So, what is happening now you see the difference this switch is
connected in such a manner that if this input side is low this 5 volt is getting a path to the
output ok. 5 volt is getting a path to the output.
If Vi is high, then this switch is drawn may be through a coil, magnetic coil. So, and it will
get connected to this one, this side. So, this switch will get connected to this side. So, this
will not be there ok. What does it mean? Now 5 volt does not get a path. So, if input is
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high the switch connects to this side and the output does not get a path. If switch is low
input is low then the output gets a path. So, what difference does it make? The difference
is that Vi is low output is high and Vi is high the output is low – ok! So, there is just an
inversion. There is a, you know in terms of logic, it is just the invert of the other. So, it is
called NOT operation and the corresponding symbols is like this.
This bubble is actually what is important over here - the bubble can be present in many
other cases, we will see this happening.
(Refer Slide Time: 26:45)
Now, so far we are talking about the 2 states binary states - ok. That is logic one, logic
high, low, true, false, ok. So, this is one particular case where you are talking about
something called tristate. This is also we will be seen and available in your digital
electronics circuit, to the course and the discussion that we shall see - ok.
So, what is it? In this case you see there is an additional input called G - ok. So, what is
the role of this G? When this G is in this case low; that means, it is remaining open,
whatever you do at the input side it does not get reflected at the output sides. So, it will
remain, it will does not get a path ok. Only when G is high then - if this G gets connected
and depending on the rest is a circuit, where depending on Vi, if it is low the output will
go low or high it will go high.
11
So, this is just going from this side to the other side, but G is what is making it enabled ok. Now why it is called tristate? When G is low; that means, it is disconnected - the circuit,
at the output does not get either 5 volt or ground, any of them it is not getting - ok. So, this
is in a sense the output is open circuit - this is electrically not connected to the rest of the
circuit which is there in the left hand side. It has got its interesting use - we shall see in the
subsequent discussion - right.
(Refer Slide Time: 28:53)
So, now this is the final slide of this introductory session, introductory lecture - more
complicated circuit, more complex circuit - we shall see later.
So, here what you are seeing is a diode based circuit diode and resistances are being used
- ok. And this is used for generating 2 different logic operations - ok. Let us see what are
the. So, there is a diode - 2 diodes ok. Connected A and B you can have more such diodes
and you know a become B and C these will get connected, but let us restrict ourselves to
2 only right. So, any of the diode is low ok; that means a 0 volt. What will happen? The
current will start flowing in this direction current, will start flowing in this direction and
0.7 volt drop will be there ok. So, the output will be 0.7 volt.
So, this particular voltage which is close to 0 volt, we shall treat it as logic low and voltages
which is close to 5 volt - little bit, treated as logic high. How much close and all those
things we shall see later, what is the range - other things, that we shall see later. So, at this
point it is sufficient to note that this 0.7 volt that we get here is treated as logic low ok. So,
12
any of them, one of them is low - so, what we find, this particular direction current is going
and the voltage over here is 0.7 volt which is the diode ON voltage and the output is low.
On the other way when both of them are high, it does not, you know, the current is going,
flowing in this direction – right! And the 5 volt and depending on the load current, a little
bit less than 5 volt, might occur at this particular place which is digital logic 1. So, what
sort of logic does it provide what sort, I mean, if you look at it, if you compare it with
previous thing - we shall see that this is AND logic - ok. Both of them high, this is the
output high - right.
Now, look at this particular circuit what is, what is it. So, A and B at the input either you
present a 0 volt or 5 volt - ok. So, when you present both of them as 0 volt. So, no current
is flowing. And when you present a 5 volt what will be the voltage here. So, 0.7 volt drop
over here. So, voltage here will be some 4.3 volt earlier these this was 0.7 volt right which
is close to 5 volt. Which we can treat as high and corresponding any one of them or both
of them at 5 volt the output is at 4.3 volt and close to that depending on the diode drop
which is in the range of 0.7 volt - ok.
So, any of them high, output is high/ What sort of logic is this? It is OR logic - ok. So,
using diode as a switch we can see that we can generate, we can get AND logic and OR
logic. Can we get a NOT logic using only diode and resistance? So, you could try, but you
might see that using only diode and resistance combination you will not get a NOT logic,
an inverter is not possible, for which we need to use transistor which we shall take up in
the next lecture where transistor will be used as a switch.
13
(Refer Slide Time: 32:49)
So, these are the references for these particular lectures. So, mostly I shall be using the
first reference and more references I shall share later.
(Refer Slide Time: 33:03)
And to summarize what we see what we have seen in this particular lecture is that a short
overview of what we have discussed so far. The digital technology provides better
performance at the lower cost. And the key to it is inexpensive building blocks and these
inexpensive building blocks are such that they it can handle digital signals and can
manipulate. And this manipulation is all switching, and the switching is associated with
14
logic operations like AND, OR, NOT. And we have seen the diode as a switch can be used
to generate AND, OR logic.
Thank you.
15
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 02
Transistor as a Switch
Hello everybody, we move to lecture 2 of this particular course. In lecture 1, that is in the
previous lecture, we had seen why digital technology is important, what constitutes digital
technology, the importance of switching, association of switching with logic relation and
use of diode as a switch. So, this is what we had seen earlier. And in that discussion we
had seen that diode as a switch can be used for developing AND and OR logic - ok. We
left ourselves with a question that whether you can get an inverter logic or NOT logic
using diode which we found that from our common understanding it is not possible, but
transistors can be used for generating NOT logic or inverter - ok.
(Refer Slide Time: 01:11)
So, in today’s lecture we shall cover Transistor as a switch. So, we shall look at its input
output characteristics and some important parameters like noise margin, transition width,
logic swing and fanout.
16
(Refer Slide Time: 01:27)
So, we start with a basic circuit of a very simple circuit of transistor based inverters. So,
what we see in the left hand side of the slide is a circuit where we see this is an NPN
transistor bipolar junction transistor, this is the base, this is the collector and this is the
emitter - ok. So, this collector is connected through this RC to power supply, the VCC a
positive power supply, we considered 5 volt here. And, the base is connected to an input
voltage Vin through a resistance which is RB, this resistance R B; this is collector resistance
RC - ok.
And output is taken from collector C - right. So, this is the basic configuration which we
shall examine. Now if you look at this circuit and we try to plot Vin versus Vout, Vin versus
Vout - ok. So, this side this x axis is Vin, independent variable along the x axis; y axis is the
dependent variable Vout. So, how this circuit will work right in the beginning when Vin is
0 ok. So, the transistor is in off state. So, at that time what will be the output? See this
transistor - this transistor is off, no current is, no IC current is flowing, no collector current
is flowing.
So, collector current: that IC into RC this drop VCC minus ICRC that is your Vout, this is your
Vout - ok.
Vout = VCC - ICRC
17
So, since IC is equal to 0 so, the voltage that you get here is the VCC which is about 5 volt
over here - right. So, how long it continues? It continues up to a maximum voltage, up to
a maximum voltage, when this base emitter junction becomes sufficiently forward biased;
so, that this starts conducting - ok, this transistor starts conducting. So, that maximum
voltage that maximum voltage we define here in general as VIL; that means, the voltage at
the input side which is considered low. The maximum of the input voltage at the input side
which is considered as low, any voltage less than that - what will it be, how will it be
considered?
It will be considered as low, logic low only because at that time you see the output is
remaining at high voltage which is an inverter action, I mean, the first part of the inverter
action, we shall see the other part also when input is high whether the output is low or not
ok. So, input is considered low up to a maximum point VIL, is it clear? So, after that the
transistor starts conducting. So, this from cut-off region transistor enters into next region.
What is that? Active region - right and when the transistor starts conducting IC is getting
increased, what will happen? This voltage, this Vout will slowly come down. We shall see
later for this particular arrangement under certain approximation this fall is approximately
linear, that relationship we shall soon see.
So, this is now the current is increasing, the voltage is getting increased. So, IB is increasing
accordingly IC increasing, βIB is the current, IC value the in the active region. And, this
will continue till it enters the next stage what is known as saturation – right, what is known
as saturation, when both base collector and base emitter junctions are forward biased - ok.
So, at this point what is the voltage here? It is approximately some 0.2, 0.1 volt or
whatever, depending on the transistor that you are using - ok. So, that is the maximum
voltage at the, sorry, that is the minimum voltage at the input side which is to be present
after which the transistor will enter, move into saturation - ok. Any voltage higher than
that in the input side, it will move into saturation, is it clear? Let me repeat once more.
So, from VIL when the transistor starts conducting which is in the active region, gradually
with increase in Vin this current increases corresponding collector current increases Vout
starts falling, it continues up to a level which is known as - when it enters the saturation.
So, after that any increase in the voltage, after that any increase in the voltage Vin the
transistor remains in saturation, we put that it comes out of the situation is it clear. So, you
we tell that particular voltage as VIH - VIH - ok. So, what happens at that voltage? At that
18
voltage we know formally that the output is in saturation and the voltage is here about 0.2,
0.1 volt also which is considered as low at the output level, low at the output level.
So, any voltage higher than that will be considered as, at the input side, will necessarily
make the output low - ok. So, otherwise speaking what is the significance of VIH? VIH is
the minimum voltage required at the input side which is treated as logic high - any voltage
higher than that at the input side will be treated as logic high ok, is it clear? So, you see
the relationship the inverter relation, inversion relationship input is low over here ok,
output is high, input is high, output is low - right. And, we will see there are two other
voltages this is the VOL that is the voltage at the output side which is treated as low any
voltage less than that will be treated as low.
Then VOH is the voltage at the output side which is stated as high any voltage higher than
that also will be treated as high. This is in general we see a characteristic of an inverter
which is also a kind of getting - there is correspondence between this transistor inputoutput characteristics, is it clear? So, we would like to do some sort of, you know,
quantitative analysis and we shall keep it very simple for our understanding of the way the
logic circuit or digital circuit works and we shall keep say, RB 10 kilo ohm ok. So, 10 all
0s are there; so, it will help - RC 1 kilo ohm, beta - transistorβ, the current gain as 50, βF
stands for beta forward, βR is beta - reverse beta that we shall take up later.
This VBE(ON) when the transistor is ON we shall consider the voltage at which it becomes
ON is remains on is 0.7 volt and when it goes to saturation there is a small increase in this
voltage, but again as I said this is an approximate analysis; we shall keep it at 0.7 volt only
- ok. But, actually there will be small increase in this voltage when it goes to saturation
and VCE saturation, we’ll consider as 0.2 volt which again as Vin increases falls little bit ok. So, this is what we are going to do.
19
(Refer Slide Time: 09:45)
Right! So, with this let us, let us look at that characteristics ok. So, the first thing that we
shall try to get is what at which voltage, at which voltage this fall starts occurring - right.
And, as we know, in this particular case, it is very simple, this VIL in this case is nothing
but voltage when it comes out of cut off region and enters the active region. And, it occurs
based on whatever values we have already taken, occurs at 0.7 volt - right. So, the
coordinate of this is 0.7 volt and 5 volt 0.7 volt and 5 volt - ok. This is this coordinate that
we see for the analysis that we are making. And, this is also known as edge of cut off, edge
of cut off. That means, at this point it is just coming out of cut off - is it clear?
(Refer Slide Time: 11:11)
20
Next, we shall see what happens when it enters into active region - ok. So, when it enters
into active region current flows along this loop 2 loops that you can see over here, one is
along this loop, another is along this loop - right. So, we shall look at we shall apply
Kirchhoff’s voltage law along this loop and from that we shall do a quantitative analysis
right. So, when we apply along this particular loop, this particular loop, what we see for
this voltage - IB will be Vin minus VBE(on) the voltage drop over here divided by RB - right.
IB = (Vin – VBE(on))/RB
From that, we can see the current through this, IB is Vin minus VBE(ON) that is the rest of
the drop is over RB divided by RB is what is your IB, is it clear?
Now, in active region we know IC is equal to βFIB and in active - this is the other loop
along which we are applying KVL.
IC = βFIB
So, this is 5 volt that is the VCC that we have already mentioned. So, this is generally
speaking - we write it as VCC because we can change it to some other voltage - other than
5 volt, if so required. For generalization purpose, we write this as VCC - ok. So, Vout is
nothing, but VCC minus ICRC and this IC is nothing but your βFIB - we will replace it with
this one.
Vout = VCC - ICRC = VCC - βFIBRC
Now, this IB - this was your equation 1 and this is your equation 2; so if you take the IB
from equation 1 and combine and place it here. So, this is the thing - that this is the
relationship that you get, is it ok? So, Vout is equal to VCC minus βFIBRC. So, RC is there IB is nothing, but your Vin minus VBE(ON) divided by RB, is it fine? So, as long as it is
remaining in active region this is the relationship it will follow and we look at Vout versus
Vin - rest of all are constant. There is VBE(ON) - will slightly change with increase in Vin.
So, we are neglecting that part - it is an approximate calculation - right! So, rest of them all the parameters are constant. So, we have Vout and Vin relationship between them is
linear - straight line - ok.
Vout = VCC - βFRC(Vin – VBE(on))/RB
21
Straight line with a negative slope of what minus βFRC by RB - is it fine? So, if we want a
faster fall – right, we want more of, more often the circuit remains in one of the two stable
switched states that is logic low or logic high. Then we would like to have this transition
region; this active region which is also known as transition region, that width, as small as
possible - ok. So, we would like to have a faster fall. So, in that case we would like to have
a RC mode compared to RB. We shall - we would like to have increase in R, but - again we
shall see later, if we increase RC then the circuits current delivery capacity - the IC part of
it gets reduced which actually makes it difficult for the circuit to get connected to many
other circuits that particular thing also, we shall see today - ok. So, there is always, when
you talk about design, there is always trade-off, ok. But, this is what we take from this
particular discussion - is that there is a linear relationship and the slope is negative for the
circuit in the active region - ok.
(Refer Slide Time: 15:25)
Now, next is saturation region - right. So, in this saturation region again we would be
interested to see when it enters saturation - ok. As long as it is remaining in the active
region, it is falling linearly with the negative slope – that, that part we have already seen
that is what we have already noted in the previous slide - ok. So, when this particular point,
this we define as edge of saturation, when it just enters the edge of saturation which
considers that it is still following the previous equation. After that it goes into saturation
region - it is no longer that linear relationship, that will be maintaining.
22
So, at edge of saturation, it is still maintaining - right. So, at that time this Vout when it just
enters the edge of saturation, at it, is at the edge of saturation is VCE saturation - right. So,
at that time the current IC we define with a suffix edge of saturation when it is just entering
here is VCC minus Vout is now VCE(Sat.) divided by RC. So, that is 5 - 5 volt we have
considered as VCC minus 0.2 volt divided by RC - RC is equal to 1 kilo ohm - that is 4.8
milli ampere - ok. If we increase the RC the current will reduce which is - which we’ll have
a look later in some other cases. So, we cannot you know just change it the way we like
you have to look at other considerations in situation like this.
Vout = VCE(sat)
IC(EOS) = (VCC – VCE(sat))/RC = (5-0.2)/1 = 4.8mA
IB(EOS) = IC(EOS)/βF = 4.8/50 = 0.096mA
Vin(EOS) = VBE(on) + IB(EOS) RB = 0.7 + (0.096)(10) = 1.66V
So, this is edge of saturation IC - right. So, edge of saturation IB is what this IC(EOS) - IC
edge of saturation divided by β- because, it is still in active region it just entering the
saturation region. So, 4.8 divided by beta forward which is 50 - 0.096 milli ampere, simple
calculation right. So, at that time what is the Vin –right. You refer back to that equation 1
that we had before. So, Vin is equal to VBE(ON) – right, the base emitter drop and IBRB drop.
So, IB edge of saturation in to RB in the KVL in the base emitter junction - that particular
loop - right. So, in this loop, this is the loop, in this loop. Sorry. So, this is the loop that I
am talking about - ok.
23
(Refer Slide Time: 18:31)
So, we in this particular loop when we impose these values – right, we have 0.7 volt, IB
edge of saturation 0.096 and RB we have taken as 10 kilo ohm so, 1.66 volt - ok. So,
thereby, we get this particular point also edge of saturation, which is also important to us
and this coordinate is 1.66 volt and 0.2 volt. Is it fine? Ok. So, any voltage greater than
1.66 volt at the input, at Vin definitely the circuit is in the saturation - right. So, that is the
significance of VIH I was trying to tell, that this is the minimum voltage required at the
input side which can be treated as logic high which you ensure for the inverter that the
output is - output remains at logic low – clear? Right.
(Refer Slide Time: 19:51)
24
Now, we come to some important parameters - noise margin, transition width and logic
swing - ok. Transition width - we have already seen, but again more formally we shall
introduce ourselves to these terms over here - ok. So, in the left hand side what you see is
a generalized representation, not specific to the example that we have taken. We have taken
the example to make a better understanding of these different terms. And all using a simple
transistor inverter, actual circuit will be more complex - which we shall take up later right. So, this is the output side - ok.
So, VOL we have already seen, the voltage at the output which is treated as low. Any
voltage less than that will be treated as low, in that example 0.2 volt. Any voltage less than
that treated as logical low, this is the shaded region over here ok: VOH voltage at the output
side, minimum voltage which is treated as logic high; any voltage above that will be treated
as logic high. So, it was 5 volt there and any voltage more than that 5 volt will be treated
as logic high without any ambiguity – clear! And, then the logic swing - this is defined as
logic swing - is the difference between VOH and VOL - ok.
Now, if you look at the input side; what is happening? This VIL as you have already seen
in that particular example, but it is true for every other cases for inverter like this, that from
0 to VIL this is treated as logic low. Any voltage, even less than 0 also, because of noise
and other things, if it is less than VIL, as long as it is less than VIL - it is treated as logic
low, the input is treated as logic low - right. And, at the input, at the input side any voltage
greater than VIH will be treated as logic high - ok. In that example it was 1.66 volt, any
voltage more than that it will be treated as logic high; the output will be low at that time right.
So, the difference between VIL and VIH - the time, the phase or the duration, if we are
continuously increasing the Vin, input voltage that is being in your transition width; the
active region in which where it is staying - ok. So, after understanding these terms once
more now, we define noise margin high, no - noise margin low as VIL minus VOL. What is
the significance of it? The significance of this is this that up to VIL we are treating in this
as logic low. Here if this inverter is connected to another inverter, another similar device
to the next stage. So, when it is at logic low, what is the voltage it is offering? 0.2 volt or
less, maximum voltage is 0.2 volt - ok.
25
Now, imagine some noise gets into - gets corrupted by additive noise - right. So, the 0 if it
is a 0.1 volt and 0.1 volt noise so, the voltage at the output will be 0.2 volt ok. So, what I
mean over here let me draw a diagram which may make it clear to you. So, I am talking
about this is being connected to another device another such inverter or other gates right.
So, here it is 0.2 volt maximum I mean when it is treated as logic low, it can be less than
that, but let us consider the limiting case - ok. And, then noise gets added say, at additive
noise and is getting added over here, so this is noise right. So, how much noise you can
allow so that this low is treated as low here. The maximum voltage that can treat as low
is 0.7 volt - ok.
This is maximum at the output when it is logic low is 0.2 volt, it can be less than that. So,
what is the difference? The difference is the maximum voltage that can be accepted as
noise which is added as with positive polarity - if it is negative value – say, 0.2 volt and
noise is minus 0.1 volt then there is no issue - ok. But, noise with positive polarity if it
comes noise it then this is the thing that we are need to remember, is it clear? So, that a 0.5
volt margin is there with me. So, this is noise margin low generally speaking for any such
situation where VIL and VOL, VOH are defined this is the difference - is the noise margin.
NML = VIL – VOL = 0.7 – 0.2 = 0.5V
NMH = VOH – VIH = 5.0 – 1.66 = 3.34V
In this specific example that we have taken from which we are trying to understand this
terms - it is 0.7 minus 0.2 volt which is 0.5 volt - ok. So, similar thing is noise margin high:
So, when the output is at logic high say VOH - right and at the input it has to be treated as
logic high - right. So, what is the - now if noise gets added, but if it is positive polarity it
will be VOH plus some value - then there is no issue. This we are in this region, but if it is
negative polarity! Now, the polarity of noise if so negative, if negative, then we are in a
bit of concern. So, this VOH can come down, it comes down and crosses VOH then we are
in a problem; the input will not be treated as high - ok.
So, this VOH minus VIH is the noise the margin of noise that - it can accommodate. So,
accordingly, these two terms are defined and in this specific example that we have taken
it is 5 volt minus 1.66 volt which is 3.34 volt. So, transition width of course, is the
difference between this VIH and VIL and logic swing (is VOH and VOL). So, these definitions
26
that you see these are general, irrespective of the example we have taken. And this is
applied to any logic family and the corresponding gates - ok.
Transition width = VIH - VIL = 1.66 – 0.7 = 0.96V
Logic swing = VOH - VOL = 5 – 0.2 = 4.8V
(Refer Slide Time: 27:15)
Now, we shall end with one important term called fanout and the example that we had
been talking about - noise margin we know, we will take it little bit further. So, here what
we see is that a transistor, a gate will never work in isolation. We know that hundreds,
thousands you know such a gates are you know working together in an integrated circuit.
So, this particular inverter is connected to many such inverters - ok. And when the input
so, this is the driver and these are the loads load 1, load 2, load N we shall figure out how
much, how many loads can be connected - ok.
So, at the input side when the input is say logic high; what will be the value here, output
will be low. So, 0.2 volt also or even less - then none of this load transistors will be on,
because it represents a 0.2 volt ok. So, you can connect since it is not drawing any current,
you can connect many such load transistor, load gate without any difficulty, load inverter
without any difficulty, is it clear?
27
(Refer Slide Time: 28:47)
But there may be an issue when the input to the driver is low. So, this is the input to the
driver when it is low the output is high, you have, you have already seen right; the
characteristics part of it - isn’t it? So, the characteristic show us like this. So, when input
is low the output is high; so this particular thing - right. So, this output high we are
connecting to many such gates - right and, whenever it is connecting these are drawing
base current - right.
And though there is no current in this direction, but there is a current in this direction for
which there will be ICRC drop; more such connection, more such more amount of current
has to be delivered. And the voltage will be keep coming down, it will not - no longer be
5 volt. So, how much it can come down? So that it is still treated as logic high at output
side there is a limit on that right, that is, 1.66 volt in this particular example. After which
it will not be treated as logic high, it will enter into the active region; this load will be
entering into the active region - ok.
IC(driver) = (VCC – Vout)/RC = (5 – 1.66)/1 = 3.34 mA
So, that will define, that will decide how many such gates can be connected - ok. So, this
is the way we calculate this one. So, for the VIH we say this limiting case is 1.66 volt and
driver at that time how much current it can deliver, VCC minus Vout that is 1.66 volt divided
by 1 kilo ohm. So, that is the 3.34 milli ampere, that is the maximum current it can deliver
without this voltage going below your 1.66 volt, the limiting value; after which it will be
28
no longer treated as logic high at the input at the load gate side - ok. And for the load gate,
when it is high, what is the current it is drawing? We have already calculated this one - ok.
IB(load) = (Vout – VBE(sat))/RB = (1.66 – 0.7)/10 = 0.096 mA
N = IC(driver)/IB(load) = 34.79 → 34
So, Vout minus VBE(Sat) divided by VBE(Sat) divided by RB - ok. So, this is your own 1.66
volt 1.66 volt limiting condition we are talking about and this is 0.7 volt over here right
divided by RB. So, this is 0.096 milli ampere, this is the current that is 1 load gate is taking
- ok. So, how many such load gates are there, how many load gate you can connect by
this? This divide the amount of current it can deliver divided by this one. And, this number
is quite big I mean 34, we have to consider more, you know other issues into it, and then
it will be clear - ok.
(Refer Slide Time: 31:49)
So, this is the last slide for this particular discussion. So, what is the effect of noise margin
- ok? So, earlier when we talked about, when we are bringing down to 1.66 volt – ok, what
becomes the noise margin, there is no noise margin there - ok. So, if you want to, because
whatever was possible the we have brought down to that particular level - any noise now
getting added, any noise now getting added at the output 1.66 volt and some noise with
negative polarity 0 point minus 0.1 volt or so - ok. It will not be treated as logic high
anymore. So, there is zero noise margin ok.
29
So, if you want to keep a noise margin of a desired value depending on the environment
in which it is operating, then you have to consider that also into our calculation, that factor.
So, this 1.66 volt will not - no longer be a 1.66 volt; it has to be plus the noise margin that
we are talking about say 0.5 volt that makes 2.16 volt - ok. So, then the driver side current
the maximum current it can deliver is VCC minus Vout; now it has now considered VIH as
well as the noise margin - ok.
VOH = VIH + NMH = 1.66 + 0.5 = 2.16V
IC(driver) = (VCC – Vout)/RC = (5 – 2.16)/1 = 2.84 mA
IB(load) = (Vout – VBE(sat))/RB = (2.16 – 0.7)/10 = 0.15 mA
N = IC(driver)/IB(load) = 19.4 → 19
So, that makes it 2.84 milli ampere - right and at that time what will be the load current for
each of the gates. So, IB(load) is 2.16 minus 0.7 divided by this base resistance - is 0.15 milli
ampere. And, then you look at if you just reduce the division, the number comes down to
19, from 34 it has come down to 19 drastic fall - isn’t it? So, if you have more noise margin
then there will be more such issues - right. So, I mean more fall in the number and then
there are other parameters also,that we have not considered in this discussion. Like the
beta that we have considered 50, it might be when you use the transistor it could be 40
also, it could be 30 also - depending on the make and there will be a transistor to transistor
variation. So, you have to keep a you know, a consideration like what this scenario is, also.
So, each of this parameter might vary and may not be you know, the VBE saturation also
we have said, it is not exactly 0.7 volt can vary little bit, VCC can vary 5 volt power supply
may be 4.5 volt or 5.5 volt. So, these are the different things for which the actual thing,
actual value we will see it that for this particular configuration from 34 to 19, now actual
practically, it can come down to 5, approximately 5 such - ok. So, these are some important
parameters - with an example we have noted.
30
(Refer Slide Time: 34:43)
(Refer Slide Time: 34:45)
So, these are the references. So, quick summary: transistor can be used for a NOT logic.
The cut off and saturations are two stable states. We have seen the input and output
characteristics and from that we have derived some very important some generalized
terms: noise margin, transition width, logic swing. And, we have taken up one example
case and put some values and understood its significance. And, fan out is also another
important parameter that also we have seen what does it mean and what is its significance
and how to calculate it.
31
Thank you.
32
Digital Electronic Circuits
Prof. Goutam Saha
Department of E and EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 03
Performance Issue and Introduction to TTL
Hello everybody. In the last class we looked at use of transistor as a switch and we also
looked at important performance metrics like noise margin, fan out, and some other
parameters like logic swing, transition width, with the help of an example which was a
simple resistance and one single transistor based inverter.
(Refer Slide Time: 00:50)
Today we shall extend that discussion and look at some other performance metrics. And
then we shall slowly introduce ourselves to TTL - Transistor Transistor Logic.
33
(Refer Slide Time: 01:04)
To begin with one of the performance metric which we would like to discuss now is called
propagation delay. Propagation delay occurs because of two reasons; one is finite
switching speed associated with the transistor. So, transistor from off to on or on to off in
that - generally there is a redistribution of charge in the transistor junctions we know that
npn transistors there are two junctions base meter and base collector junctions.
And this re-distribution of charges take finite time it is not hap happens it does not happen
instantaneously. So, this is one reason. And the other important reason is there are circuit
capacitances which cannot be ignored. Even if it is not explicitly connected between any
metal junction and the ground there is a circuit capacitance. Important over here is the
circuit capacitance if we look at, if you remember the previous transistor inverse inverter
circuit - ok.
So, we are taking this is your Vin and this is your Vout - ok. So, though we have not explicitly
mentioned there is a presence of capacitance, but there is a load capacitance which is
present. And, the more the number of load, the more the number of other transistors you
connect, more is this value because, those all - these capacitances come in parallel. And
this transistor, this capacitance needs to get charged through this path - ok.
So, there is a RC, this RC - this is RC and this is RB. So, there is a time constant associated
for pulling up the value over here. Discharging takes place when this transistor is on. So,
that path resistance is less so, it is relatively quicker. And this is visible when you see this
34
particular diagram. So, this is your one this is your input and in the input side you can see
that the input does not, is not possible to change instantaneously though you are saying
from low to high there is a finite time, time - again because of the electrical parameter
circuit parameters that are associated with the input side of the circuit.
So, this is the 50 percent time that is considered as the one by which it has got sufficiently,
you know, become low to high. And the other side if it is - since it is an inverter reaction,
when it is following from high to low - the 50 percent time; 50 percent of the magnitude
when it - when it happens that is the time between output going from high to low - ok. So,
this is the time difference that we see over here - ok.
So, this is time propagation delay output going from high to low, corresponding time
propagation delay when output goes from low to high, and you can see that this low to
high is relatively higher. One of the reason, as I said is the switching speed the transistor
when goes from off to on the charge distribution does not take - that aspect of it, does not
take much time, but when it goes from on to off - ok. So, at that time the charges that are
there that need to be taken out - so that the deeper into the saturation we want to work it in
the saturation mode; so, deeper into the saturation - more is the time required to bring back
the transistor from on state to off state - ok. So, for which this delay is more, and if you
talk about one entity then it is an average of this two which is the propagation delay.
Toward that time parameter that are important here one is rise time another is a fall time.
tPD = (tPHL + tPLH)/2
Rise time is the value from 90 percent, this is 90 percent to - sorry 10 percent to 90 percent
whatever time it requires. So, that is the rise time and fall time is 90 percent to 10 percent
whatever time is required that is your fall time. So, this is your t fall and this is your t rise
- ok. So, these are two important parameters associated with so, we shall take note of this.
(Refer Slide Time: 06:08)
35
Next important parameter is power dissipation-ok. Power is an important issue - reason
being, these transistors or the gates will not work in isolation. There will be large numbers
of them and modern integrated circuits have million of millions of them. So, though
individual gate, individual transistor or gate power dissipation may be less, but collectively
there might be very, very large power dissipation. So, this is an important quantity.
So, there are two kinds of power dissipation; one is static power dissipation, another is
dynamic power dissipation. Static power dissipation - when the transistor is in one of its
stable state - on or off. So, at that time whatever current is flowing from the power supply
we know, the voltage into current is the power that is dissipated.
And total power will be average of these two and in all our calculation we usually consider
that the time-on during which it remains at on state and time during which it remains at off
state, off state - they are equal - ok. So, that is the way we calculate this thing and the
average power - ok. And dynamic power dissipation occurs when the transistor switches,
when the transistor switches so, that time during the switching whatever power dissipation
occurs. So, this might not be a very clear at this point of time given the example we have
seen before - that the simple transistor inverter. This will be clearer when we take up more
examples with TTL and CMOS circuits - CMOS logic gates which we shall discuss little
later.
So, right now, we more or less understand this part - the static power dissipation part of it.
And one more important aspect here - the transistor power dissipation can be reduced by
36
reducing the amount of current. And that can be done by increasing the value of the
resistances, resistances without making much of a changes elsewhere in the circuits. So, if
you increase the value of the resistances current reduces, but what is the effect in other
parameter - one important parameter that is propagation delay, the time constant will
increase. So, accordingly propagation delay will increase. So, it has been seen that to a
great extent within the operating condition that can be accommodated, the power
dissipation and propagation delay this product more or less remain same - ok. So, if you
reduce power by increasing resistance values, propagation delay increases and vice versa.
So, this is called one figure of merit of course, if it is lower, the better. So, this is something
that we take note of.
(Refer Slide Time: 09:07)
Now, the circuit that we had seen before that was just an inverter – isn’t it? So, when you
talk about logic gates there are many different kinds of logic gates that are possible. So,
using that particular circuit as the base, one simple element, can we develop other gates?
So, let us look at one particular circuit over here.
So, two such inverters except the collector resistance part - they are in parallel – ok. And
this if we look at, if you compare what we had seen before - so, this is your RB, this is your
RB in earlier circuit and this is your RC so - that made parallel to one another. Now, how
does this circuit work in terms of in a logic value? So, any one of them low what happens
- and the corresponding - the other one is, say low or high. So, this is a low, this is low or
37
high what is happening? So, if this is low and the other one is also low ok, so none of this
transistor conducts - then, none of the transistor is on.
So, at that time what will be happen to the output voltage output voltage since there is no
current flowing here accept the whatever small load current will be there. So, it will be
VCC minus that drop so, output will be considered as high. But, this is low and this is high
what happens at that time? This is conducting. So, this is 0.2 volt or so, the saturation
voltage so, output is treated as low. Now, we look at the other case. So, this is - these are
the two cases that we have seen, this one is at high - ok. So, this voltage - this transistor is
on - right. So, this voltage stands at 0.2 volt - this is getting a path. So, even if this transistor
is off or on does not matter - the output voltage will be kept at 0.2 volt - ok.
So, this is what we see over here for these two cases. Effectively, if you look at the whole
of it these output is low for any of the circuit any of the input being high. And, output is
high only when both of them are low, both of the transistors are off. So, that is NOR logic
that we see and this can be extended - this is now two; three-four to the extent it is possible,
and that defines the fan-in - how many inputs can be connected to a particular gate - ok.
So, that is another term that we can define over here - that is called fan-in.
(Refer Slide Time: 12:08)
Now, let us look at this circuit, how does the circuit work. Earlier what we had seen - the
transistors, the input, inverters were in parallel. Now, what you see over here they are in
series - ok? So, when they are in series what happens - any one of them is low; that means,
38
the path through this transistor - that particular transistor is off; either this one is off or this
one is off so; that means, the path to the ground is blocked - right. So, either this one is
blocked or this one is blocked or both of them are blocked – right. So, the path is not
available. So, what will happen - this voltage minus whatever the load current related drop
over here, will be available here so, this is effectively a high voltage, high condition.
And only when, only when both of them are on - a path to the ground; a low resistance
path to the ground exists - ok. So, the drop will be 0.2 and 0.2, 0.4 volt or so - right. They
are in saturation - which is still considered as logic low, is it fine? So, this kind of circuit
behaves like NAND - if you look at the truth table any one of them is low output is high;
all of them high, output is low. And, later on we shall see that using NAND gate and NOR
gate any other gate we can develop, we can also look at that part, but we shall see later.
(Refer Slide Time: 14:02)
Now, though we said that we will be discussing more of the TTL and CMOS logic gate
later, but whatever we have discussed so far, I mean, were there any such practical IC’s
available at any given time? Yes, long back - 1960’s we had these ICs in existence and
this is one example that I have taken up from Motorola data sheet that is available as
archive. So, what you see over here - it is straightaway taken from the data sheet - one
page of it, part of a page. So, what do you see over here is a RTL this is called Resistance
Transistor Logic, because of the presence of the resistance and transistor - this IC was
available at that time. And this particular IC, these are the different pins that you can see
39
these pin numbers are there. And this was two 3-input NOR gates. Within the IC, there
were two such NOR gates and each one of them was having 3 inputs - ok.
So, this was available at that time. And, for our example case - we used you know, for
simplifying the calculation we took RB is equal to 10 kilo ohm and RC was 1 kilo ohm and
we calculated that the transition width can be reduced if we increase the value of RC
compared to RB because their slope was minus RC by RB those things were there. So, here
what we see in practical circuit that they came up with as the IC - R1 was used as, R1 is
related to your RB, 450 ohm, and RC which is R2 here is 640 ohm - that was a practical
circuit that was used at that time. And power dissipation was when input was high input
was high means transistor was on. So, current is flowing through RC through the transistor
to the ground, 55 milliwatt. And when it was off for the kind of standard loading it was 15
milliwatt and, propagation delay was 12 nanosecond. So, that is what the data sheet
provided at that time.
(Refer Slide Time: 16:24)
Now, to go to transistor-transistor logic, let us have a look at something that was
intermediate. This was called diode-transistor logic it does not mean that resistance was
not used, but just to keep, you know, this thing later. So, earlier was resistance transistor
logic, this is diode transistor logic. So, transistor remains because that only provides the
inverter action not action and regarding use of diode we have already seen diode as a
switch in our first class, if you remember lecture 1.
40
So, there we had seen this diode resistance combination - right. So, between this two input
A and B and this Y what was the relationship any of the input is low - output is low,
because current is going in this direction. Only when both of them are high the voltage is
available here that is no current is flowing all right and at that time the output was high.
So, this was effectively AND logic - right. So, you see over here in the diode transistor
logic in the first stage, you have got this particular block this particular block this particular
block, which is providing you the and logic - ok.
And after that there are two diodes what are they doing they are just doing the job of level
shifting - ok. So, how this level shifting is useful the level shifting is useful because, earlier
what we had seen? We had seen that the transistor turns on when base emitter drop is 0.7
volt.
Now, if you put another diode before that so, you need two diode drops 0.7 and 0.7. So,
then it will only you know turn on so, that is known as level shifting - ok. So, there are
these two diodes that are present which are level shifters - right. Now, this diode conducts
current only in this direction. So, in this base emitter junction wants to come out of the
saturation so, the charge need to go back to the ground for that, since diode does not allow
that path. So, there is this resistance is there which is providing a path for the charge to get
redistributed when the transistor comes out of on state to off state.
So, this is how it is there and to turn this transistor on what is required? 0.7 volt, 0.7 volt
and 0.7 volt so, 2.1 volt will be required over here then only it will be able to turn on. So,
any of this low so, the voltage over here is available is low means similar circuit you know
connected before something like this. So, low means 0.2 volt or so, over here. So, 0.2 and
a diode drop there; so, 0.7, so 0.9 volt is available here which is not sufficient to turn this
on. So, any one of them low – output, this transistor is off output will be high and when
both of them are high then only the transistor is on and the output is low. So, that is what
kind of logic is that this is NAND logic so, that is why we called it DTL NAND gate – ok.
Now, we shall get introduced to what we said earlier that TTL NAND logic - ok.
41
(Refer Slide Time: 20:12)
So, we remember the DTL circuit - just in the previous slide we had seen. So, this input
block what do you see over here - there are two diodes, and there are three diode
combination and in TTL this is replaced is with a transistor which is something like this.
This two diodes refer to two multimeter two emitters in a multimeter transistors this diode
refers to the base collector junction over here; this is the base emitter junction, this two
correspond to and this is the block which is coming in place of the one that we had seen in
the DTL case - ok.
So, there was a diode over here one level shifter. So, that level shifter the second one that
we had seen. So, this level shifter is present here as a transistor. So, this base emitter
junction is providing the diode kind of you know drop that is required - clear. So, with this
two changes in the previous circuit so, this two changes; so, this is changed this is replaced
by a multi emitter transistor. And this is replaced by another transistor - we go to the circuit
that is over there. I shall talk about this little later -what is the significance of this - ok.
So, this particular transistor which is now coming in this particular place it has got another
name called phase splitter - ok. So, how does it work - let us see. Then it will be clear why
it is called phase splitter. Now, when any of this input, multiemitter input is low what is
happening - it is happening similar to what was happening in case of DTL case. So, the
transistor, the current will be going in this direction - right. So, current is not driven
towards this transistor which is numbered as T4. So, this transistor is off so, this transistor
42
is off right so, in this transistor is off; that means, I am talking about any of them is low
any of them is low - ok.
So, the current is going in this direction not much current in the other direction so, this is
off. So, when this is off, no current is flowing in this direction right, when no current is
flowing in this direction, no sufficient I into Re drop to turn on this base emitter junction
this transistor T3. So, T3 is also off - is it clear? Right. When any one of them are low any
one low - ok. So, this is off, this is off and when both off all right - current is not going in
this direction. What is happening to this voltage? This voltage will be VCC, 5 volt minus
whatever current flowing through it as base current over here - considering some load is
connected.
So, that is a base current so, relatively small current will be there - ok. So, that drop will
be very small so, that way this voltage over here will be sufficiently high - ok. So, this
voltage will be sufficiently high. So, that sufficiently high voltage will do what - will make
this transistor on - ok. So, this transistor will be on at that time. Why the diode is required,
that part we will come later. So, right now we consider that this transistor will be on at that
time and if a load is connected here. So, load will get current from this path, this path
through this on transistor - is it clear? So, any one of them low this is what is happening.
Now, let us look at the other case when all of them are high - all the inputs are high.
(Refer Slide Time: 25:06)
43
What is happening at that time? So, the current is driven towards - some current is driven
towards this direction - right. So, this get sufficient base current for which this transistor
becomes on this transistor becomes on - so much on that it is goes into actually saturation
that part we shall see later - ok. So, then the current flowing through this transistor is so
much all right minus the base current over here that gives you sufficient drop across this
to make this voltage greater than the VBE on greater than. So, this transistor is also on
again this transistor is also on so much so that it also goes to saturation.
So, what is the voltage then available over here? So, this is saturation 0.2 volt and this is
saturation 0.2 volt 0.1 volt and of that range and this is saturation 0.7 volt. So, about 0.9,
0.95 volt is available over here - ok. So, let us consider say, 0.95 by volt on the higher side
- ok.
Now, with this particular voltage, this transistor – right, here it is 0.2 volt because this is
in saturation. So, if this diode was not there 0.95 and 0.2 this voltage would have been
sufficient to make this transistor on and go to saturation – ok.
So, this is what is prevented by placing the diode over here. So, you require actually two
diode drops; that means, about 1.4 volt or so, to make them on. So, at that time what is
happening this transistor is actually off, because of the presence of the diode - ok. So, that
is the importance of having the diode over here - ok. So, these are the other cases, this is
the other case - when all of them are high all high output low; anyone low output high.
What is that logic? That is nothing but the NAND logic. So, this is what - how this
particular circuit works. Now, one important thing over here.
44
(Refer Slide Time: 27:59)
Earlier, you we had seen the charging of the output capacitor was through a passive
resistance – right. Now because of the presence of this transistor. Now, what is happening
- it is known as active pull up which effectively reduces the resistance of the output circuit,
output impedance below 100 ohm which is of the, I mean, almost 10 times less then what
would have been the case if this was not present. So, that is why the charging time of this
capacitor decreases - discharging is through this path. So, that is small, because of this as
a very low resistance path - ok. So, effectively this helps in switching, reducing the
propagation delay. So, that is another important aspect of this and the whole of it, the one
that you see this structure is known as totem pole output.
So, this is like one physical structure if you see that. So, totem pole is something like this
ok. So, that kind of it is - that is the similarity. So, that is why it is called totem pole output
and this has got it is own advantage of charging and discharging a bit faster. So, we shall
discuss more about this TTL circuit, how it works in the next class.
45
(Refer Slide Time: 29:34)
And, just to summarize what we had seen today is the propagation delay power dissipation.
And their product figure of merit; their importance. RTL NOR gate getting formed by
parallel connection of transistors the kind of thing we have seen using electrical switches
we are getting NOR logic, we got NOR logic that we discussed in the 1st class - lecture 1.
And similarly, we got NAND logic by placing the transistors in series - ok. And we had
discussed that fan-in is you how many say, it you if you are putting it in input - how many
such gates can be - so, the maximum of that is called fan-in that is another important
parameter for this logic gates - ok. So, in the DTL NAND gate, we have seen the diode
and AND logic was there in the first stage after that there was level shifters. And, then
there was transistor in inverter.
And in the TTL NAND gates we found that in the input stage that diode AND logic has
been removed with a multi emitter transistor. And the level shifting diode has been
removed using a phase splitter phase splitter is called because the collector and the emitter
of that phase splitter transistor - they are always out of phase - ok. When one is high another
is low making one of the totem pole, one of the transistor in the totem pole output on another is off; both of them are not on simultaneously except during switching; except
during switching. That we shall discuss more later, and this totem pole output improves
switching speed.
Thank you.
46
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 04
Transistor Transistor Logic ( TTL )
Hello everybody. Today we shall discuss more of Transistor-Transistor Logic.
(Refer Slide Time: 00:21)
And we’ll cover TTL transfer characteristics and different operating parameters, TTL open
collector configuration, how it is used, TTL Tristate, and Schottky TTL.
47
(Refer Slide Time: 00:34)
In the last class we got introduced to TTL, and there we ended by saying that a phase
splitter - this is the phase splitter that we see is important when we talk about the TTL,
when we talk about TTL activity, and the totem pole output configuration. So, this is what,
how we ended in the last class.
And in this class we shall elaborate more on that. So, this is the phase splitter and also we
mentioned that this resistance cannot be made 0. So, this was there in the last class, we
made a note of it. So, in this particular thing we look at the inverted characteristics, this is
the inverted characteristics. There are 4 distinct zones, ok. So, we shall discuss each one
of them turn by turn, and the first thing when we, what we start with is the case when the
input voltage is 0, ok. So, this Vi is 0, there is a difference to VB4, this particular voltage this is VB4, that we shall discuss little later. So, this is your VB, VB4, ok.
So, when here is 0 - what is happening? Current is going in this direction, current is going
in this direction - right. And this transistor, the base current is very small the collector
current is also accordingly small. So, this transistor will be having more of IE, ok. So, it
will be firmly in saturation - right. And when it is in saturation - current is going in this
direction, so this transistor does not get enough current to be on so this T4 is off, in cutoff. And when T4 is off, no current is flowing through this. So, T3 is also in cut-off, ok.
So, these are the two things that we can see, T1 is of course in saturation.
48
What happens at the time to T2? T2 at that time is on, and the current that is flowing pastd
this T2 depends of course on the load because T3 is off - whatever current is flowing past
here, it depends on the load current, ok. For a typical load, the current over here is the base
current which is reasonably small. So, IB and RC4 - this drop is small. So, accordingly the
output voltage will be drop across this diode, and drop across this transistor, this baseemitter junction, ok.
IRc4 = IB2 negligible
V0 = 5 – 2x0.7 = 3.6V
If more load, V0 = 5 – 2x0.75 = 3.5V
A: T4 turns on at VBE4 = 0.65 V
Vi = 0.65 – VCE1(Sat) = 0.55 V
So, typically, it is 5 minus 2 into 0.7 - 3.6 volt. For a large amount of current, if it is drawn
by the load both of them can go into saturation. So, at that time these two drops will be
0.75 volt or so. In this particular discussion, this part of the discussion, we consider that
the transistor when it just begins to be on, the base-emitter junction voltage is 0.65 volt –
ok, just it starts operating; becomes active at 0.7 volt - when it is active and, when it is in
saturation it is 0.75 volt. So, this is how we look at this base-emitter voltages for an
approximate calculation of this transistor inverter characteristics, ok.
So, for that particular case, we have 5 minus 2 into 0.75, 3.5 volt will be available at the
output when a load is connected and which is drawing larger amount of current. So,
accordingly, find this point 3.5 volt at 0 volt what here in the transfer characteristic clear,
ok.
Now, as the input voltage is increased, ok, - so, slowly, slowly, current might get diverted
in this direction, ok. Now, when this VB4 is 0.65 volt just at this particular point, ok. So,
what will happen - this T4 will turn on, this base-emitter junction will turn on, base-emitter
on, this is what we have considered, ok. So, at that time 0.65 volt and this is the collector
saturation drop that is 0.1 volt. So, at 0.55 volt of Vi what we see that T4 is just turns on.
So, this is one big point A over here that we see in the characteristics - clear, ok.
49
So, now, we go to region II. So, this is the region II. So, in the region II, what has
happened? T4 has become active, ok, so current as started flowing through this. So, IE4
and Re this drop is there, ok, but this drop is not sufficient to turn this T3 on, it is still less
than 0.65 volt, ok. So, what will happen at that time? Only this one will be on and T3 is
then cut-off that is what is region two over here, ok. And at that time, at that time of course,
since this has started conducting these drop is not negligible anymore these IRc - this drop
across this Rc4 is not negligible anymore, ok.
IRC4 ≈ IC4 NOT negligible
AV4 = - (Rc4 / Re ) = -1.4
AV2 = 1 (emitter follower)
B: T3 turns on at Vi = 0.7 + 0.65 – 0.1
Vo = 3.5 – (1.4 x 0.65/1) = 2.6 V
So, at that time, if you will look at the gain across this voltage gain across this T4, ok, so
from our basic transistor amplifier principle - the gain is minus Rc4 by Re, that is the gain
that we shall see in a configuration like this alright. And the gain that we can calculate this
is 1.4 kilo ohm and this is 1 kilo ohm, all right. So, as we keep incrementally increasing it
this particular transistor will offer a gain of minus 1.4 which you see this slope by which
it is reducing. How long will it reduce? Ok, like this till this starts operating. When will it
start operating? When this voltage is 0.65 volt. Plus minus.
When this is 0.65 volt, how much current is flowing over here? So, 0.65 volt divided by 1
kilo ohm, right. So, that is the current, and that multiplied by 1.4 is the voltage that will be
the drop across this at that time, when it just starts operating. And at that time, then output
voltage will be 5 volt minus 0.75, 0.75 minus this particular drop, so 3.5 minus this drop
so that is the 2.6 volt. So, when it just begins to - become on, at that time this is the point
that B is reached, that is your 2.6 volt and at that time the input voltage is 0.7 volt over
here, and 0.65 volt over here, that is 1.35 that is VB4 - that is required, and minus the
saturation voltage over here 0.1 volt, that is 1.25 volt, that is what you will see at this break
point B, is it clear? So, this is the II zone - how it can be defined, ok.
50
(Refer Slide Time: 08:35)
Now, we look at zone III, ok. So, in zone III, T4 and T3 both are active, ok. So, you are
looking at this particular place. So, both of them are active. So, the resistance across this
base emitter junction, which in h parameter term, which is defined as hie which you have
defined here as rd, resistance at base-emitter junction can be considered - as a diode
resistance in that equivalence, ok. Otherwise those who are familiar with h parameter
representation this is nothing but the hie in the h parameter - to put a representation.
AV4 = - (Rc4 / Re || rd) = -2.8
AV3 = ΔV0 / ΔVB3 = - (βFRc3(eff.) / rd)
Rc3(eff.) = (rd(D) + rd(T2) + Rc4)/βF
AV3 = - (1.4 + 1 + 1) / 1 = - 3.4
ΔV0 = AV4 ΔVB4 + AV3 ΔVB3
AV = AV4 + AV3 = - 6.2 [as ΔVB4 = ΔVB3]
C: T3 saturates at Vi = 0.75 + 0.7 – 0.1 V
So, this resistance will come in parallel with rd, and because of which this gain will become
Re parallel rd in the denominator, and Rc4 in the numerator, ok. And rd is of the order of 1
kilo ohm similar to this. Of course, the more current flows, we know the current versus
51
voltage curve, by which at higher current, the rd value will come down. So, this will not
remain exactly at this particular value, but gradually this denominator will become less,
but for our calculation, approximate calculation, this is sufficient. So, 1 kilo ohm, 1 kilo
ohm in parallel - that is 0.5 kilo ohm and we get the gain of minus 2.8 from this part, for
this part of the gain, ok.
Now, when this one is conducting - is in active region, this is also providing a voltage gain,
ok. So, these voltage gain is at the output with respect to voltage changes that is occurring
at the base of T3. And, this can be calculated as the beta forward - that is again, this is
your rd, beta forward is nothing but that h parameter term hfe, - hfe or we know the current
gain, that is the beta in the forward direction - forward active mode of the transistor, ok.
So, at that time what is happening? So, these beta forward and the collector resistance at
this for this particular transistor and the base-emitter across this - the resistor that is there,
which is hie or rd over here the way we have represented it, clear! So, this is the AV3.
Now, this Rc3, effective Rc3, how do you calculate? You calculate as the resistance in - this
resistance - diode resistance, this resistance - over this base emitter junction resistance, as
well as this Rc4 divided by the beta forward - is the effective collector side resistance for
this calculation, which happens to be minus and if you just substitute the values - minus
3.4, ok. And the gain over here in this cascaded stage is gain forward coming from here
change in delta VB4, and change coming from this right – and, this delta VB4 and delta VB3
- the change over here and the change over here are same because of the emitter follower
- that kind of you see - whatever change will occur the same change will occurr over here.
So, effective gain is summation of these two and we get an approximate slope of minus
6.2 which of course, increases towards - when more and more currents are flowing,
flowing through it, ok.
So, this is how the third zone occurs and the T3 saturates at, this particular transistor
saturates at when this reaches a voltage 0.75 volt, ok. So, this is 0.75 volt, this is this
saturates before T4 0.75 0.7, and at the input side minus 0.1 that is the voltage that you
will see which is 1.35 volt over here, ok. Is it clear? This is the 1.35 volt that you see from
the input side from VB4 side it is 1.45, ok. So, this is the point C, that is how it is defined.
So, Vi is still getting increased - what will happen? Now, T4 will go also into saturation
and that is the voltage that kind voltage will be 2 into 0.75 minus 0.1, that will be the Vi at
52
that time and corresponding Vo will be 0.1 volt. And if you keep increasing the voltage
then what will happen? This transistor will be working - this will be sending current in this
direction, it will work in the reverse direction. This emitter will work as a collector and
this collector will work as an emitter and the current will be going in the other direction –
right; and for that the inverse beta will be very small value, ok.
T4, T3 saturate at Vi = 2 x 0.75 – 0.1 V
V0 = 0.1V
So, if you now look at the whole of it the normal stable operations - this is the region I and
region IV, ok. And in this region I and region IV what we see - how this T4 conducts. So,
in region I, we have already seen that T4 is off, when T4 is off this is high in terms of, you
know, making this transistor on and this one is low, that is in region I. And the other stable
condition is region IV; and at that time what is happening in the that particular condition;
in region IV so this is in saturation, right. So, this time this is low in terms of making this
on these two transistors on, and this is high in terms of making this transistor on, ok. So,
this transistor is on. So, 0.75 volt, 0.2 volt here, 0.95 which is not sufficient to drive both
this transistor, and the diode together on, so this transistor will be off, ok.
So, in that sense, in that perspective, they are - when one is low another is high on when
one is high the next, the other one is low. So, they are remain out of phase in that sense,
that is why it is called phase-splitter. And we have already noted in this particular zone
briefly, this T2 and T3 both of them are active, for which there is a path from 5 volt to
ground when both the transistors are, and diode is on. And there, the resistance over here,
we need to make it some finite value, we cannot make it a 0 because, otherwise large
amount of current will, you know, flow and power dissipation will be there, ok.
53
(Refer Slide Time: 15:32)
Now, we look at the - one practical, so I said that parameter was an estimated value. So, if
you look at any standard manufacturers datasheet we shall see that how the TTL gate
inverter 74 say, 04, what are the different parameters how that is been specified, ok.
So, we are already familiar with the terms like VIH, VIL and so on. VIH is the minimum
voltage at the input side which is considered as high, ok. Any voltage above that is
considered as high - that is, no issue with that, ok. So, if we look back this previous one,
so VIH according to the manufacturer for different - considering the typical loading and
all; so the value is considered for the minimum case is 2 volt, ok. So, at the input side when
it is 2 volt and above right it is considered safely as - input is considered as high; that
means, it will give, generate output which is low, ok.
Similarly VIL input - maximum value of the input voltage which is treated as low, any
voltage less than that will be treated as low. So, if you look back at this value. So, 0.8 is
somewhere here, 0.8 is somewhere here, right. So, sorry, 0.8 is somewhere here. So, at
that time the output is somewhere here, ok. So, any voltage less than that is treated as logic
low, ok.
Similarly, VOH, VOL - all these terms we have defined before and these are the
corresponding values that the manufacturer will give you, and from there what we can do
we can arrive at the noise margin-low and noise margin-high as per the definition that we
have discussed in the very first class, and in subsequent classes, and from that we can see
54
for the TTL the values are 0.4 volt and 0.4 volt, ok. This is according to manufacturer’s
datasheet.
NML = VIL – VOL = 0.8 – 0.4 = 0.4V
NMH = VOH – VIH = 2.4 – 2 = 0.4V
In addition you can see the corresponding current values, for these different cases and one
such calculation were we can one such thing that we can see for find out calculation here,
is the case where you can see this is the totem pole output and similar gates have been
connected at the output, ok. So, the IOL all right, now when we talk about this you know
these sign of the current, so any current that is going into is consider positive and going
out off is considered as negative. So, IOH is the current that you can see right which is
which is considered positive. So, let us start with IOL only because in these example IOL is
there. So, IOL when the output is low the current that is being sunk in. So, current being
sunk in IOL is 16 milliampere.
So, that is the maximum current it can sink, ok. So, that is and - this is getting into, that is
why it is positive, all right. So, this is the 16 milliampere and for the load side similar
circuit that is there. So, IIL which is coming out of it, what is the corresponding value
according to the specification given by this? That is minus 1.6, it is because it is coming
out of it, and it is getting into, right.
So, how many such then load gets can be serviced by this? So, this is IOL by IIL, all right.
And the other case happens when this is off and this is on and the current is driven in this
direction and this is in inverse mode. We know that this is going in this direction - inverse
mode – so, that time the current that is at the load side, that is your IIH is of the order of 40
microampere - the current that is going when this transistor is operating in inverse mode
that is the beta IB of T4, ok.
And corresponding IOH which is coming from here that is IOH in that case – right, for
corresponding IIH, ok. So, what is the value? That is given as minus 0.4 milliampere, ok.
So, again it is going out so that is the say that is why the sense is negative sign is negative.
So, how many such gate can be serviced? So, again you take the ratio all right and the
finite will be lowered of these two numbers, and in happened to be case that the way the
55
circuit has been designed by the manufacturer it is 10 in both the cases, and for this
particular gate, the power dissipation is of the order of 10 milli watt.
Fanout = Lower [|IOH/IIH|, [|IOL/IIL|]=10
The other important parameter is the propagation delay. So, propagation delay high low to
high, ok. The value you see 12 nanosecond and 22 nanosecond - it depends on the loading,
ok, more such loads, more such capacitors will be coming in parallel and more time will
be required, ok. And the other reason for which low-to-high is more compared to high-tolow - that we have discussed before - that the time it takes to bring it out of the saturation,
which is more in case of the transistor getting driven into saturations from saturation to cut
off - the charge redistribution that is required. In tP high to low is the case when you have
got the case, which is relatively low, and this is measured under some specific condition,
ok.
(Refer Slide Time: 22:33)
Now, TTL open collector - how does it work? So, in the TTL open collector, the last stage
in the totem pole you do not have any resistance, ok. So, this remains open. So, to make it
work we need to connect an external resistance to it, ok. So, this is the external resistance
through it. So, this is called pull-up resistance also, ok.
Now, by varying this resistance we can vary the amount of current and if you are
connecting say, a light emitting diode over here which requires more current and
56
corresponding resistance values can be decided here - to make it glow. So, that is one good
thing about it.
The other aspect of this open collector configuration is that if you connect two such gates.
So, this is a one gate right, and there is another gate and you are connecting just ANDing
these two outputs. So, together if you just analyze you see that they will give a wired-AND
connection. So, these two another such gates is there right and you just connect it over here
it will give you a wired-AND connection which is also useful in some cases. So, this is
one important thing about open collector configuration.
There is another use of TTL, the thing that we discussed earlier in terms of tri-state, ok.
So, in Tristate; that means, the output is neither able to drive current, nor able to sink
current, ok. So, that is called the tri-stated kind of thing, ok. So, neither high, nor low - it
is kind of electrically isolated. So, when this enable is low logic low - 0 volt or so, what
will happen? In this particular case you see for any of these cases, any of these cases this
particular transistor will be - this current will be drawn in this direction. So, this transistor
will be off, ok. So, this transistor is off. So, at that time this can become high - in earlier,
in normal operation - right, but because of this diode the you know, which clamps the
voltage to 0.7 volt and 0 volt over here which is not sufficient to make both of them on for
which this transistor is also. So, both of them are off. So, in enable is 0, both of them are
off in the totem pole output. Only when it is high, then it serves the normal operation of
an inverter, ok. So, this is the tri stated TTL which is also useful in many circuit.
So, we shall look at - you know TTL NAND gates, you have already seen, alright.
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(Refer Slide Time: 25:30)
So, TTL NOR gate - if you look at the manufacturers specification. So, I have taken from
a Texas instrument say, SN7402 technical document. So, what you will see here? These
two input stages are in parallel and these two phase splitters are in parallel, and the totem
pole part is common. And NAND gate of course, this is a multimeter NAND gate. So, this
is how the TTL NAND gates and NOR gates are prepared, and the operation is known.
And you will see in these cases there is an input diode over here which actually prevents
ringing due to you know transmission line transmission issues - termination issues. What
can happen? When you are taking it from high to say low right, so it may not there may be
a ringing. So, these diodes actually when it go sufficiently low this particular thing. So, it
conducts and it takes away the energy. So, this is another important thing that we need to
know in the as a practical case.
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(Refer Slide Time: 26:33)
And the last topic that I would like to just mention here in today’s class is the use of
Schottky diode in the TTL configuration, ok. Schottky diode you know is a metalsemiconductor junction and it can provide a cut-in voltage in the range of 0.2 to 0.5 volt.
So, this is clamp, this is used between base and collector of a transistor, and this transistor
because of this, this voltage is clamped to say, 0.35 volt if you take - if you manufacture
in that manner and this is your 0.75 volt. So, this is 0.4 volt or so, which prevents it getting
into saturation, so as to say, ok.
So, just stop short of saturation which is useful in the sense that it helps in bringing it out
of the saturation, the time - the switching speed increases. So, that is one important thing
where all the transistor that are supposed to saturate right that are changed using a Schottky
diode, ok. So, this is 74S00, again taken from the data sheet. So, you see this, transistors
are changed by Schottky diode, ok.
In addition, over here what you see, is that earlier there was only a resistance, from this T
4 now there is an active pull-down. So, this helps in taking the charge from this baseemitter junction when it is coming out of saturation, I mean, whatever level it goes into the
saturation. And the other thing over here what you see is a Darlington pair configuration
over here and you do not need a diode over here, because there are two such things. So, it
also helps in providing larger amount of current. So, this configuration over here together
with the Schottky clamped transistors used - as a whole, increases the switching speed,
59
and the switching speed that we are get here is of the order of 3 to 4.5 nano second
depending on the test condition and that is very useful for enhancing the transition speed.
(Refer Slide Time: 29:10)
So, finally to conclude, so what you have seen today? TTL transfer characteristics - 4
distinct zones how it works and its different operating parameters. We have seen that TTL
NAND gate is obtained from multi emitter input, while NOR gate is obtained by parallel
of the input transistors and the phase splitters. Open collector configuration we have seen
that it requires an external pull-up resistance, and it can be also used for wired-AND
configuration. TTL Tristate, we have seen that when it is disabled, none of the output none
output transistors in the totem pole configuration is on. And Schottky TTL, does not allow
the transistor go into the situation. It just stops short of saturation which enhances the
switching speed.
Thank you.
60
Digital Electronic Circuits
Prof. Goutam Saha
Department of E and C Engineering
Indian Institute of Technology, Kharagpur
Lecture - 05
CMOS Logic
Hello everybody, we discus today CMOS Logic. In the last class, we discussed TTL
Transistor Logic based circuits, ok.
(Refer Slide Time: 00:25)
And we’ll cover CMOS logic of course, and it is various configurations like tri-state and
open drain and when it is used together with TTL in a circuit; how to interface, but we
shall begin with a brief discussion on NMOS logic.
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(Refer Slide Time: 00:40)
So, a MOS device you know is a field effect device which offers very high input impedance
because its input is connected to an insulator - oxide layer, but it can be used as a inverter
just like what the transistor based BJT based inverter that we had used before ok, without
the - with the exception of that RB is not required.
So, this is similar to what we had in earlier case RC, but RB is not required because it is it is connected to an insulator - ok, its input impedance is very high- right. And, and this
is an n-channel enhancement mode, the MOSFET that we are using here – alright, nchannel is used for the electron has got higher mobility; enhancement - that means, when
a particular voltage is applied that is called threshold volt, a layer is, n-channel is formed
and as long as the voltage remains more than that, the channel is there and the current
flows and if it is less than the threshold voltage, the channel is not formed and the current
will not flow ok.
So, Vi needs to be greater than threshold voltage or this VGS needs to be greater than the
threshold voltage and at that time, if we increase the – increase, this is your drain, this is
your gate and, this is your source if we keep increasing the drain-to-source voltage right,
the current will increase linearly in the beginning, but after that there is an effect called
pinch-off effect when this VDS is equal to VGS minus VT - ok. At that time, because of the
pinch-off effect - beyond that, VDS is going beyond VGS minus VT, the ID, the current - the
drain current will remain constant.\
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Pinch-off: VDS ≥ VGS - VT
This drain current remaining constant here is termed as saturation which is different from
the saturation region we had discussed in case of bipolar junction transistor where an
equivalent IC versus VCE curve, we had seen. So, in the IC versus VCE curve that we had
seen, in case of bipolar junction transistor, this region was the saturation region there if
you remember - ok.
When the collector-emitter VCE voltage was 0.2 volt or 0.1 volt of that sort, both B-C
junction and B-E junction were in forward bias; however, in this particular case, in this
particular case, this region is called saturation region.
So, this difference is to be noted not to get confused and this region when the VGS is greater
than VT and the current increases with increased value of VDS that is called linear region
or called triode region and we have got two different equations; this is one equation which
is there in the saturation region. So, the saturation region is similar to active region in our
earlier discussion.
Saturation: ID = k(VGS – VT)2
Linear: ID = k[2(VGS – VT)VDS - VDS2]
And this equation we shall use later, keep note - take note of this in CMOS discussion and
this is the equation when it occurs for linear region. And what people have done - they in
the NMOS based logic development, this resistance manufacturing - because now the
resistances are very high. So, this high resistance manufacturing - it takes lot of space. So,
instead of that a NMOS driver based - NMOS transistor based load with gate-source, gate
and drain connected in this manner which offers approximately linear - when this VGS and
VDS are, you know, constant.
So, you can see the - you know the current variation with the voltage is approximately
linear. So, that is given, that is used as - instead of an actual resistor as a load which offers
less amount of space, requires less amount of space. And for the NOR logic and NAND
logic development using NMOS gate, you are having this particular inverter similar to
what we had done in case of a RTL circuit or electrical switch based circuit a - for NOR
63
there will another transistor will come in parallel and for NAND, another transistor will
come in series.
So, this is the standard thing that we had followed the similar thing is done for NMOS
based logic gate development also. But, one issue that we here take note of here, is that
when this transistor is on, T1 is on, the resistors must be sufficiently small compared to
resistance 2, I mean which is resistance offered by the transistor 2; otherwise the output
will not be considered sufficiently low, ok.
So, if it is you know, if both of them are same then what will happen, the output will be
0.5 of a 50 percent of VSS which is not sufficiently low - we want to make it as low as
possible, right. So, this T1 resistance will be sufficiently small compared to resistance
offered by T2 that we take note of - ok.
(Refer Slide Time: 06:34)
Because of which in the NMOS based circuit, we are having an issue that the output where
the capacitor plays a very important role the at the output junction, charging and
discharging of it because the current it the next stage will take is very low of the order of
picoampere or so.
So, this charging of the capacitor by this particular resistance which is relatively high takes
more time than the discharging of it. So, which limits the speed, which brings an element
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of asymmetry. So, from a NMOS based logic inverter circuit, we have moved to CMOS
base circuit where the particular part is replaced by a PMOS, ok.
So, how PMOS works? While in NMOS when we look at the working of the NMOS, so,
basically you are forming a, placing a positive voltage above a threshold voltage which
attracts electrons and the n-channel is formed and the current conducts. In case of PMOS
what will happen, we want to form a channel made of holes, made up of holes.
So, a negative voltage, relatively negative voltage needs to be applied. So, if the source
and substrate of it is connected to a positive supply say 10 volt over here- right; at the
threshold voltage for this PMOS is 2 volt, then 8 volt or less would be required at this side
at the input side, then only the PMOS channel will be formed and it will conduct - right.
So, when it is at low which is of course, much, much less than this 8 volt. So, channel is
formed, so PMOS is on right and when it is at low then of course, it is less than 2 volts, so
the NMOS will be off and the other case when it is 10 volt – right; so, when it is 10 volt,
so, this is also, this is 10 volt this is 10 volt. So, it is not sufficiently negative, this particular
junction - right. So, no p-channel is formed, but it is sufficiently - this particular is
sufficiently positive above the threshold voltage, so n-channel will be formed.
So, at any given point of time we have got either a PMOS or NMOS on and only during in a transition or the switching, both of them can become on, ok. So, because of which and
this PMOS on - the PMOS is made in such a manner that the though the mobility of hole
is less - that the output resistance is symmetrical for both, of both the cases about of the
order of say 1 kilo ohm and the charging and discharging is faster compared to what we
had seen before. The other important thing here - there is the, you know, when it is either
0 or 1, no power consumption is there along this path. Only during switching some power
you know, consumption will be there and, also for during switching - when this output
capacitor is getting charged or discharged - getting discharged. So, during that process
some power consumption will be there, but during static condition - unlike in this particular
case when it was on right, when it was on - ok. So, there was a current you know, flowing
so that situation does not arise here and input resistance of such a CMOS is very high 1- 0
to the power, of the order, 12 ohm and capacitance is of the order of 5 picofarad, this
capacitance which will come in a form of a shunt.
65
(Refer Slide Time: 10:42)
With this, we go to CMOS transfer characteristics and if we look at the CMOS transfer
characteristics, this is the Vi versus Vo plot and it has got 5 distinct zones. So, the first zone
that we look at is the case when the input voltage is less than the threshold voltage of the
NMOS, ok. So, when the input voltage is less than the threshold voltage of the NMOS.
So, what is happening at that time? The T1 the NMOS is off and at that time of course,
this is sufficiently small right.
•
•
•
•
Vi ≤ VT(n) : T1 OFF, T2 ON, Vo< VSS
Vi ≥ VSS - VT(p) : T2 OFF, T1 ON, Vo = 0V
T1 saturated: VDS1 ≥ VGS1 - VT(n)
Vi ≤ 2V
Vi ≥ 8V
i.e. VT(n) ≤ Vi ≤ Vo + VT(n)
T2 saturated: VSD2 ≥ VSG2 - VT(p) i.e. Vo - VT(p) ≤ Vi ≤ VSS - VT(p)
•
Vo≥ Vi - 2
Vo≤ Vi + 2
Simultaneous saturation at unique Vi(sat.) i.e. Vi(sat.) = 5V for kp = kn
So, if it is 0 volt or 2 volts. So, 10 minus 0 volt or 2 volt it is sufficiently small and it was
channel is positive channel is formed. So, for which T2 remains on - ok. So, this is what
you see over here. Next, the other case when the input voltage is more than that 8 volt that
we had talked about, more than 8 volt; that means, the p-channel - it does not get then
properly formed - it is below the threshold voltage. So, when Vi is greater than 8 volt - ok.
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So, Vi is greater than 8 volt (Slide correction: Vi ≥ VSS - VT(p) ) - what is happening? T2 is
off, but at that time definitely the n-channel has got the voltage which is more than the
threshold voltage. So, for which T1 will remain on. So, these are the two cases, two
extreme cases we have seen and you have already noted earlier, in case of that NMOS
logic inverter discussion, that the pinch-off occurs when VDS is equal to VGS minus VT we
remember that for the NMOS.
So, whenever VDS is greater than VGS minus VT, all right - that will be the saturation region
then. So, this particular case, the when you map to this - the corresponding voltages right.
So, this is happening when the Vo – right, Vo t is your VDS and this VGS is your Vi and 2
volt is your - the threshold voltage that we have considered for the NMOS also for the
PMOS.
So, when this Vo is greater than Vi minus 2, the saturation for T1 occurs - ok. So, Vo is
equal to Vi minus 2 is this line and Vo is greater than Vi minus 2 is this zone - ok. So, in
this zone, in this zone, what we see that T1 is in saturation, T1 is in saturation and if we
look at the corresponding thing for T2 when T2 will remain in saturation, just similar thing,
but applied to PMOS. So, Vo less than Vi plus 2 - when it will be remaining in saturation,
so this is the other case not sorry not of course, up to the you know this the threshold
voltage up to this point. So, this will be the case when the T2 will remain in saturation. So,
both T1 and T1, T2 remain in saturation in this zone and the rest of the zones are defined
in this manner T1 in saturation, but T2 will not be in saturation; T2 in saturation, but T1
in not in saturation ok, this is the other two.
So, when T1 and T2 both are in saturation and we apply the equation that we have shown
before. So, we get a unique solution for the voltage when both of them are in saturation
and if you know - use these particular values, so we get that for 5 volt for the transistor
parameters of both of them called kp and kn will be in this being same - which signifies,
which implies that there is an abrupt jump at this particular voltage 5 volt, in the inverter
characteristics. In actual practice, it will be little bit tapered - it will not be an abrupt jump
like this.
So, this is how the CMOS transfer characteristics - it works and from that we can define
VIL, VOH, - right; VOL, VIH all those things can be defined; for example, VIL in this
particular case definitely, we can consider up to say 2 volt or even little bit more than that
67
ok. So, similarly the VIH is you can see that is relatively higher, which is an important thing
to be noted. So, VIH is more than 6 volt in this particular case that is that would be of you
know for us to you know certainly consider - ok.
So, this is the kind of thing which is happening for this particular values that we have
considered - right and accordingly, the manufacturers will tell you for different supply
voltages, you remember the CMOS works over a very large range of supply voltages. From
3 to 18 volt compared to near about 5 volt for TTL based logic gates.
(Refer Slide Time: 16:11)
So, one particular example for a 5 volt supply case is the - different kind of parameters
that you get. So, as we said the supply voltage is say, 5 volt. Then, corresponding VIH is
3.5 volt - 3.5 volt that is what is considered, if it is 10 volt you know almost equivalent to
that is 7 volt, I mean, that region. So, 8 volt is the case when the other region that we are
entering into, the fifth region that we entered and VIL is 1.5 volt that has been considered,
VSS is 5 volt VOH is again almost equal to 5 volt - ok.
When this is for VT is equal to 1.5 volt and if we go back -so, this is your, the corresponding
VOH the 10 volt - it is the almost 4.99 volt it has been considered and corresponding VT is
1.5 volt. So, these are the different things if you can compare from the previous diagram
for a different kind of VSS and VT – ok, so - which is coming from the manufacturers a
specification and the other important thing to be noted here are the current level. The
current levels are very small. So, the input current is 10 pico ampere and a minus 10 pico
68
ampere. So, basically the two cases when it is high or low and the corresponding meaning
we all understand that it is going into is positive and going away is negative and similarly
the IOH and IOL - the amount of current it can deliver or it can sink.
So, these are the two important parameters for us to take note of. And, accordingly the
noise margins are calculated by the standard formula and for another important parameter
is the speed, that is the propagation delay for output going from high to low or low to high
which we can see is relatively higher compared to TTL and of course, if the supply voltage
increases the speed becomes faster - ok.
So, that is another important point that we take note of. Fanout is not limited by the current
it can deliver which we saw in case of TTL, but amount of propagation delay it can handle.
Static power consumption is very low this is another important characteristics and dynamic
power you know consumption is one important consideration here which is one part is
there that half C V-square, right - during charging and discharging the similar power
consumption is there the same half C V-square.
PD (dynamic) (charging / disch. of CL) = CLVSS2f
So, together it is C V-square that you can see and as many times it is getting charged in,
charged and discharged in 1 second - given by the frequency of operation - right. So,
together you get the dynamic power consumption because of the output capacitor is getting
charged or discharged and this power that is getting you know consumed during the
transition period that brief time that you have seen when both of them are active. So, that
being very abrupt and so we can neglect that. So, roughly it is guided by this power that
you see over here and with the higher high frequency it becomes - it comes in the range of
milli watt and becomes compatible to TTL that is we take note of here, fine.
69
(Refer Slide Time: 20:16)
So, we go to - this is one beautiful thing about this MOS based gates - ok. So, when we
look at development of NAND gate or NOR gate or you know combinatorial logic - we
would not read need resistive elements and other things that is - that was there in a BJT
based you know circuit development.
So, in NAND gate development CMOS we need for every NMOS another corresponding
PMOS to get the advantage of the CMOS circuitry. So, NAND gate development, we have
two NMOS in series and the corresponding PMOSs are in parallel - ok. So, any one of
them is low, any of the any one of them is low what is happening 0 so VA is 0.
So, this is in series. So, this path will not be there this path is block. So, this is blocked by
this one right when say this is 0 this is 0, but at that time the corresponding VB. So, this is
0 means this is now, this the PMOS on is on right. So, the output is getting the VSS over
here through this - ok. So, the output will be high is it clear so, any one of them being 0.
So, there is a parallel path here at the output providing the voltage and the current, the
power supply and in the series any one of them is blocking it - one of them is blocking it
ok. So, that is how what happens so, when it is both of them are 0 and when both of them
are 1. So, this is 1 and this is 1 high.
So, this is on, this is on right and this is off as well as this off it is how the PMOS will
work. So, this is connected to the available to the ground is available over here ok. So,
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logic low voltage is available - is it clear? So, that is how the NAND works. NOR is similar
- so, these two will be now in parallel and the PMOS will be in series – right; and extending
it further we can develop many kind of combinatorial logic by different combination of
this.
So, this is also something by which people are, you know, which is - drawing becomes a
bit easier. So, this presence of bubble over here actually signifies PMOS. So, this is a
symbol of a PMOS in that fashion and this is the symbol of an NMOS absence of this ok.
So, these two are in parallel and corresponding these two are in series, this is in series with
the other one.
So, the whole of it the corresponding - what corresponds to B and C, what corresponds to
B and C in PMOS – right; so, that will be in parallel with what is there as A over here. So,
that is how the combinations are formed. And, this particular combination – right; so, this
is B plus C ANDed with A right and there is that inverter.
So, that is how you get the logic and many such combinatorial logic can be developed by
simple interconnection of this which is much easier compared to what you had seen in case
of other logic family that we had discussed - ok.
(Refer Slide Time: 24:20)
.
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Now, if we take this a bit further. So, in the left hand side what you see is a circuit – right,
where the NMOS an NMOS over here is in series with 2 PMOS that you see, they are not
in parallel.
If they are in parallel, then they would have been a NAND logic forming, the other thing
that you see here at this input between them there is an inverter present - ok. So, what is it
what does it do actually? So, in the inverter, this input EN is 1 – ok; so, this NMOS is on
and this is inverter means this is low - ok, if this is high this is low, this low means this
PMOS is also on at that time - ok.
So, the output will at that time will totally depend on whatever is the input - ok. So, when
EN is equal to high, so this is on this is also on and output follows the input if there is an
inverter logic - so it will be the inversion of it. But when input EN is low, what is
happening? This is you know, off and this is also off because it is at that time this is high
- for a PMOS makes it off, right. So, both of them are off.
So, irrespective of the presence of A, the output is neither high nor low, neither you can
drive that is not nor it can sink that is not possible ok. So, this is the condition we say is
tri-stated which is neither high nor low and it offers high impedance, it is electrically
offering very high impedance.
So, similar thing can occur if we have a circuit like this the previous stage is enable bar
plus A; that means, enable complimented OR A and the NMOS is given by enable ANDed
with A we will see when enable is 0 - ok, then this is 0, right and this is 1. So, the output
will be this will be high and this will be low which will ensure that both of them are off.
So, output is electrically isolated offering high impedance and only when enable is high –
right, it is A which decides the output, A could be many other things from the previous
stages.
So, these are the tri-stated configuration using CMOS and this is open-drain. So, open
drain - how it works - similar to open collector. So, only thing, only issue is that this PMOS
now when is replaced by the external resistance, the pull-up resistance there is a protective
diode which is used in this particular case. In CMOS circuits, this protective diodes are
there in input stages as well to avoid surges because the static voltage is a very problematic
thing in CMOS based circuit. And, this one - another stage, another stage is over here
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which is when it is connected - another such say wired-AND, you know another such
circuit which is you know connected over here - ok.
So, then the logic together is providing wired-AND similar to open collector. So, this is
what we take note of from this particular discussion.
(Refer Slide Time: 28:10)
Finally, at last part of our discussion - CMOS circuits are there, TTL circuits are there,
could be cases when for less power consumption more packing density we are preferring
say, CMOS right and higher speed and associated benefits we are thinking of using TTL
and then we want to in connect these two parts for getting both the benefits. So, then we
need CMOS and TTL interface - right. And, to get a CMOS and TTL interface, when both
of them are using say 5 volt supply, the corresponding parameters for input VIH, VIL, IOH
and all.
So, this is what I have taken from the transfer characteristics that we just discussed - right
and TTL we have - I have taken from the earlier lecture we had. So, these are the two
columns where the different parameters have been put forward.
So, when TTL drives to CMOS. So, TTL drives CMOS, when you compare you find that
no issue with the current level because the CMOS because very less current of the order
of pico ampere and voltage levels are also fine. Except only one case where the VOH(TTL)
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right - VOH(TTL) which is of the order of say 2.6 volt in our earlier discussion we have seen
from the transfer characteristics with loading it can go up to say 2.4 volt or so.
This is your VOH that is the output high and, but the input voltage that is required by CMOS
for the input to be considered high is 3.5 volt for 5 volt cases - right and 10 volt cases, we
have seen above 7.5 - 8 in that range ok. So, we are comparing because both need to have
being you know, same power supply 5 volt for the compatibility. So, 5 volt is what we are
considering here.
So, this is higher right. So, that is what is only the problem otherwise there is no issue in
connecting CMOS load to TTL and for that what people use how to - how it is overcome!
It is overcome by having this is the TTL stage, this is output stage ok. So, having a separate
pull-up resistance, external pull-up resistance that you see over here – right, which actually
increases this voltage level more than what it was in - what you can get in normal TTL
cases - ok.
So, the voltage will be VCC minus whatever IR drop, voltage drop is occurring here which
will be more than the required 3.5 volt and this voltage - the resistance it has been seen to
get voltage higher than this 3.5 volt is in the order of this 2 to 6 kilo ohm, this kind of
resistance would do - ok.
So, this is what is required and when CMOS drives TTL right. So, CMOS is the say TTL
is the load side. So, again if you compare the voltage levels and all we will find that there
is no issues with the voltage levels. So, the issue is there, the current it can sink - ok. So,
the current it can sink in the case IOL CMOS.
So, this is the current it can sink 0.4 - ok. So, it is sinking. So, that is why it is told positive
and IIL when input is at logic load right the current it is coming out of the input transistor
of the CMOS is of - this minus 1.6 milli ampere. So, this is much more - right. So, if you
just connect it. So, this is going to give problem.
So, to overcome that, what is used is a CMOS buffer only. After the CMOS gate, another
CMOS gate will be put with appropriate dimensions - larger area or so, which will enable
more current to get sunk - ok. So, by which in some standard IC, is made by manufacturersso, Texas Instruments and others, so, it has been seen that the current that can be sunk is
of the order of 4 milli ampere which can take 2 standard TTL or so and if it is a low
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powered TTL more such gates can be connected. So, this is how the interface has to take
place - issues I have mentioned and it the issues are coming from comparing the transistor
parameters - for the gate parameters for these two cases.
(Refer Slide Time: 33:39)
So, references are mostly taken from the first one and some technical documents.
(Refer Slide Time: 33:44)
And to conclude what we have seen that NMOS inverters can be used, but NMOS load
resistance is preferred for less space and CMOS inverters are useful in the sense that the
charging and discharging are quicker and also it takes the static power - there is no static
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power consumption and if you look at the transfer characteristics, there are 5 zones
depending on operating condition of the two transistors whether they are in conducting or
non-conducting, if it is conducting whether it is a linear region or saturation region.
The fanout is not limited by amount of current, but the propagation delay - amount of
propagation delay we can tolerate and - because more such things connected, more such
capacitances will come in parallel. Dynamic power dissipation is the important
consideration and it becomes a bit TTL comparable at higher frequency and it can have
tristate and open drain configuration and TTL and CMOS gates are incompatible on few
counts, not all the counts and that can be appropriately taken care of when TTL and CMOS
gates are to be interfaced with one another.
So, with this we end the week 1, the first module because of the time flag and other things
certain things we have touched in a manner for which greater discussion and the references
can be referred to or supplementary materials can be also considered.
Thank you.
76
Digital Electronic Circuits
Prof. Goutam Saha
Department of E and EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 06
Basic Gates and Their Representations
Hello everybody, we enter week 2 of this course.
(Refer Slide Time: 00:19)
In the 1st lecture of this week - we shall have a quick recap of what we discussed in week
1, then we shall discuss the various representations of basic logic gates. We shall also
discuss universality of NOR and NAND gates, its usefulness and also usefulness of ANDOR-Invert gate.
77
(Refer Slide Time: 00:41)
If we recollect in brief we had a look at, in week 1, of following concepts. Manipulation
of digital signal is fundamental to digital technology; switching and logic operations are
key to - key at hardware level implementation of digital technology. Transistor based
circuits are important for realization of this switching and logic operations, because we get
inverting operation through transistors.
TTL and CMOS based logic gates have wide applications as building blocks of digital
electronic circuits. And you also remember that there are practical issues like propagation
delay, noise margin, fan out, power dissipation so on and so forth which need consideration
when we develop digital circuits are complex digital building blocks.
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(Refer Slide Time: 01:49)
To start with, we recollect that we had discussed inverter - through CMOS technology,
through TTL technology, and we have given a circuit of the inverter using TTL at the right
hand side which you can connect to. But, when we use these as a building block we shall
not present either CMOS circuit or TTL circuit everywhere, because that will make it very,
very complex, I mean, the whole circuit will look very complex.
Instead, in place of a inverter - depending on whether it is a CMOS technology or a TTL
technology or any other technology, we shall put one symbol as a building block. We’ll
know that inside, depending on the logic family that is used - one circuit or the other circuit
will be there, ok. And that is represented through a symbol the symbol over here you see,
is this one.
So, this is the symbol that we shall be using for NOT gate. We are all - we may be already
familiar with this, but to formalize this discussion we put it over here. So, this is one way
of representing inverting operation, the other way of representing inverting operation is
through Boolean expression. So, this is Y is equal to A compliment which represents
inverting operation and it is represented through A bar or A prime both are equivalent.
𝑌𝑌 = 𝐴𝐴̅
or
𝑌𝑌 = 𝐴𝐴′
So, you shall use interchangeably this two notations. This can be represented through the
truth table also. This is another representation. So, if you see a truth table which is like this
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- that is a low connected is associated with high - a high associated with low, 0 associated
with, I mean at the input, is associated with 1 at the output - and 1 is associated - 1 at the
input is associated with 0 at the output; we know that we are talking about inverting
operation. That is the inverter circuit - a digital circuit; there is an inverting operation that
is involved.
The 4th representation that we see is through timing diagram. And for timing diagram, we
just look at one - before looking at the timing diagram we look at one IC which we people
use in the lab; lab - we use TTL family because of issues with CMOS circuits the lot of
protections are required. So, mostly we will be using TTL circuits in the lab TTL ICs. So,
IC 7404 has got 6 NOT gates and these 6 NOT gates are connected - the input and output
pins are connected like this.
So, there is a VCC - and there is a ground which is required you know as power supply over
here you see in this power supply, this power supply. So, this power supply is - are
associated over here and there are 6 such NOT gates inside it, ok. And we just - if we give
at the input of pin 1 - a signal like which is low and high, you know 0 volt 5 volt, it is just
you know there are rectangular signal like this - then what will happen at the output?
Whenever, there is a low there will be corresponding high at the output. So, this is pin 1
and pin 2 that you see and that way it will continue, right. So, depending on how long this
input signal is changed you will see - you will see a corresponding timing diagram at the
output. Now, all these things that we have, you know, we have discussed so far for these
representations - in each of these, it appears - it appears that the output is instantaneous.
Like - if you look at the Boolean expression or the truth table; you have given input,
immediately you are getting output - that is the kind of, you know, understanding one may
have from this kind of representation. But, if you have timing diagram and if you expand
the time scale, then you can have the propagation delay included in the timing diagram ok. So, depending on the time scale - right; if it is in the order of second or millisecond
you might not be able to visualize it, if it is in the order of microsecond or nanosecond,
then you can see a nanosecond order of propagation delay involved.
So, that way the propagation delay based representations are useful, and this propagation
- we shall discuss and use later in some other discussion.
80
(Refer Slide Time: 06:29)
Now, we look at representation of AND gate - ok. So, AND gate again, if you look at the
circuit diagram, will be having a circuit in the TTL space which is - which looks something
like this - ok. And remember when we talk about design you know, circuit of AND gate at circuit level it is not a NAND gate then again a NOT gate is put.
So, in a NAND gate circuit itself a inverting transistor block can be put with some associate
additional circuitry by which you can get NAND and NOT together - AND operation. So,
that is the Texas Instrument, you know, the data sheet - from that the circuit has been
shown. This is a practical circuit which is in use for IC 7408. IC 7408 - that uses this
internal circuitry.
Coming to the – again, when we talk about AND gate and its use then, we’ll not be using
the whole circuitry in various representations; rather this block. So, a 2 input AND gate the block diagram, the symbol representation is like this and 3 input - it is like this. So, for
2 input, how this input and output in the Boolean representation would look like? It would
look like this - Y is equal to A AND B and what about – you see, this A and B you can
write in another manner B and A with, I mean, whether the operator - if you just change
the position, it does not make a difference.
𝑌𝑌 = 𝐴𝐴. 𝐵𝐵 = 𝐵𝐵. 𝐴𝐴
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So, this is nothing but what is known as commutative, I mean, the operation is
commutative. That means, the operands - if they change their order in the operation there
is no change in the output. So, this AND operation is commutative - ok. So, this is another
representation. So, IC 7408 - this is the structure in which, I mean, this is the arrangement
in which 4 AND gates are there - VCC, ground and this 1 2 - is the input and 3 is the output.
And if you send a signal, rectangular signal like this, in which the arrangement is such
that there are these possibilities - 0 0 then this is 0, and this is 1, this is 1 and this is 0 and
this is 1 and this is 1 - ok. Then what we expect for AND logic when both the inputs are 1
- the output will be high. So, that is what you see for each of these case this is 0, 0, 0, this
is 1.
So, if you look at - have a look at some such timing diagram, you can understand the circuit
involved in between. These 2 inputs and the corresponding output is nothing but an AND
circuit or, AND logic is involved -ok. So, it can be represented through truth table also, to
you know the way we had done - there will be you know, 2 inputs and there will be 1
output and when both the inputs are 1 corresponding output in the truth table will be 1 and
for rest of the cases it will be 0 - ok.
Now, what happens in this case when - in the case of 3 input AND gate we have, you
know, similar such truth table, the kind of truth table that you can expect is like this - so,
3 input so, there are 8 different possibilities, 2 to the power 3 - 8 different possibilities of
the input arrangement. And for each of these cases, except when all the inputs are 1, output
is 0 - right.
So, that is what you see over here. So, that is the operation and Y is equal to ABC all right
and one important thing over here if you first AND B, C - right which will generate a
output 1 when both B and C are 1 and, then this output you AND with A – right, then the
output will be 1 when A is also 1 - so, this is the case. So, BC is 1 just if you think of this
is B and this is C, this output is fed to another AND gate. So, BC is 1 here as well as here
alright - these two cases, but when A is 0 right, output is 0 because it is again getting
ANDed and when A is 1 output is 1.
𝑌𝑌 = 𝐴𝐴. 𝐵𝐵. 𝐶𝐶 = 𝐴𝐴. (𝐵𝐵. 𝐶𝐶 ) = (𝐴𝐴. 𝐵𝐵). 𝐶𝐶
82
So, if you group BC if you AND them together - all right, and then AND with A the output
remain same as that of Y is equal to ABC. And similarly, if you group A and B together
and then you AND it with C; that means, A AND B then this is ANDed with C – right, the
result remains the same - the result remains the same. So, whether this grouping or
association is done this way or the other way, result remains the same so, AND operation
is associative.
(Refer Slide Time: 12:13)
Now, we look at OR operation. So, OR operation again, the circuit if you look at the circuit
level - the circuit will be this is IC 7432, that inside circuitry that is there again you will
see that it is not NOR gate which we discussed earlier and, NOT gate which is put in
succession or in cascade rather; within - the NOR structure itself, one inverting transistor
is produced with associated circuitry with which you get OR operation - ok.
That reduces the transistor count-ok. So, again the whole circuitry we shall not be using
for our subsequent discussions or developing more complex digital circuits; we shall be
using symbols. So, this 2 input OR gate symbol is like this where A and B the inputs that
you see over here - if you just interchange the order or the operation the way you had done
for AND operation, there is no change in the output -ok.
𝑌𝑌 = 𝐴𝐴 + 𝐵𝐵 = 𝐵𝐵 + 𝐴𝐴
83
So, that is why this OR operation is commutative - right, and if you look at other
representations like timing diagram - so, for that if we use the IC 7432 - IC 7432 is again
a TTL IC which has got 4 OR gates inside it and this 1, 2 is the input and 3 is the output
and similarly, if we look at 4 possible combinations at the input the way the signal is you
know, presented to the input pins - so, you have got this 0 0 over here 0 1 over here 1 0
over here and 1 1 over here.
So, for OR logic, this is 0; and for you will see at the output of the pin, if you just look at
the wave form - all right, or the signal you will see that the output is 1 when any of the
input, is 1 that is what OR logic is. Again I have noted that before - that if the time scale
is expanded which - by which you can visualize nanosecond order you know, time indices
- then you can see the propagation delay involved in this timing diagram based
representation and of course, there is a truth table based representation - where for B and
C for A - and pin 1 and 2 if they are, any of them is 1 in the corresponding output in the
truth table will be 1 and when both of them are 0 the output will be 0.
Now, similar to AND gate we can have multiple input OR gate also - multiple input OR
gate for which we is just show an example of 3 input OR gate. So, this is the 3 input OR
gate and the corresponding logic diagram is any of the input 1 the output will be 1 - any of
the input will be 1 output will be 1 that is what you see in this truth table right. And similar
to AND OR is also associative; that means, whether you group B and C first you do B and
C ORing first and then you OR the output of this B and C with A. Whatever result you get
if you OR A and B and then its output you OR with C, the result will be the same I mean,
the what I had seen - what we discussed in case of AND gate - ok. So, similar thing is also
applicable over here. So, whatever is this – the same thing, instead of if you have got A
and B and then you are - then you are ORing with C, the results remain the same so, this
is associative.
𝑌𝑌 = 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 = 𝐴𝐴 + (𝐵𝐵 + 𝐶𝐶 ) = (𝐴𝐴 + 𝐵𝐵) + 𝐶𝐶
84
(Refer Slide Time: 16:23)
Now, we come to NOR gate. So, corresponding IC is 7402 in the TTL family. NOR gate
circuit - we have already seen before in earlier - previous week and for that we are using
the symbol the one that you see over here - this symbol, ok. This symbol we are not using
a OR and then a NOT gate rather, we are putting this bubble over here. So, this bubble this bubble whenever in relation to logic operation is present, you have to - you can
consider that there is an inversion associated with that bubble, ok - so, put together it looks
more compact.
So, this is your NOR gate and the NOR gate truth table we know, it is just opposite of OR
right, opposite - any of the input was 1 for OR, output was 1. Here, any of the input 1,
output will be then 0 - all right. And when both the inputs are 0, the output will be 1 ok.
So, this is what you see for the NOR gate. So, I have not drawn timing diagram
representation of this - so, similar thing can be drawn for the way we have done for possible
combinations, and corresponding output can be drawn - where both of them 0, the output
will be 1 - ok
And note: in 7402, it is this NOR gate IC - the 2, 3 is input and 1 is output unlike the
previous cases 1 2 was input and 3 was the output for AND gate and OR gate that we have
seen before - all right. So, this is something for practical purposes you need to take note
of. And Boolean expression we just use this is OR and then a compliment or a bar that
85
represents the NOR operation. So, this is the NOR operation in the Boolean expression of
it.
Now, one thing is interesting over here is that whatever NOR operation you have seen that
kind of truth table that you have got - if you have the same inputs complemented and then
AND it - alright, we get an equivalent representation. So, let us consider this A and B this
is AND operation - all right. So, any of the input is 1. So, this is 1 then this is 0. So, that
will make the output 0 - A is 1, that means, output is 0 right because for the AND gate 0
is the forcing input. So, 0 means output will be 0. So, instead of that, if B is 1, this output
will be 0 which will force the Y to be 0.
Only when both of them are 0 so, this is 1 and this is 1, this output is 1. So, this is this case
- this is nothing, but NOR operation, right. So, we can write this A plus B prime as A prime
AND B prime as well – ok. And, we can see that this is also commutative, the way we
have seen. And, extending this one for more number of variables, ok - so, in addition to A
B, if we have got say C D and all then you can extend the same thing the way you have
done for 2 variable cases and we arrive at De Morgan’s theorem which is saying - which
is represented in this manner –ok, this is clear.
��������
𝑌𝑌 = 𝐴𝐴
+ 𝐵𝐵 = 𝐴𝐴̅. 𝐵𝐵�
𝑌𝑌 = �������������������
𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + ⋯ = 𝐴𝐴̅. 𝐵𝐵�. 𝐶𝐶̅ …
86
(Refer Slide Time: 19:59)
Now, we look at NAND operation ok. So, NAND operation a similar again - the way we
had discussed NOR we are not having a 2 different you know symbols that is AND and
NOT a not put together rather, we are putting one single logic gate with bubble means
AND then there is an inversion associated, ok.
And the corresponding truth table is - output is 1 when any of the input is 0. Any of the
input is 0 for AND, output is 0. So, in this case any of the input is 0 output is 1. Only when
both the inputs are 1, the output will be 0 and the corresponding IC that we use in the TTL
family, is 7400. So, 1, 2 is the input and 3 is the output. So, 4 such these gates are there
inside the IC and you can have a corresponding timing diagram, ok.
And for NAND gate, what we had seen in case of NOR gate, a similar thing occurs over
here. While the NAND representation this A, B - this is the Boolean representation
complemented that is what is the NAND operation over here. The same thing we can
obtain where the inputs are complemented and then ORed.
𝑌𝑌 = �����
𝐴𝐴. 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵�
𝑌𝑌 = ������������
𝐴𝐴. 𝐵𝐵. 𝐶𝐶. … = 𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + ⋯
87
So, A bar plus B bar - how is it done. So, we just - you consider any of the input as 0, this
is symmetric so, it will do. So, then this output is 1. For OR gate, 1 is the forcing input.
So, if the OR gate input is 1 the output will be 1 – right. So, that is what is happening over
here and if you extend it to more number of variables like A, B, C over here – right, then
the corresponding expanded version in this form will be A bar plus B bar plus C bar - all
right, and so on and so forth.
So, that is giving you De Morgan’s second theorem which is also very, very useful which
is which we shall discuss more later on - ok.
(Refer Slide Time: 22:03)
Now, universality of NOR and NAND gate - this is something interesting, this is useful in
the sense if you have only one, if you think of only one variety of, you know, gate by
which you would like to get many different logic operations or Boolean expression,
realization of that - then you have to pick up either of NOR or NAND, because they can
be converted to any other logic operation by different combinations of themselves.
That is the good thing about it. So, you can have only one variety of it one kind of
fabrication process which is useful – otherwise, for AND gate and OR gate to different
variety - there are different kind of circuitry that we have seen before. So, NAND you just
having only one kind of circuitry and how we can achieve it - so, we just give some
examples of basic, Boolean operations.
88
So, from NOR gate if you want to get a - if you want to get a NOT operation – right, so,
you just need to short both the inputs and then the corresponding output will be the invert
of this, I mean, if you remember the NOR logic. So, this is A, B and Y; so when 0 0, 0 1,
1 1 and sorry, 1 0 and 1 1 - ok.
So, NOR logic - any of the input is 1 output is 0 - right and when both the input are 0,
output is 1 right. So, if you just short both of them A and B - so, common thing, common
one - then what is happening at that time? So, either 0 0 case is there, or 1 1 case is there.
When 0 0 is there, output is 1 and 1 1 - output is 0, just opposite of it - right. The other
thing for NOR gate we know, 0 is the non-forcing input - right. So, if you have a NOR
gate right which is - you connect to 0 and this you connect to A, how the output will be
realized you know, behaving - right. So, B is 0 so, this is the case and, this is the case these are the two cases - right. And at that time if A is 0, output is 1; if A is 1 output is 0.
So, that is also giving you an inversion. Is not it? Alright.
So, that is the two ways you can get NOT operation - NOT operation from a NOR gate, 2input NOR gate. And, how you can get OR operation? So, NOR and followed by - NOR
followed by NOT you get OR operation all right, just inversion of - so this was A plus B
bar. So, this is A plus B bar and again another bar. So, which we will get A plus B – clear.
And how you get AND operation?
(Refer Slide Time: 25:29)
89
Earlier, we have seen Y is equal to A plus B bar, is A bar B bar - right. So, at the input if
you send complemented A and complemented B, then you get A AND B. So, that is how
we are getting AND operation over here - clear.
(Refer Slide Time: 25:59)
So, similar thing would happen in case of NAND gate also - you can get any other
operation like AND, like inversion. For inversion, in this case right, what is the other - so,
this is one option.
(Refer Slide Time: 26:11)
90
This is one option we have already noted over here - right, the other option is non forcing
input for a NAND gate is 1 - right. So, if you give this as A and this is the corresponding
output will be.
So, this is - if this is 0, 0 1 output will be 1 - right. So, if it is 1, 1 1 output will be 0 - right.
So, you get the inversion for some such arrangement as well - all right. And, AND
operation is NAND followed by NOT. And OR operation - again we follow the De
Morgan’s theorem - alright Y is equal to A B prime is equal to A prime plus B prime. So,
if you send primed version of it, complemented version of it, you get OR operation - clear.
(Refer Slide Time: 27:07)
The last topic that we discuss in this lecture is the usefulness of AND-OR-Invert gate ok. So, when we realize Boolean expression - we shall discuss it in future classes - so,
there could be many different cases where you are having relationship like AB plus CD
plus EF inverted kind of thing. So, basically there is a AND operation involved this is
AND, AND, AND then this is OR and then finally an inversion is taking place - ok.
So, this is called AND-OR-Invert. So, if you want to realize this separately – right, the
number of transistors, you know, involved will be you know - as it is required for each of
these realizations. But, within the logic family there are you know, gates or the
arrangements can be made by which this AND-OR-Invert operation can be done with
lesser number of transistors.
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So, for CMOS, it is very easy. You can see that - this is an example of 2-1 AND-OR-Invert
gate. So, these are the 2 inputs - these are the 2 inputs over here and so that - this is the 2
and this is the corresponding 1 input. So, these 2 are ANDed - B and C are ANDed, and
this is OR with A and corresponding these are the NMOS side and, these are the
corresponding PMOS side where B and C are in parallel. These are in series here - NMOS
side, it is series, PMOS side - it is in parallel; and A will be in this side in parallel, because
of the OR operation and in this side - this is in series; that we already know how we get
CMOS circuits – so, very convenient way of getting it and we can get OR-AND-Invert
gate also in similar manner in a CMOS circuitry - ok.
TTL family also has similar such gates AND-OR-Inver gates. So, one example is 7451
which is dual; that means, two such gates are there 1 and another 2 input; that means these
are the 2 inputs that you see 2 inputs 2 inputs. 2 wide means 2 such blocks are there, right
- by which you can get AND-OR-Invert gates and this is the corresponding circuitry in the
TTL family from the TTL data sheet.
And you can have you know expanders also - arrangement by which more such gates can
be added and more complex circuits can be arrived at. This saves in transistor count, ok.
So, these are some basic gates which are useful in realization – in practical circuits or in
your laboratory experiments which you will be undertaking.
(Refer Slide Time: 30:07)
(Refer Slide Time: 30:09)
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And so to conclude, the logic circuit operation can be represented by symbol, Boolean
expression, truth table, timing diagram - we have seen that. AND, OR, NAND, NOR
operations are commutative, but AND, OR operations are associative - the corresponding
NAND, NOR are not associative which we shall discuss more, later on.
NOR operation is equivalent to ANDing of complemented inputs - De Morgan’s theorem
we have seen one version, NAND operation is equivalent to ORing of complemented
inputs - another De Morgan’s theorem. Any other logic gate or operation can be obtained
using only NAND or NOR gates which is universality of these two gates. And, AND-ORInvert gate takes less number of transistors in comparison to implementing them
separately, which is useful in many cases - ok.
Thank you.
93
Digital Electronic Circuits.
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 07
Fundamentals of Boolean Algebra
Hello everybody, in the last class, we had a look at basic logic gates and we had seen
representations of those logic gates or circuitry - using Boolean algebra. So, we shall look
more into the Fundamentals of the Boolean Algebra in this particular class.
(Refer Slide Time: 00:35)
The concepts that we shall cover are Huntington postulates - that are the basics of this
particular Boolean algebra - basic theorems that are derived from it and the concept of
duality. We shall show some examples of these derivations of theorems from the postulates
and also, we shall discuss its difference with ordinary algebra.
94
(Refer Slide Time: 01:01)
So, the - in the previous classes we are looking at two variable examples two variable logic
operations - right. And, if we look at the two variable representation - so, with two
variables, we can have two variable - we can have 2 to the power 2, that is 4 possible
arrangements in the this truth table. So, this is 0 0, 0 1, 1 0 and 1 1 - these 4 possible rows
are there with 2 variables. And for each of these cases, we can have many different ways
the functions - Boolean functions can be represented, right.
So, in one example say all of them the output could be 0; in one say output can be 1only
for the case when 0 0, is 1 and rest of the cases it is 0; output can be 1 only for the case
when input is 0 1 and rest of the cases it is 0. So, these are different possibilities and how
many such possibilities are there? Since it is - there are 4 so, 2 to the power 4 that is 16
such possibilities are there - ok.
And with this, among these 16 possibilities, we are familiar with - which operations? So,
this operation we are familiar with - NOR operation, ok; that means, when 0 0 is the input
and 1 is the output and rest of these things are 0. So, we know these operation as A plus B
prime – right, and corresponding its inverse is over here 0 1, 1, 1 right. So, we are familiar
with this operation so, this is A plus B.
We are also familiar with this operation and when both of them are 1 output is 1 - all right
and rest of the cases output is 0 this is 0. So, we know that this to be AB. This is - next is
NAND, is just opposite of it, we know this to be AB bar and some of these - yellow marked
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one. So, you see that when x is 0 output is 1 irrespective of the value of y and x is 1 output
is 0 irrespective of the value of y again this two cases. So, basically what you see here is
x prime x complement. Similarly, this is y complement. So, that way all the different you
know, these combinations are possibilities - each of the function can be represented, this
is 0 of course, and this is 1 ok, but rest of the cases we can you know, have a corresponding
Boolean expressions - right.
So, this formalization of representation and manipulation is done by Boolean algebra and
in this case we saw for two variables we had 16 such possibilities. If there are 3 variables,
how many rows will be there in the truth table? 2 to the power 3, there will be 8 rows –
right. And with 8 rows, how many possible functions are there in this side? So, for one
such combination say a function is 0 that is all the outputs are 0 in another case only one
case output is one rest of these cases are 0. So, that way 2 to the power 8 such possibilities
will be there for 3 variables - ok.
So, for any n variable cases, will be having number of rows 2 to the power n right here.
And with that you can have 2 to the power 2 to the power n possibilities of arrangement in
the form of Boolean functions - ok. So, this is we keep in mind and we understand the
importance of their representation and manipulation and for which we shall have a look at
Boolean algebra and more on that we shall discuss later.
(Refer Slide Time: 05:05)
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So, as I said Huntington postulates form the you know, basic premise of this Boolean
algebra. So, it has got 6 postulates and here we are talking about two valued Boolean
algebra. So, it has got 2 elements. And these 2 elements are 2 unique elements they are 0
1 this is the forming the set of B right and 0 of course, is not equal to 1. And postulate one
says that it is closed with operators plus that is OR and dot that is AND operator.
x + 0 = x; x.1 = x
x + y = y + x; x.y = y.x
That means if you are having an operation with this two operators the result is unique and
is a member of this set that is result will be 1 or 0. Identity element - so, for OR operation
the identity element is 0; that means, x plus 0 or a plus 0 it is x or a - ok. So, it will be the
variable itself and for AND operation the identity element is 1; that means, ANDed with
1, it will be the variable itself. So, this is the second postulate. Commutative with respect
to AND and OR operation – right, so, that is x plus y is equal to y plus x; xy is equal to
yx - we have already seen this in you know, the basic logic gate operation through truth
table, before.
x.(y + z) = x.y + x.z;
x + (y.z) = (x + y).(x + z)
This is distributive over plus that is, AND is distributive over plus that is x ANDed with y
plus z is xy plus xz; x AND y OR x dot z - ok. This is also - we can - all of these can be
verified from the truth table. And OR is also distributive over AND so; that means, x OR
yz is x OR y AND x OR z - ok. This is similar to what you see in ordinary algebra. This
does not look like you know, that of an ordinary algebra expression - this is one difference
that we take note of; more we shall take note later - ok. Again you can verify it by forming
a three variable truth table and putting the values and then calculating the output corresponding output and you can see that - that is what will arrive, you will arrive at.
0 + 0’ = 0 + 1 = 1, 1 + 1’ = 1;
0.0’ = 0.1 = 0, 1.1’ = 1.0 = 0
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And finally, after this identity, commutative, distributive, we come to complementarity
postulate where it says that if x is an element of set B then there exists a x complement
which is such that x plus x prime is 1 and x dot x prime x AND x prime is 0 - ok. So, that
is again one unique thing about a Boolean algebra unlike the ordinary algebra. And we
already see - its corresponding you know, meaning – significance. So, 0 plus 0 prime ok so, 0 prime is 1, its complement is 1, 0 plus 1 is 1. Similarly, 0 AND 0 prime is 0 and it is
1 it is 0 - ok. So, similarly will happen for 1 plus 1 prime case and 1 dot 1 prime case - that
will get 1 over here and 0 over there.
So, these are the basic postulates and we note that associative law that we have talked
about - that x plus y ORed with z separately and x ORed with y plus - y ORed with z
separately - they are the same; this is not part of basic postulate, but it can be arrived at
from the postulates that we have discussed so far.
(Refer Slide Time: 08:59)
Now, with this postulates behind us we take note of, in the form of a table, some important
identities - which is very useful in case of this Boolean algebraic - algebra based
manipulation, ok.
So, some of them are directly derived from the postulates some are represented as theorem
which can be proved by the postulates. Postulates are the axioms, self-evident thing and
theorems and other identities are actually the ones that can be proved from the postulates.
So, they - given different names which is useful in some sense later on, you can refer to it
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when you are using a particular kind of postulate or theorem to prove one particular
relationship or simplifying a certain relation - certain algebraic expression.
Identity
x+0=x
x.1 = x
Null
x+1=1
x.0 = 0
Complementarity
x + x’ = 1
x.x’ = 0
Idempotency
x+x=x
x.x = x
Involution
(x’)’ = x
Commutative
x+y=y+x
x.y = y.x
Associative
(x + y) + z = x + (y + z)
(x.y).z = x.(y.z)
Distributive
x.(y + z) = x.y + x.z
x + (y.z) = (x + y).(x + z)
So, identity we have already seen x plus 0 is x, x AND 1 is x. Null, this is theorem - null
theorem so, that means, x if ORed with 1 - anything ORed with one gets nullified I mean,
that has got no value. So, it will be - the output will be 1. So, x has no representation in the
output. And for the AND case, it is x ANDed with 0, the output will be 0 - ok. So, this can
be derived, we can see later. And complementarity - x plus x prime is 1, x dot x prime is
0 - coming directly from the postulates. So, the one that is in the brown are coming directly
from the postulates and the rests are the theorems which can be derived from the postulate.
So, idempotency means it is remaining the same - that is x plus x is equal to x, x ANDed
with x is also x. Involution - so, double prime, double complement is this variable itself.
Commutative - we have already seen x plus y is same as y plus x and xy is yx - ok.
Associative - as I said, it can be derived from these. We have already noted distributive
coming from the postulate which we have directly - noted before. And as I said it can be the theorems can be developed from postulates. More theorem theorems we shall see later,
in the next slide. So, for example, let us take this null - x plus 1 is equal to 1, ok. So, this
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is x plus 1, then it can be ANDed with 1. Where from it is coming? This is coming from
the Identity (b) - this is coming from this one, the arrow is there. all right this what.
Then this 1 can be written as x plus x prime. How can you write it? From Complementarity
(a), ok. Then you can use distributive property where x plus yz - you are using x is there is equal to x plus y and x plus z. So, this is x this is your y and this is your z - this is y and
this is your z, ok. So, yz getting multiplied over here and this is x, according to this. So,
this x is there yz is multiplied - multiplied means ANDed so, x prime ANDed with 1, ok.
So, then this is your by this - is your Distributive (b), ok. And then again you use identity,
this Identity (b) - Identity (b) you get x prime; and, x plus x prime is 1 from again your
complementarity - Complementarity (a) - is it clear? So, x plus 1 is equal to 1. So, that way
all the - these theorems can be proved and if it is asked you can write corresponding
postulates or other basic theorem that you have used in the right hand side - to explain the
steps that you have taken to arrive at that particular proof, ok.
(Refer Slide Time: 13:39)
More theorems - which is useful. When it is called the absorption - so, that is your x plus
xy is x and corresponding form over there - x ANDed with x plus y is also x. Adsorption
– ok, x plus x prime y is x plus y; x ANDed with OR version of x prime plus y is xy.
Uniting - xy plus x y prime is x; and x plus y ANDed with x plus y prime is x.
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Consensus theorem - it is interesting, where you can see that there are 3 terms over there
and there are only 2 terms over here. So, this term yz is not included in the right hand side.
So, this is a consensus term; that means, what is explained by yz in a truth table is already
explained by xy and x prime z for which it does not require another you know, reference.
So, that is why it can be simplified or it can be represented in this manner. And De
Morgan’s theorem, we have already seen. And, consensus theorem - its other version in
the product of sum version - it is called product of sum because you can see all the products
are there and this is sum version.
Absorption
x + x.y = x
x.(x + y) = x
Adsorption
x + x’.y = x + y
x.(x’ + y) = x.y
Uniting
x.y + x.y’ = x
(x + y).(x + y’) = x
Consensus
x.y + x’.z + y.z = x.y + x’.z
(x + y).(x’ + z).(y + z) = (x + y).(x’ + z)
De Morgan’s
(x1 + x2 + x3 + … xN)’ =
(x1.x2.x3. … xN)’ = x1’ + x2‘ + x3‘ + …+ xN’
x1’.x2'.x3'. … xN’
So, x plus y, ANDed with x prime OR z, ANDed with y OR z and this y OR z - is not
required in the final expression because this is an additional term which is already
explained by other two terms. Now, in the previous case as well as in this case you see that
there are 2 rows (a) and (b) - one is mostly - one is representing in a SOP or sum of product
form another is representing it in a product of sum forms. So, basically the OR operation
is done at the end and - other case AND operation is done at the end, ok.
So, these two expressions if you just compare and if you look at another interesting
theorem which is there for Boolean algebra - all algebraic expressions remain valid if the
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operators and identity elements are interchanged, ok - is a beautiful thing about Boolean
algebra; that means, operators and identity elements - so, what are the operators? Operators
are OR and AND - OR and AND, these are the two operators.
(Refer Slide Time: 16:33)
So, basically what we are telling by this that you convert OR to AND, AND to OR identity elements 1 to 0 and 0 to 1 in a any algebraic expression – right, to get an equivalent
I mean, the identity will remain valid - the resulting identity will remain valid, ok. So, that
is what this duality theorem tells. And, if you compare the left hand side and right hand
side of the 2 tables that we have seen so far - it is just is talking about that, ok.
I take this example say the first one over here - all right. So, this OR is replaced with AND
here, AND is replaced with OR and it is fine - whatever resulting expression identity you
get - it is also valid, ok. So, earlier we have seen for null 1 - x plus 1 is equal to 1, right we have already seen from basic postulates a valid scene.
So, now, what you can do if you apply duality - so, this x - OR changes to AND over here,
1 - identity element 1 changes to 0, and 1 changes to 0. Will get another relationship that
is x AND 0 with 0 - AND with 0, results in 0 - ok. So, this is also your - that was there in
the column b for the null. So, this is also a very useful theorem which is - which can used
for simplification and other cases, ok.
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(Refer Slide Time: 18:17)
And to get you accustomed with the way you use these axioms or postulates and basic
theorems we have few more you know, proof that we can quickly discuss, ok. So,
idempotency that we started with that we can have - see, we can see how it can be used in
this particular case, right. So, this x plus x - right we would like to prove that is same as x,
all right. So, start with Identity 1. So, that is the identity postulate. Then 1 can be written
as x plus x prime - Complementarity postulate all right. And this is your x this is your x
this is your you can consider this is y and this you can considered as z right then you can
apply the distributive postulate - distributive law and you can get x plus yz - y is your x
over here and z over here - so, x, x prime you get and then x x prime is 0 from
Complementarity postulate - all right. And, x plus 0 is x from identity postulate - ok. So,
the basic theorem related to idempotency can be arrived at by using the basic postulate,
ok.
Similarly, Idempotency (b) also you can arrive at, starting with - using the identity element
then the complementarity, ok – then, distributive - the other version of the distributive one,
and the complementarity and then finally, the identity element - we can get the all the final proof of this. And you can also get it from duality also that - AND is replaced with
OR there is no identity element. So, it remain same x AND x is x – clear.
So, similarly you can look at the involution - the proof of involution that is double prime
is the function itself, ok. So, in this case again, you start with the plus 0 that is identity
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element - identity postulate. So, complement - that is 0, can be written as x x prime, ok.
So, now, this is the distributive law in the other direction. So, from x plus yz, you are going
to x plus y and x plus z, ok. So, this is your x this is your y and this is your z. So, x this is
your y corresponding y and this is your corresponding z, ok. So, you have to remember I
mean, you can sometimes - you need to expand for which also you can use the distributive
law from right hand side you go to left hand side, ok.
So, after that what we are doing now - we are just changing - so, basically it is commutative
for which we can change. So, x comes this side and x prime goes to the other side and
similarly over here, all right. So, when you do that you can use the complementarity a plus
a prime what x plus x prime is equal to 1, ok. So, after doing that - this one can be written
just to you know, help the - help progressing with the proof one can be written as x plus x
prime and then you can apply again distributive law over here. So, this is your x this is
your y and this is your z. So, x is there y is it comes over here, ok. So, with that - you get
this complementarity postulate - you get 0 over here and x plus 0 with identity postulate
you get back that x, ok. So, using the basic postulates you can get all the theorems that we
have discussed.
(Refer Slide Time: 23:01)
So, we shall look at just 2 more proofs the last two ones – ok. So - the consensus theorem
– so,, in the consensus theorem we have left hand side - we have this term so, y z, we use
the identity postulate. So, we include 1. Then, complementarity x plus x prime, we put in
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this place. Then, we just expand it and then we use the associativity, ok. So, associativity
is not part of basic postulate, but as I said the basic theorem can be also used for proving
a more complex expression.
So, this is the way you are doing it all right. And, then if you just use - take x y out then 1
plus z comes over here 1 plus y comes over, here. So, again 1 plus z is 1 that is again a
basic theorem we have derived from postulates ok. So, so, this is sorry, this is your null
postulate from that you will be getting 1 - this is also getting 1. And finally, you will arrive
at a - this particular version which is a simplified version of this. So, this is your consensus
theorem – one version. Another version you get similarly or through duality - through
duality just you have to change this AND to OR and, this to AND and similarly, here it
will change to OR and this will change to AND.
So, basically if you just do it that way for all the cases we will get the corresponding
version for the consensus theorem. And proof of De Morgan’s theorem - it is done again
this is what you have seen in the previous case that you can use basic theorems also along
with postulates to derive the identity and - or the proof. And in the De Morgan’s theorem
we do it in an indirect way we can we can see that how you can be done in an indirect
manner. So, what we have to proof is x plus y prime is x prime anded with y prime ok. So,
we already know that from the complementarity - the basic complementarity, x plus x
prime is equal to 1.
So, x plus y as the whole you can consider as x. So, this is already known right and if we
can prove that x plus y and, x prime dot - AND with y prime, this one - that we seek to
prove, wish to prove is equal to 1. Then we have or we can rest our case, ok. This is indirect
way of doing it, but this is also - can be used, depending on the need. ok. So, this x plus y
and x prime dot y prime. So, basically we start with that 1 and again you use the distributive
law. So, this is your x and this is your y z kind of thing. So, x and this is x plus y and x
plus z this is the distributive law that you apply and then you are just - it is commutative
so, basically x plus y we can write y plus x and this remains the same.
Then you can apply associativity so, this is your associativity. So, basically instead of this
grouping - you are doing this grouping instead of this grouping - you are doing this
grouping, all right. And, x plus x prime complementarity is 1 and y plus y prime
complementarity is 1, ok. So, you can then - you can look at the identity sorry, null
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relationship, ok. So, this is 1 and this also 1 together you get 1, ok. So, now, we can see
that this is true so, the other one is also true.
(Refer Slide Time: 27:07)
So, to end, we shall just this part of the discussion - we shall just look at some of the
characteristics. So, what we have noted before that the Boolean algebra has certain
differences with ordinary algebra this distributive law the way we have seen it and utilized
in many different cases - this is not valid for ordinary algebra.
(x↑y)↑z ≠ x↑(y↑z); (x↑y)’↑z = x↑(y↑z)’
(x↓y)↓z ≠ x↓(y↓z); (x↓y)’↑z = x↓(y↓z)’
x↑(y↓z) ≠ (x↓y)↑(x↓z); x↑(y↓z) = (x’↓y)↑(x’↓z)
x↓(y↑z) ≠ (x↑y)↓(x↑z); x↓(y↑z) = (x’↑y)↓(x’↑z)
So, if you have got so, like five plus 2 into 6 kind of thing. So, 5 plus 12 is equal to 17.
And here if it is five plus 2 multiplied by 5 plus 6 ok. So, you will get what - 7 into 11, ok.
So, that is not - that is 77 so, it is quite different ok. So, this not valid for ordinary algebra.
Complement is not available in ordinary algebra that we already know. It does not have
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inverses for addition and multiplication - like subtraction and division, this kind of inverses
are not there in Boolean algebra which is there in ordinary algebra.
And, Boolean algebra is this 2 valued Boolean algebra the one that we have seen has got
only finite set of elements 0 and 1 for ordinary algebra that is infinite set of elements, 0 1
2 3 4 - the number can extend to any high value. And if you - if somebody thinks that
instead of AND and OR operation if we can develop a Boolean algebra using NAND and
NOR - it is not possible because the distributive law and some of these basic things,
postulates are not valid using NAND and NOR.
And earlier, we had seen that we discuss that they are commutative, but they are not
associative so, we can just the quick - you know we now know how to use it - so, if you
are talking about say, a NAND operation and then see this one and if we try to you know
check it with ABC and then NAND we shall see that they are not this. So, we can expand
it using De Morgan’s theorem and you can see that it will give you A bar plus B bar dot
C. And then this bar and similarly over here if you just look at if you just expand it you
will see the - both sides do not match.
In fact, what will match is the relationship like this. Here, we have used this operator for
NAND and this operator for NOR for better understanding, ok. And similarly, for
distributive – they do not follow distributive law over each other NAND is not distributive
over NOR or vice versa - NOR is not distributive over NAND.
But,
if you check the relationship then you will see that again using De Morgan’s
theorem, if you just expanded it and put it together instead of this x NAND y NOR z the
way put it in parenthesis – ok, it is x prime NOR with y which - y prime x prime NOR
with z which - is when there is a NAND operation between these two, then we shall get
whatever it is there in the left hand side.
So, this prime operation the complement operation comes here as well as here as well as
here. So, that is why it is called pseudo associative or pseudo distributive ok. So, and we
cannot use it in place of AND and OR operator in Boolean algebra.
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(Refer Slide Time: 31:33)
.
(Refer Slide Time: 31:35)
So, with this we conclude. Key points - n variables, we can have 2 to the power, 2 to the
power n possible functions. Six Huntington postulates form the basic premise or axioms
of Boolean algebra. And the basic theorems of Boolean algebra can be arrived at from
Boolean - Huntington postulates and these basic theorems and postulates can be used to
simplify or prove different identities which is more complex in nature and we can refer to
those basic theorems and postulates.
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And it has got - Boolean algebra has got certain distinctive characteristics that differentiate
it from ordinary algebra AND and OR operations are associative as well as distributive
over each other, but NAND and NOR operations are not.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture –08
Boolean Function to Truth Table and Implementation Issues
Hello everybody, in the last class we discussed fundamentals of Boolean algebra. We
discussed basic postulates - Huntington postulates we discussed and some basic theorems.
And we saw proof of those theorems from - many of them, how to do it from the basic
postulates.
(Refer Slide Time: 00:37)
Today we shall discuss how to convert a Boolean function to corresponding truth table.
And then we shall see how to realize a Boolean function using logic gates. And we shall
see that algebraic simplification using Boolean algebra is useful for efficient
implementation. And we shall also have a look at Shanon’s expansion theorem.
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(Refer Slide Time: 00:59)
F(x,y) = x + x’.y
So, the Boolean function some of the function that you have already familiarized with. So,
let us take one two of them; one is a two variable function. So, F(x,y) is equal to x plus x
prime y, ok, so that is x ANDed with - x prime, complement of x - x ORed with
complement of x ANDed with y, right. So, this is - we already have seen. So, if you want
to get the corresponding truth table, what we do? For this x, y variable, we substitute 0 and
0 like over here what you see, then it becomes 0 plus 0 prime. So, this is 0 standing for x,
this is 0 prime that is substituted x value and then y is also 0.
So, this 0 remains 0, and this 0 prime becomes 1 over here, and this 0 remains 0, right. So,
this one ANDed with 0 is 0, so 0 plus 0 is 0. So, this way we get one particular row of the
truth table, which we see over here filled, filled up. So, then the other option is x and y can
take value 0 and 1. So, this is that option. And then you substitute and go on putting the
values. And from the AND and OR operation, we get 1, 1, 1 for the remaining three
possibilities, and that way we can come up with the truth table, ok.
F(x,y,z) = (x + y).(x + z)
Say for a three variable case - this was where we had seen that product terms are summed
finally – here, the sum terms, this is a sum term, this is also a sum term with which we are
doing - taking an AND. So, there is a product term that is finally formed. So, there also
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follows the similar thing, this is a three variable problem. So, we shall be substituting x, y,
z - different combinations of them. We start with say 0, 0 and 0. So, x and y - both are 0.
So, we put those values. So, 0 OR 0 becomes 0 over here. Then x and z they are 0, so this
is 0. So, you substitute those values 0 OR 0 is also 0, these two are ANDed we get 0, ok.
So, this completes the first row of this particular truth table.
So, then 0, 0, 1 - another a possibility, this particular row. So, again you substitute and we
get 0 from 0 plus 0 of x plus y; and 0 plus 1 we get 1; from x plus z and 0 ANDed with 1
is 0. So, this is the second row that we get, and from that we get all the different rows and
complete the truth table, ok. This is a very simple approach. Given any function; given any
function of any number of variables you know that the number of rows in the truth table
will be 2 to the power n if n variables are there. And, we shall go on substituting each
values of the combination and work out the AND and OR operation, and complement
operation. And then finally, we will get the different entries.
(Refer Slide Time: 04:25)
Now, if you want to implement a Boolean function, any given Boolean function, we want
to implement it using hardware. So, these logic gates are there. So, each of these logic
operation, each of the Boolean operation that we do in the case of a Boolean function like
this - right, so for that a corresponding logic gate is there. So, x prime is required
complement of x is required. So, for that you have got NOT gate.
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So, we shall put a NOT gate - x is input at it and output is x prime – it is very easy to get.
So, this is ANDed with y, right. So, we will put a two input AND gate. So, there are two
inputs to this AND operation. So, one is x prime, another is y. So, this is this AND gate output is x prime y. And this x prime y is ANDed with - ORed with x. So, we shall put
two input OR gate because there are two input to this OR operation. So, this is the two
input OR gate and final output we get this way.
So, every this Boolean operation that you we do in the Boolean expression, there is a
corresponding logic gate to convert it to that and we get the corresponding circuit made.
Similarly, the other relation that you had seen so, this is x plus y ANDed with x plus z. So,
to achieve x plus y, we need a two input OR gate, ok. This is OR operation to achieve x
plus z, we need a two input OR gate that is another - this is a OR operation. And finally,
these two are getting ANDed, these two are getting ANDed over here. So, for this, two
such input are required - for this, two inputs AND gate; and, finally, at this place we get x
plus y ANDed with y plus z, ok.
So, you can just simply follow the Boolean - any given Boolean expression, operation by
operation, with the operands that are there. If it is a - there are two operands, so two input
gates will be required; three operands; three input gates will be required. And finally, the
whole expression can be arrived in the form of digital circuit implementation. Remember,
in this case, we are not talking about the propagation delay, power consumption and all
those things. It is just simple implementation of the Boolean expression, right.
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(Refer Slide Time: 06:59)
Now, well - we talk about this implementation. In the previous case, we did not bother
about those factors that can affect the realization. But, in practical cases you see, that
amount of power you consume, amount of power the circuit consumes, the fan-in - how
many input can be there, fanout - how many output can be there, propagation delays if
number of phases get - you know, becomes very much, so - many such issues would be
there. And we will always look for an efficient implementation. And in efficient
implementation, we shall try to reduce we try to you know, have a most simplified form
of representation - as much as possible.
F(x,y) = x + x’.y = x + y
So, in that case, the Boolean algebra that we have the fundamentals which we discussed
before can be of - very useful I mean, very important. So, the previous realization that we
talked about - the previous one - that x plus x prime y; we have noted that it requires one
NOT gate, this NOT operation here; one two input AND gate for this operation; and one
to input OR gate for this final operation, ok. This is - this was what was required if it goes
for direct implementation just following the Boolean expression.
But if we apply adsorption theorem, we know the same input-output combination - the
truth table, the relationship that we have seen will be available just by equivalent
expression which is x plus y – right; that is from the basic theorems. So, this x plus y if we
implement, whatever we get - we get exactly the same by implementing x plus x prime y.
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So, it makes sense that we go for this implementation than this one. So, in that case, we
just need one two input OR gate as we have seen.
(x + y).(x + z) = x + y.z
And in the other example, so this x plus y ANDed with x plus z, so from distributive law
the basic postulate, we know that this is x plus yz. And if we want to implement it, we
need one two input AND gate over here to realize yz as we have seen; and one two input
OR gate to realize x plus yz as it is there.
And earlier it was - for this case, one two input OR, one two input OR, so that is - two two
input OR, and one two input AND gate, so that was the requirement. And in this case, one
two input AND, one two input OR. So, by using Boolean algebra - by simplifying
relationship, we see that the hardware requirement is reduced. And we have associated
benefit in terms of different performance metric.
(Refer Slide Time: 09:53)
So, that was a very simple example. There can be more complex relationship arrived at by
examining a particular problem, which is given in the form of an English statement. And
when we try to convert it, just by following the statement a - may be a complex relationship
like this one may arrive at. This is just an example say, this kind of relationship you are
getting. So, we can go for direct implementation of this, the way we have just seen that how a Boolean expression can be realized in the form of hardware. So, we can have a NOT
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gate to realize C prime, then another not get to realize A prime from A then a three input
AND gate to realize ABC, then this can be ORed with C prime - a two input OR gate and
so on and so forth. And ultimately you can arrive at the final circuit which is - which will
provide you the truth table - these eight rows and you know, the corresponding column the output function.
So, the same truth table, we can get if we go for a simplification process and whatever
circuit finally, arrived at, if we just go for implementation of that – ok. So, that is - what
is the usefulness of this simplification process. And if you try to do that, in this case, by
following the postulates - basic the postulates and basic theorems that we have discussed
before in the last class, then we can see - just few steps, let us have a look. This A, when
you are ANDing with A prime - this particular thing, so you get this one and the rest of
the remaining thing remains same. So, A prime is - gives a 0. So, you are left with AC
only. So, this is the AC from here and rest of the terms are as it was.
So, then again you do AND operation of AC A prime B, AC and C - right. So, this A and
A prime again will give you a 0 and what you are left with is only AC, so that is the AC
and then the rest - the rest of the term. Then again, you go for ANDing of this. So, AC
AND with A prime BC and then you get A C C prime. So, this A and A prime will give
you 0; C and C prime will give you a 0, so 0 plus 0 is 0. So, it is as good as the output Y,
you directly connect to logic low - whatever you get is the same as doing all the different
you know, circuit operation - effectively it remains the same, ok. So, that is the equivalence
that we are talking about. And also occasionally one you know, gives theyou know,
identity to be proved that this is the left hand side - so, that this is equal to 0, I mean, this
is equal to binary 0 at the end. So, there also you can find these algebraic simplification
terms, of use.
So, another example we can see where we use the DeMorgan’s theorem. So, here in these
expression, this we have to simplify, and then implement. We can go for again as I said, a
direct implementation following the equation, but that may be more complex and not
economical. So, here in this expression, we see that there the whole expression - that is a
prime over there. So, we can apply Boolean sorry, DeMorgan’s theorem over here. So,
this becomes A prime, again A prime - double prime actually. So, this is A, and then B
prime plus C prime - the whole thing becomes a prime - ok, because it was a NAND
operation. So, this is the way you are getting it.
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Then this A is remaining. So, B prime plus C prime - this is again a complements; another
DeMorgan's theorem. So, this is a NOR operation. So, you can get B prime - double prime
and C double prime, so this becomes BC - ok. So, this expression then becomes A plus B
ANDed with A plus BC and this was what it was. So, if you just get the product of this,
then this is AA ABC AB plus BBC. So, this is the corresponding term over here. And if
you take A out, then 1 plus rest of the term; and we know one from the null theorem if one
is there the rest of the terms of is of no use.
So, from this you have A and this BC was there. So, this is your B,C and this is the other
term ok. So, this again you can just take into consideration A and A prime B plus C. So,
in this you can use the adsorption theorem. So, there A plus B plus C is there, and this is
your BC. So, again you can take C out and 1 plus B, again using the null theorem you get
from this only C, because 1 OR B is 1 only. So, final expression is A plus B plus C. So,
what you require in this case is only early it was just connected to ground here, you need
only a three input OR gate - right. And you can realize the same expression –clear. So, that
is what you would do, if so required, before implementing any Boolean expression, we
shall see whether it can be further simplified.
(Refer Slide Time: 15:47)
Now, Shanon’s expansion theorem is something which you would like to take note of. It
has got many different uses. So, what Shanon’s expansion theorem says is very interesting.
So, given any function of n variables ok - we shall see examples of smaller number - two
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variables, three variables and all. Any you know, expression of n variables, one of the
variable may be taken out, for example, here x1 - it could have been any other variable.
So, this variable when you take it out like this x1 prime and rest of the function wherever
x1 is present, you put 0 - ok. And then whatever result you get, you AND it with x1 prime.
And then you take x1 out, and for x1 - wherever x1 is present you place 1. And then
whatever you get you just OR it - sum it up. Then, you get an equivalent relationship - ok.
This is what Shanon’s expansion theorem says, right.
F(x1, x2, x3, …, xN) = x1’.F(0, x2, x3, …, xN) + x1.F(1, x2, x3, …, xN)
And to be simple, in the left hand side if you place x1 is equal to 0, then this is only 0 term
is there; and in the right hand side when you place x1 is equal to 0, so 0 prime is 1. So, this
1, this 1 ANDed with this term, so this term will be remaining. So, the other term 0 ANDed
with rest of the thing is 0. So, you will be left with this one only and left hand side you
have already substituted 0 over here. So, left hand side and right hand side is matching,
ok. Similarly, if you put x1 is equal to 1, you will get the other term ok. So, if x1 is 0 and
if x1 is 1, then these are the two cases and they are getting summed up and you get the
final relationship - final term for the function in hand, ok.
And you can look at a two variable example - how it works it out. So, this F(x,y), x plus x
prime y - you are already familiar. So, if you are taking out x right, if you are taking out x,
and we would like to write it in this form. So, x prime F(0,y) plus x F(1,y) - right, it is a
two variable problem. So, basically x1 is your x and x2 is your y that is way you are doing
it. So, we have to calculate F(0,y) and F(1,y). How will you do that? So, in the expression,
we shall substitute - in place of x, 0. So, if you substitute then 0 plus 0 prime y. So, 0 plus
0 that is 1 prime y - 1 ANDed with y. So, this is y - right. F(0,y) is y and F(1,y) is - we
substitute in place of x - 1, so 1 plus 1 prime y – so, 1 summed with anything is 1. So, this
is your F(1,y).
So, this F(1,y) is your 1 and F(0,y) is y, so that way x prime y plus x - and you get back
what you had seen - x plus x prime y, ok. So, this will be true for any other you know,
example. This is small example, but this holds.
F(x1, x2, x3, …, xN) = [x1’ + F(1, x2, x3, …, xN)].[x1 + F(0, x2, x3, …, xN)]
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And it is dual form ok. See in the dual form we know that it is these - AND is replaced
with OR, and OR is replaced with AND. So, in this case, so this is the AND operation over
here. So, this AND operation is replaced with OR. And this was the OR operation - this is
replaced with AND. This was a AND operation over here, ok. So, this is replaced with
OR, ok. So, it was sum of two product terms, this becomes product - final product of two
sum terms. So, this is the dual form representation of Shanon’s expansion theorem. Ok.
(Refer Slide Time: 20:07)
Now, this can be useful in simplification problem as well - right. So, we take one example.
So, this is a five variable problem, where the right hand side looks something like this.
And if you need to - want to apply Shanon’s expansion theorem, one variable we want to
take out. So, we will generally look for the variable which is present in almost all the terms
that you see in the expression. So, here we see that A is present - A is present in all the
different individual terms. So, it makes sense that we take A out - ok.
So, if you take A out, so then you have to get two relationship, one is F(0,B,C,D,E) and
another is F(1,B,C,D,E) and then we shall AND it with A bar F(0,B,C,D,E) and A
F(1,B,C,D,E) - ok. So, this is the Shanon’s expansion theorem that we shall be using for
taking A out. You could have taken any other variable out - B also in that case
F(A,0,C,D,E), F(A,1,C,D,E) that would be the case, and here the relationship would have
been B bar F(A,0,C,D,E), B ANDed with F(A,1,C,D,E) - so that is the way you would
have written the expression.
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So, once you take A out then what do you see F(0,B,C,D,E) - this expression how you will
you get. So, if you substitute, this is your 0, this is 0 complement ANDed with B, and this
is 0 ANDed with rest of the things. And whenever this is 0, so in the OR gate it does not
you know, contribute in any way. It is 0. It does not contribute in any way means it is
dependent on other inputs of the OR gate. And this is ANDed with 0 means this generates
a 0. So, basically you have got 0 plus 0 prime is 1 - ANDed with B plus 0. So, basically
you get 0 OR B OR 0. So, so ultimately the result is B - ok. So, F(0,B,C,D,E) is your B.
And F(1,B,C,D,E) - what it is. So, this is 1 plus 1 bar B plus 1 rest of the terms - ok.
And we know anything ORed with 1 is 1 only - from the null theorem. So, this is one this
is straight forward ok. So, you have got this two terms. Now, we just need to combine
using this Shanon’s expansion theorem. So, A bar, so A bar is ANDed with B this
particular term is B only, and A ANDed with this term which is 1. So, A plus A bar B that
is what you get. And after that you can use adsorption theorem, so this is A plus B. So,
from this to this, this is your adsorption theorem - ok. So, you get A plus B. So, this is the
simplified version for A. And we could have taken other you know, postulates and basic
theorems also to simplify it, but we see that Shanon’s expansion theorem can also be useful
in such a case.
(Refer Slide Time: 23:41)
So, finally, we look at some of the use of you know, Shanon’s expansion theorem. So, this
was our - the basic Shanon’s expansion theorem. So, where x1 was taken out - right, it is
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clear. So, in this particular function, there are x2 to xN variable. So, these again can be
expanded for another variable. And if you choose it to be x2, so this one we can write as
x2 prime this is already 0. So, we do not do anything with that. So, x2 is 0, because x2
prime has been taken out - is the ANDing term, and rest of the terms remaining same plus
this one. This whole term is this one plus x2 F - 0 in place of x2 since x2 has been taken
out this is 1, x3 and rest of the terms, clear. So, this is for this one and for the other one we
can have a similar expansion with x2. So, basically we are having x1 prime outside and
inside x2 prime being considered. Similarly, x2 prime and x2 over here and x1 outside and
x2 prime and x2 over here, and the corresponding terms here are F 0 0 and rest of the
terms; F 0 1, rest the terms; F 1 0 rest of the terms and; F 1 1 rest of the terms - ok.
F(x1, x2, x3, …, xN) = x1’.[x2’.F(0, 0, x3, …, xN) + x2.F(0, 1, x3, …, xN)]
+ x1.[x2’.F(1, 0, x3, …, xN) + x2.F(1, 1, x3, …, xN)]
Then we can go ahead with you know, further such expansion of this particular - one such
term. So, x3 can be taken out - ok. So, the first term will be F 0 0 0, and second term will
be F 0 0 1 and all, so that way what is known as nesting is possible using Shanon’s
expansion theorem - ok. So, you can go on doing it and it has got certain use which we
shall discuss later in some of the later classes - ok. So, here you see how it actually works
out for a two variable problem.
So, for a two variable problem, so say x y is there. So, x prime has been taken out, so
F(0,y) and F(1,y), so these are the two terms. So, this y is now you are taking out, so F(0,0)
F(0,1) - right. And then x – F(1,0) and F(1,1) and then if you just take the y prime outside
the parentheses bracket, so x prime y prime F(0,0); x prime y F(0,1); x y prime F(1,0) and
x y F(1,1) - that is how what we get by expanding it to this level. And for an example like
this - the one we had seen before F(x,y) is x plus x prime y. So, you have seen you form
the truth table F(0,0), F(0,1) and so on and so forth. So, we have seen that F(0,0) is 0;
F(0,1) is 1, and F(1,0) is 1, and F(1,1) is 1 - we have already seen that - isn’t it!
So, this corresponding terms we shall just AND it up from here, we shall use this F(0,0)
terms, so x prime y prime - so x prime y prime ANDed with F(0,0). So, F(0,0) is 0, then x
prime y is ANDed with F(0,1). So, F(0,1) is we have already seen – F(0,1) as 1. So, this is
your 1 - ok. So, if x y is ANDed with F(1,1) - ok, so that is your the final 1 1 over here.
So, all the terms that you can see are coming here. So, this is being 0, this term is not there,
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and this would be terms x prime y x y prime and x y that would be there in the final
expression ok.
Anyway expand it to that level ok. You can further simplify it. We are not talking about
simplification over here. We are just saying that this is the way you can represent up to
this level you can if - you know, go on expanding it to that level. And then if you just this
x prime y, and you can take x out and y plus y prime this from complement postulate - a
complementarity we can see that x prime y and this is 1. So, this x plus x prime y, we can
get back this one that is a simplification process. But if you get all the terms in terms of
individual variables, these are the three terms that we will get.
So, you can see in the truth table, this 1 is there in three cases - right. And this - there are
three such terms where all the variables expanded to the - in the maximum possible way
that is what we see, ok. This has got its use in our subsequent discussion we shall begin
our next lecture next class from where we leave here.
(Refer Slide Time: 29:05)
So, to conclude what we have seen today in this particular class is, we can obtain a function
output by substituting variables with possible binary - all possible binary combinations.
And we can get the truth table out of it. And this - any Boolean function given to us, we
can realize it using logic gates by getting those logic gates which corresponds to a specific
logic operation. And algebraic manipulation helps to get a simplified - a Boolean
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expression, Boolean algebra comes very handy in that. And Shanon’s expansion theorem
and its nested version is useful in algebraic manipulation of a Boolean function, ok.
Thank you.
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Digital and Electronic Circuits
Prof. Goutham Saha
Department of E &EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 09
Truth Table to Boolean Function and Implementation Issues
Hello everybody, in the last class, we had seen if a Boolean function is given, how to
convert it to a - how to get a truth table out of it, and we also saw how to implement a
Boolean function, and how Boolean algebra can be used to simplify a Boolean expression
and get a minimized expression out of it. And we also discussed the Shanon’s expansions
theorems.
(Refer Slide Time: 00:41)
And in today’s class, we shall discuss the canonical representation of a truth table using
minterms and also using maxterms. And we shall discuss given a canonical representation,
how we can get a two level implementation of it. And also, side by side, we shall discuss
multilevel implementation. And we shall end with positive and negative logic.
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(Refer Slide Time: 01:07)
So, in the last class, we ended with the nested version of Shanon’s expansion theorem.
And we arrived at for a two variable problem - and expression if is x plus x prime y, we
just took this as an example. So, you may not look at it this point of time. So, this is the
truth table. And this particular truth table we can see that there are 4 such terms. And the
terms that are associated with 1 from the Shanon’s expansion theorem, if we just compare,
these are the terms.
F(x,y) = x + x’.y
F(x,y) = x’.y’.F(0,0)+ x’.y.F(0,1) + x.y’.F(1,0)+ x.y.F(1,1)
= x’.y + x.y’ + x.y
And this was there in final expression that we had formed. So, these are called product
terms and which is finally summed ok, the AND terms which is finally ORed - ok. So,
interesting thing is here that only the one that are having function output 1, which is
considered in this summation process or ORing process. The one that is having 0 is
excluded - ok. And another interesting thing is if you look at the x, y combination, so when
x and y both at 0 right, so the corresponding term is x prime AND y prime - ok.
And 0 1, if x is equal to 0 this is x prime and y - this is just y uncomplemented version that
we find. So, x is one and y is 0 this is x and y prime; and both of them are one both are
uncomplemented. So, these are the corresponding term that we get which is called also
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minterm in this two variable problem. So, this minterm or fundamental product or some
standard product is nothing but a product term containing all the variables - ok. So, this x
over here is not a minterm right, but x prime y this is a minterm because it contains all the
variables. It could be in complemented version or uncomplemented version - primed or
unprimed - ok, it does not matter, but these are there.
So, you can see that for each of these two variable problem, 4 possible such minterms are
there. This x prime y prime, x y prime and x y. And what we do? We just for convenience
we term them also using m0, m1, m2, m3. This suffix 0, 1, 2, 3 comes from there decimal
equivalent of this x, y values. So, 0 0 the decimal equivalent to you know, is 0; 0 1 is 1; 1 0 is 2, and 1 1 is 3, so that is why m0, m1, m2, m3 - that is how it is mentioned. And
finally, the function is obtained by taking OR of all the minterms that has got 1 in the
function output that we have - that we notice here ok.
(Refer Slide Time: 04:21)
So, that was a two variable example. For three variables, what we will do? So, we shall
have the corresponding minterms. The minterms will be having all the three variables and
the possibilities are 8 with three variables. So, 0 0 0 - ok, for this combination at the input,
the minterm will be x prime, y prime, z prime - all of them wherever 0 is there, the
corresponding term will be prime. 0 0 1, it is x prime, y prime, z because z is equal to 1,
so z is unprimed or uncomplemented, so that way we will go up to when all of them are 1,
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it is x y z. And the corresponding a notation in terms of m0, m1, m2 go up to m7 which is
the decimal equivalent of this place - ok.
So, we already have noted that the binary equivalent of 1 1 1. This place value is 4 - ok,
this place value is 2, this place value is 1. So, if it is multiplied with 1, 2 and 4 here each
of these cases, so 4 plus 2 plus 1 is your 7. In this case 4 plus 2, so this is 4, this is plus 2,
and this is 0 multiplied with 1. So, it is 6. So, this is m6 - ok. So, this is the way we get the
decimal equivalent and the corresponding notation is presented here - ok.
F(x,y,z) = (x + y).(x + z)
And if you look at this particular truth table. This truth table we have seen the before. But
here we are looking at given a truth table, how we are converting it to corresponding
Boolean expression. Here, we are talking about expression that has got minterms. So, we
shall look at the terms that are having all ones. So, these are the terms that are having ones
1, 2, 3, 4, 5. So, 5 minterms will be there which will be summed to get the corresponding
Boolean expression - right. So, this is the one where the first term x is 0, y and z are 1 for
which the minterm is generated. So, this is x prime because it is 0, and y z, so x prime y z
- that you see.
Next one is x is equal to 1. So, x it will be x then y is 0 and z is 0 - y prime z prime. So, x,
y prime, z prime. So, this way you will get all the five terms. And this five terms you can
see m3, m4, m5, m6 and m7 - that is what you do here. And you can use for a more compact
representation using a sigma, a summations sign, where m stands for minterm the small m
and 3, 4, 5, 6, 7. So, these are the corresponding decimal equivalent places that is what you
finally, sum it up. And this is called canonical form - right. And you can have a normal
SOP form also which is just as we said the x plus yz - that is not called canonical form.
When all the variables are present in - you are coming up with the minterm, it is called
canonical form representation. So, this was a sum of product kind of you know,
representation of the truth table.
F(x,y,z) = x’yz + xy’z’ + xy’z + xyz’ + xyz
F(x,y,z) = m3 + m4 + m5 + m6 + m7
F(x,y,z) = ∑ m(3,4,5,6,7)
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(Refer Slide Time: 07:35)
And you can have the product of sum - the dual version of it. So, for that the term that was
that are used are called Maxterm - ok. So, how these maxterms are formed and designated?
So, again if you go by the dual of the Shanon’s expansion theorem the one that we had ok, so if you expand the function that we had earlier, this one, that we just used.
F(x,y) = [x’ + y’ + F(1,1)].[x’ + y + F(1,0)].[x + y’ + F(0,1)].[x + y + F(0,0)]
= 1.1.1.(x + y) = x + y
So, if you for this particular truth table, if you keep expanding it, x plus x prime y right,
and then you know all the individual terms, and you substitute it over here, only we know
that F(0,0) was 0, and rest of the terms was 1 by calculation. And then when you do it all
individual terms you generate 1, and only the last time will generate 0. So, 0 plus x plus y
and rest of the terms are only 1 – ok; so that gives you x plus y. So, this is - you are getting
from nested version Shanon’s expansion theorem, this dual version - ok, so that you can
see.
And the corresponding truth table - this corresponds to only one location that is 0 and for
the Maxterm definition, wherever there is a 0 we take it - we take it as uncomplemented,
unprimed. And whenever there is a 1, we take it as complemented. So, this is the difference
- important difference we have to take note of, between minterm and Maxterm designation.
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And of course, this is a sum term. So, there is an OR sign in between two variables; in the
other case there was an AND sign - product sign between two variables. So, this is the
important difference.
So, we see that for two variable these are the 4 possible cases where all the literals, all the
variables are there and the terms are 0 0 - x plus y, 0 1 - x plus y prime, 1 0 - x prime plus
y, because it is 1, it is x prime; x is 1 that is so why it is x prime y is 0 that is why it is y
ok, 1 1 this is x prime plus y prime. If it is 1, as I said it could be a prime; and if it is 0, it
will be unprimed - ok.
So, coming to the definition, sum terms containing all variables of a function which is
there in a particular n variable problem, so that is called fundamental sum or standard sum
or Maxterm - ok. And similar to minterms we also designated with M0, M1, M2 and M3,
where 0, 1, 2, 3 corresponding to you know, decimal equivalents. So, 0 0 this is M0, this
is M1 and so on and so forth - ok. This capital M represents maxterm, small m we have
used for minterm.
And a final expression, we get for this particular truth table just by - we are taking product
of, taking AND of all the maxterms that you have got for a particular function, where the
function output containing 0 generates that particular combination of the input, generates
a specific maxterm - clear.
(Refer Slide Time: 11:19)
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So, we look at it for the three variable example - ok. So, this x y z, all of them 0. So, if it
is 0, then it will be unprimed, uncomplemented. So, the corresponding maxterm is x plus
y plus z - ok. 0 0 1, it is x y, and z is 1 -, so that’s why z prime will be there, so x plus y
plus z prime. And that way when it is 1 1 1, we have got x prime plus y prime plus z prime.
So, this is three variable - you can extend it to n variable and the location wise so this 0 0
0 is decimal equivalent is 0; 0 0 1 decimal equivalent is 1; 0 1 0 decimal equivalent is 2.
So, you have got Maxterms M0, M1, M2 up to M7 - ok.
F(x,y,z) = (x+y+z).(x+y+z’).(x+y’+z)
F(x,y,z) = M0.M1.M2
F(x,y,z) = ∏ M(0,1,2)
For the same truth table that we had seen before - if you remember; - the same truth table
we had five 1s here right, and the minterms contained 3, 4, 5, 6, 7. Now, we are trying to
represent it using Maxterm. So, the Maxterms that are there which need to be considered
or the place where there are 0s - ok. So, three 0s are there, three Maxterms will be there
which will be finally ANDed. So, we have to see that how these - each maxterm is
represented. So, 0 0 0 these are the three different values of x y z for the first maxterm
over here - M0. So, this is nothing but your x plus y plus z - x plus y plus z, so that is that
goes here. So, next one is x plus y plus z prime, and third one is x plus y prime plus z - is
it ok? So, this is your M0, M1 and M2. And more compact representation this is the
product, Pi that is - that means, that multiplication of Maxterms 0, 1, 2 that is ANDing of
0, 1 and 2, three Maxterms - ok. Is it clear? Ok. So, this is also called canonical
representation because all the variables - all the maxterms are involved.
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(Refer Slide Time: 13:49)
Now, given one particular form, can I get the other form out of it? So, the examples we
have seen - in the first example, we had seen that three ones were there and one zero was
there. And for minterm representation – SOP, this is what we got. Ok. And for Maxterm
representation, only one term was there. So that is why you can just write it - you can
remove the phi - that is M0. So, if you see that there are 4 possible terms in the terms you
know decimal equivalent 0, 1, 2, 3. So, if three go here, the remaining one out of the whole
set, is there in the other case. So, if minterm contains 1, 2, 3; Maxterm will contain 0.
F(x,y) = x + x’.y = ∑ m(1,2,3) = ∏ M(0)
In the next example, we have seen the minterm contains 3, 4, 5, 6, 7; and Maxterm contains
0, 1, 2. So, for three variable problem, possibilities are 0 to 7, eight possibilities. So, if 5
is taken there in minterms - there is representation, SOP. So, rest three is - remaining three
is taken up in the Maxterm based representation using POS form - Product of Sum form.
So, the whole set minus one particular from representation, whatever are the corresponding
decimal equivalent places, then remaining is going for the other form, so that is the way
we can quickly convert from one form to another.
F(x,y,z) = (x + y).(x + z) = ∑ m(3,4,5,6,7) = ∏ M(0,1,2)
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The other important thing that we can observe from whatever discussion we had so far is
- in the first example, this sorry, second example the F(x, y, z) - the minterms are 3 4 5, 6,
7. So, if you take complement of F(x, y, z) - whatever we had, ok - wherever 0 was there,
1 will present; and wherever 1 was there, 0 will present. So, F prime x, y, z that is
complement of F(x, y, z) the one that we had, will be having minterms 0, 1, 2.
So, this in the SOP form - summation of these three minterms, that would be giving you
the complement of F(x, y, z), the way we have defined in that truth table. So, you can write
it in this way, m0 plus m1 plus m2. So, how can we get F(x, y, z) from F prime x, y, z, you
just take complement of it - right. If you take complement of F prime x, y, z, that is double
inversion, is the same you know the function itself. So, that is, what is that - m0 plus m1
plus m2 - taking complement of that, ok. So, by De Morgan’s theorem, this is m0 prime
ANDed with m1 prime with ANDed with m2 prime - ok.
F’(x,y,z) = ∑ m(0,1,2) = m0 + m1 + m2
F(x,y,z) = (F’(x,y,z))’ = (m0 + m1 + m2)’ = m0’.m1’.m2’
And, we have already noted for this maxterm base representation - the same function
F(x,y,z) – F(x,y,z) over here, we have noted that this is M0, capital M0, capital M1, capital
M2. So, we can see for any such truth table, if you just extend it that mi prime - mi prime;
so, m0 prinme - M0, they correspond. So, mi prime is same as - a minterm ith position, if
you take complement of it - you get Maxterm, the corresponding Maxterm in the i-th
position. This is very simple relationship - we will keep in mind, ok.
F(x,y,z) = ∏ M(0,1,2) = M0.M1.M2
mi’ = Mi
Now, given an expression to get the minterms or the maxterms - right, what we have done?
We are getting the truth table. And from the truth table we are looking at the x, y, z, or x,
y - whatever the input variable combinations. And wherever there are ones we are getting
minterms for those combinations and writing it in a particular manner and similarly for
Maxterm. So, this is one way we can get all the minterms and maxterms of a particular
Boolean expression. It can be obtained algebraically also, without going via the truth table
route.
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So, for example, this x plus x prime y is there - ok. And we want to get its - these particular
terms, minterms, that means, all the different things that are there. So, x you can write as
y plus y prime is the - from complementarity, this x is ANDed with one. So, 1 can be
written as y plus y prime. Then if you just expand it that is AND x y with - x with y; AND
x with y prime, then you get this thing. So, this is the all - contains all the literals, all the
variables, so this three minterms that you get - ok. So, you do not need to go in that
direction.
F(x,y) = x + x’.y = x.(y + y’) + x’.y = x’.y + x.y’ + x.y
So, similarly for the other problem - POS problem. So, x plus y, you can write as x plus y,
z z prime – complementarity, it is just summing up with 0, ORing with 0, it does not make
any difference in the final outcome. So, x plus z, you can write as y plus y prime. Then
you can use distributive law. So, this is x plus y; z will be coming here and z prime will be
coming here. And in the other case, x plus z is one thing and - y y prime. So, y will be
coming here and y prime will be coming in the other place. Then you can say x plus y plus
z are there in three places, x plus y plus z are there in three places – sorry, in two places;
keep one of them and these are three Maxterms that you are getting that is M 0, 1, 2 - ok.
So, algebraically also, you can arrive at the Maxterms - ok.
F(x,y,z) = (x + y).(x + z) = (x + y + z.z’).(x + z + y.y’)
= (x + y + z).(x + y + z’).(x + z + y).(x + z + y’)
= (x + y + z).(x + y + z’).(x + y’ + z)
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(Refer Slide Time: 20:03)
Now, implementations of these canonical form is very standard. So, SOP form - we just
look at one example. In this case, we will be having AND bank followed by OR gate. So,
this is example where m minterms 3 5, 6, 7 ok. So, they are getting ORed ok, in the final
- summed up in the final function output.
So, m3 is A bar B C right, A B C 3 is 0 1 1 ok. So, A bar B C is one input, generating one
minterm. 5 is generated in this - by this; 6 is generated by A B C prime; and 7 is generated
by A B C - ok. And finally, all of them are ORed, and you get a SOP realization of this.
This is called two level - ok, assuming that the variables are available both in complement
and uncomplemented form.
So, both A and A bar, they are available at the input side; otherwise, if it is only A is
available, to get A bar you need a another NOT gate - ok. So, in that sense, one may think
that it will increase another level - ok. But the assumption over here is that both A and A
bar are available simultaneously at the input side. And these are the two levels one AND
bank followed by an OR gate - which is required for this two level implementation of the
canonical form of SOP - ok.
For POS, it is similar. So, there will be OR bank followed by a multi input AND gate
depending upon how many OR gates are there - ok. So, practically this is - as I have
mentioned before - the fan in, fan out, all those things need to be considered. If it is violated
we have to take other measure by which we see that things are in order. So, here it is 0, 3,
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6 – right. 0 means A plus B plus C. So, this is your A plus B plus C - ok. So, 3, 3 is your
A plus B bar plus C bar – right. Is this ok? So, 0 - as we have noted 0 0 0, so whenever 0
is there, it will go uncomplemented for Maxterm generation. So, finally, 6 is A bar plus B
bar plus C that is your - so, all of them these outputs are summed - sorry ANDed, and we
get the final output. So, this is also two level implementation.
And what could be multilevel implementation? So, here we discuss an example of a three
level implementation - right. So, ABC. D is ANDed with E plus - and F - the summation
of E and F. So, E and F are summed up, then this is there. So, you can see three stages are
there right. So, this is a three level implementation. It could have made into two level
implementation by expanding D E, and I mean just ANDing it following the distributed
law and D F. So, this would have given you a two level, this would have given you a two
level implementation - ok.
(Refer Slide Time: 23:39)
So, you can use NAND-NAND and NOR-NOR based two level circuit for realization of
a SOP and POS forms, respectively. This is useful in certain sense that it uses only one
variety of gates - ok. And this is evident from this particular relationship - what has been
shown here for say, AB, CD and EF - this is a SOP realization. So, in this case, you can
take double complement of it. And then from De Morgan’s theorem you can see that this
AB becomes AB prime - that is your NAND operation over here; and this is NAND
operation of a CD; NAND operation of E F.
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A.B + C.D + E.F = ((A.B + C.D + E.F )’)’
= ((A.B)’.(C.D)’.(E.F)’)’
And ultimately all of them - each individual NAND output are ANDed and complemented
that means, another NAND operation is involved in the last stage - the second stage, second
level, and you get the same SOP instead of AND and OR that is this - you are having a
NAND replacing the AND bank and another NAND replacing the OR gate, the final OR
gate ok. So, by this you are getting only one variety - using only one variety of gates.
So, here is an example. So, here you see the m 3 - this is the minterm, that are getting
something - using the canonical form. It can be used for other form as well - any form like
what we had shown as an example. So, basically minterms 3 is your A bar B and C. So,
you see this output here - it is A bar B and C, so that is the corresponding NAND term will
be generated and then that minterm is finally, again with the other NAND gate outputs,
other NAND gate is formed and then you get the same SOP realization, but using NAND
NAND implementation, ok. And here in these example we are showing the corresponding
IC numbers 3 input, 4 input IC numbers, this 7410, 7420. And if you remember for two
input NAND gate it is 7400 - that you have seen before.
The same thing goes for POS representation using NOR-NOR gates. And in this case,
again the similarly the original expressions say AB plus CD plus EF - any such example
you can take up. So, this is OR gates, OR banks in the beginning which is ANDed in the
final stage - second level, ok. In that case you again you are taking double complement.
And then you are using De Morgan’s theorem.
(A + B).(C + D).(E + F) = (((A + B).(C + D).(E + F))’)’
= ((A + B)’+(C + D)’+(E + F)’)’
So, this is one NOR gate; this is another NOR gate; this is another NOR gate, finally, a
three input NOR gate combines all of them and you get a NOR-NOR level representation.
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So, similarly for this particular example, we have one NOR bank followed by another final
NOR output stage, and we can get the same result - ok.
(Refer Slide Time: 27:01)
So, to end, we just take note of one interesting aspect of the circuit level realization. Actual
electronic circuit that we using - it is just you know, it is an entity which is just taking up
some input voltage and generating some output voltage. So, for example, an electronic
circuit which takes up A and B as input, input to - it is, digital electronics switching is
involved - so, input is only logic, only voltage level or high or voltage level low. So, these
are the two cases that are there. So, basically this high or low that you are sending. So, this
is low and this is high - ok. And the corresponding output is also generated which is either
low or this is high. So, this is also similar - the possibilities, right.
And the circuit that we are having has got these characteristics. So, if input is low and low,
the output voltage is also low; input is low and high output voltage is high; high and low,
this output voltage is high; and high and high, this output voltage is high - ok. So, if we
consider high voltage as 1, binary value 1 and low voltage as binary value is 0 - ok, then
we can get this - can be converted to a table like this 0 0, low low - 0 0, output is 0; low
high - 0 1, output is 1; and so on and so forth - ok. And corresponding - the truth table that
we get is that of OR operation - OR logic operation. Isn’t it?
So, when high is associated with 1, high voltage is associated with 1, and low voltage
associated with 0, we say that what we are following is called - is positive logic. In our
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discussion before now and in future also, we’ll primarily deal with positive logic - ok, but
we need to take note of negative logic. And we will use it as it - occasion arises, ok. So, in
the negative logic, what happens? It is just opposite of it. So, a high voltage is treated as
logic low, and a low voltage - high voltage is treated as binary value 0 or logic FALSE
and low voltage is treated as binary value 1 or TRUE - ok.
So, in that case the low, low becomes 1 1 - ok, because low is 1 and low - this is 1. So, low
high is 1 0. And the output is high means here high voltage, means binary value is 0, so
this is 0 ok, so then 0 1, 0; 0 0, 0. So, if you just look at this table - ok, we can see that it
matches with AND truth table only thing - that 1 1 is written in the beginning, it does not
matter truth table all possible combinations we are talking about whether you write 0 0 in
the top or 1 1 in the top - the meaning and significance remaining remain the same.
So, same electronic circuits - same electronic circuit the box that you see here which
generates a high or low voltage depending on the low and high voltage presented at the
input, we get the corresponding - these values ok. So, the same circuit is positive OR gate
and the negative AND gate - ok. The same way for any other circuit you can see there is a
inter connection. The same circuit we can - which you can treat as a positive OR, AND.
NAND and NOR gate, following negative logic this notation this understanding - we can
have equivalent AND, OR, NOR and NAND gates. So, basically this is the thing that you
can get - ok. So, this we shall keep in mind and if we require you can make use of it in our
analysis.
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(Refer Slide Time: 31:03)
(Refer Slide Time: 31:05)
So, with this so we conclude that taking OR of minterms, canonical SOP form can be
obtained. And taking AND of it you can get POS form and the maxterm and minterms can
be obtained from truth table as well as by algebraic manipulation of a Boolean expression.
And the canonical form can be converted from one from to another. And 2-level SOP
realization can be done through AND-OR as well as NAND-NAND. And POS realization
can be done through OR-AND as well as NOR-NOR. And same hardware can provide
negative logic based realization with an alternate interpretation of high and low voltages.
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Thank you.
140
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 10
Karnugh Map and Digital Circuit Realization
Hello, everybody. In the last class we had seen how to convert a truth table to a Boolean
expression; for which we had seen minterm based SOP, sum of product presentation
representation and maxterm based product of sum representation. And, we are also seen
how to realize it using AND bank and a finally, OR gate for SOP realization and OR bank
and a final stage second level OR gate for POS representation. And, also we had seen
NAND-NAND and NOR-NOR equivalent circuit for them.
Now, if you want to have a more simplified or minimized realization of a truth table, do
you need to go for algebraic simplification of the minterm based or maxterm based
expression that you have got? Or we can we have a better method?
(Refer Slide Time: 01:13)
So, Karnugh map gives us a very convenient method to simplify a SOP or a POS based to get a SOP or PO based POS based expression. So, we shall discuss this thing in this
particular lecture, how to simplify. First we shall look at the how to represent a truth table
in the form of a Karnaugh map and then we shall also look at use of don’t care in Karnaugh
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map simplification taking upon example and then we shall look at dual circuit and selfdual function.
(Refer Slide Time: 01:47)
So, in the Karnaugh map based representation what we do actually; the truth table we
present in a different manner. The truth table we had earlier what you have seen that there
are A if it is a two-variable truth table. This is Y. So, 0 0, 0 1, 1 0, 1 1 - 4 possibilities are
there and corresponding function output that you see over here, ok.
Y = F(A,B) = ∑ m(2,3)
So, in the Karnaugh map presentation for a two-variable case we are having a rectangular
space like this, where this side is variable A and this side is variable B. The values represent
0 and 1 for B this column represents always B remaining 0 and this column represents B
always remaining 1. And this row represents A remaining 1, this row represents A
remaining 0. So, at the cross point you have got a combination or specific combination of
A and B. So, this particular place is a combination of 0 0, this is 0 1, this is 1 0 and this is
1 1.
So, all the four things that you see in the truth table are represented in the Karnaugh map
in their respective location, ok. And, in terms of minterm, if you look at it in terms if
minterm, then each of this spaces if there is a presence of 1, so, A bar B bar will be the
corresponding minterm, A bar B will be the minterm over here, A B bar will be the
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minterm over here and A B will be the corresponding minterm. And, also we also already
know how to represent a minterm in terms of it is decimal suffix. So, this is your m0, this
is your m1, this your m2 and this is your m3, clear?
So, this is how we look at it two-variable representation of a Karnaugh map and this will
be extended for three and four variable multi multivariable cases. And, if we a look at the
truth table that we had seen before that is over here before that the another truth table which
is the simpler only two 1’s are there. So, the corresponding output you can see that the
function output 0 0, this is 0, 0 1, this is 0 output is 0 - 1 0, this 1 and 1 1, this is 1, right.
So, this is what we can see as going as a mapping and the one that we had seen before 0 0
it is 0 and rest of the three 0 1 it is 1, 1 0 this is 1 and 1 1 this is 1, this we have already
seen. So, this truth table when gets map to Karnaugh map it would looks something like
this, ok.
Y = F(A,B) = ∑ m(1,2,3)
Now, if you look at this representation and the kind of logical connection between input
and output, what we can see, that in this truth table it is evident that the output is 1, output
is 1 when A is 1 and output is 0 when A is 0 irrespective of value of B, isn’t it?
(Refer Slide Time: 05:09)
You can see that A is 0, output is 0. These two cases and A is 1, output is 1. So, you can
see the corresponding when A is 0 this was the 0, A is equal to 0 case, right. So, both are
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0 and A is equal to 1 both are 1, ok. And so, from the truth table we can see that the Y
follows A. So, we can write Y is equal to A. So, which is nothing, but where this row A
remains at value 1, irrespective of the B changing from 0 to 1. So, B bar means here it is
0, B means it is 1 respective of the B changing for value A remaining 1, output is always
Y at 1.
So, we can see and output is 0 for a remaining 0. So, we can write Y is equal to A by
looking at these two value which can be put together, grouped together. So, you look at
this any presentation. So, again this 1 1 is present, right. So, this particular group can give
us whatever if this 1 was not present right A minimized version of A which had been the
case otherwise as AB bar plus AB this two minterms AB bar and AB and we can you know
it is well understood that from complementarity, we can get A (some problem), ok. So,
this is A, right.
So, this A comes over here, right and if your this was not there only B this particular these
two 1’s were present; that means, this one and this one right, ok. So, this is the case when
B is - these two cases are present. So, you can see that when B is 1, the output is 1, right
and these two can be grouped together and by which if in absence of this we would have
got a B, Y is equal to B. So, these two can be summed together and we can see that there
is a, I mean, these two can be put together and we get Y - A plus B, Y - A OR B
representation.
So, this is something which we can compare with what we have done in the past and the
basic relationship and the truth table. But, can you have a generalized rule or method by
which we can group these things? We do have such method, ok.
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(Refer Slide Time: 08:11)
So, for which we look at SOP simplification rule which is taking forward this discussion.
So, for that we look at first a three variable representation of the Karnaugh map. So, for
the three variable representation of the Karnaugh map we have got three variables A, B,
C.
So, on one side you have got C at 0 and 1 which is similar to what you had seen before
and this side we have got AB. So, four possibilities are of AB 0 0, 0 1, 1 1 and 1 0. So,
now, you remember that after 0 1 you are not going to 1 0 we are going to 1 1 because we
are looking for a logical adjacency between two neighborhood positions, two neighboring
position, two adjacent positions, which will help us in forming groups, right.
So, by logical adjacency we what we mean is that between two positions only one value
will be changing one of the A, B, C value will be changing. So, this particular position you
see 0 0 1, this particular position is 0 0 1, A bar B C bar and here next one is sorry, this
particular position is 0 1 0, next one is 1 1 0. So, only A is changing from A bar to A. So,
if it was 1 0 then two values would have changed A would have changed as well as B
would have changed which we are not allowing here to have a better opportunity or better
way of, convenient way of, forming the formation of the groups. This we need to take note
of when we form the Karnaugh map for three variable, the other side is the same.
Now, if you look at one example. So, this is the example of a function where the minterms
are 2, 4, 5, 6, 7 and we can here again the corresponding minterms, the m0, m1 we are not
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writing in this manner we are just writing the decimal equivalent of it. So, 0 0 0 this is 0,
this is 0 0 1 is 1, then 2, 3 because AB bar 1 0 is coming over here so, 4, 5 is here, right.
And, then 1 1 0 is 6 and 1 1 1 is 7. So, the minterms are like this. This was the minterm
suffix mention of those things. So, here 2, 4, 5, 6, 7 so, 0 1 2 - 2, there is a 1 present over
here, right and 4 5 6 7, 4 is here, 5 is here, 6 is here and 7 is here, ok.
Y = F(A,B,C) = ∑ m(2,4,5,6,7)
So, that way the truth table is converted to three variable Karnaugh map, is it clear? Right.
Then how we found the group? We will look at largest logically adjacent group of size
which is in integer power of 2. So, integer power of 2 is what? 2 to the power 0, 2 to the
power 1, 2 to the power 2, 2 to the power 3 like this, ok. So, that means, size of 1, 2, 4, 8.
So, these are the different things that you are looking for in while forming the largest
group, ok. So, and they should be logically adjacent, right and it in the form of a rectangle
like this which is very clear here and while talking about logically adjacent, more we shall
discuss little later.
So, the groups that we can form here you can see this is the group of 4, largest group of 4
that we can form and this is another group that we can form over here which covers all the
1’s, right. So, in the SOP realization all though 1’s need to be covered, and each group will
give us one product term the way you had seen in the previous example. So, one was giving
A and other was giving B and we had a summation of A and B to get Y is equal to A plus
B for the second example for the two variables case we have seen before.
Y = A + B.C’
So, here this particular group when you are looking at so, the product term that will come
out of it we shall see which variable is remaining constant within the group; that means,
which is not changing, right.
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(Refer Slide Time: 12:57)
So, if you see within this group C is changing from C 1 to C along this direction and along
this direction B is changing from B to B bar B bar to B right. So, only A is not changing.
So, this product term will have only one variable which is A and other variable since it is
changing it is not to be there. So, this will form one product term and this is another group.
In this group again we shall see which is not changing. So, we see that B is not changing
right and C is not changing and remaining with the value C bar. So, this will generate a
product of BC bar, right. And, we know that for this particular group A is changing from
A to A bar.
So, together when you sum it up we get A plus B C prime that is the SOP realization of
this particular truth table - ok. So, whenever … if you put it in the form of a rule; so, largest
logically adjacent group of size 2 to the power i that is integer power of 2 we shall see,
minimum number of all groups to cover all ones, ok. Each group will give one product
term. Variables remaining constant form the product term that we have said and if it is
variable remaining constant with a value 1, ok, it will be unprimed and if it is 0 it will be
primed, ok. So, very well remaining constant here with say 0 - C prime. So, … will go
there and B B over here remaining with 1, so, only B is going as unprimed or un
complemented and all product terms are finally, summed clear.
So, this is the way we shall form the SOP with the Karnaugh map based simplification.
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(Refer Slide Time: 14:41)
Now we can extend it to four-variable Karnaugh map, ok. So, for four-variable Karnaugh
map we shall be having a rectangular space where 16 different possibilities, 16 different
locations will be there, ok.
So, you can see one side is AB, another side CD. So, this side is AB and this side CD. So,
AB is having value 0 0, 0 1, 1 1 as I said because you want logical adjacency after that 1
0, right. Similarly, for CD 0 0, 0 1, after that 1 1 because of the need of the logical
adjacency and then there is 1 0, ok. So, the corresponding minterms the suffix the decimal
equivalent will be 0 1, since it is 1 1 here so, 1 0 over here. So, 2 comes after 0, 1 that is a
is 2 over here and then 3, 4, 5, 6, 7 here because of 1 1 presents present here 8, 9, 10, 11
and 12, 13, 14 and here, there is a 15 ok. So, that is the four-variable Karnaugh map the
minterms there…where are their position.
Y = F(A,B,C,D) = ∑ m(0,1,2,6,8,10,13,14)
So, if you take this example so, in these example we have got minterms 0, 1, 2, 6, 8, 10,
13, 14 just one example.
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(Refer Slide Time: 16:17)
So, 0 over here, 1 this is 0, 1, 2 right then 6, 6 this is 3, 4, 5 this is 6, ok. Then this is 7. So,
this is 8, 9 this is 10, ok, then this is 11, this is 12, right and this is your 13 and this is your
14, ok. So, all the minterms are represented in the truth table, are in the Karnaugh map.
So, you can see these their presence now you have to form the largest group of size 1, 2,
4, 8 I mean depending on how you can associate logically these groups.
So, what we can see these four ones can be group together, right and how what product it
will generate? The variables that are remaining constant; so, C and D are remaining
constant C with the value 0 .. no, C with the value 1 and D with the value 0. So, CD bar
will be the corresponding product term, right. And, A are B A and B are changing along
this group, ok. Then the other group that is possible we can see over here this is the other
group this yellow you know background. So, for that A bar, B bar and C bar; so, this is
what is remaining constant, and D is changing from D to D bar over this particular group.
For this is one it cannot be grouped with any other. So, this is all the variables come into
picture ABC prime D, AB C prime D. So, AB from this side and C by C prime D from the
column side, ok.
Now comes interesting part which I was saying that while these are evident we need to
take note that the one that are in the edges. So, in the edges say this particular one, this is,
this location is AB bar, C bar, D bar and you look at the other one this is this is A B bar C
D bar and this one is A B bar C bar D bar. So, this is this location, this is this location, ok.
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Now, between these two locations what do you see that A B bar C bar. So, this is A B bar
D bar and only the C is changing from C to C bar, ok. So, only one variable is changing.
So, though they are physically not adjacent, but they are logically adjacent. So, if nothing
else is there only this one and this one is present; that means, this one and this one is present
… we can form a group of these two.
And, what will be remaining constant what term it will be there A B prime C prime because
D is changing. So, that will be the corresponding term. So, that way all these four corner
terms B one that is shown with these you know brown this thing they can be grouped
together and the term that is remaining constant for them you can see is B prime; B prime
is constant for all these corners right and also D prime is constant. So, B prime and D
prime is the other term. So, this is valid for three variable and you know problem as well
if we look at those Karnaugh values we can see a logical adjacency.
Y = F(A,B,C,D) = B’D’ + CD’ + A’B’C’ + ABC’D
So, ultimately the four terms that we … product terms we sum it up and we get the
corresponding Karnaugh map representation.
(Refer Slide Time: 19:53)
So, now we look at the use of don’t care in the Karnaugh map, ok. So, what do you mean
by don’t care? So, some of the input combinations which is of no interest to us; for example
if you have a design problem where the input to a circuit is binary coded decimal; that
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means, only decimal number of coded with binary. So, decimal numbers input is 0 to 9.
So, the binary coding is 0 0 0 0 to 1 0 0 1 these are the inputs. So, for that whenever the
input is odd, ok; that means, 1, 3, 5, 7, 9 the output will be high otherwise the output will
be remaining low.
Now, for this code variable inputs when you from the you know Karnaugh map and all.
So, there are 16 possibilities. So, beyond 0 to 9; that means, 10 to 15 the decimal equivalent
you do not have, you know, you do not need to care because those inputs will never come.
Input is mentioned as a BCD input binary coded decimal input. So, we write in SOP this
in the minterm with representation. So, m minterms 1, 3, 5, 7, 9 and these are the don’t
care 10 to 15 are the do not care. And in the truth table though they go as a X; X means it
could be you know either way, 0 or 1 you don’t care actually ok.
So, in the Karnaugh map mapping how it will reflect? So, in the Karnaugh mapping so,
wherever your these minterms 0 1 2, this is 3, this is your 5, this is your 7 and this is your
9, those 1’s will be present rest are 0 up to 0 to 9 and 10 this is your 8, 9 this is 10, 11, 12,
13, 14, 15. So, these are all do not cares, ok. So, now how you form the largest size group;
so, to start with if you do not know how to handle the don’t care and all you are a bit you
know circumspect.
Y = F(A,B,C,D) = ∑ m(1,3,5,7,9) + d(10,11,12,13,14,15)
So, you may ignore them and you just try to form largest group possible with the help of
with the two covered all the ones. So, in that case the largest be possible over here is this
is one and this is another one that I said to the edges they are logically adjacent and you
get for from this one A prime D and the other one you can, B prime C prime D. So, this is
the expression that you will get. But, when you do that effectively what you are doing you
are considering this don’t care as 0 is it not? Since you have not covered it if you just put
the value say 1 0 1 0 that is your decimal 10 the output here generated will be if you just
substitute those values Y will become 0, right. So, effectively you are treating them as 0,
while we have the option of treating it as 0 or 1 because you do not care, right.
So, if you consider the X as don’t care that you can include consider it as one if it helps
you in forming the larger largest larger group size of integer part two, then you can go
ahead with that when you doing that you can see this three don’t care condition can be
considered as 1 and a larger group size can be formed. And, one particular group can cover
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all the ones, because there is the necessity that all the 1’s need to covered and in this
particular group you can see that only D remains constant and rest of the things A, B and
C changes. So, Y becomes D, ok. So, whenever it is convenient we shall use don’t care as
1; that means, if it helps in making a larger group size. And it is also evident if you look
at this truth table this is your D and this your Y, right.
So, you look up to 1 0 0 1 this particular case right and we see whenever D is 0 output is
0, D is 1 output is 1, D is 0 output is 0, D is 1 output is 1,. So, this is also evident from the
way if you know the truth table is formed, ok.
(Refer Slide Time: 24:19)
Now, this can be used for POS; that means, product of sum representation also. So, for
that we look at some examples. So, the example that you have seen for the three-variable
case 2, 4, 5, 6, 7, now for from maxterm point of view where 0s are to be covered, ok. So,
the maxterm are 0, 1, 3. So, these are the maxterms that are needed to be covered. So, these
maxterms when you cover it you will find this is 0 0 that is remaining constant for this
particular group. So, 0 for maxterm representation we know, whenever 0 it will be go as
uncomplemented and whenever it is one it will go as complemented.
Y = F(A,B,C) = ∑ m(2,4,5,6,7) = ∏ M(0,1,3)
So, this is sum term that is from here is A plus B and in this case A is remaining constant
with 0. So, A will become A go uncomplemented and B is remaining constant with 1. So,
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sorry C is remaining constant with 1 so, C will go complemented C bar ok. So, these are
the two sum term which will, if you just AND it, you will get the minimized POS
representation. And, if you look at from distributive law if you apply you will get A plus
B plus C prime which we got for the SOP based minimization where we considered all the
1s.
So, what we saw for a don’t care condition so, similar thing can appear for this don’t care
condition in the POS representation also. So, the same example that we had seen before;
so, the 0s that represents the maxterms so, 0, 2, 4, 6, 8 even positions they are zeroes. So,
that is, those are the maxterms and 10 to 15 are the don’t care values. So, this is what you
see over here this 10 to 15 remains the don’t care value.
Y = F(A,B,C,D) = ∏ M(0,2,4,6,8).D(10,11,12,13,14,15)
Now, you have to form the largest group of zeros, ok. So, here again at the edges we have
logical adjacency. So, the largest group that can be formed is by considering this and this;
and over here what remains constant? You see that only D remains constant with a value
0 and for SOP POS representation the remaining constant with the value 0 means it is
uncomplemented version will come in to the sum term that is formed and only one sum
term is formed, I mean, there is no other term and other variables. So, X is equal to D, ok.
So, the rule says to cover all the all the 0s variables remaining constant from the sum term
1 is prime and 0 is unprimed, product of all sums terms are generated considered and next
is considered 0 wherever helps; helps in forming larger sized groups ok.
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(Refer Slide Time: 26:57)
So, a dual circuit is something which is useful that we would like to discuss in this context.
So, the kind of circuit that we had seen before that was two-level in presentation consulting
all the maxterms. Now, in the in that particular consideration we had seen for any SOP we
can convert to NAND-NAND in any POS can convert to NOR-NOR irrespective of
whether it is a minterm based representation or a maxterm representation by using De
Morgan’s theorem of first kind and first theorem and second theorem for two respective
cases. This we discussed in the last class.
So, here also if we take up, we look at this particular example. So, this is one particular
truth table, ok. So, this is the corresponding NAND-NAND representation, that is fine. So,
if you want to get this particular truth table the representation using NOR-NOR, ok. So,
basically you are talking about POS representation, right. So, POS representation we have
to consider all the 0s and we get the directly the NOR-NOR circuit from this by the
discussion that we had before. Another way of looking at it is first, you consider this was
Y, you consider Y prime, ok. So, Y prime is what - its inversions. So, wherever there was
0, it will be then be 1. So, these are the cases.
So, the corresponding circuit that you get over here by considering these two groups A
prime B and A prime B C prime D, is it not? This is A prime B C prime D. So, this is what
you get and this is your A prime B, ok. So, from that you get the corresponding NANDNAND circuit instead of AND, OR circuit. Now, if you look at this particular circuit
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NAND can be converted to from this your De Morgan’s theorem A bar plus B bar, so that
means, bubbled OR. So, this is what you are doing this NAND gate becomes a bubbled
OR gate ok. So, this is NAND gate is also becomes a bubbled OR gate; that means, A bar
these are in inverter that is put in the before the OR gates. So, these inverters can be brought
over here so, A becomes A prime becomes A and B becomes B prime, ok.
So, now, these bubbles over here can be brought to this place, ok. So, that this becomes an
OR gate and finally, this output Y it was Y bar. So, if you take another bubble inverter of
it becomes Y, ok. So, this becomes your POS representation by simply converting this
particular circuit with the other circuit where NAND gates are converted to NOR, NOR
will be converted to NAND and complement all inputs and outputs. So, these over the
inputs, you see, ok. These inputs are complemented and complement all the output. So,
this is also output that is getting complemented.
So, this is the way you can get a dual circuit. So, from NAND you can get NOR and NOR
you can get NAND; that means, NAND is replaced by NOR, NOR is replaced by NAND
and complete all outputs and inputs are complemented.
(Refer Slide Time: 30:07)
So, the last slide of this is a particular discussion. So, there is something called self-dual
function. So, what is a dual function? Dual function is something where if you change the
AND with OR and OR with AND what you get is the dual of the given Boolean function.
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F(A,B) = A.B’ + A’.B
FD(A,B) = (A+B’).(A’+B) = A’.B’ + A.B
F(A,B) ≠ FD(A,B)
So, if this is the would function, then a given function it is dual represented in this manner
is this place of AND you are putting a OR and in place of OR you are putting a AND, and
this is AND. So, this is OR, ok. So, if you simplify then you get this one. So, obviously,
you can say that these two are different. So, these are not self-dual this is dual and the
function is different which is possible ok, but if you look at another function say AB BC
and CA, AB plus BC plus CA, ok.
This is the one and again you take dual of it; that means, change AND to OR and OR to
AND. You get A plus B ANDed with B plus C ANDed with C plus A and if you simplify
it you get back after the simplification stays steps the same function. So, this F D and this
F AB they are self dual, ok. So, if you change the AND and OR there is no difference for
such functions. So, when we can when a particular function becomes a self-dual? So, is
there is any rule? Yes, there is. So, for that let us look at their truth table.
F(A,B,C) = A.B + B.C + C.A
FD(A,B,C) = (A+B).(B+C).(C+A) = A.B + B.C + C.A
F(A,B) = FD(A,B)
So, if you look at the truth table of the one where it was not - self-dual. So, this is what
you get this is the one ok.(Sorry, there is some issue today.) Anyways, we can find out that
these are the two minterms that are there. And, if you expand the this particular case the
corresponding minterms are A prime B C, AB prime C, ABC prime and ABC, and this
case a A prime B and AB prime - right.
Now, one thing that is required for a function to be self-dual is that it needs to be neutral;
that means, the number of minterms will be same as number of max terms. What does it
mean, that number of 0s in the function output will be same as number of 1’s in the function
output. So, if it is a two variable case two 0s and two 1’s; three variable case four 0s and
four 1’s. If it is not satisfied then it is not, cannot be a self-dual function, ok. So, that is
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first condition, but that is not sufficient is a necessary condition not sufficient. So, another
requirement is the function must not contain mutually exclusive minterm, ok. So, what do
you mean by mutually exclusive minterm?
(Refer Slide Time: 33:03)
So, if there is a minterm like A, B, C, ok; its mutually exclusive minterm is A prime B
prime and C prime. If there is a minterm like A prime B C it is mutually exclusive be A B
prime and C prime, ok. So, this is its mutually exclusive minterm. So, they should not be
part of the, mutually exclusive term, should not be part of the Boolean expression then it
will not be self-dual.
So, in this particular is you can see that A prime B C its mutually exclusive term is A B C
prime. This one, its mutually exclusive is A B C prime ok, but A B C prime is not part of
is this minterm is not there. So, these A B C prime is where? Here.
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(Refer Slide Time: 33:57)
Sorry, A; its mutually exclusive is A B prime C prime ok. So, where is A B prime C prime?
So, this is A B prime C prime. So, this is 0, ok. So, that way you can see that this particular
function is self-dual because it satisfies both the cases, ok. So, anywhere it will be
wherever you see some such cases if you examine if you can find self-dual function and
for which if you just change the AND and OR the circuit will I mean look different, but
the function output will remain the same, but without any alteration in the input-output
relationship, ok.
(Refer Slide Time: 34:43)
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So, with this we conclude.
(Refer Slide Time: 34:45)
And, to summarize the logical adjacency is key to Karnaugh map based representation and
simplification. In SOP simplification all 1s need to be covered with the minimum number
of largest integer power of 2 sized logically adjacent groups. In POS its coverage need to
be done for 0s and don’t care conditions at the input side can be treated as 0s or 1s
depending on whether it helps in getting a larger sized looks and then minimize the
expression. And, duality at circuit level can convert from AND-OR to OR-AND and for
self dual function changing and or we get the same function and does not make any
difference, but from requirement of AND and OR gate, may become different, ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology Kharagpur
Lecture - 11
Karnugh Map to Entered Variable Map
(Refer Slide Time: 00:20)
Hello everybody. We are into week-3 of this particular course. So, in this particular
lecture, we shall have a quick recap of what we discussed in week-2. And then we shall
discuss five-variable Karnaugh map, and entered variable map for SOP simplification
and, POS simplification will also be discussed.
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(Refer Slide Time: 00:37)
Very quickly in week 2, we have seen that logic circuit operation can be represented by a
equivalent symbol, a Boolean expression like if it is a AND circuit, then Y is equal to A
B, truth table the different combinations of the input generating a specific output and also
through timing diagram. So, different kind of you know timing input combinations of the
digital waveform high and low will come, and accordingly output will be generated. And
we also saw that NAND and NOR can be considered for universal logic circuit as a
universal gate for different kind of logic circuit generation.
Then we looked into Boolean algebra. The basic premise of Huntington postulates and
certain theorems, and then we found that using that we can simplify Boolean expressions
and can have more efficient realization of digital logic circuits. And given a Boolean
function, we can convert it to a particular logic circuit for each operation we have a
specific logic gate associated, and we just implement one by one, and then the final
circuit is obtained.
We also saw that canonical SOP - sum of product representation using minterm, and
canonical product of sum representation using maxterm can be realized easily by two
level circuits. Two level circuits for SOP was AND and OR alternately NAND-NAND
circuit can also be used, and for POS the basic circuit is OR and AND direct from the
equation we can get, and then also, we can, we found that it with little bit of
manipulation, we can realise that by NOR-NOR circuit as well.
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We also looked at the concept of negative logic and dual circuit and found its use. And
finally, we ended the last week with a discussion on Karnaugh map based simplification
ok. So, any truth table how it can be mapped into a Karnaugh map, and then that
Karnaugh map can be used for simplifying SOP and POS representation. And also you
looked at don’t care input, and how that can be used for minimizing the circuit.
(Refer Slide Time: 03:10)
So, in today’s class before into discussing entered variable map, let us see if the number
of variables under consideration is five - ok, we have discussed Karnaugh map up to
four. So, now we are looking at these things these Karnaugh map for five-variable
representation - ok.
So, now we are in a bit you know difficulty, because for five-variable representation up
to four-variable we had a two-dimensional plane, we had considered 0 0, 0 1, 1 1, 1 0 on
one side like this, and this side also 0 0, 0 1, 1 1 and 1 0. And then we had considered
logical adjacency even at the edges and so on and so forth. But, when it becomes fivevariable, so number of the sales this number of this square boxes is 2 to the power 5 ok,
so that is 32.
So, now, this 32 the finding logical adjacency, this is a bit difficult. And one perhaps
required a 3D visualisation to understand how the is adjacency is established. So, what
we show here is a reflection map based five-variable simplification. So, in the reflection
map based, this side - this side remains what it was earlier for four-variable, and the
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other side here we are representing the remaining three-variable out of five-variable.
So, CDE three-variables are there. So, C is 0 0 C D E is 0 0 0 for this particular column
the first column ok. Next one is 0 0 1 and so on, then next one is 0 1 1, and after that 0 1
0. And this vertical line over here, the vertical line over here - this represents the axis
against, which a reflection is done ok.
For example, so these 0 1 0, it is reflection against this means, this 0 becomes 1 for the
value C. 0 1 1, it is reflection is 1 1 1 reflection means 0 and 1 that this is getting a
reflected I mean the 1 1 remaining the same 0 and 1 is. So, between then this cell 3 and 7
there is a adjacency, because only one variable is changing that is C. Similarly, this is 0 0
1 and this is 1 0 1. So, this 1 and 5 is also adjacent.
So, wherever you see a reflection along a about this axis ok, and the corresponding
positions are logically adjacent. So, this is the way we have to visualise this one - ok. So,
there can be another method, popular method, which is called overlay method, where
here this one this is 0 0 0 the first cell what here 0 0 0 0 0 all values are 0. So, in this case
the C value will be only changing to 1. So, this will be 0 0 1 0 0 this particular position
this particular square box.
So, as if this I mean both are just lying one above another ok, and the adjacency is drawn
across the overlay or vertical direction. So, in this present example the present method, it
is about the reflection about a particular axis in the overlay method just one above
another. So, we shall discuss only one of this method, which is the reflection map based
method.
The other one is similar just the adjacency first needs to be considered through just one
line above the another and from there, so because of this the numbering, the minterm
numbering in the specific cell is what you see over here 0 1 2 3 is the more more
significant bit here, and E is the least significant in terms of the binary representation that
we are showing. And then this is 4, 5, 6, 7 - 8, 9, 10, 11, then this is 12, 13, 14, 15.
Then there is a jump, because there is a 1 0. So, 16, 17, 17, 18, 18, 19 and this is 20, 21,
22, 23 is it fine ok. So, this is the way this minterms the 32 minterms will be represented
here ok. And the positions here is showing that D is remaining one over this four cells this four columns that means, total 4 into 4 16 a is remaining one for these two rows
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these two rows, this row and this row, so 2 into 8, 16, so that is the thing that you see for
other variables ok.
(Refer Slide Time: 08:17)
So, we take up one example to help us understand how this five-variable Karnaugh map
can be used for simplification of Boolean expression. So, in this example we are taking
up minterms 2, 6, 9, 11, 13, 15, 18, 19, 22, 23, 25, 27, 29, and 31 - ok. So, what is the
first job, since we already know since we already know from the previous discussion that
how this minterms are placed.
F(A,B,C,D,E) = ∑ m(2,6,9,11,13,15,18,19,22,23,25,27,29,31)
So, accordingly wherever those minterms are there, we are placing the 1’s ok. So, 2 - 0 0
0 0 1 0, so 2 is the minterm so 1 is placed here ok. Next is 6, so 0 0 1 1 0, so 6 is over
here you can see 6 is over here, so corresponding 1 is placed. So, accordingly all the
minterms, the specific positions - the 1’s are placed in the five-variable Karnaugh map
ok.
Now, after that we need to do the grouping. And in doing the grouping, we need to
consider logical adjacency. And logical adjacency in the neighbourhood region, which is
easily - clearly visible as well as D 1 that is coming through the reflection the one that
we just discussed. So, the one that we can see, which is a group of four we can see over
here, it is a group of four this there is a group of four.
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Now, about this vertical axis, you can see this or just you know reflection of one another.
So, they remain - they are logically adjacent. So, these four and these four, that this total
eight, they form one particular group. And they - that will contribute to one product term
ok. And in this particular group, which variable is remaining constant, you can see B is
remaining constant - ok. And the other variable that is remaining constant over here is
you see E, E again here E and E. So, this is also remaining constant. So, for this 8
minterms, B and E are remaining constant. So, the corresponding product term that will
get generated is B E - is it clear?
Next we look at remaining, I mean all the 1’s we need to cover through the largest sized,
which is size is integer power of two number of groups ok. So, next is this one, and this
one let us consider this one. So, these two 1, and the other two 1, they are because of the
reflection they two are neighbour and can be grouped.
Again we have already seen before that this at the edge, and this is at these two are at the
edge, they are also neighbour. So, these 1, this two 1, and this two 1 they can also be
considered as one group. And in the in that particular group, we can see what are
remaining constant B is remaining constant with a value 0 that will contribute to B
prime. And D is remaining constant with one, this is one - in both the places. And E is
remaining constant with 0. So, B prime D, E prime is the corresponding product term ok.
Now, what is left? So, this 1, 2, 3, 4 and the other 4 plus 4, 8 are covered. So, what is left
is - this one and this one. These two 1’s are not yet covered. Now, to cover that we can
see that we can I mean one thing that is clearly visible is that a group like this can be
found with you know logically adjacent four 1’s. And this particular generates a term A,
B prime. And D is remaining constant, so this product term will it will get generated.
The other thing which is not very apparent; but, again if we consider the reflection, we
can see that these two are logically adjacent easily understood ok. But, again against this
particular axis, they are one is reflection of the other ok, so that way also this group up to
this group of two, they are logically adjacent. So, accordingly a group of four can also be
formed, which is of similar size of the - as the previous one what we considered over
here and this group of four, if we just put them together right. So, this is this four
members together, you can see that A, D, and E, these three are remaining constant over
here. So, this one and this one can be covered by either of these two term ok. So,
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accordingly you have got B E right B prime, D prime E, and A prime, A B prime D or A
D E. One of these two as representation of the minimized expression of this five-variable
function through Karnaugh map - is it clear? So, similar thing we can do for previous
presentation as well.
F = B.E + A.B’.D + B’.D.E’
Or
F = B.E + A.D.E + B’.D.E’
(Refer Slide Time: 13:50)
Now, what we look at, we shall come back to this problem little later. What we
understand by entered variable map, before which we shall discuss what is entered
variable ok. So, entered variable is if you look at a truth table of three-variable as you see
here A B C, and the corresponding function output is Y, so a truth table is generated out
of it - ok, where the output is retained as a function of one of the variable, which is the
entered variable - ok.
F(A,B,C) = ∑ m(2,6,7)
So, in this case we look at two examples for the same truth table. In one case we see C as
the entered variable - ok. So, (Refer Time: 14:34) when we see C as the entered variable,
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we look at how the output function changes with respect to change in C, when other
variable other variables remain constant. So, other variables here are A and B, so A and
B remaining constant with value say, 0 0. So, what are the two positions in the truth
table? These two positions are in the truth table 0 0, 0 0 for A and B, and C is changing
from 0 to 1 over these two rows ok. So, we pair it in this manner. So, this is for A B, 0 1,
this pair is for A B, 1 0, and this pair is for A B, 1 1 ok. So, for each of these cases for
each of these cases, we get one entry into the truth table, where the variable is entered the variable is entered.
Now, we consider at this point that for this particular pair, how the output is changing
with respect to C. We see that output is remaining constant 0 irrespective of change in C
input variable, output is not changing - ok. So, Y is equal to 0 in this case. In this case,
what is happening? If C is 0, Y is 1; if C is 1, Y is equal to 0 ok, so that means, it is just
complement Y is output is complement of C. So, Y is equal to C prime for case cases,
where A B is 0 1.
And next case again we see that output is not changing, remaining value remaining
constant with the value 0, so Y is equal to 0 and this is Y is equal to 1. So, accordingly
this truth table is found, where a variable you see C prime has entered ok. So, if such is
the case in another place C can be there or another place, I mean depending on the truth
table the. So, there is a possibility of a variable entering into the mapped entered,
variable entered truth table - ok.
F(A,B,C) = B.C’ + A.B
So, instead of C, if we had a different variable say for example A entering into the truth
table ok, so A is the entered variable. In that case, what would have been the way the pair
would have been formed? So, in this case since A is entering, so B and C remaining
constant that is what you have to see so, B and C remaining constant four possibilities - 0
0, 0 1, 1 0 and 1 1 ok.
So, in for these cases four cases, we see the order the corresponding pairs, where A is
changing from 0 to 1. So, A is B C 0 0 is this one, so the colour is matched here. So,
these two cases the B C is 0 0, corresponding value A is 0 here one is A is 1 here. And
what is the value of Y at that time, Y is remaining 0. So, Y is not changing remaining
constant with 0, so Y is 0, so that way if B C is 0 1, B C is 0 1 over here, so this will be
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pairing with this one. And you see that A is changing from 0 to 1, what is happening to
Y, Y is remaining 0 so Y is remaining 0.
So, similarly for next case is equal to 1. And last one for B C is equal to 1 1, this case,
these two the these two rows. So, A is changing from 0 to 1 and at the time Y is also
changing from 0 to 1. So, Y is just following the A, so at that time we are writing Y is
equal to A - is it clear, how we are entering a variable similarly. We could have entered
B, we could have you know instead three-variable, four-variable and all the process
would have been similar. So, forming a pair and finding a relationship and accordingly
coming up with the truth table - ok.
(Refer Slide Time: 18:37)
Now, how it is useful in - how it can be used in simplification alright entered variable.
So, now entered variable map that we are talking about - in this the variable will be part
of the Karnaugh map ok, it will be included in the Karnaugh map. So, before that let us
look at the normal simple Karnaugh map based you know simplification that we have we could have done for the same example. So, this is the example right, the one that we
have taken up. And these are the two you know groups that is possible right. And the
corresponding product term that is available is B C prime and A B.
Now, we can also think of this as B C prime, the product term that is generated
multiplied by 1, ANDed with 1 any minterm that is there. So, the corresponding value
ANDed with 1. And if the minterm is not present, the corresponding input variable
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combination ended with 0, so that is why it is 0. So, this is the way also it can be
visualised with no, you know, loss of meaning. So, if we look at this way, then it will be
clearer how we are getting a SOP entered variable map based simplification. So, the truth
table that we have just seen, we are simply mapping it to a - that was a three-variable
Karnaugh map, I mean, there were eight locations eight cells. Now, since one variable
has entered A and B are the variable against, which the map is form. So, this is a four
cells are there. And in the cell we will be having entry of 0 1 and the variable - ok. So,
these are the likely members variable and it is complement form, these are the possible
members ok. So, for the same problem the present problem, we have this as the entered
variable map - ok.
Now, for the simplification, so we have to form the largest group, where all the 1’s and
the variables need to be covered, all the 1’s and the variable need to be covered. So, what
we see over here? So, there is a 1, this is the 1 - ok, so there is no other one. So, this one
is covered ok. So, this one is covered how, this A is there with a value 1, and B is there
with a value B 1. So, A B is the term, and we are considered it is just it is ANDed with 1.
So, A B is one term that will get generated - ok.
Now, we see there is a term C prime, C complement, C bar - ok. Now, this C bar we can
take this as A bar, B ANDed with C bar that is also fine, that is also is, Boolean algebra
wise expression wise, it is correct, but it is not the minimised expression. So, to get the
minimised expression, we can consider this 1 as 1 plus C prime also - right. So, there is a
hidden ok - implicit C prime here without any making any difference in the meaning of
the entered value. So, this C prime and this C prime, they can be combined together, and
for which B is remaining constant with a value B. And the variable that is entering, we
are simply ANDing it with the value that is remaining constant, which is B here.
So, B C prime is the corresponding term that is getting generated. So, same truth table
with entered variable map considering A, we shall see this is the corresponding map.
And for minimization again with one we are getting the B and C prime ANDed with 1.
And for A, we can consider one as 1 plus A without any difference in meaning, and that
will generate B and entered variable is A, so A B so B C prime A B. Here this is the way
B C prime, and A B and we get the same expression. Now, we take into note one
interesting point here that the 1 that we have seen here, which we are writing as 1 plus C
prime or 1 plus A to get a minimised expression ok. The same 1 can be written as C plus
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C prime also - right.
So, if we have a hypothetical truth table like this for the for which the entered variable is
what you see ok. Then your this 1 this C part can be combined with this, and C prime
both can be combined over here. And we do not need a separate coverage of one,
because the components that are making one C and C prime, they are individually
covered by these two groups - ok. And that will generate you a B C prime plus A C,
which is a minimized expression and no separate coverage of 1 required is it ok, so that
is what we take a note of in minimization using entered variable map.
F(A,B,C) = B.C’ + A.C
(Refer Slide Time: 24:00)
The same thing can be used for POS simplification, product of sum simplification, the
same truth table. In this previous case, we consider that it is getting wherever there is a
minterm present, it is getting ANDed with 1. Minterm absents means, it is the
corresponding input combination is getting ANDed with 0, so that is why it is not there.
So, in this case the sum term whenever is present ok, we can consider that it is getting
added, summed with the 0 ok. And if it is not present, then it is getting summed with 1
ok, so that is the way so 1 means just it the corresponding maxterm is not available ok.
So, the corresponding POS simplification so, again earlier we considered 1 as 1 plus C or
1 plus C prime -right or C plus C prime, so this is the way. So, here 0 can be considered
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as 0 AND C prime 0 AND C or C C prime ok. And accordingly, we can use it for
forming a larger group, if it is so possible.
So, in this case what we see these 0s can be combined together, these two 0s for which B
is remaining a constant with a value 0 ok. So, B remaining constant with a value 0 means
B, uncomplemented will be coming as the sum term right. And here the other group that
can be form 0, so 0 can be considered 0 C prime. So, A is remaining constant with 0, so
that is A prime will be there and B C prime is already there, so that is the way you get
the corresponding term; so, similarly for the other case ok.
F(A,B,C) = B.(A + C’)
(Refer Slide Time: 26:06)
Now, to end we look at the example with which we started, the five-variable example.
So, the five-variable example, now we would want one of the variable to be entered. So,
we will consider the variable E is equal to entering into the map. So, when variable E
enters, so then we will be forming pairs the way we have seen, so this is the adjacent
columns ok.
F(A,B,C,D,E) = ∑ m(2,6,9,11,13,15,18,19,22,23,25,27,29,31)
So, 0 and 1 is changing the rest of the values are remaining constant A B C D 0 0 0 0.
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And accordingly the corresponding output how Y changes with E that is mentioned here.
So, Y is not changing with E for the first case Y is remaining 0, Y is just opposite of G
complement, you know the complement of so 0 1 1 0. So, this is E bar, and accordingly
we have all the positions covered - ok.
(Refer Slide Time: 27:03)
So, with that we look at the five-variable representation of the truth table that we had just
seen ok, where E is one of the entered variable. So, with E entered variable in the
respective places, now the five-variable now has become 4-variable problem ok, which is
now which is more convenient. So, this is one of the advantage that it reduces by a the
number of cells reduces by a factor of two, I mean, it is divided by 2. So, 32 now
becomes 16 ok. So, 16 is a more manageable proposition four variable Karnaugh map
ok.
So, in that case these are the way the variables are entering here right. And then this is
the largest group with E contained for which B is remaining constant, so B ANDed with
E the variable that has entered ok. Then what is remaining to the covered this E prime
and 1 1 ok. So, if this 1 1 can be considered as E plus E prime, so with that one group
can be found that is this 1 1 can be considered in this manner right, so that is one group.
And this E prime will go there that is another group that is one possibility, another is
only it can be considered as 1 plus E prime right. So, each will each of these cases is
considering four possible I mean, three literals in the expression.
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So, in one case this is B prime, D prime, and this remaining with 1. And E is remaining
with E is variable that is entering, so B D E - is it fine? This is SOP. So, the one that is 0
will be corresponding prime term will be there right. And one if you consider this
particular block, so this is coming as A and D right, D is remaining constant, A is
remaining constant, and E is the entered variable that will cover.
And if this E is not included. only 1 is considered, then A B prime and D ANDed with 1
right. So, this is the these two 1’s can be covered this two 1’s can be covered as 1 plus E
or E plus this one can be covered as 1 plus E or E plus E prime right, so that way you
have got two possibilities. the way you had seen before ok.
F(A,B,C,D,E) = B.E + A.B’.D + B’.D.E’
Or
F(A,B,C,D,E) = B.E + A.D.E + B’.D.E’
(Refer Slide Time: 29:55)
So, with this we come to the conclusion of today’s class that is, this particular class. So,
simplification of 5-variable function using Karnaugh map requires that 3D visualisation,
whether it is reflection map or overlay for by which the adjacency can be found. For the
map entered variable, variation of output with respect to the entered variable is
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considered for cases when other variables of the function is remaining constant. In SOP
realization each one and the entered variable complemented or uncomplemented need to
be covered.
And POS, it is 0 and those entered variables need to be covered. And for EVM entered
variable map based SOP minimization 1 can be considered as 1 plus the variable 1 plus
x, 1 plus x prime, x plus x prime. And for POS, 0 can be considered as 0 ANDed with x,
0 ANDed with x prime or x x prime by which the minimization can be made more
efficient.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture - 12
Quine - McClusky (QM) Algorithm
Hello everybody. In the last class, we looked at five-variable Karnaugh map based
simplification, and also for … also entered variable map based simplification ok.
(Refer Slide Time: 00:27)
So, in this particular class, we shall look at QM algorithm-Quine McClusky algorithm,
which is also useful for simplification purpose. And we shall look into its important steps
that is, finding prime implicants, finding essential prime implicants, and from that
forming minimal set, and also use of don’t care in QM method.
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(Refer Slide Time: 00:48)
So, the QM algorithm - the steps, important steps are, first we shall look at getting the
prime implicants. Implicants are the product terms, when we say prime implicants, then
these are the product terms, which cannot be combined with any other product terms. So
that means prime implicants are having least number of literals for the minterms it covers
ok. So, this is cannot be further grouped with other product term.
And then from that finding essential prime implicants to cover all the minterms of a truth
table, and then from these findings getting a minimal set to represent the given function.
So, these are the different steps. And we take note of that finding this prime implicants,
this goes through a iterative process for which a computer based approach or algorithm
or programs are available or people write.
And for large number of variable - minimisation of large number of variables, these
corresponding functions, it is very useful ok. So, to understand how it works - let us look
at one example the example is very simple, it is a four-variable example. So, we shall
later compare with the Karnaugh map based simplification also how it works and all. So,
this is having minterms 0, 1, 2, 3, 10, 11, 12, 13 and 14 ok.
Y = ∑ m(0,1,2,3, 10,11,12, 13,14,15)
So, the first step as I said is to find prime implicants. And to get prime implicants, it goes
through as I said, iterative process, so let us first look at the stage-1 of the process. So, in
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the stage-1 of the process what we are doing, we do a grouping of the minterms in terms
of input variable combinations. So, input variable combinations - the first group that we
are having is those minterms, where no 1 is present in the input combination. If such
minterm exist, it will be there will be such a group form; otherwise it will not be there.
So, since in this example 0 is a minterm that is present right. So, 0 0 0 0, this
combination is present, so it is there ok. And there is only such one such possibility that
none of - no 1 is present, so that is why, there is only one member in this particular group
ok.
So, next we from another group with those inputs those for with for those minterms,
where the inputs are having only one 1 in their combination. So, 0 0 0 1 this is present,
so this is there. 0 0 1 0, so it is there. So, the other input combination, where there is only
one 1 is 0 1 0 0 that is 4. But, 4 is not a minterm in this example, so 4 is not present so 0
1 0 0 is not present.
The other option is 8 ok. So, one triple 0, so that is also 0 over here that is not a minterm
ok, it is not here in this particular you know example. So, it is also not member. So,
wherever it is a minterm is present, then corresponding value - it is available in this
particular group ok.
Now, next group we will be forming as you understand, that is why I said it is a iterative
process, in that sense, also in the way we are forming the groups. So two 1’s - two 1’s
will be present. So, two 1’s are present for the minterms, which is 3, 10 and 12. This way
you can see three - this is there right, other two 1’s that is present here is 5 for 5 is 0, so it
is not member ok. So, we have to consider the one that are present. So, 3, 10, 12 are
there. So, similarly three 1’s are present ok.
Next group that is 11, 13, 14; and last all four 1’s are present if 15 is a member, if 15 is a
minterm, then it will be there. So, it is for four-variable case. So, five-variable, sixvariable case, then there will be more such groups with four-variable combinations, with
combinations of four 1’s with combination of five 1’s combination of six 1’s and so on
so forth, it will continue - is it fine?
So, this is we - by this we get these stage-1, the one first arrangement of this QM
algorithm. And in this case the - other than what has been mentioned here, since the way
the minterms are appearing their order of appearance has changed. So, we just write the
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corresponding decimal value alongside in the right hand side to make sure that all the
minterm has been properly included from here. So, no minterm should be left, so that it
does not you know go out of our attention, so we are also writing it in this manner - ok.
(Refer Slide Time: 06:11)
So, from that we go to stage-2. So, in the stage-2 what we do, we form groups again the
way we have done before, but in a little bit different manner. So, we take adjacent
blocks, why adjacent blocks we shall tell later; so adjacent blocks of stage-1. And then
we see among the members there - the input combinations the minterms, where I mean,
they just differing by one position ok. So, we form a pair of them like 0 0 0 0 and 0 0 0 1
input combination is you know just changing the D position 0 to 1, and A B C remaining
same as 0 - all 0, so that is only one change is there ok.
So, we take up this as a member that goes into the next stage-2 first block - ok. And the
place where D is changing, we put - on the variable that is that position where the value
is changing, so that we put as a dash. Dash means, what is the physical significance of it?
That whether D is 0 or 1, dash is kind of you know, don’t care that a minterm is
produced that means, A B C is 0 0 0; D is 0 or 1 ok, there are minterms. So, two
minterms are there for D is equal to 0, A B C remaining 0 all remaining 0 and D
remaining, D being 1 A B C all remaining 0, so that is the physical significance or
meaning of it - ok.
So, similarly 0 and 2 we can combine, because only C position is changing. So, 0, 2 is
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the next member of the block, so these are the only possibilities. Now, can this first block
be combined with block-3? For this particular consideration that only one position will
be changing we cannot, because we know in the first block there was only 0.
And in this particular block two 1’s are there. So, they are differing at least by two
positions - is not it? These two positions are - they are differing. So, this - so because of
which you just cannot, so this block this block, so subsequent blocks are differing at least
by two positions - not one position. So, they cannot be grouped with this particular first
block ok. So, we are not considering them - right.
Now, we look at whether this block and this block can be combined, and what are the
different possible ways. And for that, we see this one can be combined with three,
because A B and D are having values 0 0 1 respectively, 0 0 1 respectively. Only C is
changing from 0 to 1 over here, so we write 0 0 dash 1 in this particular case. Again see
this physical significance is the same that for A B and D 0 0 1, respectively; C whether 0
or 1 there are two minterms available in the truth table - ok.
So, similarly these 2 and 3 can be combined, 2 and 10 can be combined, so this is what
we can see? Can 1 and 3 be combined sorry 1 and 10 be combined? So, this is 1 and this
is 10 right. So, we see this is 0 and 1 they are changing 0 0, they remaining constant.
Again 0 and 1 that is changing, and 1 and 0 is changing. So, more than one position it is
changing. Is it all right? So, for which we cannot have 1 and 10 combining the way we
have seen that only one position that is changing in place of that we shall put a dash rest
of the values will remaining constant - remain same ok.
So, next we see that this block and the other block ok, how it can be combined only as I
said, adjacent blocks are required. So, this 3 and 11, so 0 0 1 1 and this is 1 0 1 1 - only
one value is changing. So, it can be combined. So, the first value that is there which that
position is only changing, so that will be a dash and rest of the values are 0 1 1 ok.
So, similarly if we keep examining all right - appropriate codes, so it will be having this
particular groups found ok. Similarly, for combining these two blocks in the stage-1 of
stage-1, where only one position is differing, we have 11, 15; 13, 15; 14, 15 these are the
combinations found, and accordingly they are called the representation is mentioned here
ok.
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Now, one more job is left in stage-2. So, when you do the combination, we look at
whether every member of stage-1 has been part of a group of stage-2 ok. If it is then we
put a tick mark against it, if it is not, we keep it unticked that it could not be combined.
For a particular function or a truth table it might be so possible that it is not able to
combine, because it is not changing in one position ok. So, it will not be ticked, so it will
just remain there. So, what is its significance, we shall discuss little later.
(Refer Slide Time: 12:07)
So, we have completed stage-2 as I said it was a - it is a iterative process, so we move to
stage-3. And what we will do in stage-3, we shall look at adjacent blocks of stage-2 right.
And we see - we shall see whether they can be combined following the same principle
that is there are two members are differing only in one position ok. So, let us see whether
it is possible or not. So, 0 1 - 0 0 0 dash and 1 3 - 0 0 dash 1. Are they differing in one
position, only one position? No, 0 0 0 0 this is fine, 0 and dash, and dash and 1 ok, so
because of which we cannot combine these two, because it is differing in two positions ok.
Now, 0 0 0 dash and 0 0 1 dash. Can these two be combined yes why, first two are 0 0. D
is D position is dash only C position is changing in one case it is 0; in the other case, it is
1. So, this is a candidate. So, corresponding term will be 0 0 dash was already there. So,
this 0 1, now a dash is coming over here. And the term corresponding term is 0, 1, 2, 3.
So, this is going in the stage-3, is it fine? So, 0 1 is going in the stage-3, 2 3 is going in
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the stage-3, we can put tick mark against them right. Next 0, 2 and 1, 3 can be combined
right.
Similarly, if we look and examine 0, 1 and 2, 10 whether they it can be combined or not,
we see that it is differing in many places. So, 0 dash is differing 0 0 is not differing, 0 1
is differing, and dash 0 is differing. So, three places it is differing. So, they cannot be
combined ok. So, once this part is done - between these two adjacent blocks, we shall
look at these two blocks. And between these two blocks, we can see that 2, 10, 3, 11 - 2,
10 3, 11 they can be combined. And rest of the combinations are not possible, because it
is not it is differing more than one places ok. And 2, 10 3, 11 dash 0 1 0, and dash 0 1 1.
So, 0 1 is and dash is same 0 and 1 this is only changing, so that is a dash over here
which is coming here - ok.
And finally, between these two blocks ok, so these are the different possibilities if we
just examine the same way, we shall get it the 10, 11, 14, 15 and 12, 13, 14, 15 they are
there and the corresponding terms are this - ok. So, 12, 13, 14, 15; if we just take an
example say here and 14; so 1 1 0 dash and 1 1 1 dash. So, 0 and 1 that is only differing
in this position and this position, so we put a dash ok. So, we can examine one member
against the other, and we can do it, and if we writing a code, then we can write a code for
that - ok. See in doing that we see that 0, 1; 2, 3; 2, 10; 3, 11; 14, 15; 12, 13 all the
members have found a place in the next blocks. So, each one of them is ticked - is it ok?
(Refer Slide Time: 16:03)
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Now, finally when we are - we have reached stage-3, we shall look at what we shall look
at whether we can move to stage-4 by combining this right. So, if that is the where they
differ only in one place is there any such case, so if you look at 0, 1, 2, 3, and 2, 10, 3,
11, so if you compare these two ok, so 0 and dash it is differing 0 0 not differing, dash
and 1 it is differing, dash dash it is not differing.
So, two places it is differing zero dash this position A position and C position. So, they
cannot be combined ok. So, whether 0, 2, 1, 3 and 2, 10, 3, 11 can be combined. If we
examine this and this ok, 0 dash A position it is differing, B position not differing, C
position it is differing, D position not differing ok. So, it is differing here, and it is
differing here. Again two positions - it is differing. So, it cannot be further combined
only one position, it should change to become a member of a group in the next stage.
So, similarly over here if you look at 2, 10, 3, 11 and 10, 11, 14, 15 whether they can be
combined just for example, so this is different - A position is different, B position is
different, C and D are same ok, but A and B are different, so because of two positions
differing again they cannot be further combined. So, we can combine - examine each one
of them. And see that none of this can go to the next level, and because of which there is
no stage-4, and also none of this member over here is ticked - ok.
Now, each unticked term, now we understand the significance of this unticked term. So,
each unticked term is a member to contribute to prime implicant generation. So, each
unticked term will generate a prime implicant - ok. So, here all these will be coming
from this stage, but if any previous stage there is a unticked term ok, so that has to be
brought forward in the final prime implicant the that has that we get out of this exercise
ok.
So, in this example so these are the four prime mutually exclusive, because you see 10,
11, 14, 15 and 10, 14, 11, 15 they are the same they remain the same, so that is 1 dash 1
dash. So, they are not essentially different. So, basically these are the four terms that we
get, which will contribute to the prime implicant formation ok.
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(Refer Slide Time: 18:51)
So, all the three stages combined together, it would look something like this the one that
you see - right. Earlier we had shown it at a separate manner. But, when you work it out,
you can just keep on you know adding tables and columns and all till it converges. The
convergence is guaranteed, because you can see in each of this cases the number of this
blocks the groups are coming down from stage-1 to stage-2, stage-3, it was you know 1,
2, 3, 4, 5 here, 4 here, 3 here right, so that way the one, I mean, the extreme scenario will
be that all are dash A, B, C, D, E all are dash that means, it does not matter, the output is
1.
So, Y is equal to 1 ok, so that is one extreme case that you can see that irrespective of
any change in the value. So, all input becomes kind of you know do not care any value
whether it is 0 1 any combination output is 1 ok, so that is the you know kind of meaning
one can bring out for such cases, but it converges I mean it cannot go beyond that.
Otherwise, the convergence we had seen the where that after stage-3, it cannot be further
grouped. So, it does not go to stage-4 ok.
So, this is how it will (Refer Time: 20:04). So, this is the PI table this is called the PI
table, and the corresponding terms that we get this 0 0 dash dash and the terms. So, the
way we define it wherever there is a 0, we write is as A prime corresponds to A, and corresponding to B, so 0, so it is B prime ok. So, the corresponding product term
representing this prime implicant is A prime B prime. And the minterms that is covered
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by it is 0, 1, 2, 3.
So, B C - B is remaining constant with 0, and C is remaining constant with 1. So, B
prime C is the corresponding prime implicant. A is remaining constant with 1, and C is
remaining constant with 1. So, A C is also the A C is the corresponding prime implicant.
Finally, 1 1 a for A and B, so this is A B is the prime implicant. The minterms that are
covered, we can see at this - side by side it is mentioned ok, this is understood how we
are getting. So, the first step is getting prime implicants, and through a - through an
iterative process the way we have described so far and for these example we arrive at
this.
(Refer Slide Time: 21:23)
Now, we have got the prime implicants, we have got the product terms, if we just sum
them up algebraically, we will get Y which is correct, I mean there is nothing wrong but
whether it is giving way minimal set or not, it is not yet ascertained ok. To ascertain that
we shall look at next stage, which is next step, which is called as finding essential prime
implicants.
What does it do? In essential prime implicant table, we are looking at the requirement of
the coverage of all the minterms by the prime implicants that we have got in the previous
step through the prime implicant table. So, the minterms that need to be covered for this
specific example as 0, 1, 2, 3 - 0, 1, 2, 3, 10, 11, 12, 13, 14, 15 that are the ones that you
can see right.
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And then we write the corresponding prime implicants that we have got, and what are the
minterms that are being covered by them. So, the coverage by A prime B prime is 0, 1, 2,
3; B prime C is 2, 3, 10, 11; A C is 10, 11, 14, 15; and A B is 12, 13, 14, 15 is it fine. So,
this is the way we get the prime implicant table - right. So, this corresponding tick marks
are there.
Now, the way we look at this essential prime implicant table, and the corresponding you
know, these prime implicant – is a essential prime implicant. So, A prime B prime is a
essential prime implicant - is an essential prime implicant understand this point, because
if we remove, if it is not considered, then 0 and 1 minterms will not be covered. The
same way - 12 and 13 is covered only by A B and not by any other prime implicants. So,
A B is also an essential prime implicant, so this is there.
Now, when A prime B prime, and A B and A B, these are included, these are this need to
be considered in the SOP form right. So, what is the minterm that remain yet to be
covered, they are 10 and 11 they are 10 and 11, because A prime B prime, and AB are
covering 0, 1, 2, 3 12, 13, 14, 15; so to cover 10, 11. We have got two terms with you
know same similar complexity, if we consider that the inputs are available in
complement and uncomplemented form, so one is B prime C, another is A C ok.
So, one is covering 10, 11 as well as 2, 3; another is covering 10, 11 as well as 14, 15, so
we can take either of them - ok. And we can get one set of you know essential prime
implicant using this - a minimal set like this, another minimal set like this ok. So, this is the two possibilities, these are the two solutions that we can get out I mean two possible
solutions with similar complexity from the QM algorithm for the given example.
Y = A’.B’ + A.B + B’.C
or
Y = A’.B’ + A.B + A.C
And we can examine whether this is or not by the K-map based simplification that we
are already familiar with. So, the minterms if we map it in the K-map, this is how it
would look like ok. And one group A prime B prime comes over here, A B comes over
there ok. And the remaining two 1’s that need to be covered, this is 10, 11 in the
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Karnaugh map, you know this is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, so this is the 10 11. So,
10 11 can be grouped to like this particular one, or this one, the way it has been seen ok,
two possibilities are there. So, in one case will get A C, another case it will get P prime
C. So, one of them need to be considered, so that 10, 11 remain covers remain covered,
and A prime B prime, and A B must necessarily be present ok.
(Refer Slide Time: 25:52)
So, how we find the QM algorithm based simplified expression, if there is a don’t care
case, so do not care means in at the input side we do not care. So, we know this X by
which we are presented them in the Karnaugh map. So, what we do the method is simple,
these do not care we considered as minterm in the generation of prime implicants ok.
So, when you do that there is a possibility of getting largest sized group ok, and we
exclude it, when the coverage is required, in the finding of minterm coverage is required,
in the finding of essential prime implicant, this is what we do ok, and by which we can
ensure a minimised or simplified expression. So, we can take this example, which is just
a variation of the example that we have taken. So, 0 1 is the don’t care, earlier we
considered minterm as 0, 1, 2, 3 up to 14, 15. Now, we are considering minterms are 2,
3, 2, 15, and 0, 1 are the don’t care.
Y = ∑ m(2,3,10,11,12,13,14,15) + d(0,1)
So, in the first stage as I said 0, 1 will be considered as minterm to find the prime
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implicants. So, the prime implicants that we had got in the previous example will be this
one in this particular example as well. So, the prime implicants we shall get are this A
prime B prime, B prime C, A C, and A B by the same method.
Now, in this example, because 0 1 is something which need not be covered ok, it is don’t
care. So, 0 1 is excluded, you see 0 1 is not over here, we are starting from 2, 3 2, 3, 10
to 14 ok, so accordingly it has been written. And what we see in this essential prime
implicant formation that B prime C, and A B between themselves 2, 3, 10, 11 and 12, 13,
14, 15 all the minterms are getting covered - ok.
Y = A.B + B’.C
So, the minimised expression, we get is A B plus B prime C. So, this is what we do in
case of QM algorithm based this method ok. And we are not discussing similar thing for
POS, but we have already noted that from the dual circuit thing. So, we can find A prime
for say this example, so we can get we can get F prime, where this will be one, and this
will be one, and rest of the things will be 0 by which we can get the expression ok.
And then we take the compliment the dual of it, dual of it means AND becomes OR, OR
becomes AND, and the input, outputs are complemented. So, F prime we have
considered, so output becomes F - F ok, and inputs will just get complimented, and then
AND becomes AND, OR becomes AND means, we will get the POS representation - ok.
(Refer Slide Time: 29:14)
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So, to conclude QM algorithm based simplification first identifies prime implicants.
These are the product terms, which can may not be combined with any other product
terms, so it represents a least number of literals. And essential prime implicants are the
PI, which together cover all the 1s of the truth table. And minimal set with essential
prime implicant is arrived at for the function or getting the function -final function
output. Don’t care conditions are included in finding prime implicants, but excluded in
finding essential prime implicants for incompletely specified truth tables having don’t
care. And this is useful for computer based simplification of a Boolean expression.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture - 13
Cost Criteria and Minimization of Multiple Output Functions
Hello everybody, we are in lecture 13 of this particular course. In previous classes, we
have seen how to minimise the logic expression and get an implementation for single
input cases.
(Refer Slide Time: 00:32)
So, in this particular class, we shall look at multiple output minimization. And we shall
see that there are many different possibilities, and we have to weigh one option against
the other for which we need to define certain cost criteria. So, we shall begin this
particular lecture by defining certain cost criteria and then we shall look into the
minimization aspect.
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(Refer Slide Time: 01:00)
So, the kind of implementation we had seen before we start from there.
Y = F(A,B,C) = ∑ m(2,4,5,6,7)
So, this is a representation of a truth table where the minterms are 2, 4, 5, 6, 7 ok, this is
familiar we had already solved this particular kind of minimization problem before. And
in the SOP case, we have the realization where one minterm comes from here which is
A, and another minterm comes from here which is B C prime - ok, this we have seen
before.
Y = A + B.C’
So, in the SOP realization we have Y is equal to A plus B C prime in this manner right.
And for the same truth table, we can have a POS representation for which we are having
two such sum terms one is A plus C prime, another is A plus B ok.
Y = (A + B).(A + C’)
Now, if you want to realize this in the form of a circuit for each of the operation, we have
corresponding logic gate available. So, we consider that the inverter - inverted input
complemented and un complemented, both type of input is available if it is not the case
we can consider it separately. So, we have a two level logic implementation.
So, in this case, we are having two gates; one gate is the OR gate combining A, and the
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other A and BC prime. Another gate is an AND gate which is denoting BC prime fine.
And compared to that we are having A plus A or B generated by this one A or C prime
generated by this one. And this and gate is combining these two outputs of the OR gates
- ok.
So, if you look at the complexity and say that - which one is more costly costlier
implementation, of course, this one is the POS is the cost is a costlier implementation in
this case it is very clear, very evident here - is not it? So, we look at the number of inputs
and you know number of logic gates that are used here ok, but it may not be the case, so
simple we need to for more complex circuit specially for multiple output minimisation.
So, for which we look at defining certain cost criteria.
(Refer Slide Time: 03:32)
So, one definition is that of literal cost. So, literal cost is the number of times a literal
appears in complemented or uncomplemented form in the Boolean expression ok, so that
is what is known as literal cost. So, if we look at the previous example, so how many
times it is appearing A, B and C prime complemented or uncomplemented, both are you
know - to both are to go as literal cost, so 3 right. In this case, A, B, again A, again C
prime, so four times literals are appearing. So, literal cost is 4 that is how the literal cost
is arrived at.
Next is gate input cost. So, compared to literal cost, gate input cost gives a better
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appreciation of the complexity of the circuit that is getting implemented - ok. So, in the
gate input cost, the number of inputs to the gates in the implementation that is getting
that gets counted. So, in the previous example, in this example, how many this SOP
realization how many is the gate input cost, so 1, 2 over here, another here. So, these are
the 3, this is 3 (Correction few paragraphs later: 2 input to AND gate and 2 input to OR
gate i.e. total gate input cost is 4 and not 3). And what is the gate input cost for this POS
representation 1, 2, 3, 4, 5, 6. So, these are 6 ok.
So, here we are not counting the inverter NOT gate ok. So, if you count the NOT gate,
then we get another measure one is defined by G another is defined by gate input cost
including NOT gate count ok. So, in each of these cases see one inverter will be coming
here. So, this will become 3 plus 1, and this will become 6 plus 1 ok. If we consider the
inverter or if we do not consider the inverter, these are the two cases that is possible.
G=L+T
GN = L + T + N
Now, we can very quickly without going for the diagram and getting the implemented
circuit logic circuit in place right from the expression, we can get the gate input cost very
easily by considering these two equations ok. See, if the number of terms excluding
single variable term ok, excluding single variable term, because it does not require a gate
is T. And the number of distinct inversions is T, number distinct inversions means that if
a bar is used in two places, it will be only counted once.
A bar as literal is coming in two places distinct inversion required only one inverter one
NOT gate is required, so that is the distinct that is defined by distinct inversion. So, if
that number is T ok, then the gate input cost without considering the NOT gate count is
literal cost plus number of terms ok. So, we can see what is the gate input cost by and
literal cost by from this formula. So, in this example without looking at this gate, so
literal is 3, 1, 2, 3, ABC prime, and number of terms excluding single variable term. So,
excluding single variable term this is a single variable term which have to exclude. So,
number of term is only one. So, 3 plus 1 – 4 is the gate input cost without not gate count.
Is it fine? Right.
So, and we can count here 1, 2, 3, 4, four gates are there four gates inputs are there, in
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the other case how many literals are there four already we have seen right and how many
terms are there are two terms one term one sum term another is another term sum term.
So, 4 plus 2 – 6 is the gate input cost, and you have counted that 6, 6 is the gate input
cost, so that is how we can get just by looking at the expression without going for a
physical realization of the or drawing of the logic circuit we can get the gate input cost
ok. And if we want NOT gate count additionally in addition then we shall at the number
of distinct inversion for this ok. So, this is put in a tabular form here. So, this is 4 and this
is 6 right, and 5 and 7, if we include the NOT gate count. So, mostly it is gate input cost
that is considered in the study.
(Refer Slide Time: 08:20)
So, we look at few more examples. And this realisation and this realisation both are
equivalent ok; they represent same truth table ok. Now, we are not drawing any logic
circuit for them. So, simply by the way we have calculated using that formula, we shall
see what is the gate input cost here. So, number of literals are 1, 2, 3, 4, 5, 6 right, so 6
literals.
Y = A.B + B.C + C.A
Y = (A+B).(B+C).(C+A)
So, literal cost is 6. Number of term 1, 2, 3, so 3, and there is no inversion involved. So,
N is 0. So, 6 plus 3 – 9 is the gate input cost without NOT gate count, and with not gate
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count is also 9, because there is no inverter used. And equivalent representation POS
represented for this is A plus B ANDed with the B plus C ANDed with C plus A. Again
number of literals is 6. You can see number of terms is 3 right, and no inversion, so 9
and 9. So, both are equivalent, in terms of complexity any one of them you can pick up
ok.
Y = A.B.C + A’.B’.C’
Y = (A’+B).(B’+C).(C’+A)
There are again two equivalent representation of same truth table; one is in SOP form;
another is in POS form - ok. Now, how we see; we see how they are you know compared
in terms of the cost that we have just defined. So, literal cost in the first place is 1, 2, 3,
and 4, 5, 6, 6 ok; number of terms 2, 1 and 2 right. And inversion required A prime, B
prime, C prime, so 3 right. So, gate input cost without not gate count literal cost and
number of term 6 plus 2, this is 8. And in the other case including NOT gate count is 11.
And for the other one the previous realization, we have got A prime plus B, B prime plus
C and C prime plus A three OR terms are getting ANDed ok.
So, 6 is the number of literals, three 3 OR terms are there, 3 terms OR there you can see
right. And three inversions A prime, B prime, C prime are required ok. So, your gate
input cost is 6 plus 3 – 9. And this is the 12. So, of course, now we can consider compare
and you can say that this one is a, this one is a less costly realization, is it according to
this definition. So, these are few more examples.
Y = A.B + B’.C.D + A’.B’.D + B.C’.D
So, this is they are not equivalent.
Y = (A+C’).(A+D).(B’+C’+D).(B+C+D’)
Just here number of terms are there 1, 2, 3, 4, 5, 6, 7, 8, 9 for 10, 11 number of literals 11
literals. 1, 2, 3, 4, four terms are there. Inversion B prime, A prime, B prime again and C
prime, but B prime will be counted only once distinct inversion. So, it is 3, so that way
you are getting 15 and 18 for these cases.
Similarly, for the other and when we do this we consider two level implementation, and
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there is no restriction in fan-in or the kind of logic gates that is to be used ok; the way we
actually minimise circuit in Karnaugh map or QM algorithm using Quine-McCaskey
algorithm. So that is what we have that - is what is being considered here. But if there is
a restriction in fan-in if there is a restriction in say the kind of gate that you can use, then
of course this is not the way we have to calculate this one.
For example, if it is asked so this expression Y is equal to AB plus CD ok. So, this is to
be realised. And the restriction put is we have to use only two input NAND gate then
what is the cost ok.
Y = A.B + C.D.E = ((A.B)’.(C.D.E)’)’ = ((A.B)’.((C.D)’)’.E)’)’
So now, two input NAND gate becomes one unit -right. And we can use De Morgan’s
theorem right - successively and we can see that 1, 2, 3, 4 and 5, so 5 two input NAND
gates will be required ok. So, this is the realization.
So, there could be another realization - possible realization. So, we have to compare
against them, and depending on number of units we will pickup with the one which is
less in cost. And here you see the 10 gate inputs are required, two input NAND gates 5
into 2 10 gates. But if you look at the normal two level implementation with no
restriction in fan-in and then the literal cost is A B C D E 5, and number of terms are 2,
so it is 7. So, number of gates gate inputs required, if we go for no restriction two level
implementation is 7, but because of the restriction we are now having 10 gates, but so
and five 2-input NAND gates used in this particular problem.
Now, what is meant by 2-level and 3-level. So, let us look at one more example, I mean
2-level and more than 2-level. So, here we are realising AB CD and CE, AB plus CD
plus CE. So, if you go for 2-level implementation, then how what is the gate input cost 1,
2; 3, 4; 5, 6 6 literal and 3 terms, 6 plus 3 – 9. And you see 9 gate inputs are there 1, 2, 3,
4, 5, 6, 7, 8, 9, 7, 8, 9 right.
Y = A.B + C.D + C.E
And what about this one, we see that if we take C common A B plus C ANDed with D
OR E, this expression. Then C - D OR E getting ANDed ok, - which is OR and then
ANDed with C, and then finally this is. So, this is 3-level implementation right, and how
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many gate inputs are there 1, 2, 3, 4, 5, 6, 7, 8 right. So, instead of 9 we are having 8, so
this is for 3-level implementation. So, our discussion is on 2-level implementation the
way we usually do for AND-OR or NAND-NAND or for POS - OR-AND or NOR-NOR
circuit ok.
Y = A.B + C.(D + E)
Now, another point here in some of the literature, we will find that the total cost an
another new another definition is given for cost, which is number of gate input that is the
gate input cost plus number of gates that are used. So, additionally number of gates that
are used that are also put into consideration, which is defined as total cost in some of the
literature ok.
(Refer Slide Time: 15:27)
Now, we come to the multiple output minimization problem and we will keep this cost
aspect in our mind. And what we see is that – therefore, various possibilities. So, in one
case the first case we look at the problem, where the between two functions that are to be
realized the common term is a prime implicant, prime implicant in both the places.
F1 = B’.C + A.B
F2 = B’.C + A’.B
So, you see this is - these are the common terms between these two functions that are to
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be realized. So, B prime C, B prime C is the common prime implicant - right. And of
course, in this case the decision is obvious. So, if you go for individual realization, so
this is what we will be doing, so B prime C over here, again B prime C is again realized
over there. And then this is the corresponding circuit, which will require 6-gates 1, 2, 3,
4, 5, 6 – 6 gates. And the gate input cost for each one of them is 1, 2, 3, 4, 5, 6 - 1, 2, 3,
4, 5, 6 here also you can count 1, 2 - 1, 2, 3, 4 for literal two terms 6. So, 6 into 2 - 12 is
the gate input cost.
And if you look at the total cost I mean including the number of gates being used, it is
18. And of course, this B prime C is a candidate, which can be the common term shared
term, which can be used for both the places. So, this is the corresponding circuit. In this
case to realize this part, you would need six gate inputs 1, 2, 3, 4, 5, 6 and to realise this
part which is common you need 4. So, 6 plus 4, 10. And the gate count will be total cost
will be also 10 - 3 for this, and the 2 for the other ones, so 15. So, this is very, you know,
simple. In this case, we do not have any issue in coming up with the minimized multiple
input you know solution - right. So this is the minimized solution.
(Refer Slide Time: 17:38)
Now, look at a problem where there is no common prime implicant as such - ok. So, in
this case, so F 1 - , 1, 3 minterms and F 2 has got 3 and 6 is minterm. So, you have got
this two terms if you go for individual implementation A prime B prime, and A prime C,
these are the one that are to be realized ok. And in this case this is common right, but as I
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said, in this particular case this is to be realised, but this is not the term is you know there
in the other case as a prime implicant, it is already covered by the one of the term A
prime C right.
F1 = ∑ m(0,1,3) = A’.B’ + A’.C
F2 = ∑ m(3,6) = A’.B.C + A.B.C’
So, individually if you realise, these are the two terms. And if you calculate the gate
count in this case gate count cost, so for the first one 1, 2 3, 4 and 5, 6 this is the term.
And for the second one 1, 2, 3 4, 5, 6 and two terms 8; so this is the gate input cost, so 14
right. And if you look at the total cost 14, and 3 gates are used here, 3 gates are used
here, so total 20 ok.
F1 = A’.B’ + A’.B.C
F2 = A’.B.C + A.B.C’
But, since the common term over here is to be generated you have no choice, because the
other term requires it - ok. So, there is another way you can realize it, where you are not
generating A prime C over here rather this A prime B C, which is generated that is being
used ok. And in this case, you have got one common term one shared term, which is you
know, being utilized by both the expression.
So, in this case how does it help, it helps by reducing the gate count. In the first case, 1,
2, 3, 4, 5, 6, 7 in the second case, 1, 2, 3 right. And they are two terms 4, 5. So, 7 plus 5
12, because A prime B C is already generated in the first case, right. So, total is 12 and
the total gate count gate cost is 12 and this is 17, so if you compare you can see that you
are in gain - ok. So, it is less costly, so it is to be realised in this manner by this
expression not by individual ok.
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(Refer Slide Time: 20:33)
Now, let us look at another example, where we have got common term - right. But, this
common term is already part of bigger groups, which is already covered ok. So, let us
look at this particular example, what is happening over here. So, between these two this
is F 1 and this is F 2 ok, so between these two you can see this is this two ones are the
common term right.
F1 = B.C’ + B.D + A’.B’.C
F2 = B.D’ + B.C + A.B’.D
Now, these two 1’s can be part of a bigger group (Refer Time: 21:14) 1, therefore if you
go for individual minimisation, this is how you will realize it B C prime B D and A
prime B prime C. So, this is this term A prime B prime C. And another one term is B C
prime, which is coming from here. And the other one is your B D, so this is the term that
we are talking about ok. So, this is how you will get it. And for the second case, this
common term can be part of a bigger group ok. So, this is the corresponding realization
of it, so B D prime B C, A B prime D. So, this is A B prime D ok.
Now, the issue with this is that by making a bigger group, group of four the ones that you
are covering, it is already covered by the previous group one term B C prime over here.
Similarly, by forming this bigger group, you are covering this one this one is already
covered by this you know group of four, which is covered in the blue right. So, there is
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no necessary there is no necessity of you know grouping them in that manner. And
generating two distinct term right, one is B D, another is a B C over here rather you can
generate only one of the term this term, which is B C D and which can be shared in both
the places ok.
If you do if you do does it help in anyway, we can see that it helps in a manner, which is
depicted here if you if you go for individual you know minimization. So, 1, 2, 3, 4, 5, 6,
7 and three terms 10, and similarly the other one is 10 gate input cost is 20. Whereas, in
this case 1, 2; 3, 4, 5; 6, 7, 8 and three terms are there 11 right. In the second case, 1, 2, 3,
4, 5 this is already generated and three terms that is 5 plus 3 eight, so this is 19. So, this
is 20 versus 19 ok.
Similarly, if you look at the total count including the realization in some measure, they
are considering also the number of logic gates that are used, so this is 28 versus this is 26
ok. So, this is a better you know, less costly realization ok. So, this is what we find when
the common term is a part of bigger group, where the members are already covered by
other prime implicants in individual cases - ok.
(Refer Slide Time: 24:06)
Now, we look at the case where don’t care is there ok, and we see that how don’t care
can be considered in the multiple output minimisation ok. So, we have taken two
examples. So, in one example you see that these are the don’t cares this is don’t care for
function 1, and this is don’t care for the function 2 right.
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Now, what we can see that this don’t cares I mean you can you know come up with a
expression like this and this can be a common term the way we had seen before, but it is
better that if you have I mean a combination of this and combination of these rather than,
you know individually going for - because that we generate additional term, could get
this? What I mean to say is that one option is this one right, and this one, this there are
two ones right and then combining with this one, but that will require additional terms to
be generated right.
F1 = B.D + A’.B’.C
F2 = B.C + A.B’.D
So, this is the complexity of you know group of four, this is the complexity of group of
four. And then A third term, which is common of which is of course shared, but which
one we will required is C terms, but in this case what we are having these two terms are
always required, and you are having only one term, which is you know group of four
group of four with same complexity that is only getting generated ok. So, here these
don’t care cases, we are simply ignoring them and we are going in the manner as at as it
has been shown, and by which we are reaching a gate counter gate count cost of 14 and
total of 20 ok.
Now, let us look at little bit more you know complex thing, where the don’t care cases
are this one - right ok. So, again there is a possibility of you know in the minimized
expression having a group of this, a group of this right, similarly a group of this, and a
group of this. So, these are the possibilities right. And if you look compare all those
possibilities, then you can see that considering this one and do not care over here, and
this do not care and one over here, you can generate a shared term - is not it? So, this
term this group is shared.
And similarly, we can generate between these two a shared term and compared to
individual minimisation the way we would have done in this case as I repeat again like
this case right, and over here to cover these all these 1s ok. Compared to that if you
weigh that realization of these two, which is shared realization of these two which is
shared in this manner ok, you find we will find that the relative cost is coming to - in the
first place 18 gate input cost, and total cost is 24.
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F1 = B.C’.D’ + B.C.D + A’.B’.C
F2 = B.C’.D’ + B.C.D + A.B’.D
And if you tried individually, you can see it will go for larger value of 20 and 28 - ok.
So, this is the different way for multiple output minimization using the cost criteria that
we have defined, we can look into it and pickup the one, which is favourable. And this
was for two output. Similarly you can go extend it for three output and this is more
complex, but the concept remains the same ok.
(Refer Slide Time: 28:43)
With this, we come to the conclusion of this particular class, what we have discussed in
briefly. We have seen that comparison of different logic circuit implementation can be
done through defining certain cost criteria. We define literal cost, which considers the
number of times a variable appears in an expression either in complemented or in
uncomplemented form.
And gate input cost considers total number of inputs to different logic gates. And there is
a definition related to total cost, which considers gate input cost as well as number of
logic gates that are used. And consideration of shared terms in multiple functions,
multiple output functions can lead to an overall minimized circuit with less cost. And
don’t care conditions can be useful in deciding shared terms that can be generated for
minimized circuit.
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Thank you.
203
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 14
Static 1 Hazard
Hello everybody. In the last few classes, we were looking at minimization of circuit, a
logic circuit and different methods, different ways. And in the last class also we defined
certain cost, and we were looking for getting a lower cost in terms of hardware that is
being used for realization.
(Refer Slide Time: 00:31)
In this particular class, we shall look at some of the practical issues associated with logic
circuit implementation. And for that how we modify the circuit, which is - which may be
more costly in terms of the hardware use the way we have defined cost, but it saves the
day, it helps in overcoming some of the inherent problems associated with the logic
circuit. And the concepts to be covered, which is related to propagation delay and the
glitch that is found, and we shall dwell on static 1 hazard in today’s class.
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(Refer Slide Time: 01:15)
So, we look at again a very simple problem, the kind of problem we have seen before.
So, this is a minimization of a truth table using Karnaugh map, where there are four
minterms present. And this for this minterm, this one and this one are covered by A
prime C. This one and this one are covered by AB - ok. And there is another way we can
have this 1 and this 1 covered by BC right, but this two 1s are already covered by AB
and A prime C.
Y = A’.C + A.B
So, AB and A prime C are essential prime implicants essential, because they are
covering either this 1 or the other 1, which is not covered by anyone else. And in this
case, BC becomes non-essential, so it is redundant ok. So, the circuit for the equation
that we get for this truth table for minimized expression is A prime C plus AB. And this
is how you realise a circuit ok? We could have a - we could have obtained, we could
have had a BC also associated with no difference in meaning, but that would have
unnecessarily increased the hardware cost ok, because BC means another and gate and
that will get connected ok.
So, this is how we have seen the minimization problems so far and circuit realization.
And in doing this, what we have considered that - I mean, we did not consider the effect
of propagation delay in the logic gates ok, this was not considered. We just went by the
Boolean expression what will give us the minimized circuit ok. So, this is the
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background for - with which we start today’s class.
(Refer Slide Time: 03:22)
But, we note, taken before - that there is propagation delay in a particular logic gate,
whatever logic gate we talk about ok. So, this propagation delay is associated with for
example, now we are looking at it in terms of you know voltage that is presented ok. So,
earlier we were writings 0, 1; 1, 0 and all which is fine, but if you look at input voltage
and the output voltage, so if you were stretching it in time and all actually, we will see
that it is not very sharp kind of you know rise, so there is a kind of you know finite rise
time and finite fall time.
So, in the input side, the time the 50 percent of when it reaches the 50 percent level as a
inverter. And corresponding output that falls, output will go down go low - right, when it
reaches the 50 percent value. This is the propagation delay, which is at the output which
is high to low ok. This is propagation delay at the output for output going high to low.
And similarly, the opposite is low to high that is input is at you know 50 percent level,
when it is going form high to low from that output is going from low to high, when it
reaches the 50 percent level. So, this is propagation delay at the output low to high ok.
So, and this is because of you know usually, they will be little bit different from one
another. Because, if you look at the CMOS, there is a capacitance, we had noted before
load capacitance right. So, this charging path, so this is the charging path and this
charging path is like this right. So, these paths are different.
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Similarly, in this case this is one path and this is another path right. So, there is a small
difference between these two values ok, but average propagation delay is taken - is the
you know we add them up, and then divide by 2 ok. And for TTL, it is of the order of the
you know 10 nanoseconds, CMOS for same you know 5 voltage circuits like that of
TTL, it is of the order of 50 nanosecond. But depends on load and also for CMOS if you
increase the voltage level say, to say 10 volt instead of 5 volt, it will become say 30
nanosecond of that order ok, but that is a finite propagation delay which is to be noted in
this particular discussion ok.
(Refer Slide Time: 06:06)
Now, what is its effect because of this is what happens, because of this we will find in
the circuit there may be glitches ok. And so we will see how it occurs, but before that let
us define what is glitch. Glitches are undesired positive or negative going pulses.
Undesired means, this is positive going pulses and this is negative going pulses.
Undesired means it was not supposed to go, so it was supposed to be you know straight
like this right, but then there is some such thing happening.
And glitch occurs due to finite propagation delay of logic gates and occurs for specific
combination of input. So, for certain specific combination of input only it will happen, it
is not occurring all the time. For another combination, it will not - it may not occur ok.
And glitch is transient in nature; it is there and for a very short duration of the order of
the propagation delay. So, if something in the input is getting changed, so momentarily it
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will occur, and then it will disappear, in the stable state it will not be there - ok.
And the other definition which we need to take note of is called hazard. A logic circuit
has a hazard, if there is a potential for glitch. So, circuit which is hazard free, there is no
such potential ok. There is no such combination at the input some changes for which
glitch will occur, so that is a completely hazard free circuit ok. And a circuit with a
hazard may generate glitch, if those specific input condition or the pattern is presented
ok, so this is we take note of - right.
(Refer Slide Time: 07:56)
And then we shall look into a examples. So, we go back to our or this previous circuit
only, the circuit with which is started, this is the one ok. And this was our reduced circuit
reduced you know relationship optimized obtained at - right, and this corresponding
circuit. Now, we consider a specific case say B is equal to 1, C is equal to 1 ok, so at that
time what will happen, what is the value of the output B is equal to 1, and C is equal to 1
right.
So, in the truth table sorry in the truth table if you look at it, you will find that the B is
equal to 1, C is equal to 1 is one ok, and it is obtained from the equation also. If you just
substitute it here, so A prime 1, 1 A right, so this is the cases you get a A prime plus A
and this is 1, so that means Y will always be 1 as per the Boolean algebra right, so this is
the case.
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Now, you consider that B is at 1, so this is at 1. C is at 1 right, and A goes from 1 to 0, so
A goes from 1 to 0 right. So, when A was 1 in the stable condition before this change
takes place, so this NOT gate output was 0. Now, when A, A goes from 1 to 0, so
immediately this input is becoming 0 at that time point. But, this NOT gate output will
not go to - will not go to 1 immediately because of the propagation delay just now we
had considered in the previous slide. So, it will go to 1 after some time right.
So, for that amount of period, for that amount of period for which this NOT gate output
you know goes from o- utput goes from logic low to high ok. So, till that particular time,
that particular delay - output propagation delay low to high at that time this remains at 0.
So, this AND gate output as a 0, after the of course the propagation delay, it will get the
0, and this will this is already in 0 all right.
So, what we see that OR gate both the inputs are 0, even for small duration after that it
will become 1. So, for that small duration after again it is own propagation delay the OR
gate will generate a 0, which was otherwise 1 - ok, so that is the after that propagation
delay of course, it becomes 1 and then there is no issue. One of the OR gate input is 1
except for that transition period, is it clear?
So, this is the case when it is happening, when we see that a glitch is occurring, for that
with this OR gate output is momentarily going to low ok. But, if B is equal to 1, C is
equal to 1, and A goes from 0 to 1 will there be any issue, will there be any glitch? So,
this is 0 so this is 0. And this is 1 means this is 0 means, this was already in 1, then
change takes place. So, this 0 becomes 1 right - immediately.
But, this 1 is held, 1 will go to 0 after the propagation delay right, but by that (Refer
Time: 11:55) this AND gate output both of them are 1, so this is 1, so OR gate will be
held at 1 there is no issue. So that is what is known - that means, what was talked about
as, for the specific input combination only the glitch will occur. This circuit is having a
hazard this is not a hazard free circuit, because there is a potential glitch, but glitch will
occur only when a specific combination is presented - ok.
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(Refer Slide Time: 12:21)
Now, we define static 1 hazard, what is it? Static 1 hazard is the case when output should
remain - output is to remain at static 1, static at 1 according to Boolean logic algebra the
expression, but glitch occurs under certain condition. So, essentially what we had seen
that somehow the circuit boils down to a condition, which is after you know considering
all the different inputs, you know the values of those inputs an expression something like
this ok, so that is that gives rise to the static 1 hazard ok.
A’ + A = 1
If somehow this kind of expression is there, the and the corresponding realization if you
look at it, if you are having it, in terms you know - circuit in realization, so this is the
essence of it, finally you know it boils down to some a reduced circuit like this ok. There
may be additional gates and all, so those delays will be considered, but this is the basis of
the static 1 hazard that is occurring ok.
So, how again we whatever we just mentioned, if we try to put it in the form of diagram
for this particular circuit so, this is A right going from 1 to 0 over here at this time point,
at this time point ok, and because of this A bar will go high after the corresponding delay
propagation delay logic low to high right.
So, from this point to this point, there is a delay right. And momentarily you see at this
point of time, this and this both are low ok, so because of which OR gate output after it is
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own propagation delay, which is high to low right given by tau-two over here ok. So, it
will go to low, because both of them are low at this point, so this is going to low ok.
So, tau 1 and tau 2 could be different, but as I said in the same logic family we usually
take them as you know same tau and the low to high, and high to low also can be
different, but more or less for this you know depiction, we can show them as same. And
after that, this propagation delay this goes to high, this output will go to high, and
because of which again OR gate output will go to 1 – right, after it is for until remain low
for that period only is it clear ok. So, this is how the glitch is occurring.
(Refer Slide Time: 15:34)
Now, how we can detect you know, static 1 hazard, so is there any rule for that ok. So,
yes there is a rule, there is a method by which we can detect static 1 hazard. And later on,
we shall see if we can cover those hazards, we can make the circuit hazard free ok, but
how we can do that? So, for that we have already noted the Boolean expression, finally
you know reduces to produce a sum you know A plus A prime kind of thing for certain
condition certain specific condition of the input. The other important thing that we can
look at, even you know, without going into an optimized expression or so, just by
looking at the Karnaugh map, we can figure out the way we form the groups whether
there is a potential you know glitch there or not ok. So, how we can find it out?
So, let us look at this example, similar example similar to previous example ok. So, these
are the two 1s and these are the two 1s, so obviously we are forming a group like this,
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these two prime implicants ok. So, is there a potential hazard yes, the rule says if the two
logically adjacent cells with output 1 in Karnaugh map is not covered by a common
product term ok. So, this one and this one are adjacent. They are not covered by one
common product term, it is covered by this is this group is one generating one product
term, this group is generating another product term - is not it ok. So, it is having a
potential static 1, I mean it is having a static 1 hazard - potential glitch under certain
condition it might occur.
So, let us see how it occurs. So, we can write from this Y is equal to B prime C, this one
is B prime C, and this one is AB right. This group is AB, and this is B prime C right.
Now, when AC is equal to 11, A and C are 11. We get Y is -Y is B plus B prime, this is a
case of you know static 1 hazard the kind of thing that we have seen. So, if the input is
111, and then from that it goes to 101 that means, B goes from 1 to 0 the way we have
seen before, then a glitch negative going pulse will be there ok, so that is what we see
from this particular case. We can identify right - this is not covered ok.
Let us look at this example. So, this is an example where you know there are two such
you know prime implicants B prime C and BC prime ok. So, is there any hazard here?
So, there is no logically adjacent cells which is not having a common term. So, this is
these two are logically adjacent a common product term, these two are logically adjacent
common product term ok. And these two are not logically adjacent say this one, this one
not logically adjacent. So, they are not need not be covered ok.
So, there is no such, you know, common term is required. So, this is not having any
hazard ok, because we are in all these cases we are considering only one variable
changing right. And so, if you see that, if you consider say B is equal to 0 right, then this
term will not be there, it is only B prime C, so it will follow if C changes with
appropriate propagation delay output will change accordingly ok. So, there is no such
hazard.
So, these were three variable problem examples, we look at a four variable example. So,
this is the corresponding Karnaugh map of a given truth table ok. So, the way we
optimize - get a optimized expression for this circuit is a group of four over here, and a
group of two, right. So, this is generating you ABC right, this is generating BC and this
is generating A, C prime, D prime this term right ok. So, you just OR them and you get
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the minimized SOP realization, does it have a static 1 hazard.
Let us look at if there is a logically adjacent 1, so this 1 - this 1 and this 1, they are
logically adjacent, which are not having a common product term right. So, there is a
potential static 1 hazard. And when does it occur or which combination, so it occurs this
is the thing, so ABD. So, we can see that AB 11 and between these two what is common
D with 0, so ABD-110. So, this is common between these two 1s right; and C going from
1 to 0 C going from 1 to 0, because we know that from high to low, then there is you
know a static 1 hazard.
So, in that case ABD; ABD remaining A and B remaining at 1, and D remaining at 0,
these are the cases. And C going from 1 to 0, we are having a glitch ok. And also from
Boolean expression also we can find it out right. So, this is just examining that whether
you know, this rule prevails or not, and we can find out the condition also by this way
when the glitch will occur, and so this is how we can detect static 1 hazard.
(Refer Slide Time: 21:59)
But knowing that there is a static 1 hazard - that is not enough. We need to see that we
are able to cover it ok, we are able to cover it and the circuit does not have hazard,
because those negative going pulse or positive going pulse, I mean in this case negative
going pulse for static 1 hazard might cause some you know trigger certain events, which
is undesirable ok.
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So, in the example that we have taken before right; so since it is caused by the - I mean
during the detection process, we have seen that it is caused by the logically adjacent
terms not coming under one you know, one common you know product term - that is the
cause of it. So, the solution is to have a common product term that covers logically
adjacent 1s in the output of a function in a Karnaugh map ok, so that is the solution. So,
in this case the example that we started with right; so this 1 and this 1 did not have the
logically you know have a one common product term.
So, now we look at one common product term that can be there. So, this common
product term is nothing but your BC ok, which we saw there in the first place, but we
abandoned, because of higher cost that was getting associated with it, I mean when we
include it that is a redundant term right. But, in this case when you associate it ok, the
hazard gets covered and we can get a hazard-free-circuit ok. So, this B and C this was the
earlier circuit, now this B and C is coming over here. And how is it helping? So, B and C
11, then only the hazard I mean the glitch was there right. So, B and C 1 and 1, what is
happening this is 1, this is 1, so the output is held at 1 the OR gate any output is 1 is
output is 1 right.
Y = A’.C + A.B + B.C
So, even if A changes from 1 to 0, and you know, there are some changes happening
over here, some changes happening here, momentarily they are becoming 0, this is
becoming 0 for some time, this is becoming 0 for some time ok. So, 1 to 0 A 1 to 0, so
this has become 0, it is still 0 right, it is taking some time to go to 1.
So, this is the time we are talking about when both the outputs are 0 right, it is taking
some time to go to 1 ok. But, these two 0’s even if it is there, this 1 over here is
suppressing the glitch that could have had been in - unless a could have been there had
this output is not there ok, this additional circuit ok. So, yes it is more costly, but it is
reducing, removing the hazard would not costly in terms of you know ordered cost, but it
saves some other cost in terms of performance, where this glitches are - can cause
damage ok. So, this is the thing that we have to keep in our mind.
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(Refer Slide Time: 25:55)
Finally, we look at the other example we had discussed before, so this was the circuit.
And two - these were the two terms this was one term and this has another term BC and
A, C prime, D prime all right. And this is the so called redundant term right.
But, this generates a product term, which connects which is common across logically
adjacent 1s ok, which is otherwise would not be connected, so that is the ABD prime.
And this ABD prime if you remember that was the condition at the input side, when A is
1, B is 1, and D is equal to 0, and C was changing from 1 to 0 the glitch was occurring
ok.
Y = B.C + A.C’.D’ + A.B.D’
So, by having these three and the cases, I mean ABD prime connected here for this
particular cases, when the glitch could have been there putting such additional a three
input AND gate, and connecting to a OR gate right, you are suppressing that glitch ok.
So, this is what we keep in mind. And also we take note of that it is not that the circuit
may have only one hazard, they can be multiple hazard also I mean multiple such
possible cases all right.
For example, if in this particular example if we just simply modify like this is 1 and say
this is 1 right, then minimized representation will be like this 1 and the other 1. Now, to
make it hazard free, so there are now two potential if you look at it, there is other two
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such potential glitches ok. One is this is the one that we have already seen, another is this
particular case ok. These two are logically adjacent, but not covered by any common
term, common product term in the most minimized you know case. So, to cover this, we
need to generate this term and add it here for you know that particular minimized
expression.
(Refer Slide Time: 28:16)
So, this is - we take note of. And with this we summarise what we discussed today that
logic circuit minimization on its own does not consider the effect of propagation delay.
Glitches are undesired, short duration pulse that may occur in a transition due to finite
propagation delay for certain input combination. A circuit with a potential for glitch is
considered to have hazard.
In static 1 hazard, output should remain at static 1, but glitch may occur for that specific
combination. Static 1 hazard can be detected by examining the K-map or the Boolean
expression. K-map comes first. So we can look at the K-map and form that we can look
at these logically adjacent 1s - all logically adjacent 1s are covered by one common
product term or not. And circuit can be made hazard-free by covering hazards by
additional terms, which are otherwise considered redundant ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 15
Static 0 Hazard and Dynamic Hazard
Hello everybody. In the last class, we discussed static 1 hazard. We saw that an
otherwise optimized circuit can create issues in terms of producing glitches, which could
be troublesome in some of the applications. And in that context, we found that how to
detect such hazard for certain kind of you know circuits, and that is static 1 hazard and
how to cover it.
(Refer Slide Time: 00:53)
So, in today’s class we shall look at Static 0 and Dynamic Hazard. So, these are the two
things that we shall take up today.
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(Refer Slide Time: 00:58)
So, in static 0 hazard, we shall again - the condition that we find is similar, is analogous
to what was there for static 1 hazard. In static 1 hazard if we remember, the Boolean
expression reduced to something like A plus A prime equal to 1. Just to recollect, the
Boolean expression reduced to A plus A prime equal to 1, which always needed to be at
1, but because of the propagation delay involved in generating A prime through an
inverter, we found a negative going pulse or a glitch occurring, and we found how to
detect that and how to cover that.
So, in static 0 hazard, what is happening, the Boolean expression for a certain
combinations of the input reduces to an expression, which is something like A A prime,
which should generate 0 as far as the logic of the circuit is concerned. But, because of the
involvement of this time delay, finite propagation delay in generating the NOT gate
output, there is a glitch ok. So, this glitch will be a positive going pulse, positive going
pulse ok. So, how does it occur?
A.A’ = 0
So, if you look at the example, so this - the input A is going from changing from 0 to 1
ok, and because of the input is input is going from 0 to 1. A bar is going from 1 to 0, but
it takes a propagation delay, which is propagation delay for this inverter, this NOT gate
going from high to low, whatever time it requires, the finite propagation delay associated
with the circuit whether it is a TTL base circuit or a CMOS based circuit. There is this
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delay associated is actually included in this duration time duration the tau 1 you see ok.
So, for this AND gate, this particular time duration this 0 to tau 1 that one you see over
here is the time when both the inputs are at logic high logic 1 right, so because of which
whenever they are at 1 both of them are at 1, after the propagation delay involved for the
(Refer Time: 03:36) this particular AND gate to go to logic high. So, it will go to high.
And whenever it goes to low, it will go to low. So, during that period, it remains high.
So, this is this positive going pulse that you see for a short duration because of the
propagation delay involved here ok.
So, but for the AND gate you know I mean, AND relation for this kind of relation you
should always get a 0, which is not happening because of the finite propagation delay.
So, in static 0 hazard, output should always remain static at 0 according to the Boolean
logic, but glitch occurs because under certain input condition.
So, we look at one practical example. So, if you realise the truth table that we had seen
before for the static 1 hazard problem, the same truth table if you try to realise through
product of sum - POS, then what will we get? We will get a relationship something like
this. So, this is a known problem. This relationship we have seen earlier in the course ok,
and to realise that we are having A or C generated here, and A prime B generated over
here, and these two are ANDed through this AND gate ok.
Y = (A + C).(A’ + B)
Now, consider the input combination B is equal to 0, so, this is 0. C is equal to 0, so this
is 0 ok, and A is going from 0 to 1. So, A initially is at 0 right, so which is making
initially this is at 1 ok, so 0 and this is at 1, so this output is 0 right, this output is 1, but
for the AND gate, we need both the output to be 1 to be out the for the output to be 0.
Now, this goes from 0 to 1 ok. So, this AND gate after the OR gate after the propagation
delay go to goes to 1, but this one till this time this NOT gate output, NOT gate output
changes will remain at 1 ok. So, this output 1 goes to 0, after this propagation delay and
this propagation delay ok, so because of which here it goes to 1 after one propagation
delay, and it goes to 1 after two propagation delay if tau 1 and tau 2 are same.
So, momentarily for one propagation delay, both the inputs are at high which makes the
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output high, so because of which this glitch the one that we are talking about occurs in
the circuit ok. So, for other input combinations, it will not occur, so that is what it is
mentioned in the earlier class also, that we take note of here that for a specific you know
condition combination this thing, the glitch occurs.
(Refer Slide Time: 06:42)
Now, how we detects static 0 hazard? So, static 0 hazard detection is similar to static 1
hazard detection ok. So, two logically adjacent cells with output 0 in the K-map, if it is
not covered by common sum term ok. In static 1 hazard, it was two logically adjacent
cells with output one not covered by common product term ok. So, in this case it is the
output having 0, which goes into the making of you know, previous expression, they are
not covered by common sum term.
So, from the Karnaugh-map, we can find this one. And if you look at the Boolean
expression, which ultimately reduces to A A prime kind of thing a variable and it is
complement ANDed together for certain input combination ok. So, we do not need to go
up to the expression level, simply by looking at the Karnaugh-map grouping from which
the expressions are generated, we can detect presence of a static 0 hazard.
Y = (A + B’).(B + C)
So, we look at one example. So, this is an example, where you see this 0, this is this is
optimized expression all right. So, these two 0’s and these two 0’s, they are grouped
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together. And A plus B prime is one term this term, and B plus C is the other term and
they are ANDed together ok. So, there is a potential glitch static 0 hazard why, because
this 0 and this 0, they are logically adjacent - ok. And they are not covered by one
common sum term, is it clear?
So, how - when does the glitch occurs, when A is equal to 0, and C is equal to 0 A is
equal to 0, C is equal to 0. So, this is the two cases, when A is equal to 0 and C is equal
to 0, and B changes from 0 to 1, then the glitch occurs going by whatever we had just
discussed the examples; so, similar example over here. Now, if you look at the other
truth table a similar truth table, in relation two what we discussed in the static 1 hazard.
So, there we grouped the 1s, now we are grouping the 0’s, so this is one group, and this
is one group. And there generating term B plus C, and B prime plus C prime, and we are
ending them together to get the POS representation.
Y = (B + C).(B’ + C’)
Now, we see that the logically adjacent 0s these two, they are under common sum term
these are two logically adjacent 0s there are under common sum term, and these 0’s are
not logically adjacent. So, they need not be covered by common sum term ok. So, we do
not have any hazard here, we do not have any static 0 hazard here ok, so that is what we
take from this particular truth table, and converted to Karnaugh-map ok.
Now, we look at a four variable example. So, this particular example, you see the
presence of you know 0’s and 1’s in that truth table the way it has been mentioned. And
to get the - first the optimized expression, so we look for grouping of 0’s with largest you
know possible group size. So, this is one group, this is one group right, which is
generating this term A plus C right. Then we have this particular group all four 0’s, they
can be grouped together right. So, this is generating C plus D prime.
And the other two 0’s, these two 0’s, and these two 0’s, they can be part of one group,
group of four members, so that is between them 0 0. So, B plus C is remaining with one,
so C prime. So, this is the third term that we are getting, which is covering all the 0s
right. So, this is the optimized expression. But, does it have a, you know, static 0 hazard?
Y = (A + C).(C + D’).(B + C’)
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So, for that what we need to examine, we need to see whether the logically adjacent 0s
are covered by common sum terms or not. These are logically adjacent 0s covered by
common sum term, but here is one logically adjacent 0, I mean 0s one pair, they are not
covered by common sum term ok. So, this might lead to a glitch for a specific input
combination right.
So, is there only one possible way the glitch can occur? Nno, you can see that there is
another such thing ok, which is there you know logically adjacent, and but they are not
covered by you know common sum term is that the on you know second on possible
thing there is there no other ways glitch can occur in this particular example. There is
another way glitch may occur if you look at this 0, and this 0 ok, it is they are also
logically adjacent. So, and there is no common term, common sum term covering them
ok. So, there can be a glitch for that also - right.
So, what are the in this possibilities, the combinations? So, between these two you can
see AB and - AB remaining 0, D remaining 1, and C changing from 0 to 1. So, A
remaining 0, B remaining 0, D remaining 1, and C changing from 0 to 1. So, A 0, B 0, D
1, C changing from 0 to 1 ok. So, this is a case where ABD are 0 0 1, C changing from 0
to 1 a glitch, a positive going pulse will occur, when it was logically it is supposed to be
at logic 0.
If you look at the expression, if you substitute we can see that the same thing will be
happening. So, A is equal to 0, so this is 0 right, then B is equal to 0 B is equal to 0, this
is 0, and D is equal to 1 right. So, D is equal to 1 means D prime is 0 right, so what we
will get C and C and C prime, so C C prime is occurring right a variable and its
complement. So, this is a case, where there is a possible a you know glitch ok, a glitch
will occur if we make the make a transition if the input C make a transition from 0 to 1.
Similarly, you can check for the other cases also, right. So, this is the case when A is 1
right, B is 0 right and D is 1, d is 1 between these two right. So, A 1, B 0, and D is 1, and
C is changing - a transition from 0 to 1, glitch occurs. And the last one the 3rd one that
we talked about these two, so A is 0, B is 0, D is also 0 right between these two 0s and C
changes from 0 to 1 C changes from 0 to 1 ok. So, there is a glitch occurring right. So,
this is the way we can figure out three such you know possible glitches, and this
particular realization, this particular realization has a has static 0 hazard ok.
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(Refer Slide Time: 14:42)
Now, to cover, we do not, we have detected, but we need to think of how to cover it. And
again we follow the logic that we followed for static 1 hazard covering. So, the one that
causes the a specific hazard, we need to make sure that that cause does not arise. So, for
that what we will do simply, we shall see that the adjacent logically adjacent 0s are
covered by one common sum term.
So, in the previous example, in this particular example right, what we are looking at this
two 0s right, we are covering by a common sum term ok. So, this is the example with
which actually we started. So, this particular circuit is of this is one sum term A plus C
right A plus C ok. And this is another sum term, which is A prime plus B A plus C and A
prime plus B right.
So, this is the one with which we started today’s discussion right, so if we quickly go
back. So, this is the circuit we started with right, and we found that there is a possibility
of a glitch. So, we are looking at covering this particular hazard ok. So, these are the two
terms right. And then the common term over here is B and C, so we are forming a group
of them, so group of it, so B plus C.
Y = (A + C).(A’ + B).(B + C)
So, when we are just forming this term, this is so called redundant term in terms you
know optimization problem, but together it solves the problem, I mean the addresses the
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static 0 hazard. And what how does the circuit change? So, basically this is the B plus C
that comes over here. And when B and C are 0, these two are 0, this output is 0. And this
holds, this is AND gate input. So, if there is a 0, it will be always be a 0 right. And even
if some changes are occurring over here A going from 0 to 1, that is not going to the final
output ok. So, this is similar to what we had seen in case of static 1 hazard a 3rd AND
gate was there, which was feeding to the final OR gate ok. So, a just analogous the in
terms of POS representation, is it clear?
So, now we look at the other example, the four variable example. And there are three
glitches, three possible you know glitches that were was to be covered that were to be
covered. And so in this case what we are finding. We find that to cover this one and this
one, I mean these two 0’s these two 0’s, we can form a larger group – isn’t it? We can
form a larger group I mean group of 0, otherwise you could have one term over here,
another term one common sum term right.
So, then we were would have required three two such terms with three literals, so but we
know that we can have a larger group of four, which will make sure that all adjacent 0’s
like these two, and these two are under one common sum term. And for that what we are
having? So, in this B is remaining constant, and D is remaining constant, B is remaining
constant with 0, and D is remaining constant with 1. So, B plus D prime is the term that
will be required ok.
And the other thing is this 0 and this 0 that was that were to be put under one common
sum term ok. So, one option is to have you know like this, but again that will require
three literals literal cost would increase. And what we would like to do to avoid that we
will be having a larger group like this with only two variable invert, so that is A plus B.
So, because AB is remaining constant over four this four 0’s ok. So, with all of them
together we can see that the static 0 hazard for the circuit all the three possible cases are
covered - right.
Y = (A + C).(C + D’).(B + C’).(B + D’).(A + B)
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(Refer Slide Time: 19:36)
So far we had seen the static 0, static 1 hazard and static 0 hazard a using AND, OR, OR
AND kind of you know two level circuit, we are only talking about two level circuit here
as we have noted before. So, if we had used instead you know NAND-NAND or NORNOR for realization of these two level circuit ok, what would have been the case ok. We
may have certain curiosity about it.
So, let us look at one quick example. So, if this is a realization of A prime C plus A B ok.
So, this two level realization in this case is achieved by using only NAND gates ok. So,
these are the two NAND gates. And finally, this is the third NAND gate, which is just
combining the output of the previous two NAND gates ok. So, this is we are familiar
with from our week-2 discussions how we are getting this kind of circuits. We can use
De Morgan’s theorem also on AND, OR, and then we can get NAND-NAND kind of
circuit ok.
So, in this case what happens, so we had seen before, so we continue from there that A
bar plus A this comes when B and C are 1, is not it; B and C are 1, A and A bar A plus A
bar kind of relationship is coming. So, that is as A - you know potential glitch and when
A goes from 1 to 0 right that is the static the glitch will occur right
So, let so what is happening over here this is NAND-NAND earlier we had studied
AND, OR. So, in this case initially let us considered all the situation B is 1, C is 1, and A
is at 1 ok. So, A is at 1 means this NAND gate NOT gate output is 0 which is fine. So,
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what are the corresponding NAND gate outputs. So, this is 0, 1, 1, this is 0, and this is 0
and 1. NAND gate 0 is the forcing input. So, this is the output is 1 ok. So, 0 and 1, output
is 1 which is fine
Now, this is the thing that you see that at this point of time at this point of time NAND
gate is making this input A is making a transition A to 1 to 0 right. So, this has become 0
after 1 you know delay will become 1 right. So, but here this 0 to 1, this 0 to 1 that you
can see goes after 1 propagation delay over here. So, it will not - when it is becoming 1,
it is not immediately you know going to 0, because input 2 is fail is delayed I mean the
input of 1 is delayed by the propagation delay of the NOT gate. So, for one such delay
period of this not gate both of them are 1 - both, this one is 1 this one is also 1. So, this 1
1 will be make the output 0 for that amount of time including involving all the
propagation delay of this gate and this gate right, so that is the glitch we are talking
about. So, this similar glitch occurs the one kind of thing that we had seen for that
relation it is occurring over here also ok.
So, how to cover it? So, to cover, so this B and BC will be the 1 that we had seen earlier.
We this is the one that we had considered one AND gate and which was going to the
third input of the OR gate similarly it will be B C, NAND, one NAND gate will be there
with B and C right, and this will go as the third input over here ok. Similarly, for POS
realization right, if we go for NOR-NOR right, we shall have B is equal to 0, C is equal
to 0, this is the you know snapshot of the different logic values. Then A goes from 0 to 1
ok.
So, A goes from 0 to 1 over here, and then A bar goes from 1 to 0 like this with this
propagation delay. So, momentarily both of them are having so this is having 1 sorry and
this is also having 1 right. So, for a NOR gate 1 is the forcing input. So, this is 0 at that
time this is also 0. So, 0 0 the output is becoming 1 ok. So, this is something that we take
a note of that whether you realize by NAND-NAND or NOR-NOR or the corresponding
AND-OR or OR-AND, the result remains the same and the covering is a similar.
And one might note that if we can introduce in this path a delay which is, which is you
know similar to this delay, then this can be avoided. Similarly, if you can add you know
a buffer which is providing this amount of delay ok, but that is we only to be careful that
this delay is added in appropriate amount; otherwise it will not help the situations. So,
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better to cover in this manner, but by adding delays also we can avoid it.
(Refer Slide Time: 25:22)
So, dynamic hazard we shall discuss now. So, dynamic hazard is the case when there is a
potential for multiple transitions ok, while this circuit is required to make one transition
from 0 to 1 or 1 to 0, but it is making more than one transition. So, this is what is known
as dynamic hazards. So, basically - the changes the way we have seen in the right hand
side, so this kind of you know changes take place.
And for this one notice that one of the input variable which is actually causing this thing
is to have three or more paths to the output, and number of levels involved earlier we
saw the there are two levels. So, number of level should be three or more ok. And
inherently one can see the relationship like what you see over here A plus A prime and A
or A plus A prime and A this kind of thing so A in A inherently there is a static 1 and
static 0 kind of relationship emerging somewhere, and this is what is visible in a dynamic
hazard causing circuit ok.
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(Refer Slide Time: 26:38)
So, we shall we will look at one example is a example where you can see this is AC plus
BC prime right ANDed with CD prime.
Y = (A.C + B.C’).(CD)’
And we are looking at a situation when A is equal to 1, B is equal to 1, and D is equal to
1. So, potential you can see C plus C prime and C prime this kind of you know situation
emerge ok, so this just example. So, what happens at that time you can see from this
particular diagram, so this is the value of the other inputs ok. And C is making a change,
these are the outputs Y 1, Y 2, Y 3, Y 4 and Y intermediate outputs for the purpose of
plotting. So, C makes a change a makes a you know transition from 1 to 0 right. And
then because of that, Y 1 will go to go from 0 to 1 because D is held at 1 right, so then it
will go to 1 after one propagation delay right.
What happens to Y 2? Y 2 is - AND gate right. So, if input changes from 1 to 0, so the
output will become also 0 because C was 1 C was held at 1. So, output was 1 because of
presence of A has 1. So, because of which this Y 2 is also becoming 0 after one
propagation delay. We are considering same logic family more or less same you know
propagation delay term ok. After that it remain same at that value. What happens to Y 3?
Y 3 is AND of B which is 1, and AND of Y 1. So, both of them when it is 1 the output
will become 1. So, both of them are 1, so this is Y 1 is 1 input right and B is already 1.
So, it goes to 1 over here. So, it will take time one propagation delay for this AND gate
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right for which Y 3 becomes 1 over here.
Now, what happens to Y 4? So, Y 4 is OR of Y 2 and Y 3 right any one of them high
output will be high that is the idea. So, this is the Y 4 we are talking about. So, this Y 4 if
we look, at we need to look at Y 2 and Y 3 right. When any one of them is 1 the output
will be 1. So, you see that Y 2 is 1 here this is low, but Y 2 is becoming low in this place.
So, after one propagation delay, this will become low right. And Y 3 is going high here
in this place. So, after one propagation delay this will become high right.
Finally, Y 4 and Y 1 ANDed together is the Y right. So, this is Y 4 and Y 1 ok. So, this
is the Y 1 both of them need to be high. So, Y 4 was 1 right. So, this 1 making it high
after one propagation delay right both of them need to be high Y right. So, after that this
Y 4 has gone low here, so that is making low in this place right, then Y 4 goes high. So,
this is go is going high ok. So, then what you see the Y is like this.
And if you look at the corresponding logic here C plus C prime and C prime, so basically
it is CC prime plus C prime, so C prime only. So, when C changes from 1 to 0, output
should go from 0 to 1, the but here output is going from 0 to 1 then again coming to 0
and then again going to 1. So, instead of one transition, it is making multiple transition.
So, this is what is seen as dynamic hazard - and how to cover it? It is relatively more
difficult than static 0 and static 1 hazard.
We have to see what is the inherent static 1 hazard can be seen over here because of the
C plus C prime kind of relationship, and to cover it we will be having - it is happening
for A is equal to 1 B is equal to 1 case which we have seen investigated before. So, you
add one additional term right AB without I mean, making any difference in the truth
table as such this is the redundant term, so that will be coming in parallel to this as A B
A and B right, and that will be getting connected over here right. And after that we will
be seeing that when your A B and D is equal to 1 right, so this is at 1, AB is held at 1, so
1 and CD prime. So, basically 1 and C prime that is what we will get or C prime ok, so
only one transition will take place.
Y = (A.C + B.C’ + A.B).(CD)’
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(Refer Slide Time: 32:01)
So, with this we end today’s discussion very quickly. Summarising what we discussed
today static 0 hazard output should remain static at 0, but glitch occurs for certain input
combination. Static 0 hazard can be detected by examining the Karnaugh map or the
Boolean expression. It can be avoided also by including additional sum terms and
appropriate delay, I mean that we have noted. In dynamic hazard, potential for multiple
transition exists and instead of you know only one which is required from the logic
relation. And it requires 3 or more level of circuit. And the inherent implicit static 1,
static 0 hazard if identifying - identification of that and covering can avoid its
occurrence.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E and EC Engineering
Indian Institute of Technology, Kharagpur
Lecture-16
Multiplexer: Part I
Hello everybody. We are in week 4 of this particular course. In this class and also in the
next class we shall discuss Multiplexer.
(Refer Slide Time: 00:22)
And in this class, we shall cover multiplexer basics and higher how to get a higher order
multiplexer from lower order and its relation to Shanon’s expansion theorem.
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(Refer Slide Time: 00:32)
Before that let us have a quick recap of what we discussed in week 3. We saw that
Karnaugh map is useful for simplification, but when it becomes 5- variable we need a 3D
visualization and more than 4- variable, it is difficult using Karnaugh map and if we use
entered variable map, the map size reduces by a factor of 2. And QM algorithm, when
we have more number of variables; QM algorithm is useful and we can generate a
computer algorithm, a computer based algorithm a code for minimization. And when we
look at various realization of a logic circuit, digital logic circuit - we consider certain
cost criteria which could be get input cost total number of literal cost or it total number
of you know, gate inputs plus total number of gates that are used.
So, using those cost criteria we can think of minimizing one particular function and of
various options, we can select one particular option. And when we have to realize
multiple function, then we can see how we can use the shared terms that could be there
amongst multiple functions. And during realization, when we are doing the minimization
due to finite propagation delay, there could be glitches that can occur and during the
transition from one particular value to another and such potential glitch in a circuit gives
rise to hazard and to cover hazard, we need to include additional terms which is
otherwise considered redundant. So, this is briefly what we discussed in the last week.
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(Refer Slide Time: 02:22)
So, to discuss multiplexer we look at a truth table which is which is you know converted
to a Karnaugh map realization which is what you see over here. This is something that
we have seen before very simple ok.
The truth table is like this and, what is this truth table saying? If when A is 0; when A is
0 right. So, the output here, output here follows C. You can see 0 0 C is 0; Y is 0; C is 1;
Y is 1 as long as A is 0 and when A is 1 output follows B. So, this is 0; this is 0; this is 1
and this is 1; very simple truth table corresponding Karnaugh map and this is the
realization and corresponding hardware realization, converted this particular logic
equation is what you see over here.
Y = A’.C + A.B
Now, this one can be seen in a different way; the way we look at the you know,
algorithms. So, if A; if A means if A is true that is if A is equal to 1; then Y is equal to B.
Is not it? If A is equal to 1 this term becomes 0 dot C which is 0 and this term becomes 1
dot B which is B. So, Y is equal to B. So, you can write this way when A is equal to 1
ok; Y is equal to B right. Else – else means when A is not equal to 1; the other option
this is a binary you know possibility of 0 and 1 only is there for the variable A. ok.
If A (i.e. A = 1)
Then, Y = B
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Else, Y = C
So, when A is 0. So, what we see this is 1 dot C and this is 0 dot B ok. So, in that case
the output is only C. So, for A is equal to 0 output is C. So, we can write the truth table
in this manner also and this is corresponding you know, meaning in terms of the codes
that we write for algorithms ok.
(Refer Slide Time: 04:48)
Now, how is it related to multiplexing operation? So for that, we define what is a
multiplexer. Multiplexer steers one of the many inputs; one of the many inputs to an
output based on what the control input says - ok. This is what is the job of a Multiplexer.
So, here there is an example where - which is doing a 2 to 1 multiplexing; that means, 2
inputs are there and 1 output is there. We shall see example of you know 4-to-1 and 8-to1 and other things.
So, this is the transmission line say and these inputs - is not required to transmit every
point of time. So, when at certain point of time D 0 wants to transmit; at some other
point of time D 1 wants to transmit. So, there is no need of putting a dedicated channel
for each of D naught and D 1 because this channel is very long - according to it the cost
gets increased. So, here one channel can be used by both D naught and D 1 depending on
the need and how it is decided, who will take control over the transmission channel that
is the Y. It is decided by S naught.
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So, when S naught is 0, D naught you know gets connected to Y and when S naught is
equal to 1, D 1 gets connected to Y. So, that is the idea. Is it ok? So, if there are 4 such
things, then there will be 4 such inputs and then, the select lines will be accordingly
which we shall see later - right. So, this particular thing and what we just discussed in the
previous slide, you can see there is a similarity. So, here what we are looking at? In this
case, you are looking at an expression which is something like this. So, S naught is equal
to 0; Y is equal to D naught and when S naught is equal to 1, Y is equal to D 1. This is
similar to this relationship - ok.
Y = S0’.D0 + S0.D1
So, the same circuit in which what we had seen for A, if we assign that to S naught that
is the select input and B and C becomes data inputs which is given to D 1 and D naught
respectively. Then the previous circuit behaves like a 2 to 1 multiplexer ok, where A is
your S naught; D naught is your C and D 1 is your B ok. The same circuit, the same
hardware realization that you had seen and then, we can represent it in the form of a
block - ok. So, this is the block within which that hardware, the hardware that we had
seen before is there - 2 AND gate and 1 OR gate. So, this S naught when it is 0, this is
the control input D naught is actually getting connected to Y; when S naught is equal to 1
D 1 is getting connected to Y right.
So, that is the idea and this is the way a simplified block level representation is made and
we can make use of this block in subsequent discussion. Knowing that inside the block
there is a - the hardware that we had seen before with 2 input 2 and gate and 1 or gate
that is what makes it 2 to 1 multiplexer.
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(Refer Slide Time: 08:14)
Now, we look at 4-to-1 multiplexer. So, 4-to-1 multiplexer as per our previous
understanding, there will be 4 data inputs D naught, D 1, D 2, D 3. This is the way we
designate them and this is one output right and one of them will get access to Y
depending on the selecting lines. Again, this S 1 and S naught are binary variables. So,
for selecting 4 of them, we need 2 of them; 2 of - 2 select lines. So, in S 1 and S naught
are 0 and 0, D naught is getting selected; that means, Y is equal to D naught right. When
they are 0 1, D 1; when 1 0, D 2 and when 1 1, this is D 3 ok. So, how do we write it in
the form of a logic equation?
Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
So, this is the way we can write it right. So, when we substitute S 1 and S naught as 0
and 0, both of them are 0. So, this is 0 prime that is 1. This is 1; this is D naught and rest
of the term one of S 1 or S naught we will - for 0, for being 0, will generate the 0. So,
plus 0 plus 0 plus 0 ok. So, Y is nothing but D naught. So, for S 1 is equal to 0 and S
naught is equal to 1. This is the term associated with D 1 which will be the value of Y
and the other terms will be this term, this term, this term; this 3 term will be 0. This is
how we can write the expression ok.
And the corresponding hardware is what you see over here. So, S 1 and S naught right.
So, amongst them, these 4 possibilities are there. So, 3 input AND gates; these are the
selections. This is D naught, D 1, D 2, D 3. So, if it is 0 0. So, this is 0; this becomes 1;
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this becomes 1 and this is D naught. So, Y is equal to D naught at that time and rest of
the values these and gates at that time will be 0 only. This is D naught ok, for S 1 and S
naught at 0. So, similarly for other values also you can take and you can see that the
output is in the following this particular truth table ok.
So, 4-to-1 multiplexer, when we give a block diagram representation; so this is the block
diagram representation 2 select inputs S 1 and S naught and 4 data inputs. These are the
4 data inputs and there is 1 output and 2 select inputs. The first one is S 1 and second one
designates S naught ok. So, 0 0, 0 1, 1 0 and 1 1 and corresponding inputs are you know
assigned here and this is getting connected to Y depending on the S 1 and S naught
value. So, what is there inside this block? This hardware is there - ok. This hardware is
there, this particular logic circuit is there - right. So, when we us this as a block we know
that inside this is the logic circuit that is there, clear.
(Refer Slide Time: 11:28)
Now, let us look at the 4-to-1 multiplexer equation a bit you know, closely. So, this was
the basic equation, we had seen before. Now, if we take S 1 prime common between
these two right. So, we get S naught prime D naught, S naught D 1. And if we take S 1
common between these two; we get S 1 out and S naught prime D 2 and S naught D 3
within the bracketed term. Now if you look closely at this two, this particular term, this
particular two terms you know SOP term. What is it? It is nothing but a 2-to-1
multiplexer equation and what it this? This is also a 2-to-1 multiplexer.
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So, basically you have got this realized by a 2-to-1 multiplexer and this is realized by
another 2-to-1 multiplexer and if we write this particular function as F naught and this
one as F 1 you have got S 1 time F naught and S 1 F 1 and this again is a 2-to-1
multiplexer equation, where F naught is your D naught and F 1 is your D 1, the basic
equation if you remember ok. So, essentially in the 4-to-1 multiplexer if you see right,
there is a there is one 2-to-1 multiplexer; one 2-to-1 multiplexer and finally, another 2-to1 multiplexer.
Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
= S1’.(S0’D0 + S0D1) + S1.(S0’D2 + S0D3)
= S1’.F0 + S1.F1
So, three 2-to-1 multiplexers are there. So, if we you know write it the terms of 2-to-1
multiplexer. So, this is how what we can see this particular equation getting manifested
in the form of you know hardware realization, inside you have got 2-to-1 multiplexer
circuit, the way we have seen before ok. So, when S 1 is say 0 and S naught is 0, what is
happening? S 1 0 means F naught is selected at the output and when S naught is 0, D
naught is selected as F naught ok. So, at that time then when S naught is 0, this is D
naught is your F naught; F naught equal to D naught and Y is equal to F naught is
nothing but D naught.
(Refer Slide Time: 13:58)
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So, this line will be; this line will be going there and if it is instead S 1 is 1 and S naught
is 0 F 1 is 1 here. This line will be selected F 1 will be selected S naught is equal to 0
means, this 1 will be selected. So, F 1 will become D 2 at that time right and Y will
become F 1 equal to D 2. So, basically you are having this line going to output for S 1 is
equal to 1 and S naught equal to 0. Is it clear?
(Refer Slide Time: 14:36)
So, we can see that this way higher order multiplexer can be obtained from lower order
multiplexer in a; so, there is a generalized you know approach for this. So, this the earlier
one was 4-to-1 multiplexer was obtained from three 2-to-1 multiplexer. Now let us look
at the example of getting 8-to-1 multiplexer from lower order multiplexers. So, 8-to-1
multiplexer - how many selective inputs will be there? 8 inputs.
So, select inputs will be with 3 select inputs. We can get 2 to the power - with 3 select
inputs, we can get 2 to the power 3 up to 8 input lines getting selected and getting
connected to the output - steered to the output right. So, 3 inputs are 3 select inputs are
there and these are D naught to D 7 these are the data inputs and the S 2, S 1, S naught
that is the 0 0 0. So, this is the corresponding data input D naught is getting connected to
when they are 0 0 0. So, any other value say 1 0 1 - 1 0 1. So, D 5 will get connected to
Y. So, this is the understanding right.
And how we can get it; get 8-to-1 multiplexer from lower order. So, we can have two 4to-1 multiplexer. We can have 2 4-to-1 multiplexer, the similar way you have expanded
239
the equation before you can you know go with the same exercise. So, this is one 4-to-1
multiplexer and this is another 4-to-1 multiplexer with S 1 and S naught right which is
generating F naught or F; F naught and F 1 – two functions and S 2 is a 2-to-1
multiplexer which is selecting which of this F naught or F 1 will be going to the output
and F naught and F 1 will take oneof these input values depending on S 1 and S naught that is there. So, again we take the example of S 2, S 1, S naught 0 0 0. So, S 2 0 means F
naught will be selected right and S 1 S naught 0 0 means D naught will be selected right.
So, this is the path that will be there.
So, if we take an example of S 2 S 1 S 0 as 1 0 1 what will happen? S 2 equal to 1. So,
basically F 1 will be selected; this one will be selected as going to the output right. So, Y
is equal to F 1 will be there and this is 0 1; S 1 is this is 0 and this is 1 ok. So, 0 1 is this
is the 1; D 5 will be selected. So, F 1 will become D 5. So, Y is equal to F 1 is equal to D
5. So, D 5 will go to the output, absolutely no issue. So, this is what you can see
happening when you have got - you have got higher order multiplexer realized by lower
order.
Now, imagine a situation where, you have got in the store only 4-to-1 multiplexer; you
do not have 2-to-1 multiplexer right. So, can we realize it? Of course, because we can
always get a lower order multiplexer from a higher order. Getting higher order from
lower order, we have to follow a cascaded approach, stage by stage approach, even that
we have seen. Now to get a lower order from higher order. So, this is one example where
we are getting a 2-to-1 multiplexer from a 4-to-1 multiplexer. What we are doing? So,
there are 2 select inputs. It is made - I have made common.
So, S 2 is connected over here. So, whenever we place 0, both the select inputs become 0
ok. So, this will be selected and when you know we place 1. So, these two become 1. So,
you know this, this one will be selected. So, either this gets selected or this gets selected
right. So, either this inpute goes to the output or this input goes to the output. So, this is
nothing but 2-to-1 multiplexer; one of this two going to the output. So, you can replace
this block with this one and accordingly, you can get the a 8-to-1 multiplexer using only
4-to-1 multiplexer, otherwise two 4-to-1 multiplexer and one 2-to-1 multiplexer are
sufficient.
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(Refer Slide Time: 19:19)
Now, in the previous example, we had seen two 4-to-1 multiplexer getting connected to
one 2-to-1 multiplexer to give you ultimately a - one 8-to-1 multiplexer and before that
we had seen that 4-to-1 multiplexer can be obtained by three 2-to-1 multiplexer. So, this
is one 4-to-1 multiplexer that we have seen before which we can replace with three 2-to1 multiplexer and this is another one which can be replaced with another three 2-to-1
multiplexer. So, this is essentially a 4-to-1 multiplexer ok.
And finally, this is a 2-to-1 multiplexer. So, how ultimately how many 2-to-1 multiplexer
we can use to get the 8-to-1 multiplexer 1 2 3 4 5 6 7. So, with seven 2-to-1 multiplexer,
we can get one 8-to-1 multiplexer realized ok. So, this is one thing that we can take note
of that we can go up to that level. We can further break a 4-to-1 multiplexer to 2-to-1
multiplexer and realize it ok.
And this is one example where a 32-to-1 multiplexer is obtained from a - from 16-to-1
multiplexer and 2-to-1 multiplexer. So, 2 16-to-1 multiplexer are there, they are
generating 2 output like D 1 that is they are before and 1 2-to-1 multiplexer is combining
these 2 outputs and is generating an output. So, these are different examples by which I
hope it is clear from to you that how higher order multiplexer can be obtained from
lower order and also we have seen how lower order can be obtained from higher order
ok.
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Now, we shall look into Shanon’s Expansion Theorem and it is use in the multiplexer
you know design.
(Refer Slide Time: 21:19)
So, Shanon’s Expansion Theorem, we are revisiting it we have seen it before ok. So,
Shanon’s expansion theorem, this is the one –ok, remember this one.
F(x1, x2, x3, …, xN) = x1’.F(0, x2, x3, …, xN) + x1.F(1, x2, x3, …, xN)
So, given any function F X 1 this is the number of variables, I mean it could be 3
variable 4 variable 2 variable, I mean just it is generalized expression. So, X 1 prime so,
corresponding term X, wherever X 1 is there it becomes 0 ANDed with the function X 1
prime replaced by 0 plus - ORed with X 1 and the function wherever X 1 is there, you
replace it with 1 whatever comes up. So, you just simply sum these 2 particular products,
you get the original function.
So, this is Shanon’s expansion theorem which you have seen before. Now in the 2-to-1
multiplexer, you know, context we can see if this is my X 1 and this is select input for 0,
one will go; for 1 the other will go as output. So, if this is my Y; this is Y, then if X 1 is
0. This is the term that is going. This is my corresponding D 0, equivalent to D 0 and
when X 1 is equal to 1, this one will go to the output because X 1 is equal to 1 means this
term will become 0; the top term will become 0 ok. So, the output will become this
particular expression ok, which was given before.
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So, there is a inherent if then else, if X 1 then X 1, X 2, X 3 to X n. This particular
function and if not X 1, else that is then F 0, X 2, X 3 to X n. Then this particular
expression will be the function output. This is similar to the multiplexing action that we
see –ok, and this we can look at, we can put it into the basic multiplexers 4-to-1
multiplexer equation and for S 1 taken out as X 1 wherever S 1 is appearing we can put 0
0 0 0 and the other one S 1; this was S 1 prime wherever S 1 is there, we put 1 1 1 1 and
then, we simplify we see that we get back to what we had seen before. So, this is one 2to-1 multiplexer equation giving F naught and this is another 2-to-1 multiplexer equation
giving F 1 and finally, these 2 are getting combined this is your the third 2-to-1
multiplexer.
Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
= S1’.[0’.S0’D0 + 0’.S0D1 + 0.S0’D2 + 0.S0D3] + S1.[1’.S0’D0 + 1’.S0D1 +
1.S0’D2 + 1.S0D3]
= S1’.(S0’D0 + S0D1) + S1.(S0’D2 + S0D3)
So, similar and exactly similar to what we had seen earlier and we also note that the
Shanon’s expansion theorem can be nested. So, first you take X 1 out. So, whatever you
get this specific this specific equation you can take X 2 out right. So, by which you can
write this expression and the other expression and similarly, you can look at this
expression. This expression - this one you can take X 2 out X 2 prime here and X 2 over
here. So, this one wherever X 2 appears. In this case one X 2 prime is taken out.
F(x1, x2, x3, …, xN) = x1’.[x2’.F(0, 0, x3, …, xN) + x2.F(0, 1, x3, …, xN)]
+ x1.[x2’.F(1, 0, x3, …, xN) + x2.F(1, 1, x3, …, xN)]
So, 0 will be there when X 2 is there X 1 will be there. This is the nested version of the
Shanon’s Expansion Theorem which you have seen before and so, this is equally
applicable over here right.
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(Refer Slide Time: 25:01)
And if you do that; if you do that the earlier 8-to-1 multiplexer realization the one that
we had seen using 2-to-1 multiplexers right, by nesting we can see is shown in this
particular diagram. So, this is your F A, B, C right, the basic equation, A is your select
input. So, whenever A is 0 right, this one is going as the input and whenever A is 1, this
one is the input right.
Now, this F 0 B C this is the output of another 2-to-1 multiplexer. So, whenever this is
the B wherever B the first one whenever B is equal to 0, we put F 0 0 C will be the input
and whenever B is equal to 1, F 0 1 C will be the input ok. Similarly, there will be the
other line. And finally, this F 0 0 C, if C is taken as the select input out. So, this 0 0 terms
are there so, C is equal to 0 is this term and C is equal to 1 is this term. So, accordingly
we have these 8 possibilities; these 8 possibilities F 0 0 0 to F 1 1 1 is over here and the
individual output that are generated at every level, this follows the Shanon’s expansion
theorem, the nested version which we had seen in each of the cases and this we can see
over here also right and for any value A B C we have already noted this particular term.
F(A,B,C) = A’B’C’.D0 + A’B’C.D1 + A’BC’.D2 + A’BC.D3 + AB’C’.D4 +
AB’C.D5 + ABC’.D6 + ABC.D7
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So, if we have a function that we want to realize using this particular you know
multiplexing architecture. So, this is A B C and this is say this is the corresponding truth
table. So, wherever there is a 1 in the truth table right; so, if A B C - F 0 0 0; so, this is F
0 0 0 right. So, if there is a 1; so there is a 1 over here. So, we put the corresponding D
naught value as 1; 0 0 1, so this is the corresponding term we see the truth table out in
this particular place is 0. So, this is my corresponding input ok so, we put D 1 as 0 ok.
So, this shows that using multiplexer, we can realize the truth table. So, inside this is
what this whole block this whole block is a 8-to-1 multiplexer. We have realized it in this
manner, but effectively this is a 8-to-1 multiplexer. So, if input to that is F 0 0 0 to F 1 1
1 over here ok. This can map to the truth table by appropriately placing the values of D
1, D 2, D 3 upto D 7 ok; making them zeros and ones as per the truth table (Refer Time:
28:20) we have seen it. More of this, we will see in the next class of the multiplexer.
(Refer Slide Time: 28:31)
So, to summarize a multiplexer steers one of the many inputs to an output based on
control inputs, n control inputs can select up to 2 to the power n data inputs and steer it
towards the output. Higher order multiplexer can be obtained from lower order by
cascading. Lower order multiplexer can be obtained from higher order by appropriate
connection of select inputs. Shanon’s expansion theorem and its inherent if-then-else
structure is useful in getting insights of multiplexer operation.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 17
Multiplexer: Part II
Hello everybody, we are in the 17th class and this is where we discuss the Multiplexer,
second part of the multiplexer.
(Refer Slide Time: 00:24)
In the last class we had seen the basic concepts of multiplexer and in this particular class
we shall look at some practical ICs, Integrated Circuits which are used for multiplexer multiplexing operation and we shall look into how they are developed and how they
work. So, this class will be mostly on the practical use of multiplexer in your lab or any
project or any design activity that you plan, how you take, go for the hardware
implementation.
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(Refer Slide Time: 01:07)
So, in the first slide we discuss IC 74153 ok. So, in this particular IC we see a 4 to 1
multiplexer. So, 4 to 1 multiplexer the basic concept we have already seen we had seen
in the last class ok, but in when you practically implement it you see in this particular IC
there are 16 pins, this is 1 to 8 and 9 to 16 and this is how the circuit is made up of. So, in
the circuit if you look at it, I will discuss, it I mean with all the inputs and other things.
So, first thing you can see there is one 4 to 1 multiplexer over here this is one 4 to 1
multiplexer that you can see there are some other additional inputs you shall discuss
later.
So, this is another 4 to 1 multiplexer that we can see. So, basically this is a dual; that
means 2 4 to 1 multiplexer is there. The other thing that we can see is that the select
input B and A it is termed as B and A. So, this is common for both the units this
multiplexer and this multiplexer select input is common that is what we can see. And the
third thing we see that each of this multiplexer has separate, 2 separate inputs one called
STROBE G 1, another this is; another STROBE G 2. So, this G 1 you see is connected
you can see from here to here. So, this strobe is not getting connected to this place this
strobe G 2 is connected to these four - ok.
So, the strobe part is individual. So, this strobe is affecting only this 4 to 1 multiplexer
and this strobe is affecting only the bottom 4 to 1 multiplexer this is what we can
visualize. Now we will look at how this particular circuit works this practical circuit
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which is there in the form of integrated chip - IC. So, integrated circuit we shall see how
it works. So, when strobe is high. So, there is an inverter over there it is a actually is a
NOT operation - that is happening. So, this output is 0, if strobe is high 1 this output is 0.
So, if this is 0 for all the AND gates, the output will be 0, each of them, their output is 0.
So, the final output Y 1 will be what - 0 only that is low irrespective of whatever is the
value of B A and these are the data inputs whatever be the value - the output will be low.
So, that is what you see over here when strobe is high the output is low irrespective of X
- X means do not care, the value of B and A this is happening, for the bottom one also; if
this strobe is this strobe over here is high then this output will be low. So, this is
symmetrical - fine. So, for normal multiplexing operation, this strobe needs to be at low
ok, then this is high and get - so, the operation goes to the other inputs. Now let us just
take one particular example. So, the select input is a 0 0 ok. So, then this is 1 and this is
1. So, this 1 is connected over here this AND gate; this 1 goes to this AND gate (Refer
Time: 04:50) I have shown you the line - right.
So, this is the other input. So, these 3 inputs are 1 now. So, this AND gate output now
will be whatever is 1C 0 that is the data input. So, 1 here means first block this is dual
package C naught is the D naught the equivalent of what you had seen in the last class
ok. So, this is the data input. So, this is what when you will get 1C 0 over here and for all
the other AND gates you will see, this select input these are connected in such a manner
that one of them is 0 ok. So, one of them 0 means irrespective of whatever be the data
inputs are each of these are 0 right. So, what will be the output then is 1C here ok.
So, when this is low - right and these 2 are low and low then the output is this C 0 is the
output over here similarly over here in the bottom place also, when this is low and high it
will be C1 high low this is C 2 and this is C 3 - this is nothing but the multiplexing
operation.
So, additional thing over what we discussed in the last class you see. is the presence of
this strobe which is nothing, but a enable like control input that when strobe is high the
multiplexer is disabled when strobe is low the normal multiplexing operation is taking
place and we can have the corresponding equation over here. So, we can see if E is equal
to 0, E is your strobe is enabled. So, if E is equal to 0 then this is 1 and normal
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multiplexer multiplexing equation is there and when is equal 1. So, this is 0 this whole
thing is 0.
Y = E’.[(B’.A’).C0 + (B’.A).C1 + (B.A’).C2 + (B.A).C3]
So, is this clear? So, nothing to be scared like you know, what is this circuit looks like it
is nothing, but 2 4 to 1 multiplexer with additional enable input, that enable input is
going to the AND gates each one of them and making it operational, I mean the normal
multiplexing operation for a specific value and other value it is a fixed logic low it is you
know holding at the output.
(Refer Slide Time: 07:07)
So, if this is clear. So, we look at another circuit, multiplexer circuit which is there where
the output is inverted earlier we have seen all the output is just you know whatever is the
input output is following the input ok.
So, I is equal to D naught D 1 and so on and so forth. So, here is the circuit IC 74150 this
is a 16 to 1 multiplexer right. So, it also has got a strobe input. So, strobe now we
understand - no problem. So, whenever the strobe is high irrespective of the others what
is there in the select input output is high, why output is high, you see this is AND gate
and this is a or gate after that there is a inverter ok. So, in the earlier example we had
seen that if this is high. So, this will be 0 all of them will be 0. So, they output we will be
0, but because of the presence of the inverter now we see the output is high is this clear.
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So, only when the strobe is or the enable is low the normal multiplexing operation is
taking place. So, low, low, low, low so, all these things are low then E naught will go to
the output right E naught will go to the output. So, Y will be E naught, if this bubble is
not there - inverter is not there since this inverter is present Y will be E naught bar, Y
will be E naught bar, similarly for other cases E 1 bar, E 2 bar, E 3 bar and so, on and so,
forth ok. So, in earlier cases - examples we had considered these inputs to D naught D 1
data input. So, previous I C chip we have seen that that was use as C naught and here,
here the manufacturer the datasheet they are representing it as E I, E naught E 1, E 2, E
3.
But you know the meaning remains the same - is it clear? So, this is what we can see and
corresponding then equation becomes what - this is the basic equation we had seen which we had seen before with enable ok. Now because of the presence of this inverter
the whole thing after that there is a inverted - ok. So, this is what becomes the equation
and the corresponding logic circuits - simple.
Y = (E’.A’B’C’D’.D0 + E’.A’B’C’D.D1 + … …. + E’.ABCD’.D14 + E’.ABCD.D15)’
(Refer Slide Time: 09:28)
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Now, we look at realization of certain truth table using multiplexer - right. So, earlier
you had seen in the last class that this is possible using Shannon’s expansion theorem
and all right here we are taking some practical IC and we are looking at it is realization.
So, in this case we are looking at IC 1 74153 to the 4 to 1 multiplexer, we have changes
before with strobe or enable input. So, that is the basic equation of that and you want to
realize a truth table which is something like this ok. So, this truth table F 0, 0 whenever
these 2 values are 0 0 it is 0, 0 1 1, 1 0 1 and 1 1 so, this is 0. So, this is corresponding
you know logic equation basic logic equation.
Y = E’.[(B’.A’).C0 + (B’.A).C1 + (B.A’).C2 + (B.A).C3]
So, this we can write in terms of all the minterms B prime A prime dot 0, B prime A
prime ANDed with 0, B prime A ANDed with 1, B A prime ANDed with 1 and B A
ANDed with 0.
Y = (B’.A’).0 + (B’.A).1 + (B.A’).1 + (B.A).0
So, this looks like a multiplexer equation with D naught is equal to 0, D 1 is equal to 1, D
2 is equal to 1 and D 3 is equal to 0, is not it – right. And in the 74153 context this is our
C 1, C naught, C 1, C 2, C 3 so, C naught is 0, C 1 is 1, C 2 is 1 and C 3 is 0 ok, C
naught C 1, C 2 and C 3 right.
So, what we do? We take only half the top part of the IC 74153 or bottom part one part
of it right B and A we connect the B A you know we does just the input is connected
right. We put E is equal to 0 or the strobe is equal to 0 if you are taking the top part then
the top part of the strobe G 1 we take as 0 and the corresponding 1C 0, 1C 1 - , 1C 0, 1C
1, 1C 2, 1C 3 we put as 0 1 1 0 and we will take from Y the first part and the this
particular true table is realized is it clear.
Y = B’.A + B.A’
So, that was for a 2 variable realization. So, for a 3 variable realization we can look at IC
74151 which is a 8 to 1 multiplexer. So, 8 to 1 multiplexer, it also has got a strobe input
similar to that, but it has got both non- inverted and inverted output. We have seen noninverted output for IC 74153 and we have seen inverted output for IC 74150. So, IC
74151 has got both the version. So, basically you can have, you can use any one of them
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depending on your requirement and you want to realize the truth table which has got this
mean terms 0, 2, 3, 6, 7 ok.
Y = F(A,B,C) = ∑ m (0,2,3,6,7)
So, how do you go about? So, this is the 8 to 1 multiplexer these are the select inputs and
we know 0 0 0, 0 0 1 to up to 1 1 1 these are the corresponding data inputs and going by
the previous discussion in the earlier class and just now what you have done for 4 to 1
multiplexer 2 variable example. So, wherever these minterms are existing, corresponding
D naught value - Di value we put them as 1. So, 0 is there. So, D in place of D naught we
will put 1, then 1 is not there interm 1 is not present. So, in place of D 1 we shall put 0
so, accordingly 0, 2, 3, 6, 7. So, 0, 2, 3, 6, 7 we put 1 and rest of the places we put 0.
And we take the output from the non inverted output and the function is realized - is it
clear. So, this is the way it can be realized by the ICs in hand.
(Refer Slide Time: 13:42)
And because of this, we can tell - we can find that multiplexer can be used as a universal
logic circuit. What does it mean? It means that any logic function can be realized using a
multiplexer by appropriately placing the input values - the data input values
appropriately placing just it is how you (Refer Time: 14:08) you know place the 0s and
1s at the input side, you get the logic function realize. So, you have to just expand the
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logic function logic Boolean equation in terms of where all the minterms are present and
accordingly we will place the inputs.
So, this is a 4 variable example and if it is a 4 variable example what shall we use, we
shall we use 74150 which is 16 to 1 multiplexer. So, in this 16 to 1 multiplexer one thing
we need to take note of for IC 74150 that this is a, this is giving a inverted output this is
giving a inverted output. So, to realize what we can do let us see one example. So, this is
the basic equation of IC 74150 which you have seen before ok.
Y = (E’.A’B’C’D’.D0 + E’.A’B’C’D.D1 + … + E’.ABCD’.D14 + E’.ABCD.D15)’
So, this is the inversion that we are talking about right and so, first of all we put E is
equal to 0, that enable otherwise the multiplexing operation will be not be there. So, this
is a strobe and the truth table that you want to realize is, this is the truth table that you
want to realize ok.
So, we give select input ABCD over here like this, these are the corresponding pin
numbers right and this truth table in terms of minterms this is how you write 0, 2, 3, 4, 5,
8, 9, 10, 11, 12, 13, 15 ok. Now if Y is this particular function over here this is prime,
then Y prime is what you get over here, you take in a prime you know inversion in the
both sides. So, this is your Y prime and this is the basic multi multiplexer equation. So,
these are this is if you are trying to realize these as Y what is the corresponding Y prime?
Y’ = A’B’C’D’.D0 + A’B’C’D.D1 + … + ABCD’.D14 + ABCD.D15
Y prime is the terms that are not included here the maxterms these are the minterms ok.
So, Y prime if you write in terms of you know the terms that are left over is 1 over here,
6 over here, 7 over here and 14 over there ok. So, Y is like this, Y prime is this one is it
fine.
Y = F(A,B,C,D) = ∑ m (0,2,3,4,5,8,9,10,11,12,13,15)
Y’ = ∑ m(1,6,7, 14)
So, in this case since it is generating Y prime by this equation. So, what you need to ,you
know connect so, 1, 6, 7, 14. So, 1 D 1 D 6, D 7 and D 14 you connect to high logic high
and rest you connect to ground, is it clear. Otherwise you would have needed if you go
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by the normal thing that 0, 2, 3, 4, 5 … you put connect it one then you have to put
another inverter after this ok, but it is equivalent truth table is Y prime is wherever 1 is
there that is there is a 0 and wherever 0 is there, there is a 1. So, you can realize Y prime
that is equivalent to get realizing Y the same truth ok. So, this is what you can do when
you have got inverted output - you can make a judicious decision and that will reduce
your hardware and all.
(Refer Slide Time: 17:35)
Now, so, far we have seen that as many number of variables for realization as many
number of control input or select inputs will be required ok, but if you have got a
problem where you want to realize a 3 variable function, but you have got only 4 to 1
multiplexer available with you. Can you go ahead? It is possible if we utilize the concept
of entered variable which we had done in earlier case where entered variable map based
minimization and all - ok.
So, let us look at how this can be done through an example. So, this is one particular
truth table that we want to realize ok. So, 1 0 these are the terms main terms which is
present and accordingly if it is 2 multiplexer this realization it is very simple wherever 0
0 0 this is 1. So, this is a one present and we are just following this over here. And the
circuit is realized it is as simple as that using 8 to 1 multiplexer.
Y = F(A,B,C) = ∑ m (0,2,3,6,7)
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Now since 8 to 1 multiplexer is not present we have got only 4 to 1 multiplexer. So, we
can look at combining the inputs the way we had done in case of entered variable you
know based minimization. So, if we consider C as the variable that will enter.
So, you form pair in this manner right - if we recollect. So, here both A and B are 0 0
right. So, when both A and B 0 0, we see that Y is just invert, you know prime of C. So,
Y is C prime and for other cases we see Y is equal to 1, Y is equal to 0 and Y is equal to
1 just if you take them as pair ok, how the output is there output is not dependent on C
other variable. So, only in this case it is dependent on C, but just as C prime ok.
So, in the 4 to 1 multiplexer with a b as select input now for 0 1 this is the 0 1 case 1 0
and 1 1 this 3 cases we put 1 0 1 as you see over here right and for 0 0 we put C prime
ok. So, these also realize the 3 variable function, but using a 4 to 1 multiplexer ok.
(Refer Slide Time: 20:11)
So, this is the usefulness of this exercise and this can be extended to realization of 4
variable function using 8 to 1 multiplexer just 1 order less the way we had seen it before
how it happens for inter variable based you know minimization in a (Refer Time: 20:25)
Karnaugh map similar thing we see that one order list is required for the multiplexer to
be used for realization of the truth table. So, in this case there is another example where
we have got 4 variable - the minterms are 0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 15.
Y = F(A,B,C,D) = ∑ m (0,2,3,4,5,8,9,10,11,12,13,15)
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So, these are the minterms that we generate again we form pairs the way we had done it
for the previous example ok. So, when ABC is 0 0 0. So, 8 to 1 multiplexer means 3
select inputs will be there. So, output is just invert of D and here the output this is Y is
equal to D prime, this is Y is equal to 1 ok. So, this is the why the rest of the things will
be there in form of a table you can see what has been shown here. So, ABC is equal to 0
0 0, D is equal to 0 and D is equal to 1 these are the 2 cases. So, this is 1, this is 1 - this is
0, this is 0. So, Y is equal to just opposite of it.
So, basically it is for 0 it is 1, for 1 it is 0. So, it is D prime. So, similarly you compute
the rest of the things you will see that Y is equal to D prime over here, 1 1 0 1 1 1 and
this is D ok. So, then your corresponding realization using IC 74151 with enable as 0 and
you are taking these non inverting output then for 0 you are putting D prime. So, this is
D prime and for 7 over here ABC 111, you are putting D, D 7 as D and rest of the cases
you are putting zeros and ones as per the requirements. So, 3 is equal to D 3 is equal to 0
and rest of the D 1, D 2, D 4, D 5 and D 6 there are 1 and the circuit is realized, truth
table is realized. So, that is how this multiplexer is very useful in and used as a universal
logic circuit.
(Refer Slide Time: 22:53)
Now, we shall look at some aspect of a practical multiplexer IC which is 74157. So, this
is 74157, if I ask you how many multiplexer is there and what is the time, then you can
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see first of all - how will you investigate this circuit. So, one is strobe at the inputs and
you can see, you can see which is there common to all of them. So, if strobe is here it is a
low sorry high then it is low. So, all the all of them will be the output will be 0 ok. So,
when strobe is low then only the normal multiplexing operation is there. So, that is what
we have studied before and we are understanding. The other thing that we see that there
is only one select input ok. So, one select input.
So, this is with one select input you can get 2 to1 multiplexer right - fine and we can see
that there is one block over here, there is another block over here, there is another block
over here and there is another block over here. So, four 2 to 1 multiplexer is there ok. So,
this is called quad 4 is quads. So, earlier we had seen dual this is a quad. So, this four 2
to 1 multiplexer is there with one common select and common strobe right. So, if I write
in the form of a logic circuit, for a in a better understanding, this is what you can see.
So, this is A 1, A 2, A 3, A 4 in the, this is the as far as the you know manufacturers you
know data sheet, what we are representing this here as same the same thing as a 3 to A
naught for certain reason which I tell you later. So, similarly B 1 to B 4 we are
representing the exactly the same thing B 2 to B naught I mean basically the same inputs
just designation is different and when select is 0, select is 0 this set is selected.
So, basically this is AND-OR and or is also your NAND-NAND operation. So, that you
have seen before in earlier weeks. So, meaning remains same it should be realization
using AND-OR and NAND-NAND. So, this is an alternate representation of the same
circuit. So, what you see here is that when select is 0 this Y naught Y 3 to naught
becomes A 3 to naught this is when select is 0 and when select is 1, then Y 3 to naught
becomes B 3 to 0 - is it fine ok.
So, this selection of four such bits as a whole -so, this 4 bit as a group is called nibble ok.
So, this is also known as nibble multiplexer and this has got its usefulness say we are
talking about we shall see later in more greater detail see binary coded decimal ok. So, a
decimal number say 7, we want to code it in binary. How will you will do it, 0 1 1 1 ok.
So, this is the zeros bit first bit second bit and third bit. So, there is certain weight
associated more of that we shall discuss later in the subsequent weeks and if we represent
9, what is 9 - 1 0 0 1 ok. So, these are the way the, they are represented. So, if you want
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to output one of these 2 numbers depending on certain condition being fulfilled say
either 7 or 9 right. So, we need a group of 4 bits.
So, this 4 bits have come in as a whole either 7 will come or 9 will come and accordingly
there will be some display and other things more of that we can discuss later. So, this is
what is done and this is can be done through nibble multiplexer. So, 4 bit can be selected
(Refer Time: 27:11) if we require more than 4 bits then we have to (Refer Time: 27:17)
we have to have another such unit there. So, this is the corresponding circuit you can see.
(Refer Slide Time: 27:28)
So, now, at times this nibble multiplexer is connected in a manner where many such
units are trying to place data. So, this is one block, this is one nibble multiplexer, this is
another nibble multiplexer right and they are trying to place data over a common line
depending on which one is getting selected.
So, if this is selected that is the strobe is there right and the other I mean all this these
cases. So, corresponding depending on the value one of the 2 set of inputs will go there
right. Now if one common line is there in which all of them are trying to send data then
the data might get corrupted because if out of this 4 lines one is sending 1e another is at
the time is sending say 0 there is a you know problem.
So, when one is sending the other one must not send ok. So, and not only that it must not
also take any value take any you know, electrical energy from this particular circuit. So,
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it should remain electrically insulated. So, this is known as high impedance. So, this is
we have seen, discussed before this is achieved by a tri stated you know output. So, this
try stated output is useful whenever we are talking about sending or grouping multiple of
- multiple bits and sending from one place to another is you know it is more important in
that context.
So, in this case IC 74257 earlier we had seen IC 74157 is a nibble multiplexer ok. So, IC
74257 is also a nibble multiplexer. But now we have got an additional input over here
which is output enable ok. So, this output enable is - what does it do it is just tristate the
output; that means, if this is not - if this is high then irrespective of what is selected the
output will be at high impendence. So, neither it will send anything nor it will take
anything from the external world it is connected to - external electrical circuitry it is
connected to. Only when it is low the output will be following the, you know basic
multiplexing operations so, the nibble - as a nibble multiplexer.
So, this is different from the strobe thing which you need to understand – strobe, what
does it do, output will be all high or all low depending on how it is connected output is
inverted or non inverted. But it is having some value it is not high impedance and that
might corrupt the data over here if it is having a common bus kind of architecture right,
but in tri stated this is only a high impendence case. So, this is something which we take
note of.
(Refer Slide Time: 30:40)
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(Refer Slide Time: 30:42)
So, with this we complete the depletion on multiplexer very quickly. What we have seen
- that output is held at high or low depending on output is inverted non inverted when the
strobe enabled control input of the multiplexer chip is not activated and when it is
activated normal multiplexing operation takes place multiplexer can be used as universal
logic circuit ok.
And a lower order multiplexer can be used where the concept of entered variable comes
into picture by which we can obtain a logic function and multiplexer with tristated
outputs as additional control input which not enabled keep the output at high impedance
and nibble multiplexer is useful when group based binary operations are done ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 18
Demultiplexer / Decoder
(Refer Slide Time: 00:40)
Hello everybody. In the last two classes, we discussed multiplexer. And in today’s class,
we shall look at Demultiplexer, which is also uttered together with decoder, though
functionally they are different, but the circuit for each of these is essentially same. So,
these are the topics that we shall cover.
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(Refer Slide Time: 00:41)
And to begin, demultiplexer - the function of it is just opposite to multiplexer. So, in case
of multiplexer, if you remember, what we had seen that it steers one of the many inputs,
one of the many inputs to the output ok. So, this is, we may consider this is a
communication channel, which is shared by the inputs, whenever they feel like
depending on the control input, one of the data input is getting access to the transmission
channel.
Now, when it comes to the receiver side say this is the receiver, and this is to be
connected to multiple recipients, then there will be a control input to steer it to that input
data to one of those recipients. So, this is just the opposite of multiplexing operation.
Multiplexing was many to one, here it is one to many. So, this is the demultiplexing
operation that we have to functionally understand the function of it and realize the
circuit.
So, if it is a 1 to 2 demultiplexer that means, 1 input and 2 output ok. How do you do it is
circuit is similar, similar to what we have done in the case of multiplexer, the similar
logic we have to adopt. So, in this case this is a select input. So, when select input is low
ok, we consider that de will be steers towards Y naught the output Y naught.
And when a so at that time what is happening to Y 1, if this is low, this is always at 0.
And Y naught because of this is 0 that is 1, so 1 and D. So, whatever is the value of D,
goes to the Y. So, whenever D changes from 0 to 1, Y will also change from 0 to 1 and
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vice versa ok. So, in the case of S being 1, what happens? So, this becomes 0 AND gate,
so this will be held at 0.
Y0 = S0’.D
Y1 = S0.D
And this is 1, so, Y will get Y 1 will get the D right. So, whenever D changes from 1 to
0, Y1 changes from 1 to 0, and also when D changes from 0 to 1, Y 1 will also change
from 0 to 1 ok. So, this is what we understand as the basic circuit. If it is a 1 to 4
demultiplexer, so we shall have similar to what you have done you had seen in case of
multiplexer design, we shall have two control input through control input is S 1 and S
naught and amongst them, they will be generating S 1 prime is naught prime, S 1 prime S
naught, S 1 prime S 1 sorry and S naught prime, and S 1 S naught. These four
combination using appropriate number of NOT gates that will be you know generated,
and they will be connected to the corresponding so AND gates ok.
So, there will be four such an AND gates with 3 inputs similar to what we had seen in
case of multiplexer. So, this is the basic circuit. And again when you work with similar
to multiplexer, we shall use we shall be using a block diagram to designate a
demultiplexer. So, if it is 1-to-2 to demultiplexer, this is the block diagram. So, S naught
is the select input data is going to Y naught, when S not is 0, and Y 1 when it is going to
when S naught is 1 this is clear.
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(Refer Slide Time: 04:27)
So, we extend it to 1-to-4 demultiplexer. So, they will be then to select inputs S 1 and S
naught showing their 00 data is going to Y naught, 01 going to Y1, 10 Y 2, and 11 Y 3
ok. So, what will be the corresponding 3 input AND gates we have the output of the 3
input AND gate how will you write. So, we shall write it in this manner Y naught will be
S1 prime S naught prime ANDed with D ok.
Y0 = S1’S0’.D
Y1 = S1’S0.D
Y2 = S1S0’.D
Y3 = S1S0.D
And similarly, for others and when this is 00 S 1 and S naught 00, what is happening Y
naught is equal to 11 D is equal to D. And all list of the cases, these are 0, all three are 0.
So, output is changed Y naught output is only changing according to D ok. So, if we
have got a different combination of the select input, so we shall have Y 1 or Y 2 or Y 3
taking the value of D, other outputs remaining 0 ok. So, this is can be written in the form
of a truth table as has been shown here.
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(Refer Slide Time: 05:38)
So, we now look in to one practical implementation of demultiplexer, this is similar to
what we had seen in case of 4-to-1 multiplexer. So, IC 74155 is a dual 1-to-4
demultiplexer. So, if we look at the circuit, we can see that the select line is common so
this is the select line which is common, and this is one 1-to-4 demultiplexer, and this
another 1-to-4 demultiplexer right. So, this is we can observe. And for this we can see
that is the strobe separate strobe, and this is another separate strobe that is present, and
separate data that are present. There is one difference over here, this data over here has
got a inverter, this data over here does not have an inverter ok.
So, this is we take note of, and because of which what we see the output over here can be
written if you combine the logic circuit you know these inputs and the corresponding
output, so we can write 1 Y naught this is the output over here, as B prime A prime you
can see this connection going over here, this is B prime and this is A prime ok, so this is
we write as G 1 so this is G 1 prime because of the presence of the inverter and 1 C ok.
So, this is 1 C that is there because of the two inverter that is present here is one inverter,
another inverter over there.
And finally, the whole thing after this AND gate earlier there was there was only AND
gate at the output. Here we see after AND gate, there is an inverter. So, whole thing is
inverted ok, so this is the equation that we get. So, this is for the first case right where we
have taken this example with B and A has low. And rest of the cases will be B A prime
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and B prime A the other case that will be there ok. So, this will be sorry 1 Y 1 will be B
prime A and so on and so forth alright.
1Y0 = (B’A’.G1’.1C)’
1Y1 = (B’A.G1’.1C)’
1Y2 = (BA’.G1’.1C)’
1Y3 = (BA.G1’.1C)’
Next one will be B A prime, and last one will be B A right ok. So, now how then the
truth table will map out. So, we will see that when the strobe is at high so strobe is this is
at high, this is the value over here. So, when the strobe is at high, so that will make this
output this particular output is high means this is 0, so this a product term. So, 0 prime is
1 that is high. So, irrespective of the presence of the other value, when strobe is high all
the outputs are high, this is what we can see clear.
And what we see other than that for normal operation, so this strobes should be low this
should be low ok. Now, if we consider this 1 C the input right, if this input is here low
alright, so this is the case that you are talking about right. So, again the output will be
high for all the cases right, and what does it imply what is it significant we shall see later.
And when this is high, this is low, and this is low, and this is selected B prime A prime
both are low. So, this is the case with example that you are showing here. So, what will
happen at that time, the output is becoming low.
Now, in this case if C 1 changes from H to L what will happen? The 1 Y naught will
change from low to high right. So, output this output is following the input, but just an
inverted manner ok, so output is a inverted version of it. Do you see, this particular thing
happening right. So, similarly for every other cases, we will see that when this is selected
as low and high right, that is B is low, and A is high. So, please correct this one right B is
low and A is high right.
Then at that time when C 1 is high, the 1 Y 1 is getting the low. So, at that time if you
makes C 1 low, so if you make this C 1 low, so this will go to high, we will follow this
one over here. So, it is just following the input 1 Y 1 for this particular case right, 1 Y 1
is following the input, but just an inverted version of it, is it clear.
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So, similarly for the other inputs for other combinations. So, this is what we see for the
first set of 1-to-4 demultiplexer. So, the output is inverted in respect to with respect to
the input. And for this one what we see, there is no such inversion present. So, output is
just following the input, see you see if you are here it is C 2 is low right, and then the
output is also low. If you it becomes high, then the output will become high. So, this is
just exactly following the output the same way - is it clear? Fine.
2Y0 = (B’A’.G2’.2C’)’
2Y1 = (B’A.G2’.2C’)’
2Y2 = (BA’.G2’.2C’)’
2Y3 = (BA.G2’.2C’)’
(Refer Slide Time: 11:29)
So, now we look at another example, earlier we had seen 1-to-4 demultiplexer. So, if we
look at 1-to-16 demultiplexer, this is IC 74154 ok. So, in this case also, we had got a
strobe input right. So, this - the basic equation following the same bank of you know
AND gates at the output right, and there is a you can see this is the basic circuits.
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Y0 = (A’B’C’D’.DATA’.STROBE’)’
Y1 = (A’B’C’D.DATA’.STROBE’)’
…
Y15 = (ABCD.DATA’.STROBE’)’
So, these are the select inputs right, and the output will be you see the data is inverted
here, and output is also inverted here. So, basically then output will be following the
input. So, whenever input goes low, output will go low and whenever input goes high,
output will go high - corresponding output will go high, depending on this select inputs
right, so that is what you can see here.
And of course, similar to previous case, this will work properly, when the strobe is low
so this strobe is low. If strobe is high, irrespective of this selection input or the data input
all the outputs are high - ok. So, in strobe is low so if the data is low right, and if
selection is L L L L that means, A, B, C, D is the first one is getting selected over here,
all the inputs are low.
So, then corresponding Y naught is becoming low, least all are high. And if A, B, C, D is
0001 L, L, L, H low low low high, then Y 1 is low and all least are high ok. So, this is
the way the similar thing what we had seen before 1-to-16 multiplexer also follows the
same philosophy, and we can understand how it works.
Now, if we make strobe is equal to 0 right strobe is equal to 0, and A is equal to 0 so
strobe is equal to 0 and A is equal to 0, what will happene? What is essentially, you are
looking at you are looking at only the this part of the truth table right.
Now, depending on the select inputs that is B, C, D that is present, because this is always
low right. So, data will go data will go data will go ok, this input data will go either to Y
naught or Y 1 or Y 2 or Y 3 or finally to Y 7. So, essentially it is a 1-to-8 demultiplexer.
So, from a higher order we can always get a lower order demultiplexer by making
appropriate choice of this selection input, how you know - give place values to the input
side.
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If we had made A is equal to 1 in state right, then would have looked at, we would have
looked at this block right. So, depending on the B, C, D, the output would have been
steered to Y 8 to Y 15 ok. So, this is the understanding we carry from this particular
discussion.
(Refer Slide Time: 14:33)
So, then how to get higher order from low order demultiplexer? Again the philosophy is
similar to what you had for the details of you know multiplexer right, getting higher
order multiplexer from the lower order multiplexer. So, here is an example where we see
1-to-4 demultiplexer, we get from - how to get from 1-to-2 demultiplexer ok. So, there
are two select lines S 1 and S naught right.
So, depending on S 1, so if it is 0, so D will be steered in this direction alright, so data is
going in this direction. And if S naught is also 0, so data will go to this direction right.
So, when S 1 and S naught are 00, so D is connected to Y naught D is steered towards Y
naught. If S 1 is 1, and S naught is 0, what will happen in that case? So, S 1 is 1, so D
will be steered in this direction. And S naught is 0, so that means it will be going in this
direction, so Y 2 will get selected ok. So, we can understand that using three 1-to-2
demultiplexer, we can get a, one 1-to-4 demultiplexer right.
So, similar thing can happen for 1-to-8 demultiplexer if you want to get using lower
order, so we have got one 1-to-4 demultiplexer here, and another 1-to-4 demultiplexer at
the in the cascaded you know final stage second stage, and before that 1-to-2
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demultiplexer right. So, if we take S 2, S 1, and S naught as say 101, just as an example,
then what will happen? So, S 2 is 1, so D is going in this direction right, so it is coming
over here. Then 01, so S 1 and S naught is 01, so it will go here right. So, D will be
connected to Y 5 that means, D is getting steered towards Y 5, is it clear right. So, this is
how we can get it.
And if we have in the store, only say conceptually that only 1-to-4 demultiplexer is
present ok, so then this block needs to be realized by 1-to-4 demultiplexer, because 1-to2 demultiplexer is not available with you. So, this can be realized by a 1-to-4
demultiplexer simply by converting a 1-to-4 demultiplexer to a 1-to-2 demultiplexer.
One method we had seen before that one of the input we are making low or high.
So, this is another example, where both the inputs we are making common and
connecting it to S 2 right. So, if S 2 is 0, so it is going here; if S 2 is 1, it is going to 1 1
that is the output. So, F naught and F 1 will be connected from 1-to-4 demultiplexer 00
output and 11 output ok. And finally, these 1-to-4 demultiplexer the one that you have
seen, we see here can be realized by three 1-to-2 demultiplexer (Refer Time: 17:47) the
way we have done it before.
And similarly, this one also you can realize in that manner ok. So, this 1-to-8
demultiplexer can be obtained using only 1-to-2 demultiplexer, by here 1-to-2
multiplexer, and this here three 1-to-2 multiplexer, and here another three 1-to-2
demultiplexer. So, 3 plus 3 plus 1 - 7, 1-to-2 demultiplexer can obtaining by cascading
ok. This is similar to what we had seen, just the deduction is opposite, there we had gone
from multiple more number of inputs, to one output here, one input to more number of
outputs.
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(Refer Slide Time: 18:31)
Now, we had seen that there is a strobe input available. So, this strobe input can be
useful in getting a higher order demultiplexer from a lower order demultiplexer, because
within the strobe by using a inverter the way we show here in this example, we can get a
1-to-2 demultiplexer made.
The basic 1-to-2 demultiplexer circuit if you remember, what we had done before. So,
this is the basic 1-to-2 demultiplexer circuit right, S naught is selecting S naught to bar D
and S naught D, one of these two inputs output is selected. So, similar thing we can
employ here right, where this is the strobe input.
So, this particular combination is behaving, this particular combination is behaving like a
1-to-2 demultiplexer right. So, when A is high right, so then this is low so this is the one
that is getting selected this block is getting selected. And when A is low sorry this is a
active low, when A is low so this one is getting selected; and when A is 1 this 1 is getting
selected right. So, this is the corresponding equation. So, you can follow this equation, so
basically this A prime now becomes higher order the select line ok.
Y0 = (B’C’D’E’.DATA’.A’)’
Y1 = (B’C’D’E.DATA’.A’)’
…
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Y16 = (B’C’D’E’.DATA’.A)’
…
Y31 = (BCDE.DATA’.A)’
So, if this is S 3, S 2, S 1, and S naught, this becomes your S 4 right. So, this is your 1to-16 and this is 1-to-16 together with this one, we are getting your 1-to-32 demultiplexer
clear. So, this is basic IC 74154 equation, which has we have seen before. So, strobe we
are converting to a select input ok.
Now, we look at the other example. So, in this particular case, IC 74155 is seen. So, IC
74154, we had seen before, in this we have noted that that the strobe and data input are
going to the same circuit over here same this is basically your if you consider this as
input A and this is considered as input B, so this is what you are getting here is A prime
and B prime.
So, basically whether you exchange A with B, and B with A, there is no difference ok.
What I mean from the logic point of view output over here, they that cannot distinguish
between A and B, now how does it help. So because of the presence of the inversion over
here if you put strobe as data, if you put strobe as data and this data as strobe, then this
inverter which is already present can be used to get a 1-to-8 demultiplexer from these
two 1-to-4 demultiplexer.
And we do not need these external NOT gate, as we had see in this example, because
they NOT gate is already present there. So, how we need to connect, we need to connect
this 1 C and 2 C prime just connect them, as the select input the additional select input,
third select input, and the data is connected fate through this strobe. So, 1 G and 2 G, we
are connecting and we are feeding as data ok. So, you will look at this example and this
example. So, we can you make use of inherent, you know presence of the NOT gate
inverter in the case of IC 7415 because of the equivalence between these two.
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(Refer Slide Time: 22:52)
Now, thisse equivalence is useful, and we shall look into the next part of the discussion,
where we are using a decoder. So, this decoder is a circuit where the input bit pattern is
identified by an appropriate logic and the output will be accordingly activated. So, if you
want to decode say A B that is a you know two bit that are presented, so whether 0 and 1,
A is 0 and B is 1 such a situation has arisen or not ok.
Then how we you find it out, we can find it a would by simply a logic circuit like this.
So, if you want to realize understand this, so A prime B, so this with this we can figure it
out. So, when is A is 0 and B is 1, Y will become 1. Otherwise, it will remain 0 for other
three possible cases of A and B, it will remain 0.
So, to decode AB is equal to 11, we need this kind of circuit. So, if you want to have a
circuit which can decode all four possible combination depending on our requirement,
we can make use of one or the other. So, we can see inherently the 1-to-4 demultiplexer
circuit that we had, it is following this in a particular output you know combinations.
So, essentially if D is equal to 1, in each of these cases this Y naught, Y 1, Y 2, and Y 3,
there actually decoding the select inputs - isn’t it? So, Y naught is S 1 prime S naught
prime, so it is equal to 1. So, in this case if 00 is present, Y naught will be 1. So, if Y
naught goes high, then we can say that a 00 has been presented right, and for any other
combinations it will be 0.
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So, if you want to decode say 10 right, so D is high. And if we shall just look at Y 2,
whenever Y 2 goes high, we know that a 10 is present. So, this will be the corresponding
circuit.
Y0 = S1’S0’.D
Y1 = S1’S0.D
Y2 = S1S0’.D
Y3 = S1S0.D
So, that is why I said that decoder and demultiplexer circuit is essentially same. So, just
we have made, changed the orientation. So, this select lines now becomes the input line
ok, input you know combinations that need to be decoded, and these are the
corresponding output, and data input we are making high ok. So, if there is a strobe,
strobe also will shall make activated at that time. Basically, it is between - a
understanding a relationship between the select lines and the output in demultiplexer,
which is converted to data or bit-pattern to output in decoder.
(Refer Slide Time: 25:45)
So, the IC 74154 which is a, you know 1-to-16 demultiplexer. If you want to make it to
make it work like a 4-to-16 decoder, so what we need to do? We shall, just discussed, we
shall make this as active right, but that is active low, so that is why it is connected to
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ground. And now it is the decoding the presence of the A, B, C, D. So, these are the data
pattern.
If 0000 is present, so this is activated; If 0001 is present, this is activated and so on and
so forth. And if you want to make a instead of, you know 4-to-16 decoder say 5-to-32
decoder. So, the why we are done in case of demultiplexer, we shall use the same kind of
you know cascading using strobe and data - right. So, this is the fifth input by which we
can get a 5-to-32 decoder - ok. So, this is similar to the DEMUX concept we had,
DEMUX expansion concept that we had seen before.
(Refer Slide Time: 26:49)
And finally, while we are talking about you know decoding, and steering a input from to
one of the many possible outputs. So, this decoder can be useful or this particular
demultiplexer, decoder can be useful in generating multiple outputs. So, if you are
looking for in a particular problem multiple output, so we can make use of a decoder-OR
combination ok.
So, this decoder - so this is an example given, so 3-to-8 decoder. So, this Y naught, Y 1
to Y 7, it is generating actually all the minterms. So, if A, B, C all are 0, this will be high,
Y naught will be high - is not it? And when A, B, C is 001, so Y 1 will be high. So, this
is nothing but the corresponding minterms that is getting generated. So, if you want to
generate a function if you want to, you know realize a function F 1, which is a sum of
minterms 0, 4, 6, F 2 sum of 0 and 5, and F 3 sum of 1, 2, 3, 7.
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What we need to do, these outputs are there ok. And we are just making appropriate OR
of them so 0, 4, 6. So, this one Y naught, this Y 4, and Y 6 right. And similarly 1, 2, 3, 7
this is Y 1, Y 2, Y 3 and Y 7. 0, 5 Y 0, and Y 5. And just we are summing them up with
an OR gate, multi-input OR gate, and the job is done ok. So, this is one usefulness of,
another usefulness of decoder demultiplexer circuit.
(Refer Slide Time: 28:42)
So, with this we conclude today’s discussion. An demultiplexers steers the data input to
one of the many output to based on control inputs with n control inputs, the data input
can be steered to up to 2 to the power n outputs. Strobe or enable input of a
demultiplexer chip need to be active for usual operation. Higher order demultiplexer can
we obtained from lower order and vice versa by appropriate connection.
A decoder decodes input bit pattern and activates the output when specific combination
is present. Demultiplexer circuit can be made act as a decoder, for example 1-to-4
demultiplexer can act as 2-to-4 decoder. And, since decoder generates all minterms,
Decoder-OR combination can generate multiple output by summing the minterms that is
generated out of the decoder.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 19
Decoder with BCD Input and Encoder
Hello everybody, in the last class we discussed demultiplexer and decoder ok. So, we
have seen that how decoder can be - demultiplexer can be also seen as a decoder by
appropriate you know connection of the input, the data input and the strobe input. Now,
we extend the discussion from there where we started the understanding how decoder
works to decoding for BCD input and then we shall discuss encoder.
(Refer Slide Time: 00:47)
So, this is the concept that we shall cover in this particular class.
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(Refer Slide Time: 00:51)
So, BCD to decimal decoder; so what is BCD? BCD is Binary Coded Decimal. So,
whenever we talk about you know decimal number 0 to say 9. So, decimal means base
10 so, 10 digits are there. So, in terms of binary coding, we represent them as 0 0 0 0 that
is your decimal number 0 to 1 0 0 1 ok. So, that is decimal number 9. So, this is the basic
understanding that 0 0 0 0 is decimal 0; 0 0 0 1 is decimal 1 right, 1 up to .. it goes on 1 0
0 1 is decimal 9 right. So, when we talk about BCD to decimal decoder so, the input will
be a BCD number right and the output will be whatever the BCD number represents ok.
The corresponding output will be, you know, decoded ok.
So, if 0 0 0 0 present is there the 0 all 0’s are present. So, this will be active and rest all
will be inactive. If 0 0 0 1 is present this 1 will be active and rest all will be inactive. So,
this is the understanding this is what we mean by BCD to decimal decoder. So, this is
useful because in lot of cases this BCD numbers - this is what we shall encounter in
different applications ok. So, for that we have in a standard IC integrated circuit is
available, chip is available which is IC 7445 ok. So, what is driver etcetera we shall see
later.
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(Refer Slide Time: 02:45)
So, first we look at the what is meant by you know what is done as decoder. So, when
DCBA is all low 0 0 0 0 ok. So, what is happening here? So, you see this is the 1
example we have taken. So, this is low right so, this is all these are low right. So, this is
the inverter output so, these are all high this are all high. So, this is this high is going
here, this high is going here all these inputs of this NAND gate get high. So, for the
NAND gate what will be the corresponding output ok. The output will be low at that
time right. So, normal decoding operation we have seen that this bubble, this inverter
will not be present. So, here there is a inverter present.
So, output is made active low otherwise, if it is this inverter is not present active high at
that time the output would have been high and for rest of the combinations one of the
input would have been low. So, output would have been low. Now, since presence of this
inverter at the output ok. So, all the outputs are made active low. So, in this situation
when all the inputs are low ok; so, this output is low and all other outputs are high ok.
All other outputs are high, this is understood.
So, this is when this is low, low, low, high that means what is present here 0 0 0 1, we
shall again see the connection.
And, we can see that these 3 are high and this is high and this again this becomes low
alright. So, sorry this is low, low, low high so this is high, so this is your low and this has
become high. So, this high is connected here right and this is low right, so all these 4
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become high. And, here one of them becomes low so, this output is high and this is low
and all rest of them are high ok.
So, this is what is shown here. So, similarly it goes for every other cases. Now, with this
4 you know inputs we can have possible 16 combinations. But, since is it is we know for
sure that the input is a binary coded decimal so, only 0 0 0 0 to 1 0 0 1 is expected. So,
any other combination we are not bothered about, we do not care ok. So, for any other
combinations right the output will be high actually - this is we do not care about it ok.
So, this is what we can see. Now, when you talk about this driver as I say this is you
know, for specific purposes.
So, whenever these numbers are there and this is - a corresponding number will or LED
will glow or - some number display will be there. So, you need to send little bit of more
current than normal logic circuit operations ok. So, the output here is through open
collector which can sink much larger current then the normal TTL ok. So, this is useful
for as I said, displays and other things where, this binary coded decimal and
corresponding display is connected in tandem. So, this is the meaning of decoder driver.
So, the output stage of it; output stage of it will be open collector. So, we can see one
example.
(Refer Slide Time: 06:17)
The example is a so, this is a decoder driver right. So, here we are putting a what is it
called LEDs are connected. So, if the LED drop here we consider as 1.6 volt right. This
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resistance current limiting resistance is 330 ohm and the open collector output we know
the open collector output - how does it work alright. So, this is output stage.
So, here it remains open basically you are connecting it through a resistance, this is
resistance you are talking about to 5 volt supply right. So, this is in saturation. So, if we
consider saturation voltage is 0.1 volt ok; so, then LED current here is 10 milliampere
ok. So, this is the way we can calculate. So, for any other value of the résistance another
you know current will be. So, LED will be brighter or little less bright clear, we can do
simple calculation around it.
(Refer Slide Time: 07:17)
Now, another important application of this is BCD to 7 segment decoder driver ok. So,
what do you mean by that? So, often this BCD numbers are displayed. So, 0 to 9 is to be
displayed in a 7 segment display. So, 7 segment display how does it look like? So, if you
have seen any; so, basically there will be 7 such segments a b c d e f g and when 0 0 0 0
is presented here 0 0 0 0 is presented here right. So, these are all LEDs these are all
individual LEDs. So, this is the corresponding LEDs a b c d e f g that you see over here
ok.
But, they are arranged in a package, where it would look something like this. So, there
are you know this pins are there, this pins are there right and this is the package where
this LEDs are present. So, 7 LEDs are there. So, this whenever 0 0 0 0 is presented. So,
which LED is will glow? So, this LED, this LED, this LED, this LED, this LED and this
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LED the corresponding LED these are the LEDs that will go; that means, a b c d e f; g
will not glow right. So, when 1 is present; that means, 0 0 0 1 is present which LED will
glow b and c, b and c will glow. So, similarly for rest of the cases; similarly for rest of
the cases; now you can understand that a will glow for the cases when at the input 0, 2, 3,
5, 6, 7 these are present right.
And b will glow when these are present. So, what you can do? You can generate all the
you know, this possible cases and then this minterms and you can just simply sum them
up; this is one way of in a generating circuit. So, basically this is what is you are, you
know looking for when you are generating a BCD to 7 segment decoder. And, since we
are trying to light up LED which will glow and will you know - so, we are also
considering a driver.
a = F(A,B,C,D) = ∑ m(0,2,3,5,6,7,8,9)
b = F(A,B,C,D) = ∑ m(0,1,2,3,4,7,8,9)
…
So, this driver is again a open collector kind of you know output ok. And, we are telling
saying that this is a common anode type where, because V CC is connected to this diode,
the positive side of it they are not it is in earlier context it is called anode ok. And if you
get connected the common so, basically the output was going to each of these inputs and
the ground part is this is connected to the ground that is common that would have been a
common cathode type.
And this IC 7446 this particular IC which is the decoder driver other than the basic
concept that we have discussed here, it has got additional functionality like blanking of
leading zero, lamp test and other things ok. So, that we are not discussing that you can
think about when you make a try to get an application around it.
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(Refer Slide Time: 10:41)
So, having discussed decoder we would like to take up encoder also - encoding operation
how and what would be the circuit for a encoder. So, what does an encoder do? It is just
opposite to decoder and encoder converts and active input signal to a coded output
signal; coded output signal. So, here is an example. So, in this case this is a decimal to
BCD encoder. So, the possible are 0 to 9 ok. So, these are the input that are present and
the corresponding outputs are 0 0 0 0 to 1 0 0 1; so, the encoded one.
So, one simple, you know arrangement that you can see whenever 0 is to be you know
sent, coded. So, you just connect this one and you can see that this has got connection
with none of these OR gate output. So, OR gate outputs will be 0 0 0 0 in such a
situation. So, idea here is - there is no enable input to begin with or in a strobe kind of
thing which we shall see later. So, that one of the input is always present, one of the
input - decimal input is always present right.
So, if 1 is present 1 is pressed right. So, then what happen only this one is getting output.
So, DCBA so, 0 0 0 0 1 will be the output. If 2 is pressed only you can see that 2 is
connected here to this one. So, only B will be getting the 5 volt one here and rest all are
0. So, it will be 0 0 1 0. When 3 is pressed what will happen, you see that this is getting
connection and this is getting connection alright; so, B and A so, 0 0 1 1. So, that way it
will, you know go on and we can have an encoded version of this. So, instead of you
know 10 signal sent we can send only 4 such a signal in the encoded from which will
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carrying the information of this 4 right. So, this is the idea right. So, with m outputs we
can send up to 2 to the power m number of input in a encoded form ok.
Now in this particular example what you can see that when both I mean, as I said here
there is a condition, a constraint that one of the input is always you know, present always
present. Now, if more than one input is present - is pressed what will happen? For
example, we take the examples say 1 and 2, if 1 and 2 are simultaneously pressed,
simultaneously present 1 and 2 both are simultaneously present what will happen. So,
this will become high and this will also become high. So, the output will become 0 0 1 1.
So, it will appear that to the external world that input 3 is present instead which is
erroneous ok. So, in this case we need to think of a different kind of you know
mechanism to achieve encoding.
(Refer Slide Time: 13:55)
And then there comes the concept of priority encoding ok. So, what is that? So, here we
take an example. So, in this example we take 4 inputs only 4 inputs which I have can
extend later. So, D 3 D 2 D 1 and D naught and in this we assign higher priority to
highest priority to D 3, then to D 2 then D 1 and then D naugh -t D naught has the lowest
priority. So, and this the these are the 4 inputs. So, the encoded we need to outputs which
will encode this 4 inputs right. So, we are naming them C 1 and C naught. So, because D
3 has got highest priority, when D 3 is 1, D 3 is active irrespective of other inputs the
outputs are according to D 3 which is 1 1.
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C1 = D3 + D2
C0 = D3 + D2’.D1
We are you know that is the way we are designating it D 3 1 1. When D 3 is 0 ok, if D 2
is 1 irrespective of the other input, if D 1 is present D naught is present we do not care
about it. So, the output will represent D 2 only and we designate D 2 as 1 0, we encode D
2 as 1 0. Similarly, if D 3 and D 2 are 0 then D 1 will be seen in the output irrespective of
D naught is simultaneously pressed or not pressed and finally, D naught. So, that is 0 0
ok. So, this is what how what we see as the truth table ok. Now, see if we look at this you
know the C 1, how we can you get the you know realization of the C 1. One way of
course, is we know just looking at the combination and all and figuring out that C 1 is D
3 plus D 2, you can see the D 3 and plus D 2 right; the other one is C naught is D 3.
And, it is not plus you know D 1 when it is present because, if D 2 is present D 2 is
present D 2 has got higher priority at that time this should be 0. So, if D 2 is not present
right then if D 1 is present, it will be high ok. So, this is what we can see I mean just by
looking at the you know truth table; otherwise we have got our conventional way of
working out through Karnaugh map. So, D 3 D 2 D 1 D naught if we put it into the
Karnaugh map ok, this is what we shall see. And, this is one term we are getting here and
another term over here.
And similarly for C naught if we just put it into the map this is what we shall see this is
one D 3 and this 1 1 and this 1 1 can be group together. So, this is giving you D 2 prime
D 1. So, this is the way also you can get it ok. So, when you realize it you will get a
priority encoding; that means, when both 1 and 2 are pressed ok. So, it will not be giving
you 3 the earlier case that was seen. So, it will give you only 2 right 1 0 as the encoded
output clear. And one thing - one more thing that this is made cross because 0 0 0 0 case
will never appear that is the understanding .
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(Refer Slide Time: 17:27)
Now, let us look at one you know, practical circuit where this priority encoding is
happening. So, this is decimal to BCD priority encoding ok. So, in this case the higher
number has got higher priority, this similar to what we had discussed during the
development of the concept for priority encoding. And will look at the example where 1
and you know 2 pressed simultaneously let us see what happens. So, when 1 and 2
pressed simultaneously we shall see that this 2 over here right.
So, if this is your all this things are your - this is your active low right. So, if this is your
low and this is your low, this is high and this is high and this is your low is it ok. So, this
low will go over here and even if this is present; so, this will make this output low is it
clear and where is this high will continue and this will make this output high because, of
the presence of the other combinations. So, this is what actually is making, even if both
are simultaneously present, is pressed this one inactive and you know the corresponding
output will be there.
D = (8’ + 9’)’
C = [(8’ + 9’)’.(7’+6’+5’+4’)]’
So, what is happening here looking at the other aspect of it when 9 is low right, the
DCBA this output will be low, high, high, low. So, you can just look at the following
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circuit and you can see it is it clear. So, when 1 is present so, it will be low, high, high,
high, low, right sorry, yes this is when 1 is present.
(Refer Slide Time: 19:25)
This is the case that is what will see right, 2 is present will see high, high, low, high,
right, but when 1 and 2 simultaneously is you know pressed you will see H H L L when
1 plus 2. That is the priority encoding sorry H H L H ok, that is you know included in
this particular circuit.
(Refer Slide Time: 19:25)
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Similar thing for 8 to 3 priority encoder ok; so, this is 7 4 1 4 8 again this is an IC where
you can see the same concept. But, we have taken up this one to make you understand
how you know cascading etcetera is done in case of you know encoding operation as
well. So, here other than the basic circuit you have got 2 - you know 1 input here enable
input. And, 2 outputs are there this is group select a data and this is enable output right.
So, what you can see then when this enable input is high at that time this GS is high and
enable output is also high right. And when EI enable input is low and none of the input is
present 0 to 7 is present 0 to 7 is 8 to 3 - so, 0 to 7 are the corresponding inputs.
So, none of them are present means you know active low. So, it is low then all the
outputs are high at that time GS is high and enable output is low. So, basically this is this
low is making this low. And finally, when enable input is low and one of the input is
low, one of the input is active right. So, at that time the corresponding output will be
there if it is 7 then you know it is L L L that is 0 0 0. Because, it is active low that is
another part of it, the encoding part of it and what you see at that time if data is present
GS will become low ok. So, that a group data in this particular group it is present that is
what it is saying and enable output will go high ok.
So, this is the 2 control outputs and 1 control input is associated with this circuit and rest
of the things are similar rest of the thing as that seen before. So, if you know 7 is low
output is L L L low low low 0 0 0, if 6 is low alright, 6 is low then the output will be low
low high because it is active low. So, this is conceder as active the so, this is 0 it will go
on. And, here also there will be higher the number higher is the priority and input, output
we have seen to be active low.
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(Refer Slide Time: 22:43)
And finally, we see that how this can be used for enhancing the size of the encoder. So,
this is higher order from lower order for IC 7 4 1 4 8. So, this EI and EO Enable Input
and Enable Output are useful for cascading. So, this is what we have seen, this is the
corresponding connection. So, these are essentially AND gates is these bubbles are
present and then there is a bubble over here; so, in this making a essentially AND gate.
So, basically it is realized by IC 7408. So, IC 7408 we have seen before it is a quad 2
input AND gate. So, this is, each one is having a 8 to 3 so, this is also 8 to 3. So, put
together this is 16 to 4. So, this EO is connected to EI over here ok. This GS Group
Signal output we have seen the truth table before, the description on the truth table
before. So, this GS and the GS these are coming together right.
And this is mentioning that the priority flag - that is the priority is being you know,
provided here and the other the outputs now because it is 16. So, encoding will be done
by 4 outputs. So, these are the 4 outputs and these are the AND gates this 3 AND gates
and this is coming directly from GS. So, if you just look at the corresponding truth table
and their description, you will see if you place the data and the check the output you will
find that if say 0 is present here. So, it will be low low low low it is activated, if one is
activated it will be low low then the EO this is EO you have seen.
So, basically when we see 0 being activated and when you see 1 being activated we shall
see that, sorry 0 is high high or H H H H, because it is active low and when 1 H H L H.
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So, this the EO it will go on right and only when this was this is up to 7 here. So, here it
will go up to 15 so, it will become L L L L alright. So, this part look at it carefully how it
is done because, it is active low and this is active low - you need to be careful - so, what
is active high and what is active low how the output descriptions pan out.
So, when 7 is present low. So, this is L L L this is a thing that you have to remember.
You might get confused; so, you should be careful that you do not get confused about it.
(Refer Slide Time: 26:11)
Now, to conclude decoder driver is capable of providing higher current through open
collector output. As for example, BCD to decimal and BCD to 7 segment decoder driver
ok. And this is useful for display devices of an - these BCD numbers are displayed.
And encoder converts an active input signal to a coded output signal. And priority
encoded is useful when more than input is active. The output is according to the priority
assigned to the inputs. So, we have seen the examples where higher number was given a
higher priority, but you can change the priority as per your requirement and accordingly
the design would be done. And certain priority encoders can be cascaded to encode
larger number of inputs.
So, you saw the example of IC 74148 which has got group select output and enable input
and enable output which can be put judiciously. And from 8 to - 2 such 8 to 3 encoder
74148 we can get 16 to 4 encoder, you know - ok.
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Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture – 20
Parity Generator and Checker
(Refer Slide Time: 00:26)
Hello everybody. In today’s class, we shall discuss Parity Generation and Parity Checking.
What is parity, and how is it useful that we shall also discuss in this particular class. So,
we shall begin with a discussion on Exclusive-OR gate, and then we shall go on discussing
the parity, its generation and checking.
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(Refer Slide Time: 00:36)
Exclusive-OR gate follows a truth table as you see over here. When this is a two input a
exclusive-OR gate, when A and B both are of same value say 00 and 11, then the output
is 0 ok. And when one is 0, and the other one is 1, these two cases the output is 1 this is
what is Exclusive-OR truth table. And how we represent it, we represent this as A prime
B product term, and this is as AB prime. So, it simply sum them up, and then we will get
the Exclusive-OR function logic function.
Y = A’.B + A.B’ = A⊕B
And the symbol that we used for Exclusive-OR is A, Ex-OR B, I mean this is one particular
symbol which is equivalent to what you see over here for simplicity, for a compact
representation, we can use this symbol ok. Realization is very simple, so you will be
generating A prime B, and AB prime through NOT gate and AND gate, and then we will
sum it up. And if you are interested to realize it using only one type of universal logic gate,
which is NAND gate or NOR gate.
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(Refer Slide Time: 02:03)
So, NAND gate is useful, we can use four NAND gate a combination like this by which
we can get A prime B, A prime B plus AB prime over here ok. You can check it yourself
by – so, basically this is A prime B prime is AB prime you get NAND gate. So, from de
Morgan’s theorem A prime - A prime plus B prime. So, you can go on breaking it up in
each of these cases this in NAND function, and then we shall see that this is what you get
ok.
So, Exclusive - OR logic gate has got a symbol. So, this is the symbol for two input
exclusive-OR logic gate. And in this case, we know from this truth table if any of these
input is say B is a 0, see we put it 0 ok, then output follows the input. What is this case,
this is the case B is equal to 0 B is equal to 0. So, whenever A is 0, output is 0; A is 1,
output is 1 ok. And if B is equal to 1 that is 5 volt if you connect ok, what is this is case,
this is these two cases are there. So, when A is 0, B is 1, Y is 1, A is 1, Y is equal to 0, so
the opposite of it. So, A Ex-OR 1 is A prime ok, so this we take note of ok.
A⊕0 = A
A⊕1 = A’
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(Refer Slide Time: 03:29)
Now, multi-input Exclusive-OR gate; this is usefully a in our parity generator and checker
circuit, which we shall see later. So, multi-input Exclusive-OR gate, we look at one
example where A, B, C, D 4 inputs are there. So, A, B Ex-OR over here C, D Ex-OR over
here using the two input two Exclusive-OR logic function whatever way you will realize
it similarly, and then Y is realized by these two ok. So, this is a four input Exclusive-OR
gate, where I mean symbol as a symbol we can represent it in this manner ok.
Y = A⊕B⊕C⊕D
So, what is the corresponding truth table, so this is the four-variable truth table. So, 4 2 to
the power 4 16 possible combinations of the input will be there. So, in the beginning we
see where A is all 0 ok. So, if A is 0, just before we have seen one of the input is 0, then
Y follows the other input, so B Ex-OR C Ex-OR D, this is what it follows ok. And if A is
equal to 1, it follows the B Ex-OR C Ex-OR D its prime ok, this is what we have just noted.
Now, let us look at the truth table. So, if A, B, C, D is 0000, so 00 and 00 over here, so A
Ex-OR 00 Ex-OR is 0, this is also 0 the output is 00 Ex-OR is 0 ok. If it is 0001 this length,
so 0 0 0 1, this is 0, this is 1, 0 and 1 Ex-OR is output is 1, so you see the output is 1 right.
So, this way if you see that if one of the input is 1 out of this 4, the output is 1 ok. So, if
two inputs are 1, for example let us consider this particular case ok. So, 01 01, so 01 and
01; so, this is 1 and this is 1, so 11 both are of same value. So, the output will be 0. So, in
11, the output is 0 ok. So, you can take up any other case where there are two 1’s see A
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and D or AB AB and AB are 11. And CD are 00, so 11 and this is 00, so this is 0, this is
0, the output is 0. So, you can look at all possible cases of two 1s appearing, you will find
the output is 0.
Now, let us look at three 1s a case like this. So, A is 0, and BCD are all 1. So, this is 1, this
is 1, and this is 1. So, 01 this is 1; 11, so this is 0; so, 10 this is 1, so that way if you
continue, you will see that whenever the number of input in the combination is odd number
of 1s in the input combination is odd, then the output is odd else the output is 0 ok, this
you can verify you can check from the truth table.
And this happens for 2, 3, 4, 5, 6 as many number of you know, you can have inputs, it
will be like this. You can check for yourself a case like this, so three input case, so this is
A, this is B, and then this is taken to this is your Y, this is your C, you will find the similar
thing happening. So, A is equal to 0, A, B, C, so basically three input case, this is the
example, you will see that the exactly this similar thing is happening ok. So, this is we take
note of which is which will be usefully in our parity generation and parity checking circuit
that we are going to discuss ok.
(Refer Slide Time: 07:40)
Now, we first define what we understand by parity ok. Even parity and odd parity, there
are two types of parity. So, even parity means, in the input bits there is even number of 1s
- that is present ok. So, if you look at the you know number of 1s that are present if you
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count them up ok, in that particular group and if you see that it is even number, then you
say that that particular group has a even parity, has an even parity.
For example, this is example for 4-bit for group you know group of 4 bits, so 1 1, two 1’s
are there, so this is even parity. Here four 1’s are there, it is even parity ok. So, all 0 that
is also considered even. Please remember if there is no 1, all 0 that is also considered as
even. For 8-bit combination you can see, this is 1, 2, 3, 4, this is even parity. So, this is 4,
and 2, 6 this is even parity. Similarly, for 16-bit combination you can count them up, and
you can see if it is even, then it is even parity.
And odd parity is just its you know, similar where the input bits if you look at the you
know number of 1s that is present if you count them up, and if it generates the odd number,
then it is odd parity. So, the examples are for 4-bit cases. This is odd parity, because only
one 1 input is present. So, three 1 1 1 is present three 1 is present here, so this is odd parity.
Similarly, the other two cases if you can count them up, for example this is 16-bit input 1,
2, 3, 4, 5, 6, 7, 8, 9 ok, so nine 1s are there, so this is having a odd parity ok. Now, how
does it help what is it is I mean, if you have a in a particular group even parity or odd parity
particular parity in the particular you know, then how can it be useful. So, if we know a
priori - particular group, which is particular you know bits combination of bit, which is
sent from one place two another has got pre-define parity say, even parity ok. Then during
transmission because of noise, interference or some other thing; if one of the bit becomes
erroneous that means, it changes ok. So, one of the 1 becomes a 0, what will happen. The
parity will be changing, so what was even parity will now become odd parity ok.
Similarly, if one of the 0 becomes 1 that will also - that is also going to happen right. So,
if 1-bit changes, then becomes erroneous, we can detect that, there is an error. So, what
was supposed to be even parity is not even anymore, it has become odd. And similarly for
if it was supposed to be odd parity, we can see that it has become even. Now, if more than
one changes two changes 2-bit changes, then it will you know come back to the same thing
right. So, but the likelihood, the probability of more than one bit changing in a group is
much much less. When the practical transmission of you know, binary digits from one
place to another, if we consider that is - that probability is very less.
So, at I mean usually you can see a group of you know like this only 1-bit may become
erroneous occasionally. But, if you can detect by this method, then you can ask for
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retransmission or correct it by some other mechanism ok. So, here is an example where
(Refer Time: 11:24) instruments transmission line transmitter and receiver designed, and
it is tested for bit error rate less than 1 per 10 to the power 12 bits, you can imagine that
this is this does not happen very often. In certain cases, certain kind of noises it might
happen, but for that we have got different way to handle that thing which we may study in
digital communication course in some other contexts.
(Refer Slide Time: 11:55)
So, we are looking for, having a predefined parity and checking it, so that any error because
of you know transmission, noise or so we can detect it, and possibly correct it through
retransmission or some other means, which we can discuss later ok.
But, the message that we have in the first place, is random in nature ok. So, if there is a 8bit message that means, that message can have even parity, can have odd parity, you can
have many many different things ok. So, we do not know for sure that whether it is a having a even parity or odd parity. So, we have to enforce a in that group by some
mechanism a specific kind of parity ok, so that will help us and from the receivers side, it
will be known whether a specific you know particular parity is being followed or not ok.
So, how we can do it?
So, one example we can see, one way of doing it is these are 8-bit numbers that is message
bits X 0 to X 7, so we send it through an 8 input Ex-OR gate 8 input Ex-OR gate. So, what
will be the eight outputs output if there is a even parity here, the output will be a 0. And if
298
there is a odd parity that means, number of 1’s present is odd, then the output will be 1 that
you have checked you have seen Ex-OR gate truth table ok. So, if this is even right, then
this is 0.
So, if we considered include X 8 in that particular group, so right now instead of 8-bit, we
are sending 9-bits ok, so X 0 to X 7 and additional X 8 as parity bit ok. So, this X 0 to X
7 has even, and X 8 is 0. So, all together it is even fine. That is we are that is what we
understand.
Now, if X 0 to X 7 is odd means, odd number of 1’s are present. And X 8 at that time since
it is odd, this will be generating a 1 over here. So, this 1 and odd number of 1’s that is
present between - from X 0 to X 7 together, it makes even number of 1s. So, either way
whether this 8-bits are having odd number of 1’s or even number of 1’s, this X 0 to X 7
together with X 8, the whole group of 9-bits will always have even parity.
So, this is what we can employ to enforce an even parity in this particular message
transmission ok, irrespective of even or odd number of 1’s present, the group X 0 to X 8
will always have even parity - is it fine? So, from the transmitter it is when told, so receiver
will know that it is even parity. It will check if it is not even parity ok, then know that this
particular group - there is an error ok. So, instead of even parity if the transmitter and you
know receiver, they decide on odd parity ok. So, then how to generate - how to you know,
ensure that the particular group of you know 9-bits you will be having odd parity. So, what
we will you do, we will just put earlier these Ex-OR gate, after that an inverter ok.
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(Refer Slide Time: 16:00)
So, what does it, you know, do? So, if there is an even number of 1s present, even 1s
present ok, so this output will be 0 right this output will be 0, and it is inverted, so this
output it will be 1. So, even one and another one right. So, ultimately it is a odd number
of 1s are there. And if instead if odd number of 1s are present right, so these output will
be 1 and or NOT, NOT after inverted it will be 0, so odd 1 and 0, so total it is odd. So, this
group will be having an odd parity in from in the group of 9-bits ok. So, this is what you
will you know, do for parity generation ok.
(Refer Slide Time: 17:03)
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Now, to check parity - what will you do? So, similar to what we have done for you know
Ex-OR gate. So, for checking odd parity, we shall send it to a 9-bit, 9 input Ex-OR gate
ok. Say, if odd number of 1s are present, this would be this will be generated a 1 this will
be generating a 1. And if even number of 1s are present, this would be generating a 0 ok.
And instead of this Ex-OR gate if we put a NOT gate after this, inverter after this, then if
odd number of 1’s are present this is 1 ok, and after that because of the inversion they will
be it is 0. So, if this output is 0, you can say for sure that it is odd number of 1s are present,
even number of 1s are not present. Even parity will be detected, when this goes 1. So, this
goes 1, when this you know goes 0. And this is 0, when even number of 1s are present
over here clear right, it is very simple.
So, same Ex-OR gate which was doing a parity generation can be used for parity checking
also just by making a proper understanding of input-output you know connection, ok. And
this is say simple example of you know 16-bit odd parity checking, so these bits are present
right. And you can see 1, 2, 3, 4, 5, 6, 7 right, so 6, 7, seven 1’s are that the output will be
because it is just Ex-OR gate. So, the output, because odd number of 1’s are represent 1;
so, you can check and you can find that the output is 1. So, odd parity is detected in the
input group of 16-bits.
(Refer Slide Time: 18:59)
Now, this is - that was the theoretical or conceptual developing part, so IC 74180 is
represent as an integrated, as a integrated circuit. So, this particular chip actually does the
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function of parity generation as well as checking. So, this is a 9-bit, out of which 8 or data
bit, so 1 is parity bit, the parity generation and checking both it can do - ok.
So, you can see that X naught to X 5, and then X 6 to X 7 right, so these are the data bits.
And there is a even input and odd input, we shall discuss what it does and this is a
summation of - even output, summation of - odd output ok. So that means, it is basically
giving the odd parity, even parity, output define allowance summation means, so either the
summation of 1, summation of 0 that is what it is considering. And the rest is VCC and
ground the power and ground ok. So, it is truth table is like this.
So, when this given input even input, and these odd input. If both of them are high ok,
which could not be the case for normal operation is not it. If it is if the input is even from
the previous stage, it cannot be odd or if it is odd, it cannot be even, so both of them are
high means both it is even, and both it is odd, it is not you know practical, so that is not these two are both of them, high it is not being normal operation. So, at the time both the
outputs are low. And if both of them are low, the outputs are high. So, this is how truth
table is arranged. And irrespective of the other cases what is happening the summations
etcetera, you do not bother the output is kept like that- ok.
Now, if even input is high that means, the previous stage the input side it is high and odd
is low, so this is a correct proposition, so if one is high, another has to be low - right. And
if the summation of - if summation so basically, then the previous stage the input side, it
is said that it is even parity ok. So, if the summation of 1s, H means 1s in X 0 to X 7 is
even right, so input is even, this is also even ok. So, then what will be the output, output
will be - even parity will be detected. It even parity will be high, and odd parity will be
low. So, this even parity output will be high, and odd output will be low – it is understood.
And input is even, and summation of bits is odd, then output will be odd ok. And if input
is odd - if input is odd, and summation of 1s is even, then odd and even together the output
will be odd ok. And if input is odd, and summation of 1s is odd, then put together the
output will be number of 1s, it will be considered as even. So, this is how the truth table is
- of IC 74180 works out ok.
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(Refer Slide Time: 22:40)
So, let us see how IC 74180 in practice works - one example. So, in this case what we see
is the X naught to X 7 are the data in which we are checking the parity. So, data is
transmitted, we are just tapping it and putting it to the IC 74180 data input ok. And we
have put odd input to the 5 volt, so it is considered this is 1 and even input to ground ok.
So, what you have checking now, by this if we check, we are checking if you look at the
odd output, what will you see? So, if this is even summation of 1’s are even ok, and since
odd is kept here odd input is kept as high, so even and this is odd. So, even number of 1’s
here, and odd is there from the previous stage odd from the inputs side say even in all
together it is odd ok, so this will be high ok.
And if this is if this is odd ok, so odd and odd this is one, so put together it will be 0 right.
So, this is what it is doing, when we are talking about it the checking of it ok. And when
it does the generation part, checking part we have understood.
So, when it does the generation part, if this is even right, because this is odd so it will make
it odd. So, this even and this one together, it will be odd parity put together all of them
together is it clear. Even number of 1’s are there and this is one because of which the
output will be odd. So, if this X 8 is included here X 8 is included here, so this is even and
this is one, so together it will be odd ok.
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(Refer Slide Time: 25:08)
And if this is odd, and this odd is high, so this is 0. So, X 8 now is 0, so this is odd and this
is you know 0, so put together, it will be odd. So, this can be used to generate odd parity
in that sense checking as well as generation both are possible in this manner right.
(Refer Slide Time: 25:40)
So, we are saying that if we are I mean, the IC 71480 can be used in cascade also, this even
input or input that can be utilized properly. So, this is also getting higher order from you
know, multiple lower order. So, basically we are in this case, we are looking at checking
16-bit parity ok. So, you are getting a 16-bit parity checking done by using two IC 74180.
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So, this is X naught to X 7, and this is X 8 to X 15 alright. So, this is the lower order and
this is a higher order, put together it is a 16-bit parity checking that is done in this example
ok. So, to start with you are making with even the input side, because there is no you know,
previous stage. So, even is considered as high, and odd is considered does not low ok. So,
whatever is the number of 1’s here that is going to decide the final output. So, in this stage
whether it is even or odd that is decided by these two within this particular group whether
it is even or odd, it is decided by these two outputs. See if it is even number of 1s are
present, this will be high and this will be low - so this is high and this is low at that time.
Now, in this particular group you may 8 to 15, if it is also even, so even and this is even in
high, so the output will be this one will high, and this one will low right. But, if in this
particular group, this is odd say example this is odd, so this is 0, and this is 1, so this will
be 1, and this will be 0, and this is even. So, as a whole with 16-bits will be of odd - odd
parity, because odd it is X not to X 7 odd number of 1s are present, X 8 to X 15 even
number of 1s present. So, total odd number of 1s are present ok, so at that time odd is 1
odd is 1, even in is 0, so this is even. So, you will get put together odd out is 1, and even
out is 0 ok. So, this is how it works, and you can add more number of stages to get larger
number of this thing.
And if you are looking for a 12-bit parity checking instead of 16-bit right, then the higher
4-bits right X 14, X 15, X 13, and X 12 will connect to ground - you will connect to ground.
So, there no contribute any ones in the system ok. So, if it is 10-bits similarly you know
as many number of higher bits will be connected to the ground or say 11 bits, so will
connect higher number of 5 bits to the ground and rest will be subjected to the parity
checking. So, X 0 to X 7 will go here, and X 8 to X 10 if you are talking about 11-bit parity
checking, X 8 to X 10 will go here, and X 11 to X 15 will be connected to the ground ok,
and will take finally from here. So, this is how we make use of parity generation and
checking.
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(Refer Slide Time: 29:27)
So, to summarize; the output of a 2-input Ex-OR gate is 1 when only one of the input is 1.
For more than 2-input Ex-OR gate output is 1 if there are odd number of 1s present at the
input. Even parity refers to presence of even number of 1s in bit patterns and odd parity
refers to order number of 1s. Parity bit is added to make the big combination that includes
the parity bit one of even or odd parity useful for transmission purpose and error checking
and things like that.
And parity and generation and checking involve multi-input Ex-OR gate circuit, the
similar Ex-OR gate circuit can do both generation and checking. Higher order parity
generated - checker circuit can be obtained by cascading lower order circuit; we have seen
one example 2 IC 74180 generating 16-bit parity I mean, providing 16-bit parity generation
and checking. And parity check is useful detection of an error when a group of bits its
transmitted ok, so this is about this class.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 21
Number System
(Refer Slide Time: 00:25)
Hello everybody. We are in week-5 of this particular course. In this week, we shall look
at Number System and arithmetic building blocks. Today’s class - we shall cover some
of these concepts, basic number system, fundamentals of number system, binary to
decimal and decimal to binary conversion, octal and hexadecimal representation, and we
shall have a quick look at fixed-point and floating-point representation.
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(Refer Slide Time: 00:45)
So, before that a quick recap of what we discussed in week-4. So, we looked at logic
circuits, important logic circuits. Like multiplexer, which steers one of the many inputs
to the output based on certain control inputs. We looked at de-multiplexer, which is does
the reverse operation. So, if there are number of outputs and one input needs to be
steered towards that based on what is presented at the control input, for the selection
input - the data input is steered towards one of the data output terminal, so that is what
you had seen for demultiplexer operation.
And you also saw that de-multiplexer circuit and decoder circuit are essentially same. So,
decoder decodes a particular combination or input bit pattern, when it is present at the
input side. And decoder essentially generates all the minterms and these minterms can be
combined together with OR gates to produce many different kind of output. So,
whenever we talking about we are talking about multiple output generation, then
decoder-OR combinations, so multiple OR gates which takes appropriate minterms from
the decoder output - that can be useful.
And we also so encoder, encoder is reverse of you know decoding operation where input
signal is encoded in certain number of you know, a bits. And in priority encoder, if
number of inputs are active simultaneously, then according to the priority assigned, one
of the input gets encoded to the output. And we also looked at parity generation and
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checking using Ex-OR gate, and we found - it is useful for correcting or not correcting detecting one bit error in the transmission or in the bit pattern.
(Refer Slide Time: 02:47)
So, to discuss number system – first, we look at one example of an odometer, which we
have perhaps, all of us have seen those who drive vehicle or we have you know seen,
how the meter which takes note of the distance in the vehicle is you know, showing the
increments in the number.
So, you have seen that if 1 unit distance is travelled – say, 1 kilometer distance is
travelled, so the number gets increased by 1 unit over here ok, and then next unit and it
gets incremented. So, when all this is in decimal system, so when it you know complete
you know 0 to 9, then next digit - next digit over here say this one will get incremented
ok, so that is what you have already observed.
So, in decimal system if you look at the way the digits are presented, so 0, 1, 2, 3 ok, so
these are the valid digits up to 9, after that comes 0 in this unit place and in the decimal
place in the 10s place 1 comes into the place ok. So, this is how odometer - decimal
odometer works.
So, if we considered instead of you know 10 digits decimal system, we had octal systems
that means, only 8 digits are available, and we - let us number them. Let us consider the
representation of them is 0 to 7. So, what would have been the case here? So, you know
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1 unit distance travelled, it goes from 0 to 1 which is fine, then 2 unit goes from 1 to 2,
but when it goes up to 7 unit, which is there in the representation 0 to 7 - after that when
it travels one more unit, 1 more kilometer, what will happen? 8 is not available it is octal
system, 0 to 7 is only available, so at that time what will happen? The second place over
here ok - the 8’s place, so we will say that it is a 8’s place - if earlier one was 10’s place,
this is a 8’s place - that gets incremented by 1, from 0 to 1 and over here it comes 0.
So, the meaning here - this 1 0, and this 1 0 is different. This 1 0 is 10 - 9, after that one
more unit. Here 7 after that one more unit, so this is 8. Is it clear? So, if we talk about
binary system in the digital circuit, digital system - you are talking about binary 0s and
1s switched on or switched off this is the way we are looking at it, so a binary system
base is 2 ok.
So, 0 after that 1 unit travelled, so it is 1. So, after 1 another unit - when it is travelled,
what will happen? 2 is not available as a digit, so this 2’s placed, now will call it 2’s
place right 10’s place, 8’s place, now the second place is 2’s place. So, 2’s place will get
incremented by 1, and 0 will come over here ok. So, this 1 0 over here is 1 plus 1, which
is 2. And this way, it will continue.
And if you look at you know, this incrementing of the next higher position place ok, then
at 0 0 1 0 which is decimal 10 for that in octal will be having this is your 8 - 1 0, then 9 is
1 1, this is 1 2 that is in octal. And in binary system, if we go on you know incrementing
the way we have incremented the earlier cases one by one, we will see that it is 1 0 1 0
ok.
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(Refer Slide Time: 07:12)
Now, earlier I was talking about 1s place, 10’s place, 8s place, 2s place that is a second
position. So, the number appearing at units place, and the number appearing at the
second place in decimal which is 10’s place in octal that is 8’s place, and in binary it is
2’s place. So, this place provides a different weightage ok, a different place value to that
particular number ok.
So, if we look at the number that is 1 0, so in decimal the 1 here is appearing at 10s
place. So, 10 to the power 1 multiplied by 1, and this is 0, and it is 1s place value is 1, so
0 into 10 to the power 0. So, this is what actually it means in the amount, the amount
here is this much. Over here if it is in 8’s octal system, it is 1 into 8 to the power 1 plus 0,
and in binary system it is 1 into 2 to the power 1, so that is what we have already seen.
And by this we see if we go on adding the place value over here 1 0 1 0, so this is unit’s
place, this is 2’s place, this is 4’s place, and this is 8’s place ok. So, then this actually
goes into like this - 2 to the power 0, 2 to the power 1, 2 to the power 2, and 2 to the
power 3. So, 1 0 1 0, 1 into 2 to the power 3 0 plus 0 into 2 to the power 2, 1 into 2 to the
power 1, and 0 into 2 to the power 0. If you look at the odometer example that we had
seen in the previous slide, this is how this if you add them up, this is 8 plus 0 plus 2 plus
0, so 10, so it was decimal 10 equivalent that we had seen in the last row ok.
Similarly, in octal it is 1 into 8 to the power 1 that is 8 right and 8 to the power 0 is 1,
and 2 is a valid digit, so 2 into 1 is 2, so 8 plus 2 it was 10. So, the last row that is how
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we had an equivalent of 10 decimal equivalent of 10 for representation 1 2 in octal, and 1
0 1 0 in binary ok. So, this is the concept of place value, when we put it more formally –
so, this is what we would be able to see.
di = {0,1, …, r - 1)
dn … d1d0.d-1d-2 … d-m = dn x rn + … + d1 x r1 + d0 x r0 + d-1 x r-1 +
d-2 x r-2 + … + d-m x r-m
So, if we have a number system with a base or radix r by which the allowable digit, valid
digits are 0, 1, 2, 3 up to r minus 1, for example in octal system 0 to 7 in binary 0 and 1
only ok. So, then the number represented in this manner, where this is the point which
divides the integer and fraction part. So, decimal point in decimal system, octal point in
octal system, binary point in binary system, so that is the point over here ok.
Then its corresponding value is represented by, from these example that we had seen
here, if we continue that - this is the way the value is arrived at. So, the there are n plus 1
digit to the left of the decimal place, and that is the integer part the decimal point or
binary point or octal point, and then m digit towards right ok.
So, in that case d n into r to the power n - r is the base, plus d n minus 1 into r to the
power n minus 1 that we will continue right up to d naught into r to the power 0 plus.
When it goes to the fractional side, what happens? So, d minus 1, this is the first digit
which is multiplied by r to the power minus 1, so the place value here is 1 upon r - right.
So, this is we have to keep note of the next value - place value is 1 upon r square, so r to
the power minus 2. So, this way it continuous and we arrive at the value by this manner.
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(Refer Slide Time: 11:57)
So, you are more interested in the binary presentation - most of our work will be using
for the binary system. So, we elaborate it little bit more. So, here is a binary number only
4 digits before the binary point and 4 digit after it has been shown. And the
corresponding weights, you can see which is written in these places ok. So, these are the
corresponding weights ok.
So, if we look at this example 1010 - which is 1010. 101, what will be its value? So,
1010 we have already found out the integer part before right, which is 10 and the
fractional part. This is 1 into 2 to the power minus 1 plus 0 into 2 to the power minus 2
plus 1 into 2 to the power minus 3 ok. So, then if you add them up 0.5, and this is 0.125 1
upon 8 is 0.125, so it is 10.625. And this is the way number, so this 2 means base 2 and
this 10 means base 10. So, 1010.101 base is 2 is equivalent to 10.625 in base 10. So, this
is the way we can convert from binary to decimal ok.
(1010.101)2 = (1 x 23 + 0 x 22 + 1 x 21 + 0 x 20 + 1 x 2-1 + 0 x 2-2 + 1 x 2-3)10
= (8 + 2 + 0.5 + 0.125)10
= (10.625)10
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And some important you know, this conversion - integer part over here it is shown,
which we keep in mind. So, only 1 is 2 to the power 0 it is 1, 10 is 2, 100 is 4 ok, 1000 is
8 so this way the sum of the things that we often in encounter.
And here we remember here we remember that this is 2 to the power 8, so this is
incorrect. So, when it is 2 to the power 8 ok, it is 256. So, when it is 2 to the power 10, so
this is your 2 to the power 10 so it is 1024; so 1024 here also is represented as 1 k. So,
when we say 1 kilo bit right, it does - it means 1024 number of bits, it is it does not mean
1000 bit that is there in the decimal system.
So, in binary or digital logic digital representation of numbers 1 kilo stands for 2 to the
power 10 which is 1024, so 2 kilo 2K represent 2 to the power 11 ok, so that is 2048 if
you multiply, if you can you can see that this is 2048. So, 2 to the power 20 is 1024 kilo
that is 1 mega. So, 1 mega is represented in this manner, so that is what we take note of
and also that there will be when we talk about 256, after 1 it is 2 to the power I mean, 8
0s are there ok.
And this is another thing we often come across 11 is 3, three 1s are 7, four 1s are 15, so
if 8 1s are there, this is 255. So, if you just increase increment by 1 the way we have seen
the odometer, so after that will be the next value - 10000 four 0 here and four 0000. So,
here this way what will get implemented to 256, this is your 256.
(Refer Slide Time: 16:06)
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Now, that was binary to decimal. If it is required that we have a decimal number we want
its binary equivalent, how do you do - ok. So, we do it by let us first look at the integer
parts. So, when we look at conversion of say integer parts 10, so we first divide 10 by 2
note the quotient and the remainder. So, this quotient 5 comes over here, you see the
colour, you know.
So, again we divide by 2, note the quotient and the reminder. So, earlier when 10 was
divided by 2, 5 remainder was 0 this time when it is divided, remainder is 1. So, this 2
again we divide by 2 right, this is 1 and remainder is 0, because it is completely divisible
2 is completely divisible by 2. And then 1 again when we divide by 2, basically we get
the quotient you know 0 and the reminder remains 1 ok, so that is because only that the
digit is less than 2 - right.
So, whenever we reach here there is no further you know scope, we stop this exercise
between successive division by 2 of the original number and the quotient that it gets.
And the remainders from bottom to top the way that has been shown here, we take note
of, with the first bottom most 1 is MSB, and top most 1 is the LSB that is 1010 that is the
corresponding binary equivalent of the decimal, that is how we look do the conversion
for the integer part.
And if we do consider the fractional part earlier, it was division, here it is multiplication
right. So, 0.625 if we consider the number we have seen before, so 0.625 first we
multiply by 2, so what will be the result? 1.25. So, 1.25 we look at the number which is
the integer part of it, we will call it carry we keep it here and the fractional part we keep
it here.
So, 0.25, then we multiplied by 2 again, so we get 0.5. So, there is no carry. So, this is 0,
and this is 0.5. And then 0.5, we multiply again with 2, we get 1 and this is 0 ok. So, in
this is after that there is no further fractional part available. So, this time we will go from
top to bottom. So, the topmost one is the MSB, MSB in the sense that comes after the
you know, the binary point and the bottom most point one is the LSB. So, 0.625, it is
corresponding binary equivalent is 0.101. So, this is the way decimal to binary
conversion is done ok.
315
(Refer Slide Time: 19:11)
So, we have one more example here 23.6. So, here what we do again we follow the same
process, we divide the number into integer part and fractional part. And you keep on you
know, dividing it by 2 successively, and get the quotients, the quotient again come here,
this quotient comes here right. And we note down the remainder, and then we read from
bottom to top. So, it will come as come as 10111. So, this part this is what will come.
And for the fractional part 0.6, we keep on doing the multiplication right. And whenever
there is a carry that is value becomes more than 1 right, we note it here. And then we
read it from top to bottom. And we see that when you come over here, it is not actually
fractional part is not becoming 0 right. So, it will go on giving some value over here
right, but in practical cases will be needing to truncate it because of some finite number
of bits are available to you only - in the realization.
(23.6)10 = (10111.10011)2
So, if it is truncated at 5 bits ok, so from top to bottom if we write, then it is 10011 that is
what we see here. So, if there are 6 bits, then another you know if you do the
multiplication then whatever number come, so that that will right here we will write here
7 bits accordingly between will be presented right.
316
(Refer Slide Time: 20:56)
So, octal weight we had just seen in the discussion where we have seen the odometer. So,
if in some case, octal number based representation is required ok, then we know the valid
digits are 0 to 7, this is we have already discussed. And these are the corresponding
weights for the place value. So, after octal point, it will 8 to the power minus 1, 8 to the
power minus 2 the 1 that I have said before. So, octal the valid digits are 0 to 7 only.
So, considered a octal number 35.6 ok, then what is the corresponding binary? It is very
easy to convert from octal to binary, and binary to octal. So, what we need to do only, we
form a group of 3 - group of 3 ok, because in octal this 2 to the power 3 - 8 is 2 to the
power 3 right. Binary is base 2 and this base 8. So, 3 we represent it in this manner, 5
represented by this is the octal point which becomes a binary point, and 6 is this one
right.
So, first we represent in this manner. And after that the leading 0, before the binary point
and the following 0, after the binary point, we ignore because that does not carry any
sense, this is the corresponding binary equivalent. And if you have to convert from
binary to octal, so this is the binary number. So, this is binary point is the difference
point, so from this binary point we keep forming group of 3 ok. So, this is one group, this
is another group, this is another group - the integer part.
And when you see that only one member is there, so you can put some leading 0s to
make a group of 3. And after the I mean the regarding the fractional part again this is the
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reference point, so you form the - a group of 3. Then again to form a group of 3, you do
not have 3 digit is there, only 1 digit is there you put some - two succeeding 0s, a group
of 3 is formed right. And then for each of these group you represent the corresponding
octal equivalent. So, 001 is 1, 101 is 5, 110 is 6, and 101 over here is 5, and 100 over
here is 4 ok. So, this is way from binary to octal conversion can be done.
And there is another number system you may come across in the digital electronics
discussion, that is called hexadecimal. So, hexadecimal as got a base 16, and 16 means
then 0 to 15, I mean 16 digits will be there, but decimal numbers are up to 9. So, after
that what is done the capital letters A, B, C, D, E, F are used which is equivalent to 11,
12, 13, 14 and 15 right.
And if you look at the number representation, the weights will be 16 to to the power 0
over here units place; 16 in the second place, 16 square in the 3rd place, before this
hexadecimal point and 16 to the power minus 1 here, and then to the power minus 2 after
the hexadecimal point, it will go on right.
And the conversion is similar to octal system, again because it is 2 to the power - 2 to the
power 4 is 16, so will be forming group of 4 - group of 4 binary digit. So, if 3D.6 is to be
represented in binary. So, 3 will be represented by 4 binary digits. D ok - if you look at
the corresponding value over here, it is I mean, in the binary representation this is 1010
this is 1 0 1 1, 1100 and D is 1101 ok. So, this is your D right. So, and then 6 is 0110 in 4
binary digit. So, again leading 0 and following 0’s before and after the binary point you
ignore, and then this is the corresponding number.
And binary to hexadecimal conversion, again will be forming group of 4 with starting
from the binary point as reference. For integer part you will go towards left, and for
fractional part you will go towards right - keep forming groups. And if required you add
some leading 0 or succeeding 0s, and then you convert it to corresponding hexadecimal,
and the job is done.
And to get octal, hexadecimal to decimal conversion is already you know - integer power
to the 8 sorry, 8 to the power 1, 2, 3 etcetera or 16 to the power 1, 2, 3, so that kind of
what kind of multiplication with coefficient you add them up, you will get the
corresponding decimal value. And decimal to octal - earlier you have done for binary, it
was division by 2 for the integer part, it will be division by 8 or 16 for the integer part.
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And for the fractional part it was multiplication by 2, it will be multiplication by 8 or 16
the method the similar.
(Refer Slide Time: 26:34)
Having noted this and also earlier that - specially the fractional part ehich, do not have
you know all the number of bits that is required to get the kind of precision that you
require. So, in actual practice, we’ll be having a fixed number of bits available to
represent a number. So, with these fix number of bits in a presentation, which is called
fixed-point representation of number; the width that is the number of bits total number of
bits available to represent the number, and the position of the binary point are defined ok.
So, to give you an example if the 8 bit stored in the memory is this 10011110 ok, and it
is represented in fixed 8, 3 representation. So, this is the understanding that this is this
number stored in the memory are represented in this manner right. Then of course, the
width is 8 ok, so 8 bits to be taken. And then binary point will be fixed at you know, after
the binary point, there will be 3 digit, so 110. So, this is the corresponding value in the
decimal, if you just convert binary to decimal this is what you will get.
Instead if it was 8, 4, so 4 digit should have been there. So, same 8 bits, because width
given is the same right that is what you have mentioned here, the width to be 8, so then
what happens. So, this value, becomes integer value becomes less, and the fractional part
we have got we know more interest. And then if you add them, this is 9.875 that what is
you get in decimal equivalent.
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And instead, if it was 8, 2, it was 8, 3; 8, 4, this is 8, 2 so 2 digits will be there after the
decimal after the binary point. And again if you convert to binary to decimal, you get
39.5 ok. So, the same number depending on the number system you know - the fixedpoint representation, has different values. And one thing you note here that by shifting
these binary point ok if you are shifting it towards left, from here your shifting its
towards left what has happened the number has become divided by 2. You can see that
this number 9.875 is half of this one.
And if you shift it towards right, this was 0.110, this is 0.10. This is 39.5 it is multiplied
by 2. So, if you shift 2 units, it will be 2 to the power 2 that will come into picture you
know 2 units to the right. So, it is multiplied by 2. And if it is 2 unit to the left it is
divided by multiplied by 4; and if it is 2 units to the left it is multi a divided by 2 to the
power 2 that is 4 ok. And one good thing about this fixed-point arithmetic is that integer
arithmetic circuit can be used because integer representation is just a special case of this
where there is no bit after the binary point ok.
(Refer Slide Time: 30:04)
So, the last point just to conclude the there is another representation called floating-point
representation. So, what we have seen in fixed-point representation that is 8, 4. So, there
are you know 4 digits after the binary point. So, the precision that is available is 2 to the
power minus 4 that is 0.0625. And 8, 3 three digits, so precision is 0.125. So, here the
precision is better and here the position is bit less. But in doing that what you see the
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range over here is you know less compared to the range in the other case. And in fixedpoint representation, once you fixed the representation, the precision is always fixed ok.
So, this is what we have noted.
And one simple formula to calculate the range is the number of bits that is before the
binary point is A and after the binary point is B, then it is - can be calculated in this
manner right. So, now in so - then came another representation, it is called floating-point
representation where the binary point is not fixed, binary point in the number in the bits it will, it can move from left or to write.
The idea is always we’ll be having in a normalized version a 1 present here and rest is
the number of you know, the number of - which is after coming after the fraction. So, if
the original number is 1101.01 right, we shall shift the number you have already noted
the shift. So, we are - we shall shift the number in such a manner the decimal point
comes over here. So, normal only 1 will be present before the decimal point ok. So, this
is the corresponding number. So, how many shifts are there. So, 3 shifts are there. So, 3
shift means to the left ok, so that means, it is 2 to the power 3. So, this into 2 to the
power 3 is same as this number right.
So, in floating-point representation we note this 3 the exponent, in the exponent part, and
what is after this 1 that is 1 0 1 0 1 this part right, so that is noted in the mantissa part.
So, this we mention how many bits are reserved for exponent part, how many bits are
reserved for mantissa part also ok. We have not discussed yet the negative number or the
sign that part will come later. So, here we are talking about the magnitude part only. So,
the number will be represented in this form M into 2 to the power E, M is the mantissa
part that is what is coming after the fractional point, when a 1 is present just before the
binary point and the number of shift that is required for which the exponent terms gets
defined ok.
Number = M x 2E
So, this number will be stored in the memory, in the floating-point representation by this
convention is as 011; 011 is the exponent that is 3 over here and the fractional part with 1
in the left hand side 10101, so that is what it will that is how it will be stored in the
memory, so that is the floating-point representation. Here the gap between consecutive
numbers is high for larger numbers and small for smaller numbers. So, precision is not
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fixed. So, we shall mostly deal with fixed-point representation in our subsequent
discussion later.
(Refer Slide Time: 34:00)
So, let’s quickly conclude. Number system with base r, a base or radix r has digits 0 to r
minus 1. Place value or weight is multiplied with digit to find its contribution ok. So, if it
is multiplied with 0, then there is no contribution. To convert the decimal to binary,
integer is successively divided by 2 and remainders accumulated; and for converting the
fraction, it is successfully multiplied by 2 and carry is accumulated. And for octal and
hexadecimal system, the processes similar for the conversion but instead of 2 we are
using 8 or 16 for octal and hexadecimal, respectively.
And octal hexadecimal to binary relationship I mean, (Refer Time: 34:49) it considers
grouping of 3 or 4 binary digits. And, fixed-point representation has fixed precision.
Fixed-point arithmetic is similar to integer arithmetic and we shall discuss elaborately
that part later. And floating-point representation has variable precision and gap between
number is higher for larger numbers.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 22
Negative Number and 2’s Complement Arithmetic
Hello everybody. In this particular class, we shall look into representation of Negative
Number and 2’s Complement Arithmetic. So, we had got introduced to number system in
the previous class, but in that we did not discuss how to represent negative numbers. So,
we shall cover these concepts; how to represent through sign magnitude representation;
1’s complement, 2’s complement; how to do binary addition and subtraction and how to
perform 2’s complement arithmetic.
So, Sign magnitude representation is very simple ok. So, we have a sign bit specially in a
you know, place which is towards the left hand - left most side considered that is MSB
Most Significant Bit and rest is the magnitude ok.
(Refer Slide Time: 00:59)
So, any number the magnitude part will be represented here right and the sign part will
be represented here. So, sign if it is 0, we consider it is to be positive; 0 is taken as
positive and 1 is taken as negative ok. So, this is the convention. So, in these, if we have
got so, 8 bits to represent a number and we are considering say integers only and fraction
can be taken up later so, this 0 0 0 0 0 0 0 1 ok. This 0, this particular bit is the sign bit.
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So, this 0 means, so this is positive and rest 0 0 0 0 or and all you know all these are 0
and this is 1.
So, in the - from the previous class discussion we know that this gives a magnitude in
binary which is 1 only because it is unit plus 2 to the power 0 multiplied by the
coefficient 1 and rest of the cases the coefficient is 0. So, it is only 1. So, this is plus 1
ok. So, how will you represent a minus 1 in this convention, in this representation? So,
the magnitude part will remain same; only the sign bit changes from 0 to 1 ok. So, if we
have 1 0 0 0 and 0 0 1 like this 1 six 0’s and 1, then we know that it is minus 1. So, this 1
over here is not associated with the place value that 2 to the power something that we
have seen before ok.
0000 0001 : +1
1000 0001 : -1
So, it is not 2 to the power 7 right. So, this is only a sign bit right. So, similarly if we
consider say this particular number, how do you what is this number. So, 0 is here. So, 0
is positive this particular sign bit. So, this is 1 so, 16 16. This is four’s place 4; 20 and
this is 2’s place so, 2; 16 plus 4 plus 2. So, 22. So, this is plus 22. So, other bits
remaining the same; 0 becomes 1. This is minus 22. In the last class, we have seen if all
these are 1 right. This is 127. You can also calculate you know like (Refer Time: 03:41)
64 plus etcetera etcetera right. So, this is 0 means plus 20 plus 127. This is 1 means
minus 127 ok. So, in this representation with 8 bits; what we can represent? We can
represent from minus 127 to plus 127 right minus 1 0 etcetera etcetera.
So, that makes actually 2 into 127, 254 and 0. So, 255 numbers getting the presented by
8 bits and in this 0 is represented twice like one here, another there ok. So, one
representation is missed here - we missed. With 8 bits, you can have 2 to the power 8,
256 representations. Here only 255 numbers get represented.
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(Refer Slide Time: 04:33)
So, this is one way of representing it. Another representation is for negative number is
called 1’s complement number ok. So, in 1’s complement, what do you do? We just take
an inversion of the positive number. I mean you take a complement of the positive
number. So, this is the positive number. So, first bit is the sign bit right. So, 0 0 0 0 0 0 0
1 plus 1 that is the way we have seen it before. So, then you just take inversion of it. So,
0 become 1; 0 become 1 right and this 1 becomes 0 over here. So, 1 1 1 1 and 1 1 1 0 this
is the minus 1. Plus 22, we have seen before.
So, if you just take inversion of it. So, wherever 0 is there, it is 1; 1 it is 0. So, this is the
corresponding representation this is minus 22 ok. So, plus 127 we have seen. So, minus
127 is this representation. So, this is called 1’s complement representation. So, in these
also in this also we have got minus 127 to plus 127, 0 included. So, 255 numbers
represented and 0 is represented twice; one by this, another by this.
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(Refer Slide Time: 05:56)
Next comes 2’s complement representation. So, in 2’s complement representation, the
negative number is obtained by adding one - 1 to the 1’s complement. So, 1’s
complement, first we are having we know how to get and after that you add 1 will get 2’s
complement representation. So, for example, plus 1; this is plus 1 we have already noted.
So, 1’s complement we have seen before, add to it 1. So, this is 2’s complement. All 1’s,
all eight 1’s this is 2’s complement of representation of 1 that is minus 1. So, earlier all
this 1 in 1’s complement, it was another version of 0. So, this is not 0. So, this is
different ok. Here all eight 0’s are only 0; all eight 1’s are not considered as 0 right.
Similarly, the same example of plus 22, if we see for minus 22 in 2’s complement
representation; 1’s complement is this one, add to that add to that 1. So, we get 2’s
complement representation of minus 22 right. So, that way we can continue and we have
if you look at say plus 126, this is the representation; minus 126 means you invert all the
bits and then add 1, this is what you get for minus 126. 1 four 0s 0 0 1 0 is minus 126.
1 0 0 0 0 0 instead of 0 0 1 0, 0 0 0 1 is minus 127 and another representation that comes
which comes within the range which was earlier outside the range 1 0 0 1 0 0 right, rest
of the bits remaining same that is your minus 128 ok because now, 0 is not represented
twice. 0 is represented not by this one, only by all 4 eight 0’s. So, we could push one
number over here right. So, that is the 2’s complement representation of 128 that is
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minus 128. So, the range here becomes minus 128 to plus 127, within that there is a 0.
So, 256 numbers can be represented by this.
(Refer Slide Time: 08:31)
Now, if 1’s complement number, if you take another 1’s Compliment, we get back the
original number, is not it? So, that we have already - we can understand. What happens if
we have a 2’s complement number that is a negative number. If you take again 2’s
complement of it; so, let us look at the example. So, this is minus 1; all eight 1’s. If you
take 1’s complement of this we get all 0’s and then, plus 1, it makes the 2’s complement.
So, this is 0 0 0 0 0 0 0 1 right. So, that is what? That is your original positive number
plus 1.
So, 2’s complement of minus 1, I mean the decimal version of the minus 1 right, we get
decimal version of the plus 1; so, this was minus 22 all right in 2’s complement and if we
a look at its 1’s complement right. So, this is 0 0 0 1 all right and 0 1 0 1 add to that 1 0 0
0 1 0 1 1 0, what is that? That is your plus 22 right. So, 2’s complement - again, you do
2’s complement, you get back the original number right. So, minus again another minus
so, you get the original number back. So, this we take note of.
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(Refer Slide Time: 10:03)
Now, let us consider how we can do Binary Addition and Subtraction ok, in the binary
system. So, similar to decimal number addition and subtraction do you usually do, we
can follow the same thing over here. So, first we look at the addition part. So, 0 plus 0 is
0; 0 plus 1 is 1 right and 1 plus 0 is also 1 and when we add 1 and 1 right, it will become
2; 2 in binary is 1 0 right.
0 + 0 = 0,
0 + 1 = 1,
1 + 1 = 10
So, this is called carry also you know, this is the 1 units place and this is 2’s place ok,
carry is there right. So, when we add say 21 with 33; just you know 21 in decimal 33 in
decimal right. So, 21 we represent in this manner; 16 4 and 1 ok. This is the place - these
1’s are there, 33 right. So, this is 32 - 2 to the power 5 and this is 1; so, 33 right. So,
when you add them up 1 plus 1 is 1 0. So, this 0 comes here, 1 is the carry. So, 1 plus 0
plus 0 this is 1. This is 1 over here, then 0 comes here. This is 1 and this is 1.
So, 0 0 1 1 0 1 1 0 so, this is the number that we get right. So, this is your fifth - 2 to the
power 32 plus this is 16; that is 48; this is 4; that is 52 and this is 2; that is 2; 52 plus 2 54. So, you get this is the decimal equivalent is 54 and you can see if you do addaddition you get 54 right. Similarly, you can do it for 23 and 101. As long as the result is
within the range, we do not I mean, we can go on doing this, when it goes out of range
we have to, we cannot get the right result, valid result ok. So, this example you can also
see that 1 plus 1 is 0. So, carry is 1. So, carry 1, 1 again 0 and another carry is there so,
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three 1’s. So, three 1’s means 1 1 is the result. So, 1 is here and carry is 1 and this 1 0 0
this is 1, then rest are 1 1 1.
And again, if you convert to this to decimal you get 124 ok. And for subtraction - so, 0 to
0, it is 0. 1 to 0, it is 1. 1 to 1, it is 0 and when you subtract 0 to 1 right. Then, you have
to Borrow a 1 from the previous stage previous stage. So, that will make it 2. So, 2 minus
1 that we will make it the answer will be 1, but there is a Borrow 1 which need to be
subtracted from the 2’s place, I mean the next higher rated place that need to be
subtracted that we need to take note of that is concept of Borrow ok. So, you look at one
example. So, 21 minus 2 right so, 16 4 and 1. So, 21, we have seen it before and this is 1
0 - 2 ok. So, how do you do it? So, 1 minus 0 - 1.
0 – 0 = 0,
1 – 0 = 1,
1 – 1 = 0,
0 – 1 = (1)0 – 1 = (1)1
So, it is 1, then 0 to 1 ok. You take a Borrow ok. So, when you Borrow, this is 1 0
become becomes 2. So, 1 0 that is 2 minus 1 is 1. So, there is a Borrow; this Borrow is to
be subtracted from the next higher bit over here. So, this 1 is subtracted from 1 you will
get 0 right. So, 0 0 and this is 1. So, this is 16. This is 2 and this is 1. 16 plus 2 plus 1, 19
so, you can see 19. Similarly you can look at other example right and this is similar to
decimal addition and subtraction.
And when the sign I mean when a larger number is subtracted from the smaller number
ok, as is the case of say an example 5 minus 8, what we do in the normal decimal
subtraction? We subtract from the we put a minus sign and subtract from the larger
number ok. So, basically minus of 8 minus 5 right; so, this number comes as 3 and this is
minus 3 right. So, similarly in this case also if you require, you can do it in this manner
right. So, you just see that this is the larger number, then you subtract it see this is larger
number. So, sign is coming here; minus sign is coming here because this is the sign bit.
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(Refer Slide Time: 15:05)
Now, in this digital electronics or in the binary system, when we perform arithmetic and
we have circuits. building blocks using gates and all logic gates, then we prefer 2’s
complement Arithmetic for some inherent advantages ok. So, we shall discuss 2’s
complement arithmetic now. 2’s complement number representation, we have already
seen. So, in this addition is normal standard process and in subtraction when you have to
do this subtraction part what we do - we get 2’s complement of the original number to
make it negative. So, subtraction is - a number that is getting subtracted and then, we add
these 2 numbers. So, basically subtraction here also becomes an addition process right.
So, adder block - adder circuit can perform both the job of addition as well as subtraction
- right. For that when we are talking about subtraction, we have to represent the number
in 2’s complement form - ok. To get make a negative number out of it. So, this is the
basic concept. This is the basic concept and how it gets done? So, this is the minuend and
this is the subtrahend. So, subtrahend we are taking the 2’s complement ok. And then, we
are getting the difference.
And, addition is simple. Addition is normal process, the way we do it – say, example is
83 plus 16, we can just you have done it before; you can do it the same manner. We shall
see that 99 is obtained. Now, let us look at how 83 is - 16 is subtracted from 83 using 2’s
complement ok. So, 83, 16 here when we talk about this number to associate the value of
this number, we are talking about decimal systems; but what actually we’ll be
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performing - the operation using binary. So, first of all these 16 is Subtrahend. So,
Subtrahend we have to convert it to negative number by 2’s complement right.
So, this is the number in 16 when it is positive. So, 16 plus 16; plus 16 its 1’s
complement is this one right. Only this 1 place become 0 right; rest are 1 and then you
add 1 to it; it becomes 2’s complement. So, this is your minus 16. So, this is the first
step. So, then this number 83 right so, 83 is this 1 - 64 plus 16 that is 80 - 2 and 1.
So, this is 83 ok. You look at the weights and then you add. So, then add to it this minus
16; four 1’s and 0’s right and if you add it, the normal addition operation. So, 1- 1 this is
0 - 0; then 1 1 - 0. This is 1 1 - 0. This is 1 1 - 1. This is 1; there is a 1 carry over here.
So, this carry 1 1 - 0 and this is a final carry 1 is what you get. And if carry is generated,
discard it and the answer that you get is positive. So, the result that you get from this
operation is to be finally, understood by this manner; if there is a carry generated, discard
it right.
And rest of the number is to be taken as the final answer which is positive. So, if you
look at it this is 64 right and this is 2 and this is one 63 ok. So, that is what you get right.
This is 64 2 - 66 and 67 sorry, this part ok. Is this clear? Right. 67 in decimal now you
have to look at other combinations. So, for example, subtracting larger number from
smaller number and other things we shall look into that aspect now.
(Refer Slide Time: 19:46)
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So, 16; early it was 83 minus 16; now it is 16 minus 83. So, for that what we will do? 16
will go as 16 like this; 83 you have to get minus 83 that is the Subtrahend now. So, we
have to get minus 83. So, minus 83 you can get by 2’s complement. Again we perform
the 2’s complement you get this one right and then, this 83 - we this minus 83, we add
and this is what we get and interestingly in this case you see that carry is not generated
ok. So, no carry ok.
So, no carry is generated right and the sign bit that you see here is say 1. So, we know
that the answer that we have got is negative and in 2’s complement form. So, this answer
is of course, because of the presence of 1, it is negative and entire thing is 2’s
complement form. So, if you want to know its magnitude - 2’s complement, if you are
not very conversant, then we have to do 2’s complement of this number only to get the
corresponding positive part of it, the magnitude part of it.
So, this is what you get here 1 0 1 1 1 1 0 1 if you perform 2’s complement of it right,
then you get 0 1 0 0 0 0 1 1. So, this is 0 1 0 0 0 0 1 1. So, this is 64 2 and 1 so, 67. So,
that gives you the magnitude part, but you already know the answer is negative ok. So,
when you are doing the binary to decimal conversion right, then you convert it back to
the normal number representation right; do not use the weights on the 2’s complement,
the negative number.
And you know the numbers are negative - number is negative ok. So, carry is not there.
Sign bit is 1. The answer is negative and magnitude can be obtained by again
performing 2’s complement. So, 16 minus - 16 minus 83 we get minus 67 right. Result we shall get in this form. We know the answer is negative, no carry. Sign bit is 1 and to
get the magnitude, we perform another 2’s complement.
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(Refer Slide Time: 22:23)
Now, if we want to perform subtraction from a negative number - that is also possible,
that is also possible right. So, how we can do that? So, the negative number in the first
place, say, it is 83 ok. Same example we continue with different you know combinations.
So, minus 83 we have already found to be 1 0 1 0 1 1 0 1 in the previous example.
So, this is minus 83 and 16 is subtracted ok. So, basically it is minus 83 plus of minus 16.
So, minus 16, we have already calculated minus 16 before. So, this is your minus 16; you
add them up. So, this is what you get here right. So, we have got a carry right, we discard
this carry and if we see the sign bit here is 1 right. We know the answer is negative and
when the answer is negative, it is in 2’s complement form.
And do you want if you want to know the magnitude of the value, I mean you need to
convert from binary to decimal; then we have to take another 2’s complement of it to
find the magnitude. So, 1 0 0 1 1 1 0 1 if you take 2’s complement of it you get 0 1 0 0 0
0 1 1 right.
So, this is your 64. This is your 16 - this is your 32 rather, this 2 to the power 5 – 32. 64
plus 32 is 96, this is 2 - 98 and this is 1- 99 ok. So, 99 in decimal and the number is
negative because sign bit is negative right. So, this is the 1; whenever you are adding you
know positive with positive and here effectively it is negative with negative, you have to
be careful that it doesn’t go out of the range ok. So, if it is positive and negative. And
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negative and positive, it is always within the range right. So, this is something that we
take note of.
(Refer Slide Time: 24:37)
And if you want to subtract a negative number; so, negative number subtraction is what?
I mean it is basically addition of two positive numbers. So, this is minus 16 in first place
this is. So, this is your minus 16 right. So, since it is a subtrahend, it is there in a
subtrahend - we take 2’s complement of it then what will happen we will get back the
original number, original positive number. So, that is your 16 ok. So, this is 16’s place 2 to the power 4 right. So, this 16 and this is 83.
This is 83. And this is 16. So, if we add them up you get corresponding decimal
equivalent of 99 right and you see that this sign bit is positive right. So, if we then,
combine the different things that you have seen this is effectively addition only. For
subtraction, take 2’s complement of the subtrahend; add it with the minuend; discard
carry if there is any.
If the sign bit is 0, the answer is positive and can be directly read and interpreted. If sign
bit is 1, answer is negative and in 2’s complement form ok. If you want to know the
magnitude; that means, you want to convert from binary to decimal equivalent - the
magnitude part, then you have to take the 2’s complement of this number. And the
number will come in the form of the way the weights are placed 1, 2, 4, 8 and then, we
can convert it and you can get the corresponding number.
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So, this is how we can go ahead with 2’s complement arithmetic which we shall be
using. In the previous class, we have seen the normal integer representation - fixed point
representation. So, all these are very easily done, prominently done using 2’s point
arithmetic.
(Refer Slide Time: 26:49)
To conclude, sign-magnitude representation has a separate sign bit. Using 8-bits, the
range of numbers that can be represented using sign-magnitude representation is minus
127 to plus 127. So, 255 different numbers can be represented using 8-bits. In 1’s
complement representation, negative number is obtained by 1’s complement or inversion
of positive counterpart ok. The range is again from minus 127 to plus 127; 255 different
numbers can be represented by 8-bits.
In 2’s complement representation, negative number is obtained by adding 1 to 1’s
complement number and the range we have seen here is minus 128 to plus 127. And
when we perform binary addition, carry may be generated and in a binary subtraction
borrow may be there ok. So, these are the things that is similar to decimal addition,
subtraction, but here you are doing it with base 2.
In 2’s complement arithmetic, subtraction is done by considering addition of negative
numbers. So, basically first you convert it to a negative number, the number that is there
in the subtrahend by taking 2’s complement of it then we add it with the binary. For 2’s
complement arithmetic, rules can be framed to get the result of all possible cases of
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addition - subtraction; that means; a smaller number is subtracted from a larger number;
a larger number is subtracted from smaller number.
So, the presence of carry is ignored and if carry is not there and the sign bit is 1, then the
answer is negative and its magnitude is obtained by 2’s complement of the number. So,
these are the different rules that can be framed and by which 2’s complement arithmetic
can be performed
Thank you.
336
Digital Electronic Circuits
Prof. Goutam Saha
Department E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 23
Arithmetic Building Blocks – I
Hello everybody. In the last class we have discussed number systems and arithmetic
operation: binary addition, binary subtraction, 2’s complement arithmetic. So, we have
understood the theory behind the arithmetic operation - addition, subtraction operation
using binary numbers. Now, in this particular class we shall look at circuits by which
these arithmetic operations can be done. So, it will be extended to next class as well.
(Refer Slide Time: 00:50)
So, we shall discuss half adder, full adder, ripple carry adder and adder-subtractor unit in
this particular class.
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(Refer Slide Time: 00:58)
So, first we discuss half adder. Why it is called half? It is because it is does not consider
any carry from the previous stage. So, if you are considering addition of two numbers
say, 1 0 0 1 and with another number say, 0 1 0 1. So, in the first stage when you are
adding these numbers in unit’s place - carry is not required from the previous stage. So,
there comes the usefulness of the half adder –ok. And when - in the next stage - so, this
is 0 and this is 0 and a carry is generated from the previous stage. So, basically there are
3 inputs.
So, first stage there could be 2 inputs. So, that is what is half adder - half addition. So,
half adder has got two inputs A and B right and it generates data outputs which is one is
sum, another is carry. So, this is augend, this is addend - sum and carry ok. And we
designate by A B and S and C the way we have seen in this particular block. And, what
would be the corresponding truth table? So, 4 possibilities at the input 0 0, 0 1, 1 0 and 1
1 are the inputs - then corresponding output 0 added with the 0, carry is 0, sum is 0. 0
added with 1 carry is 0 sum is 1. 1 0 sum is 1 carry is 0 and when both of them are 1
carry is 1 and sum is 0.
So, how we write it in the form of a logic equation to realize the circuit? So, the carries C
is you can see it is simply A and B ok. This is the minterm associated A and B - both are
having value 1 and sum is obtained – sum bit is obtained with A prime B and A B prime.
So, this is your A prime B and this is your AB prime you sum them up and that is
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nothing, but XOR operation. So, this is the circuit which is there is side this particular
block ok. This is half addition.
C = A.B
S = A’.B + A.B’ = A⊕B
(Refer Slide Time: 03:12)
Now, when you talk about full addition, as I have mentioned before, we are also
considering the carry input. So, then this particular block will be having 3 inputs. So, the
basic data input A and B - that particular addition process and carry that is coming, if it is
there from the previous stage right. So, this is the carry-in now you are separating it from
carry-out. So, this is input. So, then there are with these 3 inputs - there are 8 different
possibilities in the truth table.
So, we, if we investigate the truth table for carry in 0 we have what we had seen in case
of the half adder, the truth table simply follows the half adder. And, when carry is equal
to 1 then we are looking at - if carry-in is 1 and 0, 0 then the output is 1 this is 1; and one
of the inputs is 1, then a carry is generated and this sum bit is 0. And, when all of them
are 1 then carry is 1 and this output is also 1.
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So, how we write an equation for this - Boolean equation for this. So, we can use
Karnaugh map for minimization or we can take the minterms and then we do algebraic
manipulation. And, by that we can find that carry-out is AB, ACin BCin ok, if we
combine these product terms, we get the carry-out, right. So, just we can see for
example, when A and B both are 1. So, A and B both are 1 here and here – right. At that
time, irrespective of carry-in is 0 or 1 right - the output, carry-out is 1, you can see.
When A and C in this particular term A is 1 and Cin is 1. So, A is 1 here and Cin is 1
here. Cin is not 1 here -so, this is not 1 here. So, Cin is here and C in is here this is this
are the 2 cases right and both the cases - in these 2 cases, irrespective of the value of B
you see the output - carry output is 1, right. So, accordingly you can find out otherwise
you can minimize also using standard process and you can find the carry out is like this.
And, what about the sum bit? You can again see in this particular truth table when one or
three 1s are present in the input combination - in this input combination one or three 1s
are present, then the sum bit is - sum output bit is 1.
So, that is that is nothing, but a 3 input XOR operation right. So, that is A XOR B and
then XORed with the Cin that is what gives you the sum output. So, then the circuit is
simple. So, basically this is the 3 AND gates generating AB, ACin, BCin terms and that
are ORed to get Cout and this 3 input XOR gate, that is generating the sum bit.
Cout = A.B + A.Cin + B.Cin
S = A ⊕ B ⊕ Cin
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(Refer Slide Time: 06:39)
So, full adder generation using half adder. So, if you have got half adder circuit made by
someone and several such units are available and you want to get full adder what you can
do. So, we can see that two half adders and one 2 input OR gate are sufficient to get a
full adder out of it ok, out of those basic units. So, how we can get that we can see over
here.
So, carry-out we have this is the basic equation we can write it in this form also C in has
been taken common and out. So, Cin A plus B right. So, this is OR operation right. So,
this OR operation includes all the minterms except A prime B prime right. So, if A and B
both are 0 that time only the OR output is 0 otherwise OR output is 1 for all other
combinations; so, all other - all 3 combination ok. Then what you do? You take AB
prime and A prime B out over here.
Cout = A.B + Cin.(A + B)
= A.B + Cin(A’.B + A.B’ + A.B)
= A.B + Cin.A.B + Cin(A.B’ + A’.B)
= A.B.(1 + Cin) + Cin(A.B’ + A’.B)
= A.B + Cin.(A ⊕ B)
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Why? Because, we need the XOR relationship from the half adder to be used in this full
adder development, and this Cin AB is taken here. So, if you take to common then A B
ANDed with 1 OR Cin that is AB only - right. So, we can see A and B are given as
input, we can generate this term from one half adder this color you can see, this colour
right.
So, A B over here and A XOR B - we can generate by this - right. And, then this, the rest
of the terms that is A XOR B which is already generated to be ANDed with Cin here and
for the sum generation this A XOR B is also XORed with Cin. So, this is - this can come
from the another half adder block. So, this A XOR B these A XOR B output from first
half adder that is going to another half adder right, this is half adder the XOR input and
Cin to get the final sum output and the other input where A XOR B is ANDed with Cin.
S = A ⊕ B ⊕ Cin
So, this Cin you can see that is getting ANDed with Cin to generate this particular term,
this particular term right. So, this two terms are now available A B and Cin ANDed with
A XOR B over here and we just need to OR them. So, this is the way we can get it.
(Refer Slide Time: 09:24)
Now, we have seen 1 bit addition - right. So, if you want to multiple-bit, some bit
addition for example, say 4 bit addition how we go about. So, in that particular case we
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need multiple such blocks of full adder. So, inside the full adder we know the circuit that
is there. So, that has been seen in the previous slide.
So, this is the full adder slide ok. So, this is the full adder block and full adder block we
are using to develop 4 bit addition ok. So, what you can see over here is this, each of the
full adder, this is the first stage which I said it could have been half adder also ok. And,
then the corresponding inputs are numbered A: with A 3 to A naught as different bits and
number B: B 3 to B naught, 4 bit number - different bits.
So, A 3, A 2, A 1 - A 3, A 2, A 1, A naught supplied to one of the input of the each of
the full adder and B 3 to B naught to the other ok. And, carry of the first stage is fed us
carry of the second stage, carry of second stage is fed us the carry of third stage and carry
of third stage is sent as carry of the fourth stage. So, this is way we normally do the
addition and this is the final carry right. So, then this whole thing together, it will give
you sum bit sum bit, these are intermediate carry - ok.
This C naught C 1, C 2 or intermediate carry; so, the final output will be S naught S 1 S 2
S 3 and C 3 ok, the way we have seen it here right. And, if we are using full adder
instead of half adder for the first stage we shall make the C minus 1, first carry input 0
right. And, if it is a block which is to be cascaded with another block, there is block
proceeding to it, then that block carry output which is C 3 will be fed as input here. So,
in a previous block, carry output, will be fed as input to this particular block ok, if that is
to be used in cascade there are more than 4 bits to be added and this is the 4 bit unit right.
And, if you just look at one example how the addition takes place say, 1 1 1 1 is your A
and B is your 0 0 0 1 - three 0 and 1. We have taken this specific example you can see
right this is the very simple addition, but each of this cases one carry is generated. So, 1
plus 1 this is 0. So, carry is there. So, carry this 1 carry 1 and 1 this is 0 another carry is
there, this 1 and 1 again carry is there. So, this is a final carry. So, the carry which is
generated in the first stage C naught right.
So, this again goes as – to generate C 1, C 1 generates C 2, C 2 generates C 3. So, as if
the carry ripples through each of this adder - that is why it is also called ripple carry
adder – addition ok. This is the maximum you know distance it travels; so, as to say
maximum path - ok.
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(Refer Slide Time: 12:56)
Now, if we remember how we conducted 2’s complement arithmetic. So, subtraction we
got by addition ok. So, how did we do that? We got negative number of the original
number by taking 2’s complement of it. And what was 2’s complement? It was inversion
that is 1’s complement – 1’s complement then plus 1.
A + (- B) = A – B
So, remembering - remember that concept of 2’s complement arithmetic and we can see
how in the hardware we can implement subtraction 2’s complement - by 2’s complement
method by using adder circuit. So, now what we have got, this is the 4 bit full adder. So,
within it they are four individual 1 bit adder and we have already seen before how a 1 bit
adder is made using basic logic gates right. So, this 4 bit adder has got these 2 inputs,
adding logic, and this is the sum output and this is the final carry right.
So, the subtrahend the one that we want to subtract, we pass it through a bank of NOT
gate - inverter. So, at this point we get 1’s complement right and then we need to add 1.
Now, you can see the C minus 1, we made the first stage full adder, which could have
been half adder just for the addition purpose unless it is cascaded or so. But, here we can
see when we want to use this as a subtractor right then we need to add 1. So, that one can
come - can be fed here. So, automatically - you do not need to have any additional thing
to do. So, instead of this carry input 1 right which is doing the 2’s complement of the
number B..
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It is used to get the 2’s complement of the number B ok. Then we add, then we see the
result and we interpret the result based on the carry and other things the way we have
seen it before right. And so, how I mean - let us see the example. So, 15 minus 1 right.
So, 15 is your 1 1 1 1. Remember that here, we are using these four 1s. So, the sign bit
over here is implied - is the 0 over here. And, 1 is your 0 0 0 1 right. So, when you take
1’s complement of it. So, this is 1 1 1 0 right and then you add 1. So, what you get over
here? 1 1 1 0.
So, this is a carry that is getting generated we shall discard it and if you consider the you
know, in this case the sign bit then this would be 1 and then finally, there will be carry
generated right. So, these are implied things - the sign bit over here is implied right ok,
as long it is within the range we have no issue. So, this is this 1 1 1 0 is your final
answer. So, if you convert it decimal it is 14 right.
(Refer Slide Time: 16:35)
Now, we look at how we can get within the same arrangement, same framework both
addition and subtraction. So, for that what we are doing? We are - we have placed in
example of 8 bit adder subtactor ok. So, 8 bit adder subtractor so, we have got one 8 full
adder right. So, this is 1 full adder 1 2 3 4 5 6 7 8, we can see 8 full adders there and, the
numbers A naught to A 7 and B naught to B 7 right.
So, this is the way the numbers have been placed right. Now, you see one thing that this
B number B naught B 7 is passing though a XOR gate and one of the input to the XOR
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gate is connected to an external input. So, this external input we are representing as SUB,
standing for subtraction right. So, when you put it 0 right; that means, no subtraction is
taken place. So, it will be normal addition right. So, when this 0, XOR gate we know, the
XOR relationship - any input XORed with 0, it is the input itself right.
If SUB = 0, then C-1 = 0
Ex-OR gate output = Bi ⊕ 0 = Bi
F.A. output = A + B
So, at this point, at the output of the XOR gate right - what will come, it will come the
number B itself right; B 7 to B naught that will come and then this is 0. So, this will
come as a 0 right. So, it will be a normal addition, standard addition. Now, instead if we
have got SUB is equal to 1; that means, we are interested in doing subtraction. So,
subtraction is - when it is 1 of course, this carry, so called carry here, it will become 1
and B i XORed with 1 is B i prime.
If SUB = 1, then C-1 = 1
Ex-OR gate output = Bi ⊕ 1 = Bi’
F.A. output = A + (-B) = A - B
So, you will get inverted inversion of B over here complement of B - 1’s complement of
B and 1’s complement of B and added with 1, we get 2’s complement right. So, then this
2’s complement get added and then the normal output -we have seen before or we
understand how 2’s complement arithmetic takes place. So, it will be A plus minus B
that is A minus B. So, this is a single adder-subtractor unit which is performing both the
job of addition as well as subtraction depending on what you give here as input. If input
here is 0 this is addition, input here is 1 it is subtraction right.
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(Refer Slide Time: 19:26)
Now, we shall look at two examples how it happens in the hardware. So, we look at an
addition example to start with. So, the numbers that you want to add is 90 and 50 ok. So,
in decimal of course, and then the corresponding binary equivalent you have to get. So,
this is your 90 this is your A and this is your B right. So, this is your 64 right this one
represent, this is 16, 64 and 16 80, this is your 8 right, 64 plus 16 - 80 and 80 and 88 this
one is representing 2. So, 90 right so, this particular number is 90.
So, this we will put as A 7 to A naught. So, A 7 to A naught this how this is blue one that
you can see is A 7 0 1 0 1 1 0 1 0 that is how it is placed, is it and then 50 right. So, 50
for 50, what we are doing we have to convert first it to binary. So, this is your 32 plus 16
that is 48 and this is your 2 that is 50 right. So, this is in a different color. So, this is your
B: B 7 to B naught. So, 0 0 1 1 you can see 0 0 1 1 and 0 0 1 0. So, this is what is placed
here right and since it is addition operation. So, this input over will be 0, this carry input
here 0 and what will be the corresponding XOR output.
So, this is 0 - the same number will come over here, 0 0 1 1 and 0 0 1 0 and for the other
input of full adder will be the same as what is the original number is of course, because
there is no such case of inversion. Now, if you perform the addition you can see what is
happening intermediate carry and the final carry that will be generated and the sum bits.
So, 0 0 0 over here so, this intermediate carry output is 0 and sum is also 0. So, this is 0,
this is 1 and this is 1 right. So, sum is 0 this carry is 1 so, this 1 0 0 for the full adder. So,
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this is 1 and carry is 0. So, 0 0 1 that gets added. So, sum is 1 carry is 0; so, 0 1 1 for this
particular full adder for this particular full adder. So, sum is 0 and carry is 1.
So, this carry 1 - 1 these two sum bits - 2 bits addend and augend bits so, 1 and 1. So,
this is 0 and carry is 1 this 1 0 1 this 3 getting added. So, this 0 this is 0 and 1 0 0 this is
finally, you 1 and the carry is 0. So, this is the number that will get 1 0 0 0 - 1 0 0 0 1 1 0
0; what is the value right. So, this is your 64 after that it is 128 this is 8 - 36 and this is 4;
40 ok 40 clear. So, we shall look at one subtraction example right.
(Refer Slide Time: 23:07)
So, the same 90 and 50 is the original A and B we start with so that it becomes easier to
understand. So, this is your 90 and this your 50 right. So, A is placed as 90 this is the
blue colored one that you can see right and 50 is the brown colored one. So, that you can
see over here that is where how the 50 is placed. Now, the subtraction is - input is 1
because you want to do subtraction. So, the carry-in over here for the first adder is 1 ok.
So, this - because of this 1 there will be an inversion taking place for the XOR gate
because, 1 and 0 XORed is 1 right 1 and 1 for the second one. So, this is 1 and this is 1
XORed is 0. So, this is the way for the rest of the things right. So, this is how the full
adder input will be now looking like for each of these full adder. Now, if your perform
the addition so, this is 1 and 1 and this is 0 right. So, you just add them up. So, this is 0
and carry is generated as 1 ok. So, this is 1 0 1 - these 3 are added so, this sum is 0 carry
is 1.
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So, 1 1 sum is 0 carry is 1; three 1 sum is 1 carry is 1; 1 0 1. So, this is 0 carry is 1. So, 1
0 0 - 1 0 0 sum is 1 carry is 0 then these two are 1 and 1. So, sum is 0 carry is 1 and these
two are 1 1 sum is 0 carry is 1. Is it fine? So, this is the number. So, this 1 that is you are
getting here we discard it and this is what you get and the answer we know that it is
negative. So, basically this is representing that the number is sorry number this 1 is
getting discarded ok (result is positive).
So, if you have the concept of sign bit here so, this 1 will add will that sign bit. So, this
will become 0 and there will be a 1 here, that 1 will get discarded and this value will be 0
sign bit will be 0 right; if we include the implied sign bit here right. So, this is the
answer. So, answer here what we see, this is 32 right and this is 8 32 plus 8 this 40 clear.
So, this is how we do addition and subtraction and from the basic circuit that we have
seen.
(Refer Slide Time: 25:59)
So, to conclude half adder adds two binary digits to generate sum and carry. Full adder
also considers carry input, full adder also considers carry input from previous place and
thus has 3 inputs and 2 outputs ok. A full adder unit can be obtained by two half adders
and one additional OR gate. In ripple carry addition, carry output of one full adder is
connected as carry input of the next full adder. And, subtraction can be done by full
adder circuit - by 2’s complement method. Here, 2’s complement is achieved by a bank
of NOT gate and making the carry input 1. And finally, a full adder and the bank of Ex-
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OR gates for the subtrahend or addend input can give a circuit that can perform both
addition and subtraction ok. So, this is what you have seen in this particular class.
Thank you.
350
Digital Electronic Circuits
Prof. Goutam Saha
Department E and EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 24
Arithmetic Building Blocks – II
Hello, everybody. In the last class we had looked at adder-subtractor circuit, we defined
half adder, we defined full addition and then we looked at 4-bit addition, even 8-bit
addition and there we had seen ripple carry addition.
(Refer Slide Time: 00:33)
So, in today's class we shall look at how the propagation, what is the propagation delay
in ripple carry adder, how it is calculated and then we shall look at some circuit which
gives us fast addition; I mean where the addition done, addition is done in quicker time.
So, addition is done means - subtraction is also done when we talk about 2’s complement
arithmetic.
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(Refer Slide Time: 01:03)
So, we begin with what is the delay in ripple carry addition right. So, if you remember
the example where in 4-bit addition 1111 that is A was added with B 0001. We found
carry that was generated in the first stage – right, with that ripples through the
subsequent stages to come to get to arrive at the final carry. So, 1111, when it was added
with 0001 so, carry generated here; so, this carry is finally, coming to the final stage. So,
that is why it is called ripple carry.
So, if we place the numbers at a time say, t is equal to 0, and we assume that each of the
basic gate delay has a propagation delay tau, minor variation can be there - it is
approximately tau for each one of them - right and of course, we take note of that XOR
gate required a AB prime plus A prime B that kind of circuit which requires 2 tau gate
delay - that is the two basic gate delays if you consider the way it is arranged. So, if that
is the case then how much is the delay in completing the ripple carry addition for 4 -bit.
So, the maximum delay path the critical path that we shall see so, that is when the
number is placed and you have to wait for the carry to arrive at the endmost adder. So,
that is the time that will consider right. So, t is equal to 0 and we have noted that the
carry is generated by AB plus BCin plus ACin. So, that is one bank of AND gate and
there is OR gate. So, 2 tau delays is there to generate the first carry C note, right. So, this
will go over here, right and then again AND operation and OR operation will take place
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so, another 2 tau. So, C 1 will require another 2 tau that 4 tau C 2 6 tau and C 3 final
equal required 8 tau. So, if it is 8-bit it will require 16 tau. So, we see the propagation
delay here is cumulative and for n-bit addition 2n tau delivery be there, for the
generation of the carry.
Ci = Ai.Bi + Ai.Ci-1 + Bi.Ci-1
Si = Ai ⊕ Bi ⊕ Ci-1
And, let us see what is happening for the in the sum-bit generation. So, we considered
see S 3; so, S 3 will be Ai XOR Bi, right. So, this XOR first part is done in to 2 tau time
right, the XOR gate released 2 tau and C 3 C 2 is available at 6 tau. So, after that another
XOR operation is required. So, the 6 tau and 2 tau together 8 tau will be the time after
which S 3 is also available. So, that is the maximum time it is required.
So, others are available it earlier, but if you consider as a whole this 4-bit addition will
require 8 tau amount of time in maximum case, when carry is there at the endmost point.
(Refer Slide Time: 04:46)
Now, we said that we’ll look at some mechanism by which this addition - this time can
be reduced, right because you have seen if the number of bits are more then the delay is
you know getting accumulated, that is if bit is n, it is 2n tau - that kind of thing.
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So, one way of doing things is to investigate the carry generation equation and if we look
at it; so, this is the basic carry generation equation right and we see that there is a
recursive a kind of you know, activity within the equation. So, C i generation is waiting
for C i minus 1 C i minus will wait for C i minus 2. C i minus 2 will wait for C i minus 3.
So, there is a I mean, it is happening in cascade serially one after another and because of
which the delay is getting accumulated, ok.
Ci = AiBi + AiCi-1 + BiCi-1
Ci = AiBi + Ci-1(Ai + Bi)
Ci = Gi + PiCi-1
So, the method that we shall try is to make this process parallel instead of serial. Let us
see how we can do it. So, to do that, we are defining two terms. So, first of all we are
writing C i as A i B i and the C i minus 1 taking common A i plus B i and then we are
writing in it is in this way, ok. So, it is easier to for notation purposes also every time we
do not need to write two variables. So, one is G i which is A i B i another is P i which is
A i plus B i; one is obtained by AND gate after one gate, basic gate delay and this is
obtained by OR gate, 2 input OR gate after again one basic gate delay.
Gi = AiBi
Pi = Ai + Bi
Now, the first one is called generation term, and the second one is called propagation
term. What - why are they called so? Generation term if G i is 1, if G i is 1 then carry
will be generated at that stage it does not matter whether a carry was there in the
previous stage or not, if both A and B are 1, A i and B i are 1, so, C i will be 1 it does not
really matter whether previous stage is generating any carry or not. So, that why it is
called generation term.
And, what is the propagation term P i, what is its significance? If P i is 0 whether P i is 0
or not we can figure it out come this stage itself. If P i is 0 then when if the carry is there
in the previous stage it will not get propagated because C i - C i minus 1 is ANDed with
P i, ok. So, only if P i is 1 propagation term is 1 and if there is carry in the previous stage
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then that will contribute to generation of the carry in this stage. So, that is why this called
propagation term, right.
So, this is the significance of it. Now with this G i and P i - right, we try to revisit the
equation. So, C naught is G naught plus P naught C minus 1; C minus 1 is in the first
stage. So, from the previous stage if it there or if it is the very first stage it will be 0,
otherwise if it is in cascade so something will come from the previous stage, right.
C0 = G0 + P0C-1 … (1)
C1 = G1 + P1C0 … (2)
Substituting C0 from Eq.(1) in Eq.(2),
C1 = G1 + P1(G0 + P0C-1)
C1 = G1 + P1G0 + P1P0C-1 … (3)
And, C 1 is G 1 plus P 1 C naught the basic equation this equation, only this equation we
are implying. So, this C naught, we can substitute from equation 1. In equation 2, so, that
is what we are doing here. So, if you do that what will happen C 1 is G 1 plus P 1 G
naught plus P 1 P naught C minus 1, this is what we have got and by this - by this what
have be achieved in terms of delay. So, G i and P i generation 1 tau it is there. So, this is
one AND gate this is one AND gate two input and three input AND gates.
So, they are generating output in one tau and finally, this is all; that is one tau. So, 3 tau
after 3 tau we get the value of C 1. Earlier using ripple carry mode what was the time
required for C 1? It was 4 tau. So, there is some benefit. Whether this benefit is there for
larger number of bit addition - 3 bit, 4 bit let us see in the next slide.
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(Refer Slide Time: 09:43)
So, for that we investigate the basic equation of C 2; C 2 is G 2 plus P 2 C 1 that is the
basic equation the recursive equation C 1, ok. So, C 1 we substitute from the previous
equation as G 1 plus P 1 G naught plus P 1 P naught C minus 1, then we expand it, ok.
So, again what we see that each of these P i and G is are generated after 1 tau. Each of
these AND gates which is doing a parallel operation will take 1 tau, ok. So, 2 tau and
final one OR gate to combine all these product terms, right. So, another tau. So, it is
obtained after 3 tau delay. So, even for 3-bit addition, it is 3 tau, carry is generated after
3 tau.
C2 = G2 + P2C1 … (4)
Substituting C1 from Eq.(3) in Eq.(4),
C2 = G2 + P2(G1 + P1G0 + P1P0C-1 )
C2 = G2 + P2G1 + P2P1G0 + P2P1P0C-1 … (5)
And, C 3 for 4 bit operation again basic question is G 3 P 3 plus P 3 C 2; C 2 we can
substitute from equation 5 here and again will get equation similar to this. There also we
can see that G i P i terms will generate in one tau and this product terms another tau and
final one OR term - it is total 3 tau. So, irrespective of the number of bits, we can see that
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the time required to generate the carry here is 3 tau by this - bringing this kind of the
parallelism instead of the serial mode of carry generation that we have seen before.
C3 = G3 + P3C2 … (6)
From Eq.(5) and Eq.(6)
C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C-1 … (7)
Now, one need to be careful about - you know how many gate it is getting connected to
the fan-in fan-out issues. So, as long as that is not violated it is able to - you know,
provide this much of current or sink current. So, there is no issue, but that is something
by way - for which we cannot you know indefinitely extend it, we have to confine it to
certain number of bits ok.
So, now that is the way the carry is getting generated. So, carry is generated after 3 tau,
right and what about the sum bit. So, A i XOR B i that is already available through XOR
gate in 2 tau and the carry - we are waiting for the carry to come which is 3 tau for 4 bit
addition or so, I mean which is the same. So, 3 tau and 2 tau together after 5 tau we are
getting the final result maximum 5 tau. Earlier it was you have seen that it is 8 tau. So, in
this case the delay is not cumulative.
And, how we realize this circuit? Ok. So, the circuit realization is little bit more complex
than what was in case of this normal ripple carry addition. So, we are showing you now
two such bits here two such sum bits and carry bits - that is getting generated.
So, this is your A 1 B 1 and this A naught B naught and this is G 1 P 1 and G naught P
naught are getting generated by AND gate, OR gate, and AND gate, OR gate –ok. Then
C naught will require G naught plus P naught C minus 1, right. So, this is the G naught is
coming over here, this is ORing - P naught and C minus 1. So, this is another input of the
OR gate, ok. So, this is how C naught is getting generated. and, what about C 1? C 1 will
G 1 plus P 1 G naught plus P 1 P naught C minus 1. So, G 1, right and then your P 1 G
naught - this is your P 1 G naught and then P 1 P naught C minus 1 this is P 1 P naught C
minus 1. So, that is how C 1 is getting generated.
Si = Gi ⊕ Pi ⊕ Ci-1
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Now regarding the sum bits that is to be generated we can generate from XOR B also
you can calculate and you can see that G XOR P XOR C i is also giving the same output.
So, it is preferred that we generate it from G XOR P i instead of A XOR P i because it is
connected to the external world. So, how the it will load and other things that is not much
known to us how it is getting driven in the external circuitry. So, here we know how
much current it can handle and other things.
So, we when we generate the final sum bit we take the XORing from Gis and Pis instead
of Ais and Bis, A i and B i.
(Refer Slide Time: 14:34)
So, this is a commercial IC; IC 7483 A you can search and you can see there are other
ICs is also 7483 and which thus 4-bit fast addition and here this is you know, different
manufactures has got different way of representing the number. So, the here these A
naught, A 1, A 2, A 3 that is mentioned, B naught, B 1, B 2, B 3 is mentioned, output is
S naught to S 3, this is the manufacturer follows. But, input we have used C minus 1; and
C 3 the final output - carry output. They are using C naught and C 4, ok; so, one value
more.
So, in some other manufacture you will see, in place of sum bit they are using the sigma
sign - summation sign 1 summation 2 and so on and so forth. So, these are certain small,
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small differences that you have to take note of when you are using it practically in lab or
in your personal hobby project or mini project - digital electronics project.
The other thing that you take note of is the use of you know NOR gate, NAND gate and
here it here again NOR gate, instead of the kind of thing AND and OR that we have used
ok, for which again if you work it out then will see the same logic we shall see one
example at the end for a carry look ahead adder circuit ok, group carry generation in
relation to that particular discussion. So, this is something we take note of when we use
this kind of IC.
(Refer Slide Time: 16:25)
Now, these are in a 4-bit fast adder, and we need 8-bit addition, so, how we go about it?
Now, here again we shall be using cascading - right. So, this cascading – for cascading,
we shall be using one adder and this is another adder. Now, in between how we are
connecting? The output carry that is generated here is going as input carry. So, this is
nothing, but the mode which is similar to ripple carry addition. Is it not? So, this carry
input 13 here carry input of the more significant bits will be waiting for this C 3 to get
generated from the previous stage, which will required 3 tau.
So, if you got another such stage here after this. So, this is 4-bit, this is 4-bit, so, this is
another say 4-bit over here. So, it will wait for 6 tau to generate this particular carry
right. So, that way this becomes within the you know, across stages across these 4-bit
blocks, the carry ripples from one IC to another. So, that becomes cumulative within this
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block it is not when we are looking for this kind of arrangement. Is it ok? Is it
understood? ok, but each of this block is a fast adder you know the kind of addition that
we have seen before which is called carry look at adder. And, here again we are showing
the arrangement of getting both addition and subtraction using fast adder and for that you
are using the similar approach that we have done before.
So, we are having a bank of XOR gate here and bank of XOR gate here and this sum
input is 1 when we are doing subtraction and which adds to the carry initial carry in the
2’s complement of this B 7 to B naught number. So, this is 1’s complement at the XOR
gate output and 1 that is getting as input carry over here, ok, right. And when it is
addition this sum will be 0. So, basically only B naught to B 7 will come over here; no
inversion will be done and this is 0. So, this is normal addition that will take place.
So, we take note that within the, you know across this blocks it is carry is rippling.
(Refer Slide Time: 19:05)
Now, we look at a mechanism, a method by which that particular aspect can be
addressed, ok. If we have got fast addition in our mind right and we are having a
situation where more than 4-bit addition is required say maybe 12 bit, 32 bit, 16-bit or so.
So, how we can what can do to speed it up. So, to do that let us again look at the basic
equation of the carry generation.
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So, the carry that is C 3 is going as input to the next block that we had seen. So, you are
looking at this C 3. So, how C 3 is getting generated? So, this is why C 3 is getting
generated in the first carry - fast adder, ok. So, this term - this term ok, we - if when it is
1 this C 3 is getting generated, irrespective of there was a carry to the input to this block
or not, ok. So, this we define as group carry generation term group carry, generation term
G 3 to 0, ok, is it clear? And, this particular term in different color, when this is 0, then
even if there is a carry present at the input of this block this is not get propagated. This is
similar - exactly similar, you will see the equation and other things that we’ll get is
exactly identical to the ones that we have seen in the case of fast adder development - is
it not?
C3 = G3 + P2G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C-1
G3-0 = G3 + P2G2 + P3P2G1 + P3P2P1G0
P3-0 = P3P2P1P0
C3 = G3-0 + P3-0C-1
So, this we say - this we say group carry because it is generated from individual A i's and
B i's the propagation term the ORing of A i's and B i's individual bitwise ORing. So, this
is the group carry propagation term right. So, now, we are looking at this as a group. So,
this is 4-bit adder, fast adder. So, this is your C 3 and this is C minus 1 and this is C 3
and this is where your A 3 to 0 and this is your B 3 to 0 ok.
So, how what you can write now? Now, that you have defined them, so, C 3 is equal to G
3 to 0 P 3 to 0 C minus 1, it is similar to the equation that we had seen before if you
remember, ok. So, this is the kind of equation that we had seen before. So, earlier we
were doing bitwise carry generation; now it is block wise carry generation, right.
So, this is what we are doing it and this is group carry generation term and group carry
propagation carry term. Earlier it is only G - generation term and propagation term here
group generation term and group carry propagation term, that was bit was this is block
wise, ok. This is the difference. Clear? Now, if there is another block of after this which
takes C 3 input and generates C 7 ok.
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So, this is C 7 can be written from the generation terms and propagation term that is
generated at that particular block G 7 to 4 and P 7 to 4 and with input as C 3 this just
similar thing, right for the next particular block we can write it in this manner. Now, this
C 3 we can substitute from the previous equation over here and then expand it, that is
what you will get, the, similar again, identical to the treatment that we have done when
we developed fast adder.
So, that way we can go on doing it for the next stage and next stage and all. So, for you
know 16-bit addition, so, C 15 is getting generated in this manner, right. Now, each of
these terms if you look at them. So, that if you are generating them at which of these
output if you are additional you are generating this group carry generation term G 3 to 0
and P 3 to 0 each one of them if you are generating and if you are making use of them to
generate the C 15, then how much time is required? So, this G 3 to 0, this will require 3
tau. Why? Each of these Gis and Pis requiring 1 tau, this product term is another tau and
the final ORing is another tau.
C11 = G11-8 + P11-8G7-4 + P11-8P7-4G3-0 + P11-8P7-4 P3-0C-1
C15 = G15-12 + P15-12G11-8 + P15-12P11-8G7-4 + P15-12P11-8P7-4G3-0
+ P15-12P11-8P7-4P3-0C-1
So, G i - each of these group carry generation term will required 3 tau and group carry
propagation term will require 2 tau. So, the term here these are 2 tau 3 tau, these are 2
tau, this is 3 tau for their generation. So, the higher of two is 3 tau, and this 3 tau and
then there is product 1 tau then finally, is an another ORing. So, this is after 5 tau getting
this particular carry here - this particular carry here.
So, you need to have an aggregator to add each of these terms - need to generate this
group carry generation group carry propagation term. And, and we see that the equation
is similar these aggregator can also take individual bits also to generate the
corresponding carry at individual level the carry - ok. This is what we can understand by
comparing the equations.
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(Refer Slide Time: 25:40)
So, this is one circuit for look ahead carry generator IC 74182, and this particular one
takes four such terms, four generation terms and four propagation terms, ok, four
generation term and four propagation terms. So, this could be group carry group carry
generation term and group carry propagation term as well or normal basic numbers, ok.
Then, the corresponding you know, because the basic equations remain the same, they
way we have seen it before.
And, this is the input carry and theses are the output carry for individual stages,
individual stages and this is the final again group generation term and propagation term
for multilevel use, next level use. And, this is the corresponding circuit and we told that
again we are having you know inverter, then NOR gates and other things which make us
think like the example that I had given before. So, for example; this circuit. So, let us
investigate one such particular block and see whether it matches with the equation or not,
ok.
So, this is the block that we you know, look at. So, this output over here is the input here
is G naught bar and P naught bar that is getting ANDed, right and this input is G naught
bar - G naught is coming from here and Cn - and Cn here is active high, but then there is
inverter. So, this is Cn bar. So, input to this this NOR gate is G naught bar P naught bar
and G naught bar Cn bar.
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So, input to the NOR gate which is generating Cn plus x, the first level a carry - first is
the this one, ok. Then you apply this DeMorgan theorem, right. So, this G naught bar P
naught bar the whole bar ANDed with - because this is OR sign is becoming AND term
and each one of this terms is inverted - complemented. So, G naught prime C naught
prime ANDed this way. Then you again perform DeMorgan’s theorem, ok.
So, this becomes G naught complement of complement that is G naught and P naught
complement of complement that is P naught. Similarly, this is G naught and this is Cn
ok, right, you can follow it? Then when you perform the product to get each of the
finally you know, sum of product form. So, G naught G naught this gives you G naught.
So, G naught Cn, G naught P naught and P naught Cn. And if you take common G
naught, then 1 plus Cn or P naught which is nothing but, G naught and P naught Cn. So,
we get back the basic equation G naught plus P naught Cn here is C minus 1 the one that
we have used - that concept. So, this becomes your you know, C 1.
Cn+x = (G0’.P0’ + G0’.Cn’)’
= (G0’.P0’)’.(G0’.Cn’)’
= (G0+P0).(G0+Cn)
= G0+G0Cn+G0P0+P0Cn
= G0(1+Cn+P0)+P0Cn
= G0+P0Cn
And, if it is group carry - these are the group carry terms; this is G 3 to 0 plus P 3 to 0
and this C minus 1 and this is your C 3, ok, have you understood it? And, similarly for
other terms depending on whether it is group carry or normal generation propagation
term, it will generate for that particular bit or for that particular block.
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(Refer Slide Time: 29:29)
(Refer Slide Time: 29:30)
So, with this we conclude today’s class propagation delay is cumulative in ripple carry
adder. If basic gate delay is tau, if we consider that as tau then n-bit addition is done in
2n tau time since the placement of valid data. Carry look ahead adder does serial to
parallel conversion - internal process for ripple carry by which the addition is completed
in 5 tau time. Please remember, this is 5 tau time within the block.
Cascading parallel adders where carry output of one block is fed as carry input of the
next block makes the carry ripple between blocks with cumulative delay, ok. And, to
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avoid that, we can have additional group carry generation and propagation terms and by
which we can get carry look ahead by a aggregator and that reduces the time for
generation of the carry, ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture – 25
Overflow Detection and BCD Arithmetic
Hello everybody, we are discussing arithmetic building blocks. And in today’s class we
shall discuss Overflow Detection in adder and also, how to perform BCD Arithmetic.
(Refer Slide Time: 00:27)
So, we shall see BCD adder and subtractor circuit and also here will have some idea
about the underlying concept - theoretical concept, that is 10’s compliment. And, we
shall also look at have a look at what would have been the case, if we had employed 9’s
complement for BCD subtraction. And, during that course we shall also look at the
equivalent - similar relationship for binary subtraction that can employ 1’s complement.
We have to use 2’s complement subtraction; so, what could have been the case we had
used 1’s complement subtraction.
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(Refer Slide Time: 01:07)
So, first we discuss the overflow detection. So, for that we again revisit the number
representation; so, in this particular case we are looking at 4 bit number representation.
So, that 4 bit considers also the sign bit ok. So, when we consider sign bit with 4 bit we
remember that in 2’s complement format we could represent a number from minus 8 to
plus 7 ok. We remember that and how the numbers were there. So, these are the numbers
so, 0 0 0 0 was 0; 0 0 0 1 was 1; 0 0 1 0 was 2 so, up to 0 1 1 1.
So, these basically behaves like a sign bit that was 7 and 1 triple 0 was minus 8, 1 0 0 1
was minus 7, 1 0 1 0 was minus 6, that way 1 1 1 1 was minus 1 we remember that, isn’t
it? So, if we are now looking at the possibility of the overflow; so, that occurs when a
positive number is added with a positive number and the value of that is more than 7 ok.
So, it goes out of the range and a negative number is added with a negative number. So,
the output becomes more than minus 8 I mean, less than minus 8 from the negative
number representation concept.
The magnitude is more than 8 so number is more than minus 8 ok. But, when you are
adding a positive number with negative number the result I mean, if the positive number
and negative number to begin with are within range. So of course, the result will be
within the range because one is getting subtracted. So, magnitude will be within the
range ok. So, we do not have a case of overflow when we are having a positive number
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added with a negative number. So, positive number added with positive and negative
number added with negative, there could be possible cases of overflow..
If we look at examples: so, 0 0 1 0 and 0 0 1 1 if we add them up simple binary addition.
So, 0 1 0 1 - sign bit is positive absolutely no issue 5 is within the range so, there is no
overflow. So, whereas, when you are adding 2 with 7 ok; so, 0 0 1 0, 0 triple 1. So, if you
add them up you see 1 0 this is 1; 1 1 0 here - there is a 0, then there is a carry, then this
1 and 1 - 0, there is a carry ok. And finally, this is 1 and there is no carry, of course there
is no carry here is it clear right; this C 3. So, there is no carry, that is what we see 1 0 0 1.
Now, this is if you look at actually the meaning is 9 of plus 9 we know addition of 2 and
7, if you had been in you know binary coded - this was not a sign bit right.
But, it would have been represented at 1 0 0 1, but we know that this is a number
representation where, the maximum positive number is plus 7 and 1 0 0 1 is over here it
is minus 7. So, it is out of range so, there is overflow. Now, we look at the example of
negative number with negative number. So, minus 2 and minus 3 say let us look at that.
So, minus 2 is 1 1 1 0 from here you can see this is minus 2 and minus 3 is 1 1 0 1 you
add them up. So, this is 1 this 1, 1 1 - 0 right there is a carry over here ok. And, then 1 1
1 there is a 1 and there is a carry over here right and that carry comes here and we ignore
that carry and this is 1 0 1 1. We see the result is 1 0 1 1 is minus 5 which is correct
which is a valid number - valid number and the result is also correct, it is within the
range and if you have minus 2 minus 7.
So, what we see minus 2 is 1 1 1 0 and minus is 7 is 1 0 0 1 we have already seen that
right. So, if you add them up 1 right this is 1 this is also 1, 1 1. So, there is no carry here
1; so, that is basically no carry you can see no carry. Why I am writing this that would be
cleared later and this is 1 1 - 0 and there is a carry. So, this is a carry over here, I can the
ignore the carry 0 1 1 1. So, what is it? It is a it is plus 7 which is of course, not the right
thing ok. So, this is the case of having a overflow. The answer would have been minus 9,
but it is minus 9 is out of range minus 8 is the maximum that you can have ok. And,
these are examples of positive with negative we can see that there will never be a
overflow because, the magnitude is always within the range - right.
Now, how with then can we can detect if we have you know a adder you know fed with
these numbers, then how we can detect with just can develop a simple logic circuit which
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will take input from this adder, the sum and carry bit that is getting generated right. If it
is a 4 bit additions S naught to S 3 that will get generated and carry will also be
generated right. And, intermediate carry if it is available C 2 C 1 C naught will also get
generated. So, what we can see the overflow occurs when these are the two cases when
the sign bit here, if this is 0, sign bit here is 0 and sign bit here which is S 3 is 1. So, this
is a case A 3 prime B 3 prime and S 3.
So, this is the case when it occurs, you see in the other cases it will not occur right. When
if S 3 is 0 you will see that this will not generate this output to be 1 and the other case
when it, occurs the sign bit here is 1 1 and this sin bit that is getting generated S 3 is
opposite right. So, these are the cases when A 3 B 3, these two are 1 and S 3 is 0. So, we
are taking S 3 prime. So, we add them up then we can get it right. And, if we have access
to intermediate carry C 2; C 3 is the final carry that is getting generated right. Then we
can see that whenever there is overflow; wherever there is overflow, the C 3 is the final
carry and C 2; the carry just before that C 3 and C 2. Just before that they are I mean, if
one is 0 another is 1.
So, if you take XOR of that you can get the overflow detected right. For other cases you
can see this is 1 1 and similarly this is 0 0 you will see that there is no, such case that is
generating the carry for C 2 and C 3. So, this is another way just having a XOR gate. So,
if you have got access to C 3 as well as C 2 otherwise A 3 B 3, those are the input data
and S 3 is getting generated you can put them together with a logic relation like this.
And, you can get overflow detected. Is it clear? Right. And if there is a overflow we have
to take remedial action.
O = A3’B3’S3 + A3B3S3’
= C3 ⊕ C2
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(Refer Slide Time: 09:15)
Now, we will look into BCD addition and subtraction. So, before that again we look at
how BCD numbers are represented. So, BCD numbers are binary coded decimal, we
have seen you know, BCD decoding and other things before. So, we are already familiar
that BCD numbers are from 0 to 9. So, this is the decimal number, decimal
representation you have got digits from 0 to 9 right and corresponding binary codes are 0
0 0 0 to 1 0 0 1.
So, in BCD coding the number more than that is not valid and if that is called 1 digit. If
you have got a 2 digit decimal number say 53, how do you represent it in BCD. So, 5 we
represent as 0 1 0 1 fine and 3 is represented as 0 0 1 1. So, BCD coded 2 digit decimal
number 53 - 53 will look like two 4 digit binary number 0 1 0 1 0 0 1 1; 0 1 0 1 0 0 1 1.
If it is a binary coded decimal the corresponding decimal is 5 and 3. So, group of 4 you
have take. So, if you we look at some example so, 10 so, 1 and 4 0’s right; 99 - 1 0 0 1 1
0 0 1; 100 - 0 0 0 1, 0 is 0 0 0 0 and 0 is 0 0 00.
So, this is your 12 digits will be required to represent 100. Similarly, if you are looking
for you know 6902 a 4 digit decimal number getting the presented. So, 6 will get
converted to 0 1 1 0, 9 is 1 0 0 1, 0 is 4 0’s and 2 is 0 0 1 0. So, this is the way you
represent binary coded decimal and you are talking about addition and subtraction of this
kind of numbers, these kind of number representation. So, how do you do that?
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(Refer Slide Time: 11:25)
So, first let us look at some of the theory that goes into the you know, development of
the circuit for BCD addition. First of all we see that the result of BCD addition is valid
when the sum is less than or equal to 9 because, up to 9 you have got valid BCD
representation. So, if you are adding 5 sorry, if you are adding 5 decimal which is
represented in BCD as 0 1 0 1 with 2 which is represented as 0 0 1 0 then we will get 0 1
1 1. So, that is 7 which is absolutely no issue right. Similarly, 3 with 6 you get 9
absolutely no issue.
But, problem occurs when the number - sum of this number is more than 9 ok. For
example, over here so, 0 1 0 0 that is your 4 and this is your 7 ok. When you add it up 1 0
1 1 which is you know as a binary you know number 1 0 1 1 you know if you look at the
weights. So, this is your 8 2 1 - 11 that is fine, but 11 is not a valid BCD, I mean. decimal
representation. There is no symbol for that and we are looking at symbol which is 0 to 9.
So, up to 1 0 0 1 you can have a number presented here a group of you know 4 digit. So,
this is not a valid BCD ok. You look at another example say, this is your 9 right and this
is your 8, if you add them up you get 1 0 0 0 1 and there is a carry ok. So, this is again
something which goes - going out of the range the when get added up it is 17, 17 is not
what we’ll get I mean within a decimal representation as a symbol ok. So, these are the
cases when we are having issues, when the number is going more than I mean results
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becoming more than 9. And, we can see a solution can be obtained by a simple addition
of 6 in each cases ok, let us see how it happens. So, this was 1 0 1 1.
So, this result when it is more than 9 you have to develop a logic circuit that will add 0 1
1 0. So, if we add it up what will happen? So, this is 1 this is 1 1 0 and that is a carry
which is added with 1 is 0 there is a carry with 1 0 and this is 1 ok. So, this is now a
proper BCD coded representation of the result. And, if there is one 1 so, you put leading
0s which does not alter the value. So, this is 0 0 0 1 - 1 BCD number right. So,
corresponding decimal is 1; 0 0 0 1 is 1 and this is another number; so, 0 0 0 1 - 1 1.
So, if you take it to a display device through this 4 digit which converts to a 7 segment
display driver and all. So, the display device will show 1 and 1 which is 11 and which is
the correct result. Is it clear? Right. So, similarly in this case this was 17, I mean, if you
look at its corresponding binary weighted value - right and if add it with 6 right. So, this
is 0 1 1 1 that is 7 and this is 1. So, we can check for every such cases it will happen in
that manner - right. Whenever the number increase is more than 9 you add 6 you will get
the corresponding - a correct representation of, in the BCD format ok.
So, this is so, we will keep in our mind and try to develop the appropriate logic function
for this.
(Refer Slide Time: 15:45)
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So, what is that logic because it will be part of the circuit right, you have to develop the
corresponding adder - BCD adder. So, we see that for decimal result I mean, when we
are doing the representation, when it is remaining between 0 to 9 ok. So, the addition
whether it is required or not addition of 6 is required or not if we take this as output Y
ok; so, Y will be 0 that time the 0 means no addition is required; no addition of 6 is
required ok. Now, instead - of result being you know 0 to 9, if it is 10 11 12 and up to 18,
it is possible two numbers getting added is 9 and 9 that is the maximum.
So, in each of these cases, this output is 1 because, addition of 6 is required and what are
the corresponding representation for - at that time. These 10 11 12, if you have the adder
for sum bits are S naught to S 3 and the carry bit is C 3. These are the corresponding
representation 0 1 0 1 0 that is your 10 and 1 0 0 1 0 that is your 18 ok. So, there can be
you know with 5 such bits 5 such bits you can have 32 different possibilities. So,
possibilities more than 18 - 19, 20 etcetera that will never occur if the input digits are
you know, BCD ok, because maximum 9 and 9 can be given as input. So, we do not care.
So, those values are don’t care, I mean you do not really bother about what will happen if
in the case of 19 is presented, is it fine - right.
So, this truth table we need to convert to an equation and we can see that this truth table,
if you can just simplify using standard process algebraic or Karnaugh map or QM
algorithm with them you can see that a relationship something like this emerges. So, if
you just quickly have a look at so, C 3 means right. So, whenever C 3 is there right you
need to have the Y flag the addition of 6 you know high, isn’t it. Because, that is C 3
means the number is 16 or more S 3 S 2. So, this is your S 3 and S 2. So, S 3 and S 2
mean, if both of them are there; so, this is the case - these are the cases.
Y = C3 + S3S2 + S3S1
So, S 3 stands for 8 and S 2 stands for 4 so, 8 plus 4 12. So, 12 and more – right. These
are the cases of course, at that time you are having a value which is high and S 3 S 1. So,
S 3 occurs; that means, it is 8 and 1 S 1 is also there; that means, 2 right. So, you can see
all those cases S naught is there or not there, the number is more or 10. So, these are the
cases you can see which perfectly fit this equation and otherwise as I said you can do the
minimization by standard process taking the minterms and then minimising by Boolean
algebra or through K Map - Karnaugh map or QM algorithm and this is what you get.
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So, basically we have to it realize this combinatorial logic in hardware and then the job is
done ok. But, the how the overall circuit will look like let us see.
(Refer Slide Time: 19:33)
So, this is how the overall circuit will look like for the adder - BCD adder. So, here what
you have got, you have the first adder, 7483 the 4 bit adder generating is not is S naught
S naught to S 3 that what you see. And, this is your C 3 right and if these BCD adder
takes you know carry from previous stage you will take it will take. So, that carry will be
used here and this is the logic circuit to generate your whether the 6 will be added or not.
So, this is taking C 3 this is your C 3 getting connected here, this is your C 3 right, then S
3 AND S 2 - so S 3 AND S 2 and S 3 AND S 1 ok.
So, this AND gate S 3 S 1, this is S 3 S 2 and finally, it is ORed. So, if it is 1 means 6
need to be added and if it is 0; that means, no addition is required; I mean no addition
required means here in this particular case since, we have to put an adder; so, basically 0
is getting added ok. So, this number, the number that was added before, it is now brought
forward to the next adder right next 4 bit adder and here right the number is when this is
Y is high. So, 0 1 1 0; A 3 is 0 A 2 is 1 A 1 is 1 and A 0 is 0 right. So, what does it mean
at that time, then 0 1 1 0 that is 6 is getting added. And if this is 0 so, this will be 0 0 0
and 0 right. So, no addition I mean, no number is actually getting added.
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So, the final thing will be the BCD digit and if there is a carry right. So, that carry will be
displayed (Correction: Cout from OR gate output) with leading 0s we had shown
otherwise, if there is another BCD number getting added like 53 example; I had given
before then this carry will be taken their to bring next BCD adder we make. So, there it
will be given as input is it clear. So, this is how a 1 unit of BCD adder will act.
And, we look at one example here. So, 49 is getting added with 58. So, 0 1 0 0 1 0 0 1
and 0 1 0 1 1 0 0 0 so these are the corresponding you know this is represented in BCD 4
and 9, 5 and 8 and when we add it up ok.
So, there is a carry here what is generated. So, the number is more than 9. So, 6 is getting
added. So, this is the corresponding number that is 7 will be there and this carry is now
getting added with the next numbers 4 and 5 ok; so, 4 and 5. So, though it is
corresponding number and 1 is getting added 1 0 1 0 we get direct that again is not a
direct BCD ok. So, we add 6 here. So, you get 0 and a carry is generated as and then you
put the letting 0’s. So, the result is 1 0 7 ok. So, if you look at in decimal it is also in 1 0
7 you can add it up then see.
(Refer Slide Time: 22:57)
Now, BCD subtraction; so, to do BCD subtraction we shall look at what is known as
subtraction by 10’s compliment. So, we have done subtraction by 2’s complement in
binary it is somewhat similar. So, what is done here? So, we’ll consider you know, here
subtracting a smaller number from a larger number - so two possibilities: smaller from
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larger, larger from smaller ok. So, say the example is of the 7 minus 4. So, what we do
first the subtrahend the way we have done 2’s complement, here we shall do 10’s
complement ok.
So, 10’s complement is 10 minus the number is we will give you the 10’s complement of
that and that is the negative number of you know in that sense. So, this will give you 6
right then you add it up 7 plus 6 - it is 13 right. And, if carry is present the result will be
positive you can see the similarity between 2’s complement addition of a negative
number ok. So, you ignore the carry and difference is without the carry you remove the
carry sorry 13.
So, remove the carry so 3 so, the answer is 4 positive. So, 7 minus 4 is positive 3 ok.
And, had it been 4 minus 7 how would - how would have been the case.
(Refer Slide Time: 24:25)
So, we’ll take 10’s complement of 7 which is 10 minus 7 is equal to 3; 4 plus 3 is 7 and
when you see there is no carry. So, basically 7 is 0 7 right. So, carry is absent means
result is negative, again you can see the similarity with 2’s complement you know,
subtraction. So, now the difference - the result already in that case was in 2’s
complement from if it is negative. So, we have to do another 2’s complement to get the
original I am, the magnitude of the result in proper binary coded representation ok.
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So, in this case you will be doing - in this case when it is negative you if you want to
know the magnitude so 10 minus 7 - 10’s complement of 7. So, 10 minus 7 is 3 right. So,
the answer is negative and the value of it magnitude of it this 3; so, minus 3 ok. So, this
is how you can perform 10’s complement subtraction for decimal numbers and now we
come to the representation of the decimal number in BCD and how the circuit will look
like. So, to do that we see that we would require one 10’s complement generator here.
(Refer Slide Time: 25:43)
And, if the result is negative another 10’s complement generator here ok, if the result is
positive, it is not required ok. But, when you are looking at hardware it will be in place
so, whether you use it or not that that is a separate thing. So, first we look at how to
generate 10’s complement ok. So, the circuit over here you can see can generate 10’s
complement, how does it do. So, it is doing it by in this case this is your 1 0 1 0 when
you are looking for 10’s complement ok. So, this will be 1 so, this is 1 0 1 0.
So, 10 and the number for which you are looking for 10’s complement that will be that
you want to subtract ok. So, subtraction we know already how to do it using a 4 bit
adder. So, this is a bank of XOR gate. So, if it is 1 the inversion thing will be coming
here - inverted thing right. So, that is 1’s compliment will come and then this 1 means
this is the carry will be getting added. So, that is giving it the 2’s complement and
together when you do it then you get 1 0 1 0 - this is value will get the corresponding
binary coded decimal part of it in the corresponding negative number of or the 10’s
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complement of the original decimal number ok. And, if there is a carry you have to
ignore it right, is it clear.
And, if X is equal to 0 what will happen the same number will get passed the same
circuit can, in that case you can do the addition also it is for subtraction it will be
recurring to have this particular value to be 1 ok. So, this is the 10’s complement
generator. Now, during subtraction how does it work it out ok? So, the subtrahend is put
here right and minuend the number from which it is getting generated; so, that will be put
here. So, we are doing BCD addition BCD addition you have already seen before right.
And, if BCD addition generates carry then there is a result is positive and we do not need
to do anything, I mean you have to just take the result as it is right. So, if it generates
carry so, then this output will be 0. So, these output 0 means here this is 0 right. So,
basically you are not do anything you are that number is getting passed here. And, and
here the sign you can see that to be positive is it fine, and what happens when the number
is - when this number is this carry out is 0 that means the number is negative right.
(Refer Slide Time: 28:53)
So, at that time this will be 1 and we need to take 10’s complement of this. So, this is
what we when you do then you get the 10’s complement of it, is it clear? So, this is one
BCD subtractor unit.
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(Refer Slide Time: 29:19)
And, to end we shall have a quick you know, understanding of what is 9’s complement
and 1’s complement, I mean in decimal system and binary system and how it is useful in
subtraction. So, in a 9’s complement what we do actually we subtract the number from 9,
not from 10 ok. So, for the same example of 7 minus 4; 9’s complement of 4 is 5. 9
minus 4 - 5; so, 7 plus 5 is 12. So, if carry is present the result is positive and at that time
we have to do, what we have to do this carry - it is also often called, sometimes called
end around carry.
So, this carry would need to be added to get the result, if carry is present, carry need to
be added to get the result. So, 2 plus 1 - 3 that is positive and because of the presence of
the carry it is positive and the value is 2 plus the carry that is 3 ok. And, the other case
when 4 is subtracted - 7 is subtracted from 4. So, 9’s compliment of 7 is 9 minus 7 it is 2
ok.
So, 4 plus 2 is 6 and carry is absent means result is negative understood. So, here the
carry was present here this 6 there is no carry it is 0 I mean; that means, it is 0. Then the
result is in 9’s complement you have perform another 9’s complement to get the
magnitude of the negative number that is giving the final result. So, 9’s complement of
this 6 is 3; so, the answer is minus 3. So now, if you look at 1’s complement subtraction
for binary numbers so, this is your 7 and this is your 4. So, 1’s complement we have seen
it before basically it is just inversion of it ok.
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So, 1’s complement of this 0 1 0 0 is 1 0 1 1 you add them up 1 0 0 1 0 carry is present
so, result is positive. And, what you have to do in 2’s complement it was result was just
like that in this case this carry needs to get added, the way we have done here for 9’s
complement – in 1’s complement the carry needs to get added. So, 0 0 1 0 added with 1.
So, this is 3 and the result is positive. And larger from smaller -so, this is 4 minus 7 case.
So, 0 1 1 1, 0 triple 1 - 1’s complement is 1 triple 0; so if you add it up 0 1 0 0 with 1
triple 0 you get 1 1 0 0. So, the carry is absent. So, result is negative and to get the actual
difference, you have to take 1’s complement of that. So, you have invert these 1 1 0 0 all
the bits so, 0 0 1 1 so, that is 3. So, that is minus 3 that is your answer.
(Refer Slide Time: 32:35)
So, with this, we just look at the summarizing points of this particular class. Overflow in
an adder occurs when the result goes out of range for 4 bit cases it is minus 8 to 7. For
you know, 8 bit cases and other cases you have to have corresponding understanding of
the overflow and the logic relation that we will get - will be accordingly take input from
the bits which is closer to the - which is designated as sign bit or carry of the previous
one and the current one - I mean which is there in the closer to the sign bit ok.
And, in BCD addition if the result is more than 1 0 0 1, then further addition of 6 that is 0
1 1 0 is required and BCD adder will require to 4 bit binary adder and logic circuit to
decide when this 6 is getting added. And, BCD subtraction will require 10’s complement
generator circuit and normal BCD adder.
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So, together two 10’s complement generator circuit and 1 BCD adder you can do BCD
subtraction ok. And, 9’s complement subtraction will and 1’s complement subtraction in
decimal and binary respectively they have got similarity. And, we have seen examples
how to do that and you can convert that to circuit with you had known for 2’s
complement and 10’s complement.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture – 26
Magnitude Comparator
Hello, everybody. We are in week 6 of this particular course. In today’s class, we shall
look at Magnitude Comparator.
(Refer Slide Time: 00:24)
And, before that we shall have a quick review of what we discussed in week 5.
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(Refer Slide Time: 00:27)
If you remember, we discussed number system and the representation of numbers in
binary and the code that we arrived at were weighted codes in the sense that every place
has got certain weight associated with it. When it is binary, before the binary point we
had weights like 1, 2, 4, 8, 16 so on and so forth and after the binary point it was half, 1
upon 4, 1 upon 8, 1 upon 16, so on and so forth, ok.
And, to convert decimal to binary the integer part was successively divided by 2 and
remainders were accumulated and for the fractional part; part coming after the binary
decimal point - it was successfully multiplied by 2 and the carry was accumulated. And,
we had seen that fixed point arithmetic has fixed precisions and it follows integer
arithmetic, and for negative number representation sign magnitude was discussed and
also 2’s complement, 1’s complement all those things were there and then we discussed
2’s compliment arithmetic.
And, then to design circuit, for addition and subtraction we saw ripple carry addition and
how we can convert a ripple carry adder to a subtractor, ok. And, then we discussed carry
look ahead adder for fast addition where the carry generation process was converted to
parallel from serial by unlooping the iterative equation. And, then we discussed overflow
detection, how to detect overflow if the number goes out of the range and then we also
discussed BCD addition and the logic behind it and how to arrive at those logics.
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(Refer Slide Time: 02:27)
As I said in today’s class we shall discuss magnitude comparison. So, magnitude to be
compared is between two numbers and the numbers I mean, whenever we talk about
comparison the first thing that occurs to our mind why not subtract one number from the
other. Say, one number is X another number is Y. So, if X minus Y is 0, then it is equal the numbers are equal; and if X minus Y is positive the number is X is greater than Y; if
X minus Y is negative then the number is - X is less than Y, ok.
This is the thing that will occur to us and of course, we can get a magnetic comparison
done by subtraction process, ok. So, that we can do and for that we can have a subtractor
circuit developed from 2’s complement by using 2’s complement arithmetic and full
adder circuit. So, in that the way we have seen it before how the subtraction works using
2’s complement arithmetic. So, when X is equal to Y and X greater than Y, we see that
carry-out generated is 1, ok.
So, we have to refer back to 2’s complement arithmetic by which the subtraction is done,
those examples we studied, that we had done in the previous class. From there we take
the important point that if X is equal to Y and X greater than Y then carry-out that is
generated is equal to 1 and if carry-out generated is 0, then the number is negative that is
X less than Y, I mean, the result is negative. So, X is less than Y, ok. So, remember that,
ok.
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Then, from that we can get the logic for X less than Y very easily, that if the carryout is 0
no carry is generated then the result is X less than Y. So, in that case we can the
corresponding outputs X less than Y we can directly you know get from Cout prime,
complement of carry-out, ok. And, when carry is generated then there are two
possibilities one is X is equal to Y, another is X greater than Y, right. So, X is equal to Y
will occur when all these sum bits are 0, right.
So, at that time we can follow this particular logic, that all the each of the sum bits are 0,
no digit is 1. So, that means, that the numbers are equal result is 0 and carry-out
generated is 1 that is following 2’s complement subtraction. And, if any of the sum bit is
1, any of the sum bit is 1, so, that is - that follow OR logic by which we can AND it with
Cout, the carry is all already generated. So, that gives you X greater than Y logic, ok.
(X < Y) = Cout’
(X = Y) = Cout.S3’.S2’.S1’.S0’
(X > Y) = Cout.(S3+S2+S1+S0)
So, this is the basic idea and of course, when you are generating multiple output
functions you can see that whether output of one can be used I mean, some intermediate
output can be used in two places two different places. So, accordingly certain
minimization you can think of otherwise the basic logic in which - this is what we are
arrived at.
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(Refer Slide Time: 06:17)
So, but when we look at magnitude comparison and our objective is to generate only X
greater than Y, X is equal to Y and X less than Y, we do not actually need the subtraction
result that is s 3, s 2, s 1, s naught, ok. So, we are doing more than what is expected from
us in terms of magnitude comparison of two numbers, isn’t it? So, can we have you
know can we use less hardware, you know another kind of circuit by which we generate
only the result that compares two numbers, ok.
So, we’ll go 4-bit number comparison the way we had seen before or larger number of
bits. So, we begin with 1-bit magnitude comparison. So, two numbers are of 1-bit, ok.
So, if X and Y are of 1-bit. So, the number possible you know the possible combinations
the way we can compare them when X is equal to 0, Y is equal to 0; X is equal to 1, X is
equal to 0; Y is equal to 1, X is equal to 1; Y is equal to 0 and X is equal to 1 and Y is
equal to 1. So, these are the four possibilities by which you can do the comparison.
And, in this case you can see that 0 0, X and Y both are 0; that means, X is equal to Y.
So, this will be 1, neither X is greater than Y nor X less than Y. So, they are 0 and 0
clear. So, X is equal to 0 and Y is equal to 1. Of course, Y is more and X is less. So, X is
less than Y that is equal to 1 and rest two are 0. X is equal to 1 and Y is equal to 0, so, X
greater than Y is 1 and when both of them are 1 that is they are equal, so other two are 0;
is it fine?
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So, by this we can figure out that X greater than Y is occurring for this combination. So,
we can get it by XY prime. So, G we are giving G for greater than X greater than Y.
And, then X less than Y, right that is occurring for this particular case sorry, this
particular case. So, that is X prime Y, X is equal to 0 and Y is equal to 1, clear and
finally, X is equal to Y is occurring for these two cases, the other two cases left is this
one and this one. So, this is X and Y both 0. So, that is X prime Y prime and X and Y
both 1, so, XY so, you add them up sum them up to get the final expression. So, these are
the you know, the basic logic by which you can get 1-bit comparison done. So, we do not
need to do other things, ok.
(X > Y): G = X.Y’
(X = Y): E = X’.Y’ + X.Y
(X < Y): L = X’.Y
Now, since we are generating XY prime and X prime Y, right do we need to additionally
generate X prime Y prime XY, so; that means, two other AND gates and then OR it up,
or we can make use of this and see whether you know another you know gate not more
than one gate is required to get the final X is equal to Y output generated, ok so, that we
can investigate.
So, for that we can see that X prime Y prime ORed with XY, we can write these as X
prime OR Y ANDed with X OR Y prime. You can see that X prime AND X - it will
become 0. So, X prime Y prime will come from this particular term first this thing and
YX will be there from these two and YY prime will be 0, ok.
So, once it is there then this particular term X prime Y came from DeMorgan's theorem
you can write in this manner and this one also in this manner and finally. So, we have got
our XY prime and X prime Y, and then again, we apply on this particular term
DeMorgan's theorem. So, we can get a NOR relationship. So, a NOR of this two, these
two terms which are already generated or need to be generated we get X is equal to Y
logic, we do not need to generate separately these two, ok.
X’.Y’ + X.Y = (X’ + Y).(X + Y’)
= (X.Y’)’.(X’.Y)’
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= [(X.Y’) + (X’.Y)]’
And, the other thing that we can see that we can generate these XY prime and X prime Y
by NOT gate and then ANDing which is possible, ok, already in some cases you are
generating X you know, inverse of X - X complement somewhere or Y complement, you
can make use of it or we can generate it. But otherwise also we can see that if we have a
NAND gate between X and Y we are getting XY NAND which is nothing, but X prime
plus Y prime, ok.
(X.Y)’ = X’ + Y’
X .(X.Y)’ = X.Y’
Y .(X.Y)’ = X’.Y
So, when you AND X with that so, XX prime will become 0. So, XY prime will be
generated here and if you AND Y with that right, with this one so, X prime Y will be
generated and Y and Y prime will become 0. So, we can get generated this one, you do
not need then one additional - of those two NOT gates rather one NAND gate will do.
So, by this we can get this made clear. So, that is for 1-bit comparison.
(Refer Slide Time: 12:07)
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Now, let us look at how to do 2-bit comparison, right. So, for 2-bit comparison then the
number we are having is X 1 X naught and Y 1 Y naught. So, X 1 is the more significant
bit and X naught is the less significant bit; accordingly, it is for Y, ok. Now, we know
that X as a whole the number will be greater than Y, if X 1 is greater than Y 1, isn't it?
More significant bit; so, if X 1 is more than Y 1, what is the option then; that is X 1 is 1
and Y 1 is 0, then irrespective of the rest of the bit 0 0, 0 1, 1 0, 1 1 all the time right you
are having X greater than Y all these cases. So, this is your X 1 and this is your X naught
and Y naught, and this is your Y 1 and this is your Y naught right because more
significant bit is larger than this, ok.
So, in this case we do not need to worry about the other things, ok. So, when X 1 is equal
to Y 1 that both of them are 0 or both of them are 1, then whether X is greater than Y or
not is decided by the you know, X naught Y naught comparison, right. So, this is at that
time only you look at it. So, this is we know between you know, comparison of two
numbers.
So, basically we are looking whether X 1 is greater than Y 1 and also we are looking at
X naught is greater than Y naught when X 1 is equal to Y 1. Now, if you remember the
way we had compared 1-bit generation, so, X 1 greater than Y 1 we can get if we do 1bit comparison of X 1 and Y 1. Whether X 1 is equal to Y 1 we can get by 1-bit
comparison of again X 1 Y 1 where the equality part is looked at X is equal to Y output
is looked at and X naught Y naught we come from 1-bit comparison of the lower
significant bit X naught and Y naught.
So, what we do? We generate two 1-bit comparator, we use two 1-bit comparator, right.
So, one is to generate G naught, E naught L naught by the same equation that we had
done before and another is for G 1, E 1 and L 1. And so, we write - so, basically this is
the generic 1-bit comparison you know, circuit. So, instead of X and Y we are writing X
i, Y i to indicate the bit position. So, 0 position you know position 1 and position 2 or so,
ok. Is it clear? So, this is the way circuit is made.
Now, if we look at this X greater than Y thing, so, X 1 greater than Y 1 is your G 1 - it
will be given by G 1, right. So, if G 1 is high G 1 is true then X will be greater than Y
irrespective of the other things, right. When G 1 is not high, right - then two possibilities
are there, that the number is equal or number X 1 is less. So, if the number is equal E 1
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then you look at whether this lower significant bit G naught is high, I mean or not lower
significant of X is more than Y or not, ok.
(X > Y) = G1 + E1G0
X = Y) = E1.E0
(X < Y) = L1 + E1L0
So, this way you get the logic for X greater than Y. So, similar thing you will get for X
less than Y, where we look at L 1 if X the higher significant weight is lower of course, it
will be less and if they are equal then you look at the next significant bit, lower
significant bit whether it is less. Then, it will be as a whole the number will be less and
when it will be equal - when both E 1 and E naught are equal, then only it will be equal,
is it ok. So, two 1-bit comparators and additional logic circuit will give me 2-bit
comparison, ok.
(Refer Slide Time: 16:43)
Now, if we extend it, we can get n-bit comparison which includes 4-bit comparison the
way we have seen - subtraction and all of two 4-bit number before. So, in this case, X
greater than Y and the numbers are X naught to X n minus 1 and Y naught to Y n minus
1 and we are looking at as a whole X greater than Y or equal to Y or less than Y or not,
ok. So, we will be having n number of 1-bit you know comparison circuit the way we
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have seen before and then we look at the most significant bit first, G n minus 1 if this is
high then of course, X greater than Y, right.
If it is not high - low then if the most significant bit is equal; if it is less than - the most
significant bit of X is less than, then you do not, you know, need to go to next step. If
they are equal, then you look at the next significant bit. If the next significant bit is also
equal that is E n minus 1 and E n minus 2. So, that tells that both the most significant bit
and next most significant bit they are equal. Then you look at the next significant bit,
with that that is more than the other or not basically we are talking about in this case say
0 0, this is also 0 0 this is X and this is Y, right.
So, if both are equal then you are looking at whether X, this particular position is more
than this or not or the other case: when both are 1, right then whether this is 1 or not. So,
this is where we are when we are discussing - we are looking at this case. So, if they are
again equal if you see that they are equal, so, it could be 0 0 could be 1 1, then you look
at the next case whether this is 1 or this is 0. So, this is the way the equation can be
understood, right. X is equal to Y will come in this manner and X less than Y we look at
where this L n minus 1, E n minus 1 L n minus 2… So, this is similar to the other case,
greater than case. Is it ok?
(X > Y) = Gn-1 + En-1Gn-2 + En-1En-2Gn-3 + … + En-1En-2 … E1G0
(X = Y) = En-1En-2 … E1E0
(X < Y) = Ln-1 + En-1Ln-2 + En-1En-2Ln-3 + … + En-1En-2 … E1L0
Now, when you develop the n-bit circuit with a 4-bit comparator which we shall see
later, it might so require that you are looking for 8-bit comparison ok, but you have got
you know, 4-bit comparator IC or 4-bit comparator circuit available with you. So, you
would like to cascade that you need like to connect to another IC, is it not. So, that is
what your intention will be. So, in that case you need to have option for connecting
inputs, ok. So, in this case when you do that, you do it this way - that the input is coming
from lower significant bits. So, current IC is, current circuit is comparing the more
significant bits.
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So, what we will do? So, everything is remaining same then all current ones are equal;
more significant bits are equal, then you look at whether X is greater than Y that is
coming from the lower stage lower significant you know, bit. So, it is greater than Y in
or not, and if all are equal if X is equal to Y in is equal then the as a whole it will be
equal, right and similarly for the less than cases. So, now, we are putting a out and in
prefix in these cases because we are now in a position to accept output of comparison
from lower significant bits from another logic circuit, ok.
(X > Y)out = Gn-1 + En-1Gn-2 + … + En-1En-2 … E1G0 + En-1En-2 … E0.(X > Y)in
(X = Y)out = En-1En-2 … E1E0.(X = Y)in
(X < Y)out = Ln-1 + En-1Ln-2 + … + En-1En-2 … E1L0 + En-1En-2 … E0.(X < Y)in
(Refer Slide Time: 20:57)
Now, we come to a 4-bit comparator IC which is used in practice right and which is IC
74 one IC 7485 and you can see what is there this is a 4-bit comparator IC, ok. So, these
are the X 4-bits and these are the Y 4-bits these are the inputs that I said that it can come
from lower significant bits where you know the lower significant bits are getting
compared in another IC or another circuit and these are the output of this stage, which
also considers the input, right.
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And, if you look at the circuit these are all these blocks are 1-bit comparator we can see
over here, right and we have used you know these bubbles naught option. So, we can just
compare and see it. For example, this particular AND output, this particular AND output
is 1 when A 3 is equal to 0 and B 3 is equal to 1. How is it that? You can see that if A 3
is equal to 0, this output will be 1, right and B 3 is equal to 0, right B 3 is equal to 0 then
this is B 3 is equal to 1 then this one is also coming. So, both of them are 1. So, this
AND gate output will be 1. So, this 1, this is 0. So, this output will be 1, sorry this output
will be 0 because this is AND gate and at the input of it 1 it is inverse. So, that is 0 is
there, ok.
So, if B 3 is more than A3 this cannot be 1. Similarly if you look at this particular AND
gate, so, if A3 is equal to B 3 if you look at the connection A 2 is equal to 0, B 2 is equal
to 1, then this output will be 1. So, that also ensures that in that case, in that case the
output will be 0. So, this is the way the circuit has been developed, right.
(Refer Slide Time: 23:08)
And, if you look at the function table of IC 7485, as we have discussed it is similar if A 3
is greater than B 3 right, irrespective of what are the other you know inputs as well as the
cascaded inputs the output will be A greater than B, and if A3 is less than B 3, then it
will be less than B 3, right. And, when A 3 is equal to B 3 at that time you look at
whether A 2 is greater than B2 or not if A 2 is greater than B 2, irrespective of the other
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cases a greater than B, ok. So, this is follows what you know what basic comparator
logic should follow, ok.
Now, comes you know when all of them are equal all these current bits. So, this is the
case A 3 B A 2 A 1 A naught are equal to B 3 B 2 B 1 B naught; so, at that time if A
greater than B right, then at the input, then A greater than B at the output. So, it is now
looking at the lower significant bits – it is comparison of that. Similarly, others and
where A 3 is equal to B 3 then this is if this is high then this will be A equal to B.
Now, it is not expected that at the input side ok, both X greater than Y and X less than Y
both will be equal to 1, because either it is high or it is less, ok. So, that is what is
expected, right. But, in case it happens for some you know reason, the circuit is made in
such a manner even though it is not expected that if both of them are high then the output
in this case A greater than B. So, both of them are low if both of them are low then both
of them are high, this is what is there which we shall see can be used to our benefit in
some configuration, ok.
So, this is not, is going to happen in normal cases, but according to the logic circuit that
has been developed this is what the function table gives us; as such this is a don’t care at
the input side, ok. But, because this is there in the final truth table we can see that it can
be put to some you know, useful now configuration of comparator circuit for larger
number of bit comparison and that part we shall take up in subsequent slides.
(Refer Slide Time: 25:55)
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Now, as I said it can be used for comparing more number of bits because of the option
that is available as input. So, if you look at 8-bit comparison. So, of course, the lower
significant bits need to be placed here and here this X is equal to Y input is kept high the
others are kept low, X greater than Y and less than Y, clear? And, so, these outputs X
greater than Y equal to Y and X less than Y whatever is getting generated here in this
three cases are fed as input to the next IC and the final output is taken from here, ok, is it
clear?
Now, if you look for say 24-bit comparison, how will you go about? So, you will be
requiring you know 6 such ICs. So, the first case we will be connecting in this manner,
right that is the input pin number 3 that is X equal to Y in that will be high and other two
will be 0. So, for the first one, right and after that you are connecting the Y you are
connected it. So, final output will be generated from here, right and in this case the final
output generation will depend on the logic operation done in previous cases.
So, basically this IC - comparator will wait till you know this previous comparator
generates its output, this will wait till this one generates its output. So, that way you see
the propagation delay is you know, cumulative in nature, ok. This comparison result will
come, but it will be the delay of each of this stage will get added which is how it is going
to work.
(Refer Slide Time: 27:56)
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But, we can have another configuration when we are using the same you know six
comparators only for 24-bit comparison. So, there we can put, we can put five such
comparators here in the first place in one stage which will be giving, which is giving
comparator output after one unit delay that happens within the comparator and after that
it is another level. So, it is a two level comparison, right and you see how intelligently
the connections have been made. As such for 5 you can get 5 into 4, 20 inputs, but how
24 inputs have been placed there?
So, for this you know least significant 4-bits are connected in the standard way, ok. So,
the A is equal to B is high and the other two are low, right. So, there goes 4, 4 inputs and
we have another 20 inputs to place, right. So, that is placed 5 of them are placed in rest
four in the first stage. Here 5, 5, 5, and 5. How? And, then these outputs are put over
here. So, the first one is these two and rest this four A naught B naught to A3 B3 are
coming from these four, ok.
So, how does it work? So, in the first place this A 4 B 4 we are placing it here and A 4 if
it is greater than B 4, then it is fine. It is A greater than B it will go in that manner. So,
the corresponding output will be generated, right? A greater than B, otherwise if B 4 is
more than A4, so, if the A less than B will be generated if other bits remaining same, if
all of them are remaining same because this is a lowest you know lower significance
compared to other.
Now, if they are equal all these are same, they are equal that is where the problem could
have been there, right. But, if they are equal we have seen in the previous case in the
function table as I was telling there, if they are equal you see the outputs are also equal,
if both of them are high and both of them are low output are also LL and HH in this
particular case. So, both of them will be low or both of them will be high in that case.
So, when they are fed as A naught B naught here so, both of them are high and both of
them in low. So, they do not contribute to the comparison that is equal and contribute in
the sense that input is compared - you know equal. So, if everything else remains same
and the output is generated you know, depends only on A 4 and B 4 comparison so as to
say, ok, then if both of them are low and both of them high will generate same high-high
and low-low output here and over here same high-high and low-low and the output will
be A is equal to B in the final case. So, the fifth bit can be inserted in that - here like this.
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So, similarly for the other cases; so, 4 into 5, 20 and this is 4, ok. So, that is a clever use
of this thing and by which we can see this because of the parallelism the propagation
delay can be reduced.
(Refer Slide Time: 31:25)
So, with this, we come to the conclusion of this particular discussion on comparator.
Magnitude comparison of two numbers can be done by subtracting one number from the
other and developing suitable logic circuit to generate this X greater than Y, X is equal to
Y, X less than Y output. We shall see in the next class the ALU basically, arithmetic
logic unit does it in that manner only; we do not have separate comparator circuit within
it. A direct approach for magnitude comparison of two numbers can avoid subtraction in
this place value of the bits being compared is useful, I mean if it is more significant bit
they differ then we can arrive at the decision from that directly.
IC 7485 is a 4-bit comparator with option for connecting input from lower significant
bits that are getting compared in another IC 7485 or logic circuit. And, delay at every
stage can add up for larger number of bit getting compared when you connect them in
serial, but there can be an option of parallel multilevel arrangement, ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 27
Arithmetic Logic Unit (ALU)
Hello, everybody. In this particular class, we shall discuss Arithmetic Logic Unit, often
we term it as ALU, the abbreviation of it.
(Refer Slide Time: 00:27)
And, arithmetic logic unit as you understand from the very name of it that it is one unit
within which both arithmetic and logic operation are to be done. The idea is that if you
are looking for a circuit which is to be used in a general purpose device. So, you do not
know for sure that what this circuit is you know, going to do. So, when we require it will
do some logic operation, in when required it will do a different logic operation or it
might do an arithmetic operation of one kind or the other.
So, would you like to have many such you know, possible circuits and then invoke one
of them when it is required and others are remaining you know, idle at that time or would
you like to have a device which can do all the different function, many different
functions and you have appropriate selection input by which you choose which
arithmetic or logic operation you want to do, ok.
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So, for such general purpose you know, device you would be preferring an option like
having an arithmetic and logic computing unit and which will be used by the main
processor or the other you know, processing units, ok. So, this is the idea. So, you can
understand that when you are talking about such unit, it is relatively complex in design
when you look for practical use of say using it for 4-bit, 8-bit kind of thing and many
different functionalities are involved.
(Refer Slide Time: 02:11)
So, what we shall start, we shall start discussion on this by you know in step by step
manner. So, that we you know, do not get you know, frightened by looking at the bigger
circuit - more complex circuit having you know, about 70 logic gates or so.
So, first we look at a simple circuit where we are doing a 1 bit you know operation and
the operation that we do here is either a logic operation NAND or NOT or a half
addition, ok. So, this is the thing that we are doing, right and so, it has got two inputs A
and B, A and B. So, these are the operands we can say and the result of you know, the
operation is coming from coming out in Y naught and Y 1, Y naught and Y 1 and S is the
select input, only one select input is there. So, it is selecting, if S is equal to 0, then Y
naught output will be a logic operation of A B - NAND of AB and at that time Y 1 if you
look at Y 1, if you sample Y 1 you will get A NOR B, ok.
If S = 0,
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Y0 = (A.B)’
Y1 = (A + B)’
But, if S is equal to 1, then what you get is the half addition. So, Y naught will be the
sum bit which is XOR of A and B, right. So, A prime B plus AB prime and Y 1 will be
the carry bit. So, this is the carry bit. So, that is AB you all know about it. So, we have
seen this before, right.
If S = 1,
Y0 = A’.B + A.B’
Y1 = A.B
So, how would you write the circuit inside the for this simple 1 bit unit? So, we -, very
simple you know logic function and arithmetic function that we have seen - so, we’ll be
writing S prime, when this is the half bit at the case for Y naught S prime AB prime for
here for this particular case and S - plus that is ORed with when S is equal to 1, A prime
B ORed with AB prime. So, this is now we will write it, and if you do simplification then
you can see this is the way Y naught will be related to S, A and B.
Y0 = S’.(A.B)’ + S.(A’.B + A.B’)
= S’.A’ + A’.B + A.B’
And, if you look at Y 1 how will you write it? So, S prime AND A plus B prime, right
and S A B this is coming from here, right. So, if you take it there. So, this you from the
you know, De Morgan’s theorem S prime A prime B prime then S A B. You can see that
this is you know the simplified version of it. So, realize them. So, it does the operation.
So, it is little bit simple.
Y1 = S’.(A + B)’ + S.A.B
= S’.A’.B’ + S.A.B
Now, let us look at a you know more complex thing.
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(Refer Slide Time: 05:11)
So, here we are having a 2-bit operands, right. So, A naught A 1, here and B naught B 1
and the corresponding outputs are Y naught Y 1, and we have additional input carry-in;
and carry-out, here, additional output. And now we have got two select inputs S 1 and S
naught ok. So, what we see here? So, we look at a function table, ok. So, for S 1 and S
naught 0 and 0 - 0 0 so, we ignore the carry-in, we do not take into consideration the
carry-in at that time and the output at that time is A NAND B; NAND of AB, ok. So, by
this what we mean? We are meaning bit wise operation, ok, right. So, that means, Y
naught is A naught NAND B naught Y 1 is A 1 NAND B 1. So, that is what we mean by
this. Is it ok?
So, similarly for 0 1 we are having NOR operation, bit wise NOR operation. So, these
are the things that is happening for you know these cases 0 0 and 0 1. And for 1 0, if
carry-in is 0, Y is equal to A and if carry-in is equal to 1, this is A plus 1. Now, we are
are introducing a term plus to differentiate it from the sum operation that we do with this
symbol +, ok. So, A plus 1 and when this selection inputs are 1 1, right if carry-in is 0
this is A plus B and carry-in is 1 this is A plus B plus 1, ok. So, that means, it includes
the carry-in, right. So, basically what you are doing is full adder - full addition. So, this is
what we are doing. Is it ok?
Now, how to develop the circuit for this? So, we can see I mean basically it is a now 5
variable problems S 1 S naught and you know Cin is there. So, of Cin is 0. So, you know
to make it understandable here. So, if Cin is 0, ok. So, at that time for this option, S 1 S
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naught 0 0, ok. So, when a naught B naught both are 0, this is NAND. So, this is the line
we are talking about. So, this is 1, right when one of them 0; A naught is 0 and B naught
is 1 NAND output means this is 1. When both of them are 1 NAND means this time it is
0; when A naught is 1 and B naught is 0 this is 1. So, this is the way you can complete
this one and this is the corresponding truth table (Corrected: rows shown by } in K-Map
are interchanged), right and you can have a relationship you know going forward for a
five variable problem and minimize and you can the circuit, and you can see if it is now
multiple outputs are there whether you can take some intermediate output to the next
level.
So, this is the way you can visualize a 2-bit arithmetic logic unit which is doing you
know, two set of - two logic operation. And essentially this is one mathematical
operation; arithmetic operation this is one - just carry part is included in one case and
carry is not included in the other case, basically it is not two different. So, basically with
two inputs you can have four possibilities two is assigned to arithmetic and two are
assigned to – two are assigned to logic, ok.
(Refer Slide Time: 09:32)
Now, we go to something which is actual arithmetic logic unit IC that you might use in
the lab - this is IC 74181. So, you can see it is a 24-bit IC and in this IC - this is a 4 bit
arithmetic logic unit; 4-bit arithmetic logic unit and the inputs are A naught to A 3 where
you can see them A naught to A 3, A 1, A naught, A 1, A naught, A 1, A 2 and A 3 this
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is active low, right and B naught, B 1, B 2 and B 3, right. So, these are the inputs. So,
selection; so, selection is designated by S, S naught, S 1, S 2, S 3. So, what it means. So,
it tells us that some 2 to the power 4, 16 possible you know operations is possible,
actually not - you can do more than that because you have it has got as a additional unit
input called M; M stands for mode. So, if M is equal to high it is logic operation and M
is equal to low, it is arithmetic operation.
So, for each of these cases of M you have got sixteen possibilities. So, total thirty two
different possibilities are there sixteen arithmetic operation and sixteen logic operation is
possible through this particular ALU, ok. And, this is the carry input which can be taken
from previous stage or you know, another logic circuit and this is the carry output which
we can take to the next circuit so it can be used for ripple carry addition if so, you know
required, ok. And, other than that look at you have this group carry generation and group
carry propagation term that is getting generated out of this which is useful, which would
be useful and we shall see one such you know frame work by which these two group
carry terms are used for fast addition.
So, internally it is doing fast addition, but if it is to be connected to the next stage or
other stages, if you want ripple carry then this is there Cn plus 4 and if you want look
ahead carry generation for which you need G and P term getting generated - they are also
there, ok.
So, equality A is equal to B this output is generated, but not A greater than B or A less
than B that I told, right and then these are the main outputs for these operations - A and
B, where A and B are operand, are generated from F naught - generated at F 1, F naught,
F 1, F 2 and F 3. Is it clear? Right.
So, when you look at the function table we shall see the arithmetic operation that are
being done include addition, subtraction, shift of operand A, A is considered as main
operand here, by one position, right. So, then magnitude comparison - not directly
because there is you know, there is no direct output as A greater than B or A less than B;
A equal to B is there, but not the other cases. So, by some other means we can do it and
we shall see that logic operation like NOT, AND, NAND, OR, NOR, Ex-OR, Ex-NOR
they all, these common things are there, but more than that also it is there, ok. So, this we
shall see.
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(Refer Slide Time: 13:07)
So, this is the function table, ok. So, again it might look little bit you know heavy, but
because there are you know, thirty two different possibilities are there. So, this is M is
equal to H right the logic function it is generating, ok. So, this - these are the different
logic function for choices of S 3 to S naught say L, L, L, L; that means, all of them are
low. So, at that time the - whatever at the function outputs F 3 to F naught will be the
complement of A 3, A 2, A 1 and A naught. So, that is what it says, that is what you will
get, right. That is the why the circuit is different. We shall look at one example also after
few slides, is it, ok?
So, next one is similar you know, the different logic functions we can see the one that I
told that NOR will be available, ex-NOR is there. So, many other things are there we
shall see what are they and what are the representation and similarly for logic M is equal
to low, so, depending on presence of carry and absence of carry and presence of carry the
meaning is different if in one case if it is A minus 1 when carry is included it is F is equal
to A, ok. So, it is just input is passing through to the output. So, the different cases A
plus B and A plus B plus 1 right. So, these are so, A minus B and this is A minus B
minus 1, right. So, these are the different functions that you can get and make use of, ok.
Now, one thing important here the A is equal to B the magnitude comparison output, the
magnitude comparator output here is open collector, ok. So, open collector we
understand. What does it - what does it mean, basically you need additional you know,
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resistance and it is connected to the power supply through which actually the circuit
operates. Other than that what we know - it can deliver more current? So, other than that
we know that it can offer wired-AND connection also. So, if you have another say a you
know 4-bit comparison being done by another say ALU which also has got open you
know, collector output for A is equal to B. So, those 4-bits and these 4-bits, if you just
add the, you know may provide connection I mean just connect the wires there. So, it
will be giving an AND logic.
See both of them are high right then you can say as a whole this 8-bit number is high and
as a whole 8-bit number is equal; if one of them is low then of course, equality is not
established. So, something else is happening, right. So, this you - this is giving you a
very quick you know comparison between two numbers which are being compared in
two different ALUs, by making use of the wired-AND option of an open collector
output, ok.
So, there is no multiplication as such, but A plus A means 2 into A which is basically is a
left shit of one unit of A, ok. So, that is what we can see and for magnitude comparison
there is no such you know, separate input. So, you can look at the result, this carry
getting generated. So, it is noted what is the implication of the carry, right; when you are
doing the subtraction when you are doing the subtraction ok. So, L H H L so, what is it?
So, this is the one, ok.
So, in one case it is A minus B minus 1 and other is A minus B. In the last class for
magnitude comparison we have seen that how to get it done through subtraction, right
and so, we told at the time that ALU will be using subtraction for that. So, if it is low and
this is low right then we can tell that this is A less than B - less than equal to B; it is low,
this is high, it is A greater than B you can see the 2’s complement arithmetic how it is
done. This is high and this is low; then it is A less than B and if it is high it is high then it
is A greater than B by which you can get the magnitude comparison done, by
understanding this carry output Cn plus 4 in presence of or absence of Cn .
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(Refer Slide Time: 18:10)
Now, the function table as I said, they had these logic functions, right. So, if you look at
you know closely the closely the logic functions that are there we’ll see that the outputs
here connects to this table on a one to one basis, ok. So, what is that and what is this
table? So, this table we had seen in one of the you know, earlier weeks of this particular
course. So, if two inputs - what are the many different functions that are possible, ok. So,
we found that 16 possible functions could be there with these two inputs 0 0, 0 1, 1 0, 1
1, ok. One possibility is that for each of this case the output is 0; one possibility is that
only for 0 0 the output is 1 and rest of the cases it is 0. One possibility is that the for 0 1
it is 1, rest of the cases is 0.
So, with this four we can have again 2 to the power 4, 16 different combinations of 0’s
and 1’s, generating sixteen different functions ,sixteen different functions, right. We had
seen where we had got AND, OR and those kind of cases. So, if now what each of these
cases L L L L the first one we designate it by number 1; second one we designate by
number 2. This is number 1, this is 2, this is 3 and so on and so forth. You can identify
that in this particular - this function table this function table right 1 is somewhere. So,
here is your 1 which is not there in other places because each one of them is unique, ok.
So, L L L L for this thing this is A bar and you can see this is 0 0 this is 1 and this is 1
this is 0 0. So, this is A bar. Similarly, you can find out 2 appearing here, 3 appearing
here and that way each of theses functions possible functions are actually covered by this
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logic operation. So, if you need any one of them, you can make use of them if so
required by invoking appropriate selection input, by invoking appropriate selection
inputs. Is it clear?
(Refer Slide Time: 20:51)
Now, this is the IC 74181 circuit. If you look at the you know, manufacturer’s data sheet
and all how it is there so, as I said it is a bit complex. So, is that is why we began with
simpler you know version of it, ok, but now we are in a position to understand what it
represents and how it works or so, and we can look at one example case . Look at one
example case where the selection input is all 0 right, M is equal to 1; M is equal to 1
means it is logic function and B is all you know zeroes, right; Cn is also 0.
So, if this is the case 0 0 0 0, then what we are expecting; F is equal to A prime this is
bitwise you know, complement operation, right. So, we expect that F naught will be A
naught F naught sorry, A naught bar right; so, that means, when A naught is equal to 0, F
naught will be 1; A naught is equal to 1, F naught will be 0. So, this is what we expect;
similarly for other cases, right.
So, and it does not depend on B and Cn is immaterial. So, that is what we expect and we
can see whether it is happening or not let us you know look at one such example case.
So, this is where A naught is given. So, we have considered the case A naught given as 1
in the blue, and A naught given as 0 in the brown, ok. You can see the colors, right. So,
when so, I am trying to make it cleaner. So, this A naught is 1, ok.
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Then what is happening? This is 1 is coming over here; for NOR gate 1 is there means
this is 0 the output is 0, and the other inputs this AND gates you can see it is coming
from selection all selections are 0. So, these are 0 0. So, this is also 0 0 because one of
the input is connected as the selection input which is 0 0 right. So, 0 0 this NOR gate this
output is 1, ok.
Now, we look at the other cases. So, this is this XOR gate - 0 and 1 this is the input. So,
this is thus this output is 1. So, the for the final output for F naught this is the XOR gate
which is giving an input 1, and we have to look at this NAND gate output. So, this
NAND gate output it has got M is equal to 1 here because it is a logic operation. So, the
NOT gate output is 0. So, 0 to a NAND gate output means it is 1, ok. So, 1 1 for an XOR
gate you know, the output is 0 this is clear. So, for A naught is equal to 1, F naught is
equal to 0.
Now, if A naught is made 0. So, this is made 0, what is changing? What is different
here? So, A naught is 0 means this is becoming 0. So, this NOR gate output, now all the
inputs are 0 so, this output will now become 1. This NOR gate output is already 1
because of you know the selection lines are 0, right. So, this is 1 1 means this is
becoming 0, right. So, this XOR gate - one of the input is 0 and the other input is 1
because of you know the M being 1. So, NAND gate is output is 1, ok. So, 1 and 0 then
this output is 1, is it fine?
So, you can see that this is happening. So, we can see for other cases also and it works in
that manner.
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(Refer Slide Time: 25:18)
Now, what we look at other than this the way the function table it works and all how
ALU can be - work in tandem with look ahead carry generator so, IC 74181 and IC
74182, ok. So, look ahead carry generator is 182 which we had seen before, right when
we discussed fast adder. So, here we show you a framework which the is available in the
you know manufacturer’s data sheet if you go to the TI’s – Texas Instrument’s website
and all, you can figure it out.
So, where we can see that the addition - where we are using 64-bit addition. So, for this
64-bit addition we are using basically 64-bit operation we are doing using 16 ALU each
is 4-bit, right each is 4-bit long. So, 74181 as you can see the first level 1 2 3 4 5 this way
sixteen such cases sixteen such units will be there, ok.
And, the G and P term we had seen in the ALU that these are the terms that are there. So,
four of them can go to one IC 74182, right and these IC 74182 is generating C n plus x,
C n plus y these carries-in you know. So, that is getting connected here for each one of the generation process right. So, this we have seen in the previous case how 782 works rather 182 works, right. So, similarly for this one, similarly for this one; so, four such
look ahead carry generator will be there, ok. So, they are again generating this look
ahead carry generation and propagation term out of them because the circuit dissimilar,
right and then this will be again fed to next level of IC 74182 which has got which can
take four inputs, and then we can get the final carry out of it.
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So, basically this is the way you can use 74181 and 74182 and using multiple levels you
can get the carry ahead of you know, normal ripple carry based addition would have
given, ok. And, you have - we have already noted that the 74181 also generates it you
know normal carry which can be used for C n plus 4 which can be used for ripple carry
addition if it is so required, ok.
(Refer Slide Time: 28:20)
So, to conclude we find that ALU is a versatile unit that can perform arithmetic and logic
operation on operands according to control inputs which is coming through the selection
lines. It is a 4-bit ALU IC 74181, with the mode select input and depending on whether it
is high or low, logic or arithmetic operations are done and it includes commonly used
NOT and NAND these operations and in fact, it is - it can generate all possible
combinations of two variables that is 16 possible functions.
And, arithmetic operation includes addition, subtraction and magnitude comparison by
indirect manner and then it has got additional inputs like ripple carry, group carry
generation, propagation term equality and IC 74181 can be connected to IC 74182 you
know the - a combination can be prepared by which look ahead carry for more than 4-bit
arithmetic is possible, ok.
Thank you.
411
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 28
Unweighted Code
Hello everybody. In today’s class we shall discuss Unweighted Code.
(Refer Slide Time: 00:25)
So, we have seen binary coded number and we have seen that the weight associated with
binary code is 1, 2, 4, 8, 16, so on and so forth before the binary point and half, 1 upon 4,
1 upon 8 etcetera after the binary point. We shall see these are - we shall look into what
is the need of having unweighted code. Then we shall discuss two important such codes,
gray code and excess 3 code and also, we shall discuss ASCII code.
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(Refer Slide Time: 01:01)
So, if you remember the quick revisit of the binary code. So, 4-digit numbers B 3, B 2, B
1 and B naught ok. So, with that - with the binary code this formula you remember the
corresponding values. So, for any number with base or radix r so this is the digits and
this is the corresponding value. So, if we consider this number 1010 and if it is 8421
code normal you know 2 to the power 0 etcetera this way, the standard way of
associating weight, the value will be for this one 8 will come, and for this one 2 will
come, ok. So, 8 plus 2, 10 will be there.
dn … d1d0.d-1d-2 … d-m = dn x rn + … + d1 x r1 + d0 x r0
+ d-1 x r-1 + d-2 x r-2 + … + d-m x r-m
So, there can be other kind of weighted code where this is not exactly like this r to the
power n, r to the power 1, in the way it is increasing the - integer power is increasing
based on the position, ok. So, there can be other way of putting weights. For example, if
it is a 2421 code. So, the first position is associated with the digit will be having a code
weight of 1, second position 2, third position 4, and the fourth position is having a weight
of 2. So, that is for 2421 code. So, that is also a weighted code because weight associated
is 2. It is not 2 to the power 3 - 8 that we see for 8421 code, ok.
And 1010 if we are using 2421 code, what will be the value? So, the 1 in the; this place the 3 place will be having value 2, and then there is a 0, then there is a 2 for this
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particular one and then there is a 0. So, 2 plus 2 the value will be corresponding this the
equivalent will be that of 4 for this 2421 code in 1010 representation, ok. This part we
understand, I mean regarding weighted code.
Now, what could be the issue with weighted code for which we might need to look into
different form of unweighted code, ok. So, one of the issue that you can see in this
particular case. So, when we are changing the number from 0 to 1 to 2, so this is your 1,
this is your 2, then 3, 4 so on and so forth the decimal equivalent - the consecutive
increase in the number. So, from 1 to 2 you can see that 2 digits are changing, 0 1 is
becoming 1 0, ok.
So, from 3 to 4 you can see 3 digits are changing 1 1 is becoming 1 0 0, ok. So, what
could be issue with that? So, this is the way the weighted code you know is 4 2 1 code
the why we have seen it is you know is there. So, let us see one possible you know issue
with such kind of coding.
Consider there is a conveyer belt, the one that you see here, over which some material is
there and the conveyer belt is moving in this direction, right direction as has been shown
with the arrow, ok. So, it is moving from zone 1 to zone 2, for where some activities are
taking place and the conveyer is goes is suppose to go in this direction, right. And if you
are sending a binary code of the zone where the - this particular material is lying at a
given time to a control unit, through a mode of you know digital transmission of data.
So, from zone 1 - 0 0 1 it is going to 0 1 0, that is the way it will be kind of you know,
shown in that control room, right.
Now, from 001 to 010 since these two digits are changing, if so happens because of
various you know delay our elements associated with the bit positions and the changing
of the value, the coding of the value and its transmission, there this 1 is changing, when
this 0 has not yet changed. So, 1 this 1 is changing faster than the 0 that is suppose to
change to 1. They are not exactly you know, changing in the same time, and after that it
is going to 010 of course, after some delay.
So, at some point of time the 001, after that 000 will come and that will make an in
interpretation that the - it has moved from zone 1 to zone 0, when it is suppose to go to
from zone 1 to zone 2, is not it. So, basically the conveyer belt is moving in the reverse
direction. So, that might cause or that might cause some alarm or emergency some
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issues, with this you know particular thing. So, if people would prefer in such a scenario
for consecutive numbers that only 1-bit you know, if it is possible to make change, ok.
So, that gives rise to what we call gray code.
(Refer Slide Time: 06:33)
So, in gray code two consecutive numbers are - do differ by only 1. So, the distance
between two numbers in terms of the positions in the is only 1, ok. So, if we look at
example of some such you know, gray code from the initial value say, 0 to 10, the way
we had seen for binary code. So, these are the corresponding equivalent 0, 1, 2, 3, the
consecutive number we already know 5, 6, 7, 8, 9 and this is 10, right.
Now, corresponding gray code if you see 0 is 0, right there is no ambiguity about that, 1
is 0 0 0 1 absolutely no issue because only 1-bit is changing, right. Now, here when it
comes to 2, it is 1 0; 2 bits are changing. Here it is 1 1, ok. From 2 to 3 this is 1 0 this is 1
1, from this 1 1 now only 1-bit can change. So, this 1 1 is now 1 0, right. So, is there any
rule by which we can get you know, this number from you know binary to gray or you
know some sort of way the number can be generated, not heuristically.
So, one such method, one such method is through reflection. So, how is it that? How is it
let us see. So, first 0 and 1 - we have no issue, two numbers 0 and are 1 is getting you
know represented in binary as well as gray. So, this is this 0 1 you reflect, like this is a
mirror, so this is 1, this one is getting reflected and this is a 0.
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Now, some additional bits are required because the number you know the count we are
trying to increase. So, you put 0 0, 0 in the first two and 1 in second; so, 0 0, 0 1, 1 1 and
1 0. So, that gives you 0 1 2 3. You can see over here the first four. So, first 4 number is
obtained.
Now, to get next 4 numbers what we shall we do? Again, we will do the deflection. Now,
we shall take this 2 digits together, so 0 0, 0 1, 1 1 and 1 0. So, if we reflect, so 1 0 is
reflected here 1 1 is reflected here 0 1 is reflected here and 0 0 is reflected here, ok. So,
again we shall put 0s here and 1s here. So, by which the third digit comes into play, so
that will give us 8 such consecutive numbers.
And similarly, we can go for - this 8 will be represented here, so that gets reflected like
100 is reflected here, 101 is reflected here and then we will put to place the 4th digit here
first block 0 and second block one we shall get the consecutive numbers. So, this that is
the way we can get it and we can see that the gray code is formed, ok. So, the I mean
generalized at by reflecting n minus 1-bit gray code we can get in the gray code, ok. So,
this is one way of getting the gray code, right.
So, gray code in 10 is 1010 this is 1111. Of course, you can understand that this is not a
weighted code, ok. If you try to at associate some weight a like 8421. 2421 any other
weight you see that it is it is not working, ok. But good thing about it is that the
consecutive numbers are only increasing by 1-bit, so there is no ambiguity of you know
one of the number - one of the bit is changing slower than the other resulting in some
you know, interpretation of a different number coming in between, right.
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(Refer Slide Time: 10:30)
So, if we have a situation where the input is binary digit and the output is gray code - that
is what is required and then how we go about it, how we can get a the codes converted
and also vice versa. I mean we have gray code we want a binary code, right for some
reason, for some you know application. So, to do that if we look at the you know, the
mapping the we can come up with a very simple relationship where the nth bit, the most
significant bit, right, if it is a n-digit conversion that we are looking at that means the
gray code of that and the Bn will be exactly the same, ok.
Gn = Bn
Gi = Bi+1 ⊕ Bi for i < n
So, here if we take this 4-bit example; so, B 3 and G 3, so G 3 will be same as B 3, right.
And for other values, G i is B i plus 1 XORed with B i, ok. So, what does it mean? So, B
3 straight away goes as G 3, so G 2, ok, so the next gray code is B i plus 1 this is 2. So, B
3 XORed with B 2, ok. Then we shall get this one. G 1 is B 2 XORed with B 1, I mean
same way G 1 we get B 2 XORed with B 1, G naught we will get B 1 XORed with B 0.
So, if you just put it into the form of a you know bank of XOR gate you can get it in this
manner. You can see that whether this is working for example, if you say first case, so all
0, right, so 0 comes over here, right, so the 0 0 0 0. So, this is 0, 0 0 XORed is 0, 0 0
XORed is 0, 0 0 XORed is 0 – no issue, right.
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So, next one is 0 0 0 1, you can see 0 0 is 0. I mean 0 comes here this 0, the next one is 0
0 XORed 0, next one is also 0 and 0 1 XORed is 1, ok. Now, comes when there is a
difference. So, binary code is 0 0 1 0, right. What is happening now? Shall we get 0 0 1
0? Let us see. So, 0 comes over as 0 directly, 0 0 XORed is 0, now 0 1 XORed is 1 and 1
0 XORed is 1, that way we can verify rest of the numbers and we will see that such a
simple circuit works, as a code converter.
Now, for gray code to binary code conversion; so if you look at the reverse way the
mapping is done we can see that G 3 can directly go as B 3 and second bit B 2 can be
generated by XORing G 3 and G 2 and B 1 can be obtained by XORing B 2 the output
that has been generated, using G 1, right and B 1 XORed with G naught you can get B
naught, ok. So, we can again put those values and can see this is the way simply you can
get the binary code generated from the gray code, ok.
Bn = Gn
Bi = Bi+1 ⊕ Gi for i < n
(Refer Slide Time: 14:13)
Now, we come to another kind of you know, code which is called Excess-3 code. So,
here we are trying to represent BCD numbers - binary coded decimals. So, 0 to 9 these
are the you know 10 numbers. So, in binary coded decimal we have 0000 to 1001, ok.
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So, in excess-3 code what are doing, this 0 to 9 is represented by 0011 to 1100; that
means, whatever is the binary code, add to that 0011 we get excess-3 code. Why? Why
are we doing this? I mean what is the benefit out of it, will be cleared very soon, ok, we
shall discuss that part.
So, first we see that how it is represented; so this is the way it is represented. So, if we
are representing a number 5 3 in BCD code it will be 0101 for 5 and 3 0011 is not it, but
in excess-3 code this will be at 3 0011, so this is 1000 and this is 0110. So, you can see
that 5 is 1000 and 3 is 0110, right 5 and 3, ok.
So, similarly 6.9 if you want to represent again 6 is here you can see 1001, right and 9
here is 1100, ok. So, this is the way I mean, the representation is there and this is for
many other cases we can see for example, if you want to represent 487. So, 4 is 0111 in
excess-3, 8 is 1011 and 7 is 1010. So, this is the way the number will be represented, ok.
So, this is coming in computation with you know BCD code, and accordingly we shall
see the benefit, in subsequent slides.
And regarding code conversion; so how to convert from one form to another? So, one
approach could be the case where each of this XS-3 code. So, if I say if I represent them
as X 3, X 2, X 1 and X naught, right we can form a form a have a truth table where this
is X 3. What is the value of X 3 for different representation now? B 3, B 2, B 1 and B
naught, right. And the numbers that are not there like 10 to 15, right, 1010 at the input
site 1111, so those are the do not care cases, ok. We do not care about what will be the
value, right. So, with that we can have a you know, minimization process Karnaugh Map
QM or Boolean algebra by which we can get the value of X 3 then we can get X 2, and
get X 1, and X naught as a function of B 3, B 2, B 1 and B naught and you can realize it.
So, this is one way of you know, getting it.
The other one could be just having a 4-bit adder, right, a 4-bit adder by which you can
add and get it and the reverse process, reverse process means from XS-3 to binary. So,
we shall have B 3, right. We shall see how it is it can be represented as a function of X 3,
X 2, X 1 and X naught for different values, again we shall consider do not care to get this
and realize after minimization or we shall have a subtractor by which we are subtracting
0 0 1 1 from the excess-3 code - we shall get back the binary code, ok.
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(Refer Slide Time: 18:20)
So, the benefit we shall see - you will see over here, ok. So, compared to BCD arithmetic
you will see that excess-3 arithmetic is simpler, ok. So, let us see how the arithmetic is
done. So, if you are looking at addition of say two numbers for which the - no carry is
produced, no carry is produced, right. What is the implication of it? So, let us consider
two numbers 5 and 2. So, corresponding representation is 5 is 1000 in XS-3 and 2 is
0101 in XS 3, because 3 get added with normal - the binary coding, right. So, if you add
if you add, so this is 1, this is 0, this is 1 and this is 1. So, no carry is produced here of
course, no carry is produced, so we shall look at example where carry is produced.
So, no carry is produced, so this representation 1101, right this is a you know, valid XS-3
code, right and this the valid you know, number I mean valid number in the sense the
number which is which does not produce any carry, right but within it , it has 2
additional 3s, 2 additional 3s that goes inside it, ok, one from here another from here
compared to binary coding. So, basically what you get here is XS 6, the binary coded
number plus 0011 coming here as 0011 coming from here.
So, if you want to get the XS-3 version of the result which is our intention, what we need
to do? We need to subtract it subtract 3 from it, right because it is XS 6, if you subtract 3
we will get XS 3. So, the result will be if you subtract from here you get 1101 subtracted
with by 3 we get 1010, ok. So, this 1010 is the XS-3 version of - XS-3 of the number 7
that we see as corresponding decimal equivalent, is that clear, right.
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So, we no carry is produced the resulting number, resulting number is a valid XS 6
number, ok. To get XS-3 we have to subtract 3 from it and that is how it will. it is to
work, ok. And carry is not produced up to what? Up to 1111, when this result is there in
XS 6. So, that is your in its binary it is 1001, and that is your 9 decimal that is 1100 in
XS 3, right is it clear. And when it goes beyond 9 go, right and this addition becomes
more than you know 1111. So, the carry is produced, ok. So, that is the you know, in the
binary coded decimal cases more than 9 basically we are getting carry, right. So, if we
look at another example where carry is getting produced. So, 5 and 7, so this is 12. So, 5
is 1000 and 7 is 1010 -1000, 1010. So, if you add them up, we get 1 and 0010, ok.
So, how do we go about it? So, in this case when carry is produced. So, this is 0010 you
just fine with you know, normal kind of cases, but XS-3 we have to add 3 with it, you
have to add 3 with it. So, 0101 will be the case here and for this 1, if you are using this
for another BCD addition another XS-3 addition another - so, the digit is there. So, this
will go as a carry otherwise, if it is the end of it then we shall put a - put it in the 4-bit;
that means, which is getting added with 3 basically, so that is 1 and the 0 0 will come will come over here, that is the XS-3 version XS-3 representation of 1, that is 0100,
right. So, this is the way it is it be represented.
So, in what you see, that in one case 1 is getting added another, sorry 3 is getting added
in this case; and 3 is getting subtracted over here. So, you just need to see whether the
carry is present or not accordingly the number 3 which remains constant - that will be
either getting added or will get subtracted. So, that is - that is going to help us in addition
subtraction, adder subtractor circuit for XS-3 in comparison to BCD adder or subtractor
that that we have developed before, ok.
So, if you are looking for you know, addition of 2 - you know addition of numbers
decimal numbers with 2 digits. So, these are the, this is an example, so 25 is added with
57, so 25, 2 and 5, and 5 and 7 they are represented in XS 3. So, this is the addition
result, ok. So, in that addition result here carry one is generated, ok. So, when carry one
is generated what we have to do? For this particular XS-3 digit, of the decimal number
we have to add 3. So, that is what we will get 0101.
So, 0101 is the decimal representation of 2, ok. And when you add carry over here by
which what we see the number is 1110 and no carry is produced here no carry is
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produced here. So, no carry is produced we shall follow this. So, 3 needs to be
subtracted; if you subtract 3 from it you get 1011 and this 1011 is decimal equivalent of
8. So, final result is 82, ok.
(Refer Slide Time: 24:45)
So, XS-3 adder unit. So, XS-3 adder unit. So, the example that was discussed is over
here in the left-hand side. So, what we do? This is the basic adder 7483 and then these
are the 2 inputs, right. If carry is generated, carry is generated - what is happening? This
is another adder, ok. So, if carry is generated we shall add - this is coming as 0 this
output will be 0. So, 1 1 is getting added, ok, 1 1 is getting added and this is the carry
which might go to the next stage and if it is the end of it then you see this is 0, this is if
carry is generated this will be 1 and this is 0 and this is 0 carry is not there this is 0, ok.
And if no carry is generated, if no carry is generated - then what happens? So, this will
be 0, so this will be 1 and this is this one is permanently connected and then this is 0,
right. So, 1101, so this is 1, this is 1 0 1. So, what is this? It is the 2s complement, 2s
complement, this 1101 is 2s complement of 0011, ok. Remember that, right. So, 0011, 1s
complement is 1100 plus 1 is 2s complement which is this. So, we do not need a carry-in
over here in adder because it is already there, ok, right. And then we do 2s complement
addition, we will get the subtraction. So, this is the way we can get very simply the XS-3
adder circuit made compared to if you remember BCD, BCD addition, ok.
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(Refer Slide Time: 26:44)
Now, coming to XS-3 subtractor, one good thing about XS-3 number is that if you just
invert the number, invert the bits - then you get 9’s complement, right. You do not need
for BCD subtractor if you remember, we discussed 10s complement generator circuit or
if we had used 9s complement you know arithmetic, we would have used 9’s
complement generator circuit. Here we do not need an elaborate or you now more
complex these 9’s complement or 10’s complement generator circuit because inverting
the bits we can get the 9s complement of this, ok.
So, 9s complement subtraction we have already discussed before in an earlier class. So,
we just so the implementation here. So, say 9s complement of 2, right if you look at, so 0
1, 0 1 is in XS 3, right. 0 0 1 0 in binary XS-3 0 1 0 1, if you take 9s complement of
these 2 it is 9 minus 2 which is 7, and 7 if you just look at it , it is 1, if you 1010 in XS-3
and you just invert the bit here you get the 9’s complement, is not it. And what is the
process? If we remember for 9’s complement you know based subtraction.
Add 9’s complement of the subtrahend with the minuend. If carry, result is positive - add
carry, also add 0 0 1 1 for XS-3 because if you want XS-3 we need to add this one. If no
carry, result is negative and we have to subtract 3 for XS-3 and we can invert the bit - we
get the result, ok. So, this particular law by which you know - this shows the logic circuit
by which you can get it, right.
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So, this is showing this is showing when there is a subtraction. So, there is an inversion
getting done, ok. And this circuit is familiar the BCD these XS-3 adder circuit and here
what you can see if there is no carry if there is no carry result is negative, right and
subtraction is done and inversion of the bit. So, inversion of the bits is happening to get
you the final result, is it ok. So, compare it with other circuit we do not need as I said 10s
complement generator and other circuit. So, this is why XS-3 is useful and of course, it is
an unweighted code.
(Refer Slide Time: 29:29)
And finally, this is ASCII code where - whatever we are working in the computer or the
computer is talking to a printer and all. So, in that case the control code - control values,
control codes and alpha numeric codes the print of the characters etc these are all
generating ASCII code for communication from one place to another. And ASCII code
the full form of it is American Standard Code for Information Interchange, right and this
has been standardized for computer hardware, ok.
There was some other code which EBCDIC, extended binary coded decimal interchange
code which IBM introduced for its device, but this ASCII code is now you will see it is
prevalent and you know people are using it. And it is a 7-bit code, so 128 possible codes
are there, right and if you just look at how things get represented say one of the
character, we type say is capital A, right. So, capital A you can see the in the example.
So, these are the more significant bit bits X 6, X 5, X 4 and these are the your significant
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bits X 3, X 2, X 1 and X naught, right. So, 1 0 0 this column and this row if you see 0 0 0
1 coming from here. It is how capital A is represented.
And how small a is represented? We will see that this is small a. So, between these two,
only one value is changing, this 0 is changing to 1 and rest of the values are remaining
same. So, small a is 1 1 0 this instead of 1 0 0, this is 1 1 0, rest of the values are
remaining same that is your small a. Similarly, between capital B and small b we see that
only this place the value is changed - 6th place, right, 7 bit - this is the place it is
changing.
Now, how 0 - if you type 0, how 0 is represented? So, 0 you can see over here this is 0.
So, 0 1 1 and four 0s, 0 1 1 and four 0s, this is the one, right. How 1 is represented this is
1. So, 0 1 1, 0 - three 0s and 1, ok. So, these are the different things. So, out of this say
carriage return when we press Enter and all; so then what is the corresponding ASCII
code based on which some action is taken? So, carriage return is 0 0 0 1 1 0 1, this list is
not exhaustive, right all 128 options are not given. These are mostly - these are printable
characters that you can see, ok.
(Refer Slide Time: 32:16)
So, with this we come to the conclusion. The change of more than one digit for two
consecutive numbers in binary code will give problem in certain applications, if one digit
change is slower than the other for which, we discussed gray code and we have binary to
gray and gray to binary conversion using Ex-OR gates.
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Excess-3 code is the one where 0011 is added to the binary coded decimal and if XS-3
addition and subtraction uses simpler circuit than BCD adder or subtractor the circuit and
it involves addition or subtraction of 0011 that is 3 in both the cases. And ASCII
character, ASCII code is a 7-bit code by which control codes for peripherals and
printable characters can be generated and exchanged.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 29
Error Detection and Correction Code
Hello everybody, in today’s class we shall discuss Error Detection and Correction Code.
In the last class we saw unweighted code, and we continue with the discussion of codes
which are not weighted. And here, we shall see the code word that is generated is useful
for detecting any error in the bit position. And if possible, correction will be done for
some specific kind of coding.
So, we shall discuss Hamming distance. And while discussing it we will also shall
include discussion on parity code that we have seen before; even parity and odd parity.
And then we shall look at a specific code called Hamming code, its generation and how
it is used for 1-bit error correction and 2-bit error detection.
(Refer Slide Time: 01:12)
So, first we look at what is hamming distance. So, hamming distance is the number of bit
positions by which code words differ from one another, ok. If there is one code word and
there is another code word, we look at the bit positions where they differ. And how we
can get it? We can take bit wise Ex-OR operation of it, ok. So, whenever the bits are of
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same value; I mean code words in particular position, so if it is 1 1 or 0 0 Ex-OR gate
output will be 0, and when they differ that is 1 0 or 0 1 the output will be 1.
So, these Ex-OR - bank of Ex-OR gates, we look at its output and see how many places
it is work. So, if those ones we count then that will give us the distance between two
words, two code words, ok. So, that is what we say as hamming distance, ok.
So, to any group of binary digits and another digit this is the way we can calculate the
distance, ok. So, we have seen parity coding, so let us look at an example of even parity
coding. And there we look at two data: one is some random data we are talking about,
later we shall look at some specific data to find out some minimum distance or so, ok.
So, this has got 1 2 3 4, four 1. So, even parity we are looking at, so the parity bit that is
getting generated will be 0. Ultimately, all the bits including the parity bit will be even,
so that is the objective, right. And another data is this it has got five 1, so the parity bit is
1 after Ex-ORing, right. So, we refer to that discussion on parity code where Ex-OR
gates were used for generation and detection of parity; parity bit - parity code related
error in the transmission-reception, ok.
So, eventually we have got six 1s over here. So, if you look at bit wise Ex-ORing of this
two, so we shall see that here is 1 1 four 1s are here another one, so six 1s are there. So,
we say between these two the distance is 6, ok. So, that is how we calculate the distance
hamming distance between these two code words, ok. But for even parity code - so, if
you look at another case say where the original data is differing only in 1-bit position.
So, this is one case all 0s right. And just 1-bit is changing, so it has become 1, right. So,
what will be the corresponding code word; here all 0 so that means the parity beat will be
0. And one 1, so parity beat becomes 1 so that even number of ones is there finally
including the parity bit, right.
So, now, this is the minimum distance between to start with. Now when we do the ExORing and accumulate we see that two 1s are there. So, this is 2. So, for this kind of
parity coding where 1-bit parity code is introduced, we shall see the minimum distance is
of 2, right. So, that is what we take note of.
Now the rules is to detect b bit errors, number of you know bits if b, then the hamming
minimum hamming distance is required is b plus 1; in the code words, So, we take the
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code words generated for detecting the this error, error detection code - so, the minimum
distance required is b plus 1. So, Hamming distance for this parity coding the kind of
parity coding we have seen before is 2; minimum Hamming distance 2. So, we can
correct 1, we can detect rather 1-bit error, ok. And for correcting b bit errors what is the
minimum hamming distance required? The rules says; it is 2 b plus 1, right.
•
To detect b bit errors, minimum hamming distance, dmin = b + 1.
•
To correct b bit errors, minimum hamming distance, dmin = 2b + 1.
So, to correct even 1-bit error we need the hamming distance 2 into 1 plus 1. So, 3, right.
So, with this kind of coding we can detect 1-bit error, but we cannot correct any, right.
So, this is what we have seen in the past on a error detection code using parity;
introducing a parity bit, ok. Here we have taken the example - even parity, it will stand
good for odd parity also, right.
(Refer Slide Time: 06:20)
Now, we look at another kind of coding called Hamming code, where we shall see how
to correct a bit error as well. Not only detection is what we have seen as an example in
parity code, ok. So, Hamming code is something where we are putting not one parity bit
more than one parity bit at specific positions. So, what are those specific positions?
These are 2 to the power i-th position. So, what are the 2 to the power i-th position? So, 2
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to the power 0 is 1, 2 to the power 1 is 2, 2 to the power 2 is 4, 2 to the power 3 is 8. So,
these are meant by 2 to the power i-th position, ok
So, if we have a total code word, total code word that includes these parity bits which are
included for the coding purpose and the data which contains the information or the
message or the numeric value whatever, right. So, if we include all of them together then,
whatever code word is found the 2 to the power 0 that is 1, that is first position 2 to the
power 1 - 2, 2 to the power 2 - 4; then 2 to the power 3 - 8. So, these positions will be
filled by parity bit, ok.
And the rest of the positions will be filled by the data like 3rd position, 5th position, 6th
position, 7th position, ok. So, this is the way count will progress. So, with P 1, P 2, P P 4
these 3 parity bits we can go up to D 7; right that means, total code word will be 7 - 4
data bit and 3 parity bit will be required in this kind of coding. So, whenever we go
beyond that we have to introduce a parity bit over here P 8, so with that we can go up to
D 15. And here whenever 16 position comes, right we have to introduce a parity bit P 16
and then again D 17, D 18 will continue. So, this is the way things are done in this kind
of coding. Is it clear? Ok.
So, with this we can understand that with m parity bits, m greater than equal to 2 the
number of bits that we can code message bits or data bit is n, then 2 to the power m - 2 to
the power m need to be greater than m plus n, ok. So, that is what we can see. Here 4
parity bits are there P 1, P 2, P 4, P 8, so m is 4. So, 2 to the power 4 is 16, right 16 - it
needs to be greater than m which is 4 plus n. So, here n we can go up to data we can go
up to 11. So, 15. So, you see up to 15, because at 16 position another parity bit will
come.
If m parity bits (m ≥ 2) are used to code n data bits then, 2m > m + n
So, this is what we can see over here. Is it clear how are how we are introducing the
parity bits in the code word hamming code? Fine.
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(Refer Slide Time: 09:46)
So, you know the position of the parity bit alright, now how we generate the parity bit.
So, the values will be 0s and 1s, ok. So, what will be those 0s and 1s, of course it will
depend on the data, right. So, how it is generated? So, to generate parity bit for a system
which is called hamming 7, 4 code, that means total length is 7 and number of data is 4:
D 3, D 5, D 6, D 7 and number of parity bits are 3; P 1, P 2, and P 4, ok. So, we take this
example.
So, what we do first? Each of this position 1 to 7 we are coding in binary, right. So 1, its
binary coding is 0 0 0 1; 2 binary coding is 0 0 1 0 alright. So, this will continue 7 is 0 1
1 1. So, to generate P 1 - to generate P 1 we shall consider all the positions of the data
where in the units, in the units place there is a 1; is it fine? So, D 3, D 5, D 7 so these are
the places we have a 1 in the unit place. So, P 1 will be generated by Ex-ORing these
bits; whatever these bits whatever message you are having. So, these are the places
whatever the bits are there, we Ex-OR all of them together and then you get P 1.
So, how to get P 2? P 2 will be obtained by looking at 1s that are present in the 2’s place.
So, this is all P 2 will be generated, so it is not coming. So, D 3 right, then D 6 and D 7.
They have got 1 in the 2’s place, so D 3, D 6, D 7. You can see that. And how P 4 will be
generated? Now you can understand, you can extend the idea. So, we shall look at 1s
present in the 4th place, right. So, 4th place 1 present here in D 5, then D 6, and D 7. So,
that is what you can see. Is it ok?
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So, if you extend it if you extend it you can see for example, if you are having total code
word is - code length is 12, code word length is 12 right, and P 1, P 2, P 4, P 8; so 4
parity bits are there and then 8 data bits are there. So, if you want to code it, then the
parity bits need to be generated. So, P 1 again you look at places where there is 1 in the
units place, so P 1 you are generating. So, D 3, D 5, D 7, D 9, D 11 this is there, right.
Similarly, P 2 – similarly, P 2 we will look at places where there are 1 in 2’s right, so D
3, D 6, D 7 already there you can see that D 10, and D 11 these two - they join in P 2
generation when there are 12 bits, 12 bit code word. So, P 4 - P 4, D 5, D 6, D 7 was
already there D 5, D 6, D 7 up to this then in 4th place you can see over here the D 12
has got a 1, ok. So, D 12 will come. And finally, for P 8 in the 8’s place where there is 1.
So, P 8, D 9, D 10, D 11, and D 12, ok. Is it clear now?
P1 = D3 ⊕ D5 ⊕ D7 ⊕ D9 ⊕ D11
P2 = D3 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D11
P4 = D5 ⊕ D6 ⊕ D7 ⊕ D12
P8 = D9 ⊕ D10 ⊕ D11 ⊕ D12
Now, you can see if you put various numbers and all, so the minimum distance that you
can get over here is 3 between 2 code words. And for which it can detect as I said it was
b plus 1, so b will be 2 and can correct which was 2 b plus 1, so this is 1. So, this is what
it can do, ok. And of course, what you can understand by doing this we are actually
increasing the length of the message, right length of the data. So, actually out of which
useful data is 8; 8 is something which is unknown and P is the one that you are
introducing. So, at the other end; so 8 out of 12 will be useful in this kind of coding and
in the 7, 4 code 4 data bit out of 7 will be useful. So, this is the way one can actually
define the rate at which actually information is going from one place to another.
So, because of the introduction with the this parity bit you can see actual rate though you
are sending 7 bits, but your message conveying bit is only 4. So, rate has been reduced.
So, this is one thing that we need to take into account that when we are doing it to get
some benefit out of this kind of you know methodology there is some cost associated -
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this cost is additional bit, that need to be sent along with which will bring down effective
data rate; effective transmission rate, fine.
(Refer Slide Time: 15:36)
Now, let us look at an example, ok. So, in this case the data is 1 0 1 1 and 0 1 0 1. So,
basically 8 data bits are there. So, 4 parity bits will be required. So, data bits are placed D
3 and D 5, D 6, D 7, D 9, D 10, D 11, D 12,, right. So, this is the way they are defined.
So, this is D 3, D 5 up to this is D 12, the rest are your - you know the nomenclature how
they are designated.
So, to get P 1, so D 3, D 5, D 6, D 7, this is D 9, D 10, D 11, and this is D 12. So, D 3, D
5 D 7, D 9 D 11 this you need to take. So, D 3 is 1, D 5 is 0, D 7 is 1, D 9 is 0, and D 11
is 0, right. This is the way you look at it. Ex-ORing means we shall look at the number of
1s. So, if the number of 1s are even, the output will be 0 and if the number of 1s, total
number of 1s are odd then the output will be 1. So, number of 1s are even in this
particular Ex-ORing. So, the output here is 0. Is it clear?
Similarly, for P 2, D 3, D 6, D 7, so you can substitute all those values we can see that
this is 0. P 4 - similarly we can see here there are 3 1s. D 5, D 6, D 7, D 12 so, D 5 is 0
over here, D 6, D 7; D 6, D 7 are 1 1 - 1 1 and D 12 - D 12 is 1, ok. So, three 1s are there,
so the output is 1. And finally, P 8 you can say that this is 0, right.
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So, then the coded data will look like this 0 0 because P 1 is 0, P 2 is 0, P 4 is 1. So, P 4
is coming over here D 3 is 1, so D 3 is there. So, the ones that are in bold is the parity bit,
ok. So, this is the way the coded data will be generated and to be sent, ok.
(Refer Slide Time: 18:03)
Now let us see how the corrections - called 1-bit error correction that is possible through
this Hamming code, ok. So, if we just look at the way it is generated, so for example if
we consider that in this particular case D 7 bit is received erroneously, ok. Just for
example; actual example we shall see later. So, D 7 bit is generated, received
erroneously. So, whatever was there it has been flipped, ok. So, what we do, in the
receiver side other than what was required to generate the parity bits D 3, D 5 D 7, D 9
the 1s position with them we also Ex-OR the P 1; is it ok.
C1 = D3 ⊕ D5 ⊕ D7 ⊕ D9 ⊕ D11 ⊕ P1
C2 = D3 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D11 ⊕ P2
C4 = D5 ⊕ D6 ⊕ D7 ⊕ D12 ⊕ P4
C8 = D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ P8
So, if all these where odd if all these were odd - D 3 to D 11 then P 1 would have been 1
or I mean the number of 1s there that were odd. So, together it would have been even; is
it clear. So, if we include P 1 in the Ex-ORing process. the way you had done for you
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know single bit parity code, ok. So, inclusion of P 1 in the receiving side in the Ex-OR
operation would have made everything even the whole of it is even. So, D 7 was not
erroneous then this Ex-OR operation together with P 1 would give me 0. So, if all of
them together was 0 then P 1 would have been 0 which is the case in in a specific
example or if it was 1 it was 1. So, effectively all of them become even parity, right.
So, D 7, if not erroneous this C 1 generated will be 0. But if D 7 is erroneous it will
generate because of it has flipped, so odd number of 1 will come there, so C 1-bit will
become 1, right. D 7 let us see what else which other area where it is there. So, see D 7 is
over here again, D 7 is over here again and it is not there with C 8, right.
So, D 7 flipping will not affect C 8, right. So, if you now put them together; I mean if
you take the receiving side so what will it generate; C 8, C 4, C 2, C 1 it will generate 0 1
11 from this side to this side. And this refers to 7th 0 1 1 1 is 7, ok. So, that indicates that
7 bit is erroneously received. And if you invert it you will get the actual information,
right. So, this is how 1-bit error correction is done. So, it will be true for any other bit
position. You will see that only corresponding place over here is getting you know,
flipped or getting a 1, because of the flipping over here, ok.
So, the example that we are taking the code word, right we consider for a change not D
7; D 7 is already understood that 11th position the bit has changed, bit has flipped. So,
this 0 has become 1, right So, we shall then perform with the parity bit that is there
wherever D 11 is present, D 11 is present - D 11 is present here, right. So the D 11, D 11
is present here, and D 11 is present here. So, these were the places which was 0 before in
the generation process, now this has become 1, and parity bits got added, ok. So, it is not
there with this one - D 11 is not there.
Now if you do the Ex-ORing operation you can see 1 1 1; three 1s are there. So, output
will be 1. This is your P 2, this is your P 4 right, this is your P 1, this is P 2, this is P 4,
and this is P 8, so this is 1 this is 1. In this case, four 1s because of presence of you know
this P 4 this three 1s it finally it will become 0 and because of this three 1s are there this
is 1. So, what we get: 1 0 1 1 C 8 to C 8, C 4, C 2, C 1. So, this is what we are getting.
So, this indicates 11 in decimal. So, 11th position there is error and if you flip it in you
can get the corrected bit, ok.
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And note that the flipping can occur even in the parity bit position, because when the
message is coming you do not know because of the noise or some issue which bit
position has flipped. It is no less probability that the data bits will get you know,
corrupted, ok. So, if say, any of the parity bit is getting corrupted say; P 4 is getting
corrupted, ok. So, P 4 is getting corrupted means P 4 is there in the sorry; let us consider
that P 8 is getting corrupted. So, P 8 is there with this one only this particular case; P 8 is
not there in any other places. So, only because of it has changed - it should have been
you know, even parity whole of this thing. So, this output would have been 0. Now this
output will be showing 1 - C 8. And since P 8 is not there with anyone of them right, so
all of them will be showing 0 because they are not getting affected all those bits are in
order.
So, 1 0 0 0 is that what you will get and the final you can say that 8th position is
erroneous, ok. Is it clear? So, if it is 8th position then P 8 is erroneous; P 8 is erroneous.
(Refer Slide Time: 24:37)
Now let us look at 2-bit error detection that is possible here, ok. So, let us see how- what
does it mean. So, we consider a case where this D 7 is erroneous and D 5 is also
erroneous, ok
So, what will happen in this case: C 1 – since 2-bits have flipped. So, C 1 will be 0 only
right, if 1-bit flips then it will give a 1 when you consider the parity bit and all overall it
is even parity. Since 2-bits have been flipped, so it will be giving you 0. So, you cannot
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detect any error over there, ok. So, here D 5 is not there, so D 7. So, in this case this will
give a 1 because only 1-bit has flipped D 5, D 6 - D 5, D 7 is there in C 4. So, 2-bits have
flipped, so it will not detect any error. And C 8 does not have D 5 or D 7,so it will not
detected anything.
So, only C 2 will give you an indication that there is an error. But it is not - it cannot
correct it because it is indicating 2, ok. if only 1-bit error was there, right, there you
could have seen that it is P 2 that has been erroneous, ok. But, that is not the case here, so
more than 1-bit correction is not possible, so D 5 D 7 cannot be corrected, right.
So, similarly D 3 and D 5 if you see, so D 3, D 5 both flipped so that means this will be 0
- it cannot detect anything, so 0. And D 3 is here D 5 is not present D 5 is here D 3 is not
present, so there they will generate 11. And you are in this, C 8 is, neither of D 3 or D 5
are there, so this will be 0, ok. So, this again because of C 8 to C 1 is not all 0, so a error
is detected, error is detected, ok. So, if there are 2-bits erroneous definitely we can see
that it will be detected. So, the final C 8 to C 1 will not be all 0, right.
Now more than 2-bit flipping let us see 3 bits case. So, we take an example where D 3, D
5, D 7 they have flipped, ok; which is possible this is one random case, right. So, C 1
three have just changed. So, for which then - if 2, then one cancels the other. So, here
then it will detect an odd parity not even parity, so this will be 1, right. The other case D 3 and D 7. So, it will detect both of them is you know flipped, so no error will be
detected similarly no error will be detected. And in this case D 3, D 5, D 7 are not there,
so 0 0 0 1.
So, error is detected. So, 3 bit error is detected, ok. But we were saying that it can detect
2-bit error. So, 2-bit error detection is guaranteed, 3 bit error in this case detected - got
detected, ok. But let us see another example whether it is getting detected or not.
So, D 3, D 5 and D 6 - let us consider that these 3 bits have got corrupted, have got
flipped, ok. So, D 3, D 5 is there in C 1 generation. So, since 2-bits have got flipped, so it
will not be detecting it will be 0. D 3 D 6 is over here, 2-bits got flipped it will be 0. D 5
D 6 is over here 2-bits got got flipped it will be 0. And in this case, none of the D 3, D 5,
D 6 are there, so it will be generating 0. So, 3 bits are erroneous, but the output is 0, so it
will be seen as that no bits, no error is there in the code word, ok. So, that is why you are
saying that it can detect 2-bit, error and can correct 1-bit.
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So, this is the basic premise of error detection and error correction, and with Hamming
distance, and the relation between Hamming distance, and the number of bits it can
detect and number of bits it can correct, ok. And there are many other options available.
So, the idea here was to give you an idea or foundation and how digital circuits can be
made around it. And we have seen that this Ex-OR gates. Ex-OR relations are useful in
this.
(Refer Slide Time: 29:28)
So to conclude: we can see that the number of bit positions by which the code words
differ called is called Hamming distance and the Hamming distance is related to number
of bits it can detect as erroneous or number of bit it can correct as erroneous; I mean
erroneous bit it can correct, ok. And in Hamming code generation: 2 to the power ith
position we need to have parity. And Ex-OR operation is there for generating the parity
bit as well as looking at the receiver side. And from that we can arrive at for the
correction bit position and for detection whether there is error or not, ok.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 30
Multiplication and Division
Hello everybody, today we discuss Multiplication and Division. You may have
wondered, we were discussing addition and subtraction and we have not touched
multiplication and division. One reason is it is very complex and you need actually
repeated number of addition and subtraction. And, we were discussing combinatorial
circuit.
(Refer Slide Time: 00:42)
So, there are other ways, other approaches use using you know, sequential logic circuit
concept to arrive at this two. But let us venture into combinatorial circuit based binary
multiplication approach and similarly for binary division in this particular class. So, in
the beginning we shall look at the concept of binary multiplication, and division and then
we shall look at the a one such circuit logic circuit ok.
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(Refer Slide Time: 01:18)
So, binary multiplication if you understand, if you are multiplying similar to you know
decimal multiplication here only we are using binary digit ok. So, if you are multiplying
0 with 0. So, the result will be 0 of course, 0 with 1 it will be 0, 1 with 0 it will be 0 and
1 with 1 it will be 1.
0x0=0
0x1=0
1x0=0
1x1=1
So, if we are looking at multiplicand x and multiplayer y which are called, both are
called factor. And the result is the product then if we put them in the form of a truth table
the relationship is x and y is your m ok.
m = x.y
Now this is for 1 bit right, but if you are increasing the number of bits so here is an
example of 4 bit multiplicand multiplied with 2 bit multiplier. So, the example is taken is
of 13 and 2. So, this is 26 you know all right in from decimal multiplication. So, here
how do? You do first you multiply with 0 the way you would have done in the case of
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decimal multiplication. So, 0 multiplied with 1 1 0 1 this will be just 1 bit kind of thing
each of this is 1 bit operation.
So, this is the AND operation that you do, so it is all 0 right. Then we shift it I mean this we do not consider, this particular place and the next position we have 1 multiplied
with 1 1 0 1. So, this is 1 1 0 1 only. So, this is what we are having now. So, 0 directly
comes here as the m0 the value in the first place, units place. And, 0 1 – 1, 0 0 – 0, 1 and
0 - 1 and this is 1. If there is a carry we’ll add it - normal addition. Is it fine? And we can
see this number to be what this is 16, this is 8, 24, and this is 26 - it works. Is not it?
And if we want to look at example with carry when we are doing the multiplication. So,
basically this is 13 with 3 it is 39 right. So, 13 - 13 remains this is 1 1 - 3 we are
multiplying. So, this is your 1 1 0 1, this is your 1 1 0 1. So, this 1 directly comes here
and rest you have to do by going through the addition process. So, 0 1 – 1, 1 0 – 1, 1 1 –
0, a carry is generated here. So, this carry and this 1 - so 0 and a carry is generated here.
So, this carry is the final carry. And you can see this to be 32 and these 3 together is 7 we
know, so 39. Is it fine?
Similarly, for 4 bit you know, 4 bit into 4 bit multiplication if you are looking at then we
have got an example 1 1 0 1 with 1 0 1 1 so 13 into 11 so this is 143 in decimal. So, here
first with multiplication with 1, 1 1 0 1 comes then 1 1 0 1 it is just shifted by 1 bit so
this 1 will directly come here. Then 0 is multiplied so all 0 then finally, 1 1 0 1. Then you
do the adding and if you perform that you will see that it is coming this way this is 128
and these four 1s are 15 so 143. Is it ok? We have understood how binary multiplication
is done in reference to decimal multiplication that we are already familiar with.
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(Refer Slide Time: 05:05)
Now, if we look at the hardware or the logic circuit for realization of this multiplication.
So, first you look at 4 bit into 2 bit ok. So, in this case this is a 4 bit number, now it is
generalized. Earlier we have taken specific example. So 4 bit number could be anything
which we represent using x3 x2 x1 and x naught and this is as y 1 and y naught. So, first
we are multiplying y - x3 to x naught using y naught. So, that is AND of this here x3
with - x3 x2 x1 x naught with y naught, bit wise AND right.
So, this is represented here, this is represented here. Is it clear? Ok. And then this y 1
ANDed with x 3 to x naught so this is there right. And when you perform the addition,
these two will be added and this will directly go as m naught ok. And then this addition
will come as m1 and there may be a carry and all those things will be happening. So, if
you look at the corresponding circuit, one possible circuit - right. So, first bank of AND
gate, 2-input AND gate – right, one input of it is y naught, in every case you see is y
naught - right.
And the other input is x 3 in the first case to x naught in the last case - right. So, this is
the AND output so this AND output directly goes - this as m naught ok. And whatever is
generated, this x1 y naught x 1 y naught over here is to be added with next - it is called
partial product, ok. So, in this case - this next case you see, all of them are y1, this is y1
right and this is x3 to x naught. So, whatever is generated by this AND, right x naught y1
need to be added with x1 y naught - that is getting added, right.
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And with that whatever output is coming I mean, that is going here as m1 and the carry
will be fed to the next place - this x2 y naught, x1 y1 addition. So, x2 y naught, x1 y1
addition, so this is coming as carry from the previous stage and this output will be m2
and so on and so forth, this is the way it will go on. So, 4 bit number you know - these
bits over here is m and this is n. So, total, m plus n number of bits are possible in the
product ok. So, this we understand ok.
(Refer Slide Time: 08:00)
So, now we look at little bit more complex thing. So, this is 4 bit cross 4 bit
multiplication ok. So, that is why you see a little bit you know, the complexity of it for
which we have reserved it towards the end of the combinatorial logic circuit related
discussion. So, this is the way it has been arranged, stage by stage. So, we have seen
before it was 4 bit by 2 bit this is the bank of adder where we had ended the result.
Now 2 more bits are there 3rd bit and 4th bit for which you see another two such bank of
adders are there ok. And this will give you finally, m naught to m7 - right. And to
understand it, let us look at one example since this place is already clumsy I have taken it
to the right hand side ok, but it will not be difficult to understand and which example
shall we take. So, we shall take that 13 multiplied by 11 example ok. And we shall see
that how it works in hardware all right, in this particular adder based arrangement. So, 13
x 3 to x naught and 11 is here y 3 to y naught over here ok.
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So, the first row this x 3 to x naught so this is your 0 this is the first row adder input that
we are talking about, so this is the first row adder input. So, this 0 is there in this
particular place right and after that x 3 y 1 so x 3 y 1. So, when we multiplied - all these
things it is 1 1 0 1 - right. So, this is 1 1 0 1 that you get and the other one is other input
of the this particular adder, is x 3 x 2 x 1 x naught ANDed with y naught - y naught is 1.
So, that is also giving you 1 1 0 1 right. So, this 1 1 0 1 is a shifted version you see here
it is 0 right and here it is not getting added with anyone so this is your 1 1 0 1 right. So,
this 1 is finally, directly going here as an output right for the product generation. So,
these are the inputs of the this half adder, bank of half adder that your - bank of adder
you are having the first one is half adder, rest of full adder - is it ok. So, when you add it
up when you add it up then what you see this is 0 1 is 1, 1 0 is 1.
So, this input of the adder ok. So, this half adder - this full adder output is one of the
input of the next adder, next set of adders. So, this is the input to the next set of adders
that is going as the adder output ok. So, this is what you see in the next group. So, these
are the adder output and output from the previous stage this is the carry that you get from
the previous stage and then again you multiply it with what - y2 with x3 x2 x1 x naught;
y2 is 0 so it will be all 0.
So, that is what we see here 0 0 0 0 right. Is it fine? Then again you add it up. And that
addition result will come - this addition result is coming here, this addition result is
coming here, this addition result is coming here, this addition result is coming here. If
there is any carry it is coming - the carry is coming here right. And then again you AND
it, then multiply it with 1 with this 1 1 0 1. So, this is 1 1 0 1 then again you see the
result. So, 0 1 this is 1 0 0 1 1 0 that 1 is coming over here carry 1 1 0 and this is 1 right.
So, you collect all these ones and that is giving you your final result that is 1 triple 0 1 1
1 1 ok. So, due to paucity of time I mean, otherwise you can put them over here
individual places and see how it is happening right. So, you have just placed side by side,
but you can in a bigger picture you can put all those values and keep adding it one after
another. And you can find that you are able to arrive at this result ok. And for other set of
numbers also – fine. so you can move to division right.
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(Refer Slide Time: 13:22)
So, binary division - in this case, we are having two outputs ok; one is quotient another is
remainder. And the dividend is getting divided by the divisor all right. And if dividend is
represented by capital D divisor by small d quotient by q and remainder by r then this is
what you get ok. And how division can be implemented, it is similar to what you had
done in your decimal division. So, if you take an example like say 1 0 1 1 is getting
divided by 1 1 ok.
D=dxq+r
So, first of all this 1 0 is small all right. So, when if you multiply if you have to multiply
it with a 0 or the leading 0 does not make any sense. So, this is 0 0 if you subtract you
get 1 0 only and then you take the next bit so that is 1 0 1. So, now you can you have 1
over here - possibility is only 1 or 0 is not it so 1 means this is 1 1 ok. So, if you subtract
this is 0 this is 1 and this borrow that you have taken - so borrow was here so 1 1 it now
cancels ok. So, you get 1 0 then you take the next value. So, basically this is 1 so this is 1
0 1. So, again a 1 goes there so 1 1 right. And then again if you subtract you get 1 0 and
it stops here.
So, your quotient is 1 1 all right quotient is 1 1 and remainder is 1 0 right so 1 0 1 1 is 11.
So, what you have got is 3 and it was you are dividing with 3 you got quotient 3 and
remainder 2 it is fine 3 into 3 plus 2 that is 11 - is it ok. So, that was 4 bit getting divided
by 2 bit. So, if you have got an example with bigger - so, this is 7 bit getting divided by 4
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bit ok. So, the first case you take 1 so basically; 1 1 0 1 here so if you subtract you get 1
right; only 1 and 2 leading 0’s right. So, you bring 1 - 1 from here, but then you this
number is smaller right. So, 0 you have to take as quotient.
So, this 0, so it is - if you subtract you get only 0 1 1 only. So, you bring next 0 so you
still see that the number is smaller. So, you have another 0 over here - two 0s right. So,
then subtract - 1 1 0, then you bring 1 from here and this is 1 1 0 1. So, this is a case
where there is no remainder. So, therefore, remainder depending on the value that is
there ok. So, the original number 1 1 1 0 1 0 1 this is 117 and you are dividing with 1 1 is
0 1 that is 13 and what you have got here is 9, quotient is 9 and remainder is 0 - ok.
(Refer Slide Time: 16:46)
Now, to implement it - we shall look at again array based structure - right. And in this
array we shall use the at the cross point a unit cell. So, this unit cell here looks something
like this ok. So, we shall explain it what it is right and we shall see one example of
course, the way we had seen before. And so for that – so, this unit cell has got what you
see here input x and y and this is a full subtract, x minus y full subtraction that is there
ok.
Subtraction we have learnt using 2’s complement right, but we can have standard
subtractor, full subtractor circuit as well ok. So, for example, this is a full subtractor truth
table ok. So, this is borrow-in, this is borrow-out this is the difference and this is x from
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which y is subtracted ok. So, 0 0 this is 0; 0 1 x minus y you are talking about so 0 1. So,
difference is 1 and borrow is 1; 1 0 this is 1, no borrow is required; 1 1 this is 0 0.
So, this is 0 0, but there is a borrow from the previous stage – borrow-in. So, basically it
is 0 minus 1, that particular case. So, this is 1 1. So, this is 1 1 right. So, that is basically
0 minus 2. it becomes 1 plus 1 becomes 2. So, if you would take a borrow from the
previous stage so this is borrow right. So, borrow is 1 means 2 it becomes from the
previous stage because it is a higher place. So, the difference is 0. So, 1 1 this is the 0 0
and 1 1 1 then basically 1 and you are taking a borrow so which is becoming 3, 3 minus
this is 1 and 1 - 2. So, basically 1 borrow and 3 minus 2 is 1.
So, this is the way you can get the truth table. And if you look at now the relationship,
you will see that the difference is coming for the cases where there is only odd number of
ones here even number of ones; so, this is 0 ok. So, again here again here so basically
this is XOR between x y and b-in. And similarly, if you look at b-out, it is x prime y plus
x prime b-in plus y b-in. It is similar to carry, but in the carry generation case this was
not x prime this was c-in, carry-in ok.
d = x ⊕ y ⊕ bin
bout = x’.y + x’.bin + y.bin
So, this is the way we can get the full subtractor circuit right fine. Now this full
subtractor, there is input b-in and there is output b-out, ok. And then this out, this full
subtractor output goes to a 2 to 1 multiplexer ok. So, there is a select line 1, select line
right 2 to 1 multiplexer circuit and the relationship we already know. So, if this is 0, if
the input over here is 0 then x is passed as the unit cell output - there is the catch, there is
the nice thing about it, the full subtractor algorithm or the approach that we shall see ok.
So, if it is 0 then this one what is to be subtracted in this particular cell that only gets
passed not the subtraction result, not the - not the difference ok. And if this is 1 then the
difference gets passed, the difference gets passed. So, this is what we need to take note of
and this is the thing. And what the other output you see that whatever is being done here
same information, same select input is going to the next stage. So, there could be other
such cell which is asking for same kind of you know, select input for the multiplexer for
that particular stage. Is it clear?
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So, borrow-out, borrow-in, the number from which this number to be subtracted and
finally, the result which is number from which it is subtracted or the difference ok,
depending on the select input right. And this is the way we represent the unit cell right.
So, these are the corresponding inputs. So, borrow-in, select output, select input, or
borrow-out, this is number to be subtracted, this is subtrahend, this is minuend and this is
the output whether it is minuend or the difference ok.
(Refer Slide Time: 21:39)
So, again a bit complex circuit right, but this is doing a division of a 7 bit number by a 4
bit number ok. If you want 8 bit number to be divided by is you know, 4 bit number then
1 more stage here over here need to be - need to be added, ok. So, that is the way it has to
be seen ok. And you see that the arrangement is the way we normally divide, we divide
from the higher bits. So, d6 is here D6, D5 - D5, D4, D3, then D2, D1, D naught.
So, gradually it is making a right shift ok. So, in sequential logic based circuit
development of multiplier and you know, divider the kind of shift is required, left-right
these are all taken into consideration ok. So, this is the circuit right and now what you
can see that this borrow out that was getting generated that borrow out, its inverted form
is actually getting fed as the select input of the multiplier ok. So, in the final stage if a
carry is generated carry is generated. So, this is 1 so this is then will become 0 ok. So,
when carry is generated then if you go back.
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If it is 0 then the number from which it is you know subtracted, the minuend will come
here and otherwise the difference will come, is it ok. So, this is what is the case. And this
inverted part of the carry is what is going to give you the quotient and this is what is
going to give you the remainder. So, this is the remainder will come ok. So, this is the
algorithm which has been arrived at and given a, given a shape through a unit cell base
array divider circuit ok. (Note that in this paragraph there reference to carry actually
means borrow for a subtractor circuit.)
So, now, we can to appreciate it let us quickly go through an example. So, the example
you take is the same one that we had taken before that is 117 divided by 13 all right. So,
this is the dividend and this is the divisor ok. So, dividend then these bits D6 to D
naught, these are there. So, first we shall take up D6 D5 D4 D3. So, this is 1 1 1 0 so this
is D6 D5 D4 and D3 - that is in blue ok. And divisor is 1 1 0 1. So, this is divisor the that
is in brown is it ok.
Then what you are doing. We are doing the subtraction and in each of the subtraction, we
are looking at the borrow. So, 0, 1 is subtracted from 0 so this is 1 right. So, this borrow
is coming over here 1 1, 0 right 1 1, 0 again 1 1, 0. So, final carry (borrow) is 0 right. So,
its inverted is 1 so that is your q3 ok. So, this is 1 right and this is the borrow-out the
final that is getting generated that you can see. So, when q3 is there so the difference
result will be going to the next level of subtractor - this thing, group ok.
So, that is what you can see here so this is your 1 1 this is 0 is coming here this
subtraction is 0, this subtraction is 0 all right. In this case the subtraction result was- 0 to
subtraction of 1 - so 1 is coming here ok. So, these are the bits that you get for the
minuend. And for the subtrahend, first place it is 0 so that is the 0 over here and next is
your d3 d2 d1 d naught so 1 1 0 1 and for this particular subtractor over here.
So, D2 gets introduced. D6 to D3 were there so D2 getx - is getting introduced here. So,
this is in blue. So, D2 is – 1 1 1 0 then it is 1. So, this 1 is coming over here. Is it fine?
So, next you do what? Next you do again subtraction of this particular set - right. So, this
is your - you are here. So, 1 1 – 0, 0 to 1 this is 1, 0 minus 1 is 1 borrow is 1, 1 1 0 this is
2 right. So, there is a this is 0 so this is again 1. So, this is 0 minus 1 is 1 and then there is
a borrow-out which is 1 ok. So, this is - there is a barrow-out. So, then its inverse is 0.
So, this is your quotient q2 ok.
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So, this inverse is now going to the multiplexer input - all these multiplexer inputs. So,
when it is 0 then the mineuend, not the difference, will come to the next level of full
subtractor ok. So, here this result 0 will not come so this 0 will come over here ok. So,
this 0 will come over here this 1 will come over here and this 1 will come over here not
the difference result ok. That is what we have seen - the operation of the multiplexer.
So, for now this particular subtractor we are having 0 introduced for as D1 and what is to
be subtracted is again this 1 1 0 1 in the brown and for this particular place it is 0 only
right fine. So, then again we perform the subtraction and see. So, 0 to 1 we have a
borrow of 1. So, 1 1 it is 0, 1 1 it is 0, 1 to 0 this is 1 right. Then 1 to - 1 to 0 this is again
1 and then there is a borrow-out ok. So, again there is a borrow 1 that is present so its
inverse is 0. So, you get q1 also and then again this is 0.
So, what we will see the minuend coming to the next level of subtractors ok, not the
difference result. So, that is what is coming over here right 0, this is 1, this is 1, this is 0
and this is 1 is coming as the D naught bit. So, you have got 1 1 0 1 over here is 0. So, to
be subtracted this d3 to d naught so this is 1 1 0 1 ok. Now, if you subtract right you see
that this is 0 0 0 all of them are 0 and the borrow is 0. So, it is inverted is 1 and had there
been some number present that would have been the remainder.
So, remainder here is 0 all 0 all I mean, r3 r2 r1 and r naught ok. These are 0 0 0 0 right
and your q3 q2 q1 q naught. So, this is your q3 and this is q naught you take all the
borrows right so 1 0 0 1 ok. So, this is the way it is done you can try with some other
number also right. And wherever you have seen that only 0 is getting added or the first
stage, instead of full-subtractor we can have half-subtractor right we have not discussed
that logic truth table or the circuit, but we can similarly get it, fine.
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(Refer Slide Time: 30:43)
So, with this we come to the conclusion of this particular class.
(Refer Slide Time: 30:45)
So, product from binary multiplication of two 1 bit number is obtained from logical
AND operation of the numbers. And for getting more than 1 bit numbers - the
multiplication result, we can get by adding the partial products after appropriate shift.
And the combinatorial circuit to get multiplier performs that shift within the arrangement
ok. And binary division will generate quotient and remainder and it involves subtraction
of divisor after again appropriate shift.
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So, the combinatorial circuit for that using cell array performs that shift within the
arrangement. And as we discussed that; it can be done by sequential logic circuit by
some other arrangement which in certain sense can be considered efficient in certain
context, more of that we shall take up later.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 31
SR Latch and Introduction to Clocked Flip-Flop
Hello everybody. We are now in week 7 of this particular course. We shall begin
Sequential Logic Circuit from today’s class.
(Refer Slide Time: 00:25)
And we shall have a quick recap of week 6, I believe it was little bit heavy. Because that
was the last week of the combinatorial circuit discussion, so lot of advanced things were
there. I hope you could assimilate them. But as we have done in case of combinatorial
circuit - we made a soft start with introduction of basic gates and all. Then we moved on
to build more complex circuits. So, similarly we shall start softly with basic components
of this sequential logic circuit by which we shall make more complex circuit in the a
later classes, ok.
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(Refer Slide Time: 01:10)
So, we discussed a magnitude comparison of two numbers, and how outputs like X
greater than Y, X is equal to Y, X less than Y was generated - were generated. And in
that case we had two kinds of approach: one is of course by subtraction and another is by
comparing the more significant bits of two numbers successively, ok. And then we
discussed arithmetic logic unit, and we saw that one device which is versatile in nature depending on the selection unit it does perform one of the many different arithmetic or
logic function. And we saw that how all these devices can be cascaded and more number
of bits can be handled together.
Then we discussed unweighted codes, ok. And then we saw that how gray code was
advantageous where two consecutive numbers change by only 1-bit position. And we
also discussed the excess-3 code, where we saw that the BCD arithmetic, the way you
had conducted before - that can be made simpler by excess-3. And then we looked at
error correction and error detection codes, and in that context we defined Hamming
distance. And we saw that minimum Hamming distance in a particular coding paradigm;
how that can be useful in deciding or in understanding how many bits can be corrected or
how many (error) bits can be detected, ok.
So, in that context we discussed a parity code, standard parity code - even parity, odd
parity code which we discussed in one of the earlier weeks. And also we discussed a new
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code - Hamming code which can detect 2 error and correct 1 error, correct 1 error in bit
position, ok.
So, this is was in brief what we discussed in the - and of course yes, we discussed
multiplication and division, right. And we saw bit you know, seemingly complex circuit,
but we had examples by which we could appreciate how the processing was done
through the array based structures, in the unit cells, and finally the results were obtained,
ok. So, each of the cases we have defined the unit cell properly and looked at the solution
by taking specific examples.
(Refer Slide Time: 03:46)
So, with this we start this week’s discussion as I said, we shall start with defining basic
units of sequential logic circuit which is memory element also called flip-flop. But
before that we shall see what is a bistable circuit.
So, bistable circuit is something where the circuit is stable in one of the two positions; bi
stands for 2, right. So, both the positions are stable, right. So, if you look at this you
know, a switch where you are applying a specific force by hand and all, and then you are
connecting the switch to this particular place. Then you remove that hand pressure or you
know this whatever force, external force the switch will remain in that position.
But if you again put a force and bring it here again it will remain there if you do not
force it to go to another position. So, each of these states is stable, ok. So, in bistable
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circuit, we can store 1-bit of information. That that is whether this output is high, Vcc or
output is 0, right. So, together you can store in the context of binary representation of
information, 1-bit information - we can store in the bistable circuit.
Now moving over to digital circuits. So, let us see if we have 2 inverters connected one
after another right, and we place a 0 volt here what will happen to it - to the inverter
outputs in these cases. The first will be this 0 volt to the 5 volt, right. So, logic 0 will
become logic over here and again it gets inverted it is logic 0, ok. This is understood.
Now while this ground is here you connect a feedback. So, this feedback is key; this
feedback is very important in developing the basic cell and the sequential logic circuit,
right. In the combinatorial circuit we did not discuss, we did not include feedback. So,
the feedback comes in the sequential logic circuit discussion.
So, you connect the feedback the way you have seen from output to the input; why, there
is no issue no ambiguity because this is 0 volt and this is also 0 volt. So, this is logic 0,
this is also logic 0, this is logic 1. Now if you remove this ground like this circuit
becomes like this. What will happen to the circuit? It will remain at this 0 volt, this 0 volt
here is driving this one, and this 0 volt is driving this 5 volt 5 volt this 0 volt. So, it will
remain in that place like you know, as a stable formation right, this output will be 0 volt.
Now instead of this ground if you had started with a 5 volt here, then a feedback, ok.
And then you remove that you know, 5 volt; how would have been the output in this
case? Output would have been stable 5 volt, ok.
So, this is what we can see a bistable circuit in the context of digital logic representation,
right. But what we find here that this way of you know, applying external you know, this
ground or 5 volt - this is a bit inconvenient. So, you would look for something which is
more convenient to trigger from one particular state to another.
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(Refer Slide Time: 07:29)
So towards that, let us look at this circuit where we are having instead of NOT gate we
are having two NOR gates, ok. So, you can see the feedback happening here. And we
can write, we can draw the same diagram in a different manner which is you know,
cross-coupled, ok. But there is one feedback you remember and one is in the forward
path, but this is the way you can draw it, ok. And we give these inputs some name S and
R and more about that will be clear very soon, ok. And this is Q and we shall see that it
happens to be the cases, where we are operating it the way we operate it, this V3 will be
inverse of V2. So, this is 0 volt, it will be 5 volt and vice versa.
So, that way we can write it to be Q bar, ok. But we shall you know, see more of it in the
subsequent discussion, right. So, consider that both of them are 0 0 at a given time, ok.
So, for a NOR gate 0 is a non-forcing input ok. For OR and NOR, 1 is the forcing input.
For OR gate if 1 is there output will be 1 irrespective of what is there in the other input.
And for NOR gate if 1 is there output will be 0 irrespective of what is there in the other
input. Isn’t it? So, these are forcing inputs, right. So, 0 0 is non-forcing input. So, it will
look at what are the other inputs by which the output will be decided.
So, if to start with you consider that this was 0, right. So, then this 0 0 this is 1 right and
this 1, right is making it 0. So, this 0 and 1 if the previous value was 0, right then it will
be 1. And from the symmetry you can say if this was 1 this would, this would have been
0. So, if you look at this truth table this is what you can see; that 0 0 then 0 0 and 1 1. So,
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whatever had made the previous value 0 or 1 that will be continued with when this two
are 0. So, the prior value of Q it is latched into, ok. This prior value of Q is latched into,
is it ok. So, this is what we see with 0 0 present.
Now let us see if you present a 0 here and a 1 here, ok. So, 1 is a forcing input
irrespective of what were the past values or so, because this is coming from external. So,
this is - this will make it 0 right, and this 0 0 we will make it 1 even if the previous value
was 0 and 1, whatever. So, ultimately this 1 forces it to be 0. So, when this is 0 1 right, S
is 0 and R is 1, irrespective of what is the previous value the output is always 0, right.
And similarly again from symmetry this is 1 and this is 0 this is the case, right. This 1
will force it to be 0, this 0 0 this is 1. So, output will be 1, right Q will be 1. So, this is
what you can see, is it all right.
So if it was set, this now stands for - S stands for set and R stands for reset. So, when S is
1 and R is 0 we say this particular latch this is basically - it is called latch because it is
latching whenever we are putting a 0 0 value. So, whatever the past value which made
the Q 0 or 1 because of 0 1 or 1 1, 1 0 that was present, it latches on to the past state;
you know, the past value - past state. So, that is why it is called latch. So, this S stands
for set and a R stands reset. So, 1 0 is a setting of the latch and a 1 0 of S and R. And 0 1
of S and R is resetting of the latch, ok. Is it fine?
Now what would happen if 1 1 was presented here? So, the output would have been 0 0
which is fine, I mean as such that is nothing, no ambiguity about it. But after 1 1 if you
try to put into that resting state when the past value would be latched on to - so, after that
if you put 0 0 then what happens actually, that this 0 and this is external 0, so both are
now non-forcing, right. And this 0 is over here. Now depends I mean, which one of them
gets the 1 before the other. Ideally one can say that both of them will get 1 you know,
together. So, that 1 will go to the feedback to the respective cases. So, both 1 will
become 0, ok.
So, that is the ideal case (but actually) where the propagation delays are identical - but
whatever be the fabrication process or so we will see that one of them - which is not, for
sure because of the way it gets fabricated, different transistors and other things are there
in the circuit element, passive element so, one of them will be having a higher you know,
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propagation delay than the other. So, that will respond slower which we cannot say as a
designer which one is you know, going to acquire the 1 value before the other, right.
So, that is something which becomes a bit you know unpredictable. And a race between
these two - who wins and that is something which we would like to avoid in a SR latch
use or application, ok. So, that is why this 1 1, we are saying as not allowed, clear.
(Refer Slide Time: 13:50)
So, how do we again look into you know, the representation part. So, we will not write
all those you know basic gates that we have used, instead we can prefer to put it in the
form of a symbol which will help us in making bigger circuits, ok. Otherwise this circuit
will become a bit you know clumsy - too many you know, logic gates and all.
So, when we say SR latch, so this is the way we can put it. And if you look at the
textbook, two different symbols have been used. In one case Q and Q bar are output –
inside. In both the cases, we will see SR is there, ok. And that means, this is Q and this is
the invert of it that is what we have seen in the cases; the allowable cases, right. And, in
another representation Q bar - Q and Q bar taken - kept outside, but now there is an
inverter, a bubble that is a NOT operation; that opposite operation that is being shown
here. So that means, whatever is the value here it is opposite here, ok. So, these are the
two conventions we will find in the textbook.
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So, now we can, whatever truth table we had seen before, now we can put it in a more
compact form since we are trying to come up with a compact representation. So, 0 0, so
previous value is retained, previous state is retained; 0 1 of S and R output is 0; 1 0
output is 1 - state becomes 1 and 1 1 is not allowed. So, we had seen the way the NOR
latch works. So, have we - if we had connected you know NAND gates in the same
manner right, so what would have been the corresponding you know, truth table, ok.
So, in the NAND latch if you look at it. So, NAND - for AND and NAND what is the
forcing input, 0 is the forcing input, ok. So, if AND gate - 0 is there then irrespective of
the other input, the output will always be 0. And for NAND gate if 0 is there output will
be 1 irrespectively of the other input,. So, in this case if you just look at this first, this
particular block, so we will see that if this we are giving it a name S bar and R bar
because that is the way we see - we shall see that relationship with this particular table;
the previous NOR latch.
So, if both of them are 0 0 right, so the output will be become 1 1, right. And if both of
them are 1 1, then it is non-enforcing input. So, it depends on the previous value. So, if
the previous value was say 0 and this was 1. So, 0 and 1 this will be 1 and 1 1 it will be
0. So, previous value will be retained. And previous value was 1 and 0. So, this will go to
1 and 0 - 1 1 it will become this 0 it will go to 0 and this will become 1, and 1 will come
over here and 1 1 it will become 0 ok; the other case, right. You can see it from
symmetry also, right.
So, this 1 1 is your previous state, right. Similarly you can see 1 0 will be output will be
0, 0 1 will be 1, and 0 0 is 1 1 because is forbidden because after that if 1 1 follows its
output becomes unpredictable and depends on the race between this gate and this gate,
ok.
Now if we are looking for a SR latch made out of this and we want a truth table like this
so what we need to do; we need to put a NOT gate before it, isn’t it. So, a NOT gate
before it and this NOT gate you can get by a NAND gate also, by joining the 2 inputs,
right. So, this S bar becomes S here and R bar becomes R here. So, you can use IC 7400
which has got you know which is quad 2-input NAND gate to realise this one, fine.
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(Refer Slide Time: 18:16)
So, this is one IC where within it, the SR latch is already made, ok. So, this particular IC
if you see there are 4 such latch one - IC 74279 - 2, 3, and 4. So, 1 and 2 - is normal SR
latch, ok. Since it is made of NAND, so you can appreciate that the input will be S 1 bar
it is given a name S 1 and R bar, ok. And in the other case you have got 2 inputs, S 1 bar
and S 2 bar. So, this is a 3 input NAND gate and this is R bar. So, for the other gate we
have got only one input. And for that we shall have a truth table something like this;
how, ok.
So, you can see that if this particular case all of them are 0 this is forbidden, because then
the output will become 1, right. And then if S 1 is 0 then this output is 1; this output is 1,
right irrespective of S 2 is 0 or not because one of the forcing input has become 0 for
NAND gate. And at that time if R bar is 1. So, this R bar is 1 right, just by considering
the way we had considered it before we can see that this is 1 this R bar is 1, so 1 1 it is 0
and 0 is fed back here - it is 1. So, the output is 1.
Similarly, from symmetry, if S 2 was 0 at irrespective of S 1 the output will be 1. And
when both of them are 1, right; that means, this is non-enforcing and R bar is 0, then the
output becomes 0, right. And when all of them are 1 the output is in the last state, ok. So,
this is what we can see for IC 74279, where the latch is already there inside the IC we do
not need external connection using NAND gates.
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(Refer Slide Time: 20:36)
Now, one application of, there will be many applications, we shall see later and complex
sequential logic circuit will be made. So right now, we can see one application where a
debounce switch can be made using SR latch, ok.
So, what do we mean by debounce switch? So, when we are basically connecting a
mechanical switch which is kind of you know having a spring load kind of thing. So,
whenever it is getting connected here, right. So it will make a connection-disconnection,
connection-disconnection, connection and then it will settle, so there will be a small
vibration, right. And when it disengages from here, this is the output that we are talking
about here when it disengages when it is connecting here it is making a oscillation, but it
is connected to 0, so it does not make any difference here. So, only when it is getting
connected at this place, getting closed, at that time there is a small vibration because of
the you know, spring action that is there.
So, you will see you will see that whenever it is getting closed for example here, so there
is a small vibration taking place. High-low, high-low it is getting disengaged getting
engaged, right. When it is getting open and connecting to this place, so it is a immediate
so there is no such issue again it is getting here. So, while ideal case we want this, but
actually this is what is happening, clear. So, this ringing can create issues, because it
might say that number of you know 0s 1s you know, come into the picture which might
create difficulty. So, it can trigger many events when, actually one event has taken place
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one such closure has taken place, it may count that 1 2 3 such closures have taken place.
And each closure might you know, can get counted and lead to certain action going
forward, ok.
So, that is something which may be needed to be I mean, avoided in certain application.
So, for that we can use SR latch, right. So, in the SR latch the switch is - one is S and
another is R, right. So, when it is disengaging from R and connecting to S, so there is a
ringing over there, ok. So, whenever that is happening, so 1 and 0 the output is becoming
one because it is getting set after that when it is getting, S because of the ringing, so it is
becoming 0. So, this is a 0. So, previous state is retained, ok.
So, there is no issue with that, is it clear. Similarly when it is coming to when it is getting
disengaged from S and coming to R right, it is getting disengaged no issue, but when it is
connecting to R there is a small vibration. So, R is becoming 1 0 1 0 for sometime. So,
whenever R becomes 1 for the first place and this is 0 right, so it will get reset; so it has
got reset. After that during ringing this is - this remains 0 and this is 0. So, 0 0 means
previous state is retained, ok.
So, if you now take output from here, there will be no effect of bounce. So, effectively
we have got a debounce switch.
(Refer Slide Time: 24:04)
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Now, we move little bit further, ok. We look at further use of latch, the basic latch by
introducing an enable input, ok.
So, this is the basic SR latch which could be made up of NOR or NAND, as the case
might be, ok. So, that is - that part we shall see more you know, elaborate circuit later.
So, what we are doing here that we are putting, we are making SR go there through two
AND gates like this, which has got an enable input. So, when enable is 0 so these two
outputs are 0. So that means previous state is retained, ok. So, this is the case - no
change. And when enable is 1, when enable is 1 and that time depending on whatever we
is this SR value this 1 1 is forbidden of course, the normal action takes place; is it clear.
So, we are not allowing the SR input to affect the final output at any time - at all the
time. We are only allowing it when it is enabled, ok. It is like strobe or you know, the
kind of thing that we had used before; for multiplexer, demultiplexer those circuits if you
remember, ok. So, the circuit, this circuit is acting only when or made to work only when
enable is at 1, ok.
(Refer Slide Time: 25:55)
So, what is its implication? So, if will look at a timing diagram, right. So, you can see
that when enable is at 0 like this place, this place, this place, this place, right whatever
changes are there it does not actually I mean, the Q will remain at that value in those
cases. So, t1 - t2 is the window in which any change can be accommodated. So, S was 1
and R was 0, and the Q was 0, so that makes I mean, if enable was not there whenever
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this S and R; S was 1 and R was 0 - the Q would have been 1. But the enable comes over
here only here at this point at t1. So, at that time only Q will go to 1, right.
Now t1 to t2 there is no change in S and R. So, Q remains at 1 at t2, at this point t2 after
that enable is 0. So, after that R becomes 1 and S becomes 0 at some point of time over
here. But that effect does not get reflected in the output Q – why? Because enable is at
low, right. So, again it gets trigger; again it gets the enable signal over here at t3. At that
time, it sees - it finds what is the value of S and R at that time. So, S is 0 and R is 1. So,
that time it will go to - it will become reset. So, in between before the enable was there if
S and R had changed their value, it would not be captured by the final output, right. So,
only when the enable is there whatever is the value of S and R that gets transmitted and
reflected in the final output. So, this is the idea, ok.
So, whenever we want the SR flip-flop to work we put the enable, otherwise we allow
the S and R input to settle if there is any transient and all. We do not want the final
output gets you know, changed before S and R are you know, properly settled. So, enable
is giving that you know option - period for the inputs to get settled.
(Refer Slide Time: 28:28)
And this gives rise to what we end with today’s discussion - is called clocked SR flipflop, ok. So, the sequential circuit that we shall discuss it is called - it will be actually
synchronous sequential circuits. So, most of the sequential circuit are synchronous
sequential circuit, where the state change takes place synchronous with an external clock,
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ok. So, this external clock actually totally decides how the these different the sequential
operation of the different kind of elements inside the circuit, ok.
So, this particular clock would have you know a waveform something like this right, so it
goes high and low and all. So, this is one clock cycle, right and in each clock cycle you
are looking for one state change if it is so desired by the input to that particular bistable
circuit. In this case, this particular SR latch that we have discussed, ok.
And usually latch with a clock is called a flip-flop, ok. But then you will see that in the
text it is says latched SR flip-flop. So, basically latch type is SR flip-flop. So, basically
they are referring to latch SR flip-flop, but in other text, generally speaking, presence of
clock - flip-flop means a presence of a clock, and latch means it is just the last stage of
where the memory part is there, where the value is latched into, ok. So, that is the way
distinction is often made in this particular field,.
So, then how this clocked SR flip-flop would look like. So, in place of now enable we
are putting the clock, ok. So, whenever the clock is high, right. So, the input, change in
the input can be this S and R can be reflected in the output, ok. So, in this case for SR
flip-flop, this is a SR latch right, and this is the AND gate and this was enable as before.
So, we have put the clock over there, right. And for NAND based circuit we remember
that this was a NOT gate, right one 2-input NAND gate were put together to get S and R
otherwise this was S bar and R bar, right.
So, we can now use the other input of the NAND gate to put the clock, ok. And we can
see the clock is 0 this output will be 1 1, these are the forcing input for the NAND gate.
So, 1 1 means, right a for a NAND gate 1 1 means previous state will be retained
because that this is non-enforcing input for the NAND gate. And only when it is 1, so
this is now non-enforcing. So, based on S and R the value will be transmitted here and
accordingly the final value will be arrived at, ok.
So, this is the basic SR clocked flip-flop circuit. And the symbol for this is this - the one
that you see here. And this is also called level triggered flip-flop, because we’ll see edge
triggered flip-flop in the next class. So, level triggered flip flip-flop means whenever
clock is at a particular level. So, that time it is allowed to trigger, allowed to change the
state, ok. And if we had put an inverter over here, a NOT gate over there, then the
change would have been in this stages of the clock when the clock is low; isn’t it. So, at
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that time would have said that, if this is positive level triggered high level triggered, so
that would have been negative or low level triggered, and at the time there would have
been a bubble sign over here, ok. That is a difference. Is it clear?.
(Refer Slide Time: 32:45)
So, with this we conclude today’s class. A bistable circuit has two stable states. To
summarize - its value changes only by external trigger. SR latch - 0 0 is the input when
the previous state is latched into, 1 1 is not allowed. And we can get bounce-free switch
out of ordinary switches using SR latch. And in gated SR latch or clocked SR latch there
is additional input which enables SR input to go - pass through, make changes in the
final output. And in synchronous sequential circuit this clock is very important and one
state change we are looking in every clock cycle, synchronized with the clock, ok.
Thank you.
467
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture - 32
Edge - Triggered Flip – Flop
Hello everybody, in today’s class we shall discuss Edge-Triggered Flip Flop. In the last
class we introduced ourselves to sequential logic circuit, the fundamental -primary
elements of it. We discussed SR latch and clocked SR latch.
(Refer Slide Time: 00:32)
And we found that how a level triggered SR flip flop is made ok.
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(Refer Slide Time: 00:41)
Now, why we require an edge triggered flip flop ok. We require it because when it is
level triggered during when the clock level, the clock output is high, the output can
change. And if there is any feedback from output to input or some input is changing I
mean, there is some transients and other things that is coming into the picture from
different other parts of the circuit. So, that might cause more than one change in the state
during the period the clock remains enabled. Is it clear?
So, instead of one state change we can have more than one state change taking place.
And that is not desired and that might put the different you know, calculation out of gear
in the design process or in the implementation process. So, we need to ensure that only
one state change takes place and that takes place synchronous with the clock and for that
we are looking for something called edge triggering.
So, edge occurs only for very short period I mean, when the clock is changing. So, either
positive edge triggered or negative edge triggered if that is the way it works then we can
ensure that only one state change will take place per clock cycle. Is not it? So, to do that,
people have thought about various means, we shall discuss them. So, one thing that
immediately comes to mind is to make the clock pulse width, during which it remains
enabled, very narrow ok - so narrow that it is of the order of the propagation delay and
by which the feedback or some changes that is coming from other part of the circuit
because of clocking in that particular cycle - so, by that time it comes it has become
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disabled. The clock pulse high has become low if it is a positive, high level triggered flip
flop ok. This is the idea that effect of this clock - clocking right that will be not getting
reflected back in this particular cycle itself that is the idea. So, for that people have
thought about - the clock is the normal clock here and a pulse forming a circuit ok. And
this is giving a positive you know, this edge triggering ok.
So, this pulse forming circuit - so one way of getting it, something like this we had seen
in the discussion related to hazard before, if you remember ok. So, this is effectively a
NOT gate. So, the clock is going high here from say low to high at that time. So, this
NOT gate output after the propagation delay, it will go from high to low right. And when
you AND these two, then for a short period after this propagation delay right you can see
a small positive going pulse.
So, this clock will be available only for this circuit ok. So, because directly getting a
clock with a very narrow pulse is difficult, I mean, getting very stable clock. So, a pulse
forming circuit like this ensure a small a narrow pulse width ok. Similarly if you want a
negative going you know, negative going edge a negative a pulse, a small pulse width narrow pulse width for negative triggering ok. So, if it is low level triggered basic circuit,
basic flip flop ok.
Then at that time you can have NOT and OR combination ok. And you can see that we
can get a narrow pulse width which is negative going ok. So, for this particular circuit
though the basic part of the circuit is level triggered, but effectively you are getting a
edge triggering; this is not actual edge triggering, but effectively it is edge triggering ok.
So, this we can consider and go ahead this ensures one this thing.
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(Refer Slide Time: 05:35)
So, again what we shall see, what we shall try to do is to again make a compact
representation and by which for edge triggered circuit - the edge triggered SR flip flop
we shall have a representation like this, where this you can see this triangle like shape
here that indicates that it is an edge triggered ok. So, absence of any bubble here inverter
means it is positive edge triggered and presence of a bubble like this, that is a inverter ok.
So that means it is a negative edge triggered - is it clear?
And for the truth table, we can indicate this by putting this arrow mark going upward that
it is positive edge triggered and when this edge comes so, 0 0 the now we are indicating
that only one state change is taking place per clock cycle it is we are ensuring. So, then
the previous value is written; 0 1 it is 0; 1 0 it is 1, and 1 1 as was discussed before it is
forbidden and so the corresponding timing diagram ok. So, the way we had seen before,
now we can see that whenever - in the earlier case, if there were when it is high more
changes in S and R occurs, I mean then it would have been reflected.
But here it will not be reflected, only in these edges, these positive going edges in edge
triggered flip flop, the circuit’s state is allowed to change ok. So, at that time it will see
what is the value of S and R. So, here it was allowed to change Q as 0. So, that time S
and R are 0 so no change ok. So, here again it is at T 1 it is allowed to change at that time
it finds that S is equal to 1 and R is equal to 0 ok. So, then the output becomes 1. So,
after that here the clock is high this has become 0 this has become 1 you can see that
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thing if I draw the diagram. But no change in the output has taken place. Had it been
level triggered, immediately there would been a change.
So, that is not what is happening and it will happen again I mean, it will depend only
again in the this edge whenever it comes and depending on the value of S and R at that
time - so S is equal to 0 and R is equal to 1 ok. So, it gets reset it becomes value become
a 0. So, this is the way it progresses this is a difference between edge triggered and level
triggered flip flop and their timing diagram.
(Refer Slide Time: 08:34)
So, now we look at other varieties of flip flop that is used in the sequential logic design.
So, one is called D flip flop. So, what is - how D flip flop is designed, how does it look
like? So, the D flip flop - we know this is basic the SR flip flop part of it. So, this was S
input and this was R input and this is the clock that is already known to us. So, you put
an inverter between S and R by which these - there becomes only one input to it because
S and R are connected in this manner ok.
So, this is a single input of course, the clock trigger is there I mean, other than that clock;
and the Q is the output and Q bar of course, a complementary output is there. So, this is
the way the flip flop is arranged ok. So, for D flip flop, whenever the clock is you know,
0 or 1, I mean, no edge has come - this is normal say 0 or 1 ok - so, irrespective of the
value, previous value will be retained. So, whenever it is 0, so S is 0; inverter here - so, R
is 1 and edge comes, what will happen? It will get reset.
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So, if there is a 0, 0 will be there in the output and instead of these, if this was 1 then this
is, S is 1 and this will be 0 because of the inverter right. So, the output will be, when the
edge comes, output will be 1. So, whatever is the input that gets transferred to the output
and remains stored there, remains stored there ok. And this is how the D flip flop works
and more of it, its application - we shall see later.
Now you will see that all these circuits when we employ in complex sequential logic you
know, implementation - we need in certain cases clearing the circuit or presetting the
circuit, clearing the state or presetting the state, at a given time. One important
requirement is during initialisation ok. So, you have connected many flip flops and you
have made a complex circuit out of it. So, how would you start, from which state do you
start? Usually you may want to start it from say 0 0 0 or say 1 1 1 whatever it is or it
could be from 0 1 0 something which you know, is predefined ok. So, in that case we
need something by which it can be initialised in that manner ok or some state can be
introduced without the application of the clock.
So, that is called asynchronous presetting or asynchronous clearing, So, for that what we
can do? So, this is the clock part of the circuit right. So, we can just put another such OR
gate right and whenever we put preset is equal to 1 and a clear is equal to 0. So, this is 1
and this is 0 which will make irrespective of the clock. Now clocking is not required that
is why it is asynchronous whenever it is made like this then this is your, this will be set
to 1 and this will be 0 and only when both of them are 0 this OR gate will be acting on
this input - when both of them are 0 right this is a non-forcing input for the OR gate.
So, whatever is coming from here - this AND gate and this AND gate through clocking
and whatever is present in the D flip flop, so that will be deciding what is the output. So,
similarly for clearing will make it 1 - this is 1 and this is 0. So, that will make it 0 and
this will become 1 right, this is clear. So, this is shown for a D flip flop and then in the
case of symbol again, to make a compact representation – we’ll be putting here pr and
clear that is preset and clear.
So, it was this because it is active high preset, active high clear. So, if active low then we
would have put a bubble here and the put a bubble here. So, instead of you know this
high if there was a NOT gate put before this. Then we would have put a bubble over here
- is it clear. So, this has been shown for D flip flop it could be for SR flip flop also it
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could be possible for any flip flop this kind of you know, asynchronous preset clear can
be designed.
(Refer Slide Time: 13:44)
Now, we come to another type of flip flop which is called JK flip flop. So, JK - SR was
set reset there were two inputs. So, JK flip flop you can see that two inputs are there. So,
this JK flip flop, if you see how the connection is made. So, this is the normal SR flip
flop these SR latch and the SR flip flop with clock, so this third input was not there ok.
So, without this it is the standard SR flip flop please understand this part.
So, this feedback - eliminate this a feedback then this is your S and this is your R. Isn’t
it? It is standard SR flip flop. So, what has been done to get the JK flip flop is Q is
connected to this R and we are giving a different name of the input, K to distinguish - to
differentiate it from SR flip flop. And Q bar is coming to where the S was there as a third
input to the AND gate ok. And we are giving the name J - is it fine. So, this is how the
JK flip flop is made right.
So, how the truth table now becomes different from the truth table we had for SR flip
flop ok. So, if we investigate, we see that whenever J and K are 0 and 0 this is AND gate
0 is the forcing input. So, this input will be 0 and 0 irrespective of what is fedback or
whatever you know, the other things I mean, whenever the clock - appropriate clocking
is there alright. So, what does it mean? The last value will be there, clear, first part right.
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Then if this is 0 and this is 1 again 0 is a forcing input. So, this will be 0 right and this
input, this input if Q was 0 and this is 1 please understand this part; if Q was 0, 0 will be
feedback here. So, this will be 0. So, 0 0 means previous value will be retained. So, if 0
was there it will remain at 0, 1 will remain at 1 ok. Instead, if previous value was 1 and
then this was 0. So, this 0 comes over here this 1 comes over here and clock is enabling it
so this will become 1.
So, 0 and 1 - what does it mean the output will become 0; it is reset. So, in either case
irrespective of the past value was 0 or 1, the output becomes 0. So, 0 1 output becomes 0
is it clear. So, from symmetry, you can say for 1 0. the output will become 1. And then
comes the last case for which actually this feedback is given and SR flip flop is different
from JK flip flop otherwise thee remain the other three rows of this truth table is same.
(Refer Slide Time: 17:14)
So, when it is 1 and 1 and say this is 0 and this is 1 the previous value and you have
made it to 1 1 and the clock is enabled now. So, this 0 comes over here ok, this clock this 1 goes over there and we are just you know, activated the clock at that time. So, what
has happened to the output? So, 1 1 - 1 this output is 1 AND gate and this is 0; so this is
0.
So, 1 and 0 - S and R the output will become 1 and this output will become 0 - is it clear,
so if this was 0 it becomes 1. Again from symmetry you can figure out because it is
identical right. So, if the previous output was 1 and this is 0 and it would have been 0 and
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this would have been 1. And so basically it toggles at that time - is it clear. So, this is no
more forbidden which was the case for SR flip flop - the 1 1 input.
Now if 1 1 is given the previous state is just inverted. So, this is what is the JK flip flop
truth table and the symbol will be like this. And if you are having a what is that called
active low preset and clear so this is the way the symbol will be presented. So, this is
basically referring to negative edge triggered JK flip flop.
(Refer Slide Time: 18:51)
Now, we look at something called master slave flip flop - ok. So, when you say master
and slave so there will be something which is driving the circuit and slave means the one
which is just following it, just carrying it forward ok. So, the JK flip flop example we
can take. In this case you see that this is one SR flip flop, so the slave is always SR flip
flop ok. And the master is depending on the flip flop type. Here we are talking about JK
flip flop right.
So, this is the JK flip flop with the feedback and all and this feedback is coming over
here which will be carried to the next level ok. So, there is an intermediate output at this
two points. And what is notable here is that there is a clock which is connected, I mean
whatever clock goes here the inverted - the clock if it is active for this is logic high so
when it goes to logic low right, so when it goes to logic low -so, this will go from logic
low to logic high.
476
So, when this is active at 1, this is level triggered, each 1 of them is level triggered - you
can see that there is no pulse forming circuit and other things are there. So, when this is
active this is inactive and when this is inactive this is active. So, how does it actually
then help? So, when it is active so because of the input, whatever the input is present the
output comes up to the master output; it cannot go to the final output because this part of
the slave is now inactive ok.
Now, slave - when this becomes inactive 0 now slave becomes active right. So, the
output of this master whatever was there this inactive means the previous state will be
retained this these are all 0 means 1 1. So, previous state will be retained, so master
output is retained so, that master output now goes to the final output ok. So, now, even if
the feedback is there right and it is asking for to toggle and all. But the clock I mean if
the both the inputs are 1 - so, the value will be coming and resting I mean, value will be
coming here, but it will not be able to change the output.
Because the master is now disabled, because clock is low and when clock becomes high
slave becomes disabled. So, because of which this is a toggle, but the output will come
over here ok, but it will not be going to the next stage slave stage. So, only one state
change is you know guaranteed within this. But if something is coming from different
other places when this clock is high - it need to be stable so that is another part of the
story.
And effectively then we are getting that whenever it goes - it was high master has
changed whenever it has gone low this slave is changing ok. And after that there is
effectively no change can occur slave can change here, but no way the output can alter at
time because the master has gone low. So, effectively you are getting a negative edge
triggering over here - is not it. So, that is another way of getting the edge triggering in a
roundabout way you can say ok, where; individually they are level triggered and we do
not have restriction on narrow pulse width and things like that ok.
But there are conditions like the input need to be stable, input need to be stable and all
ok. And instead of JK flip flop, if you want SR master slave or D master slave then we
need to have this initial stage to be D or SR. And the slave will always be SR flip flop
because there are two inputs coming from Q and Q bar of the master ok. And this is one
way people have I mean, this is the compact way people have made a presentation of
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representation of master slave flip flop. So, the clock is level triggered, but the output is
changing at the following edge ok. So, this is your flip flop indicator and with it there is
a preset and clear available ok, then asynchronous so it will be indicated in this manner.
(Refer Slide Time: 23:51)
Now, we shall look at edge triggering by input lockout, this is something which is
perhaps you would be finding very close to what an edge triggering circuit should look
like. So, no round about way, no narrow pulse width and the pulse forming circuit or
master slave and basically stable input at the master. So, all those things, parts can be
you know, conditions can be eliminated, and let us see how it works and we take a D flip
flop as an example - ok.
So, the basic circuit you can see that there is one kind of you know latch here this is
another latch and this is another latch ok. So, 1 2 3 4 and 5 6 right, and one point to be
noted that here there is a this 3 is 3-input rest all are 2-input. Now we see how this circuit
works how this circuit works - we shall go through examples. So, you consider that D is
initially 0; D is initially 0 and the output could be 0 or 1. That part we shall see - it can be
any one of them ok. These output is only linked here, it is not fed back to any other stage
right.
So, whenever D is 0 this output is, because it is a forcing input for the NAND gate, so
this output is 1. And we are talking about the clock remaining, this is a positive edge
triggering we are talking about. So, clock is at 0 means it is inactive - the output is not
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changing its value. So, let us see how it is happening. So, clock is 0 means this is 1 and
this is also 1 right. So, this 1 is feedback here, this 1 is there coming from this feedback
and clock is also 1 right. So, this 1 is again going back to this place this 1 is over here so
1 1 is making it 0 right.
So, 1 1 the previous value will be retained; if it is 0 it will be 0 it will be it 1 it will
remain 1 and vice versa I mean, the Qn and Qn bar will be just the opposite - is it clear.
Now what happens? Clock changes from 0 to 1 ok? So, what are the gates that will get
affected first? The gates that are connected directly to the clock ok, so clock becoming so
sorry this is 0 and this is 0 and this 0 is fedback here ok. So, clock becoming 1 means
this is becoming 1, so these three 1s, these three 1s make it 0.
Now clock has become 1 here, but this particular gate this 0 is over there. So, this 0 is
holding it to 1. Is there any other change? No, because when this 0 is it has become here.
So, 0 feedback here this 0 is holding back it to 1 there is no such change. So, this 1 and
this 1 together it is 0. So, what we see that 1 and 0 will be occurring ok. So, that will
make this 0 go to 1 because for the NAND gate this is forcing input and this 1, 1 fed
back - it is 0. So, whatever be the previous value 0 or 1 this will be 0 and this is 1 ok. So,
if D is 0 Q becomes 0 that is what the D flip flop - how it should look like.
Now whether it is edge triggered or not, let us see. Now the clock is at 1 right. We have
seen that when clock becomes high it is changing like this - clock has become 1 right.
So, what is the - what are the outputs at that time this was 0, D was 0 ok. So, D was 0
means this is this was 0 and this is 1 clock is at 1, this is 0 means this was 1 this was 0
right and what else? So, this is 1 and this 0 is coming over here right I am talking about
this stage, I have not talked about you know, changes ok. And this 1 is coming over here.
So, this 0 is here clock is 1 ok.
So, now, all the inputs have been understood and we are over here at this stage right
before changing the D. So, clock is 1, now we have changed D from 0 to 1. What
happens when that changes from 0 to 1? So, we have to see where it gets first affected,
where it first affects. So, it first affects this particular NAND gate because D is
connected only to that right. So, 0 to 1 when it becomes so this becomes 1. So, what is
the corresponding effect? So, these gate - already the other input of it is 0 ok.
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So, 0 and 1 - it will remain at 1 only, isn’t it. So, and this 1 is fed back here and it
remains 1 only so it remains 0. So, there is no, nothing, no other gate is getting affected.
So, at this change you see the 1 that are important so all of them are remaining at the
previous value. So, even if input has changed the input is locked out. So, this is what is
happening, even if the clock is high change over here is not making any difference right.
Only when clock from goes from 0 to 1 there is a difference there is a change occurring.
(Refer Slide Time: 30:25)
And you can see the same thing occurs if the situation was for D is equal to 1 and clock
was 0 ok. You can you know, see that the same way you can look at if the changes that
are taking place ok. That this output will become 1 and this output will become 0 at
when the clock goes from 0 to 1, and when it is clock is at 1 and if input changes from 1
to 0 ok. This output will change from 0 to 1; this output will change from 0 to 1. So, this
1 gets fedback here, but the other input of it is 0 so 0 will hold back it to 1 and no further
change that gets transferred to the final stage ok.
So, similar analysis like what we had done before, if you do we shall see that and the
immediate outputs are shown. That 0 to 1 there is a change the output becomes 1 if this is
1 and when clock is at high then at 1 when it is 1 to 0, the changes are taking place only
here. But after that no further changes are there.
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So, basically though there is a change in input, the input is getting locked out ok. So, this
is what we note and this is the way you can get edge triggering for D flip flop by locking
out the input. So, similar thing we can do for SR, JK other type of flip flop.
(Refer Slide Time: 32:06)
And finally, for a D type edge triggered flip flop we can put asynchronous preset and
clear and this is a standard circuit that I show you, IC 7474 ok. It is a dual; that means
two such positive edge triggered flip flop is there with asynchronous active low preset
and clear. So, this preset and clear are there you can see this preset input is going directly
over here ok.
So, if it is 0 and this is 1, so this will become 0 and this will become 1 right. And then
this output will become 1 and this output will become 0 right. So, that is active low so
when it is low it is becoming high right. So, if you look at the cases when the clock is 1.
So, basically the clock will be 1 at that time sorry clock is inactive clock. So, this is 0
and this is 1 and so these many things you can see is it fine ok.
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(Refer Slide Time: 33:30)
So, with this we conclude today’s discussion. What we have seen? In a level triggered
flip flop there can be more than one or unintended state change in one clock cycle. If
clock is passed through a pulse forming circuit that generates a very narrow pulse width,
effectively an edge trigger circuit can be obtained. Master-slave arrangement uses two
level triggered flip flop which work in two different phases of the clock.
And edge triggering using input lockout does not require separate pulse forming circuit
or master slave arrangement. And D and JK flip flops we have seen; how they work their
truth table. And we also noted that asynchronous preset-clear inputs are useful in settingresetting a flip flop without clock trigger.
Thank you.
482
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology Kharagpur
Lecture – 33
Representations of Flip –Flops
Hello, everybody! In the previous classes we have got introduced to flip flops. So, we
have seen clocked flip flop, edge triggered flip flop. And we had seen representation of
flip flop in the form of truth table.
(Refer Slide Time: 00:28)
We shall look at some other representation of flip flop in this particular class, which will
be useful for analysis of sequential logic circuit and synthesis of sequential logic circuit
which will come up in future classes.
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(Refer Slide Time: 00:43)
So, we start with SR flip flop and what we discuss now is representation through
Characteristic Equation. So, truth table of SR flip flop we had seen before in a compact
form like this and more elaborate form which can be represented here ok, so this truth table
is also called characteristic table in some of the literature.
So, if you remember that for S and R when input are 0 and 0 then if current state is 0 next
state will also be 0, current state is 1 next state will also be 1 that is previous state is
retained ok. If inputs are 0 and 1 then the flip flop will be reset irrespective of what had
been the previous state. So, whether it is 0 or 1 next state is 0 and 0, so this is the case we
have seen in a more compact representation; when it is 1 0 it will be set irrespective of the
previous value it is 1.
So this is the case in more compact representation. And when it is it is 1 1 it is not allowed,
1 1 is not allowed. So, if you want to get a characteristic equation that represents this flip
flop what we will do, so this is the current value based on which the next one is obtained.
So, we get - we form a Karnaugh map or any other minimization technique also is useful.
So, the idea here is we want to represent Qn plus 1 as a function of SR and Qn that is the
idea ok. So, you can take minterm based representation and then we can minimise it using
Boolean algebra or any other technique. Karnaugh map is handy, so we look at the
Karnaugh map based representation of this logic equation right.
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So, SR 0 0 if Qn is 0 then the Qn plus one is 0; 1 Qn plus 1 is 1. If it is 0 1 it is reset. So,
0 0. If it is 1 0 it is set. And 1 1 -since it is not allowed we put it, put a don’t care here that
means, from the equation whether we get it 0 or 1 it does not matter because, the value
will never appear at the SR flip flop input a case of both being 1 right. So, we shall use
that don’t care either as 0 or as 1 depending on how the groupings can be obtained and a
minimized representation can be made available ok.
(Refer Slide Time: 03:50)
So, for this case what we see the largest group of this 1s that can be covered is coming
where this don’t cares are included and for that we see that S is remaining constant with a
value of 1. So, what will be coming here S will come as one of the product term I mean,
there is no other term which is getting ANDed with it. And this 1 is not covered this 1 is
already covered, but together you can form a larger group, group size of 2 in which we can
see that R is 0 here R is 0 here.
So, the variable that will be coming here is R bar one term one literal and the other one is
Qn - Qn is remaining constant with a value 1, so Qn will be coming for this one ok. So,
then we sum it up and we get Qn plus one represented as S plus R bar Qn ok. So, this is
the characteristic equation of SR flip flop. Is it clear - right.
𝑄𝑄𝑛𝑛+1 = 𝑆𝑆 + 𝑅𝑅� 𝑄𝑄𝑛𝑛
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(Refer Slide Time: 04:50)
So, next we look at characteristic equation of J K flip flop right. Characteristic equation of
J K flip flop again we shall start with the truth table. So, truth table with J K and Qn these
are current value based on which the future value will be coming at the next clock trigger
and when we try to represent again similarly as a function of J K and Qn right. So, we
would like to have a Karnaugh map based representation first and then we shall see how
to - how to get a minimized representation right.
So, how SR flip flop and J K flip flop you know truth table differ or characteristic table
differ. So, up to this 0 0 input, 0 1 input and1 0 input they are the same right. So, 0 0 Qn,
0 1 0, 1 0 1. So, only place where it differs is 1 and 1 right. So, when 1 1 is presented as
input, in SR flip flop it is not allowed, in J K flip flop the output - the next state toggles.
That means, whatever has been the previous state, 0 it becomes 1 and if it was 1 it becomes
0, so that is what you have seen over here in a more compact representation.
So, for getting the minimized representation in the Karnaugh map, so 0 0, 0 1 and 1 0 will
be having same entry as that SR flip flop and we can get it directly from the truth table
also right for 1 1, for 1 1 now we have got a different entry earlier it was not allowed so
we put don’t care right here. If it is 0 if it is 1 1 then the next value will be 1; and if it is 1
next value will be 0 right - this is understood. So, with this we go ahead with the minimized
expression; how to find the minimized expression - we know again by forming the larger
486
group possible and we have to cover all the 1s if you are looking for SOP representation
right.
(Refer Slide Time: 06:58)
So, this is one group which is covering these two 1s and this another group which is
covering these two 1s and what we see here that Qn is remaining constant with 0 and J is
remaining constant with 1. So, J Qn bar will be one product term that is coming and which
will represent this group. And this group will be represented by similar to what we had
seen in the previous case, so this is your K remaining with 0. So, K bar and Qn is with 1
so Qn so these two product terms when you sum it up you get the characteristic equation
of J K flip flop fine, clear, ok.
�
����
𝑄𝑄𝑛𝑛+1 = 𝐽𝐽𝑄𝑄
𝑛𝑛 + 𝐾𝐾 𝑄𝑄𝑛𝑛
487
(Refer Slide Time: 07:42)
(At D or Delay flip-flop, irrespective of previous state) this input, 0 is just pushed to there
next state right. And if 1 1 is presented right. So, the output will become 1 1 irrespective
of what is the previous - in previous state the next state will be 1 1 right. So, when we put
it into the form of a you know, Karnaugh map we have 2 variables ok, so four such entries
will be required.
So, for D is equal to 0 this is 0 and 0 right irrespective of Qn being 0 or or 1 and D is equal
to 1 this is 1 and 1 irrespective of Qn being 0 or 1 ok. So, in this case we have only one
particular product term coming out of this because, only one group is sufficient to cover
both the 1s right and for which D is remaining with a value, D is having a value 1 right.
So, Qn plus 1 is simply D ok, so it is just the - so this is the characteristic equation of D
flip flop, clear.
𝑄𝑄𝑛𝑛+1 = 𝐷𝐷
So, here we introduce another flip flop which we call T flip flop or toggle flip flop right.
So, basically if we try to visualize what would be the internal circuit of logic circuit of T
flip flop, then we refer to how J K flip flop is made and then if we connect if we connect
both the inputs of J and K and tie together remember between SR and D we had a inverter
here there is no inverter ok, from SR to D we had put S as D and then R was D inverted
ok. So, there was a NOT gate here there is no such NOT gate directly it is connected, so it
becomes a single input flip flop right.
488
So, all those things pushed inside - inside the logic circuit within a particular you know
group ok, where all the elements are there then what we get is a single input flip flop. Of
course, it is clock positive triggered and all and the Q and Q bar this is outside that is why
these bubble is there if it is inside the convention is not to put the bubble I mean this
symbols Q and Q bar if they come inside bubble is not put - we have discussed this before.
So, this is your T flip flop ok, so this T flip flop then what would be it is truth table right
or characteristic table. So, this is your if 0 is presented at the input ok. So, this is like J and
K both being 0 0 so previous state will be returned, so if it is 0 it is 0; 1 it is 1. And if 1 is
presented so it is like for J K flip flop both the inputs are 1 because T is equal to 1 so the
output will toggle alright the next state will become the invert of previous state.
So, 0 becomes 1, 1 becomes 0 - is it fine right. So, if you try to get a characteristic equation
out of it, the minimized expression, so we can see for T is equal to 0 the previous values
is retained. So, 0 is 0, 1 is 1. And T is equal to 1 so it just toggles so 0 becomes 1 and 1
becomes 0, is it ok.
So, now what we see that larger group of 1 is not possible only 1 member groups are there,
so this is one group and the other the other one is over here. So, it is T this is T and Qn bar
alright and this is the other one is T n bar this is 0 and Q n, so this is your T flip flop
characteristic equation is it right. So, we shall make use of all these things later, in
subsequent classes we shall see how to make use of it.
�
����
𝑄𝑄𝑛𝑛+1 = 𝑇𝑇𝑄𝑄
𝑛𝑛 + 𝑇𝑇 𝑄𝑄𝑛𝑛
489
(Refer Slide Time: 11:46)
Next is another representation through excitation table ok. This is interesting! While
characteristic equation and characteristic table or truth table are useful for analysing the
circuit, excitation table and the one that is to follow, we shall discuss that also, that is
useful, that are useful for synthesis - design of circuits. So, all those examples we shall
take up in subsequent future classes. So, right now we are learning how to represent flip
flops in various forms, through various representations.
So, what excitation table tells us? So excitation - what sort of excitation should be present
at the input of the flip flop right. So, input of the flip flop is S and R for SR flip flop right.
Other one is clock, clock is a simply triggering and based on what is presented at S and R
the output you know, changes - the next state changes and of course, there would be
reference to the previous state feedback etcetera etcetera that is another part of the story
here. The external excitation, external input that is there to trigger, needed to make a
change in the flip flop that is the - that is what we are trying to figure out.
So, in that reference, in that context, for SR flip flop we are looking for excitation when
we see that the previous state was 0 and next state is also 0 - current state to next state
right. So, previous state was 0 and next state is also 0. If that is what we observe, then can
we figure out what was the input at S and R? We can figure it out from the truth table if
previous value was 0 and next value is also 0 ok, so that means, in one case we can see
that previous state is retained 0 0 right.
490
So, previous value will be retained, so we are talking about 0 previous value was 0 and
next value is also 0. So, it will occur when the previous - when the input is 0 0 that is
possible and instead of input is you know, input being 0 0, if input was 0 1 then also the
next state will be 0. Please understand this part ok.
So, if we refer back to more elaborate truth table of SR flip flop ok. So, we can see if this
is 0 1 and previous value is 0 next value is 0 and 0 0 previous value is 0 next value is 0 So
in both the cases it is happening right.
(Refer Slide Time: 15:10)
So, if this is what is observed, we can say that either of 0 0 or 0 1 was presented at SR to
make this happen that it has changed from 0 to 0. And how we can represent it in more
compact form? We can write this as 0 X. X stands for don’t care. So that means, S need to
be 0 and R could be any of 0 or 1 for which if the previous value was 0, next value for sure
will be 0 ok, this is what is coming as entry into the excitation table. So, 0 to 0 you can see
the input required to be is to be 0 0 or 0 1 in more compact form 0 cross - 0 X. Is it ok?
Right.
Now, what are the different possibilities of this transition because, it is a 1 bit kind of thing
alright. It will - flip flop contains only 1 bit of information. So, 0 to 0 is one possibility
that we have already explored, so the other one is 0 to 1 - 1 to 0 and 1 to 1 right. So, in
each of this cases we can figure out if such transition does take place then what has been
the excitation at the SR input, so for 0 to 1 right.
491
So, the previous value was 0 next value is 1, so you can understand from the truth table
that input required to be 1 and 0 - it is becoming set. 0 0 will not occur - will not help
because, previous value will be retained right. So, if you put 0 0 then 0 will be remain 0
only, so only option left is you have to put 1 and 0 right. 1 to 0, 0 and 1.
(Refer Slide Time: 17:10)
And for 1 to 1 for 1 to 1, you can have 0 0 case this is 1 to 1 if you have 0 0 right previous
value is retained and if we have 1 0 that also will make sure that the next value is 1, in
either case for these inputs being present if the previous value is 1 next value for sure will
be 1. So, that is R needs to be 0 and S can be any of 0 and 1, so that is the case where we
say - what we say as cross 0. Is it clear?
So, the excitation table of SR flip flop looks now something like this. So, it is re-reading
of the truth table or characteristic table and putting it in a different manner, that if this is
what we desired if the circuit has to move from states - one state to another and the states
are represented by individual elements which are flip flop then to make certain changes
happen what should be present at the input ok.
So, this is looking at it from the reverse direction right. Characteristic table, truth table - if
this input is there what will happen what will - what change will occur. And excitation
table - if this change is to occur what is to be present as input ok. So, this is the way these
two representations differ from each other.
492
(Refer Slide Time: 18:48)
So this is for SR flip flop, so we can see how it would be for other flip flops ok. So, for JK
flip flop - for JK flip flop, so again this transitions, all this 4 transitions are to be considered
so 0 to 0 right. So, if 0 0 is present previous state will be returned and 0 1 is there - that
also will make that the next state is 0 for previous state being 0 ok. So, this is 0 cross and
similarly 1 1 like previous case. So, 0 0 and1 0 both the cases it is becoming if the previous
state was 1 so the next state becomes 1. So, this two we can see we can visualise from SR
flip flop excitation table ok. Now coming to the other two cases.
So for 0 to 1 - 0 to 1 in SR flip flop it was only 1 and 0 ok. But in JK flip flop for 1 1 input
we know the output toggles ok. So, if the previous value was 0 the next value will become
1, also for the case when input is 1 1 right. So,1 0 as well as 1 1 - why 1 1 because the state
toggles 0 becomes 1; and why 1 0 because that is how the things get set I mean, set similar
to SR flip flop setting ok. So, these two cases we can see that a 0 to 1 transition is possible,
if that is the excitation at the JK flip flop input right. So, we can put this as 1 cross, similar
to what we did for SR flip flop truth table excitation table.
Similarly, for 1 to 0 transition, earlier it was only 0 1 now 1 1 is also possible because of
this toggling part of the truth table in the JK flip flop ok, so this becomes cross 1 right. So,
this is how it differs and what is it is significance and other things ok, if we want to realise
a circuit using SR flip flop or JK flip flop, how these things will come up that we shall
explore in future classes.
493
Now for D flip flop, it is relatively straight forward. So, we know if the next state is 0 right
the input need to present is 0 if the next state is for 0 to 0 cases. 1 input need to be present
is 1. Again from 1 to 0 since next state is 0 input need to be present is 0. 1 to 1 again input
need to be present is 1. So this is the excitation table of D flip flop.
And for excitation table of the T flip flop ok. So, we have got 0 to 0 so previous state is
retained, so this is 0. 0 to 1 toggling ok. So, input to be need to be 1. 1 to 0 again toggling,
so input need to be 1. And 1 to 1 previous state is retained - so, input is to be 0 fine. So
this is how excitation table is - through excitation table we can represent different flip flops
ok.
(Refer Slide Time: 22:28)
Now the excitation table, whatever we have seen there, we can put in the form of state
transition diagram, this is another way of visualizing what is happening in a flip flop ok.
So, for a particular flip flop we have got a one I mean, two states because, it has - it stores
one bit information; state when it is the output is 1 and state when the output is 0 ok.
Transition means when the excitation comes at the input, it is supposed to make I mean, it
is now can make a transition. So, whether it will make a transition to next state as 1 or it
will remain in the same state that is 0 if the present state is 0 ok. So, that is explained, that
is visualized pictorially in the form of state transition diagram through a diagram.
So, if we look at the SR flip flop state transition diagram, so this is pne state with value 0
right and this is another state current state described by 1 ok. Now when it is at state 0 and
494
it receives a input 0 0, what will happen? It will remain in the same state, so that is what
is shown through this line and this arrow mark will be there to show where it is. And if it
is at state 0 and if it receives 0 1, if it receives 0 1 what will happen? It will stay at 0 only.
Isn’t it? Right.
So, 0 - it is remaining at 0 for the cases 0 0 and 0 1, so we can see from the excitation table,
also from truth table we can you know, in an inverted way, we can figure it out - right.
Now it is at 0 so 0 0, 0 1 we have seen. If it receives a1 0 what will happen? It will get set.
It will become the output, the next state will be become 1, the state of the flip flop will
become 1 right. So, it will move to 1, so that is what is shown through this arrow over here
- from 0 it is coming to 1 and when the input presented is 1 0 - is it ok. Now it is at state
1, the state at 1 and it is receiving you know, whatever is allowed other than 1 1 everything
is allowed 0 1, 1 0 and 0 1 right, so these are the three things that are allowed for SR flip
flop.
So, if it receives 0 0 it will stay at 1 only if it receives 1 1 sorry, 1 0 it will remain at 1 right
and if it receives 0 1 then it goes back to state 0, it goes to state 0 is it ok. So, for each of
the stable state, for SR flip flop, this bi-stable circuit, we can figure out for the allowable
inputs what would be the next state and it can we can pictorially depict it through state
transition diagram as you have seen here.
So for JK flip flop again current state is 0 right, if it receives 0 and 1 it will stay here, if it
is receives 1 0 it will go there, if it receives 1 1, four – all, now 1 1 is also possible, then
also it will go to 1 ok. At 1, if it receives 0 0 it will stay here, 1 0 it will stay here and if it
receives 0 1 it will go to 0 and 1 1 it will go to, again it will toggle, it will go to 0 similarly
ok.
For D flip flop right stable state 0 if it receives 0 it will stay here if it receives 1 it will go
to 1. If it is at 1 if it gets one it will stay there if it is - if it receives 0 it will come to 0.
And for toggle flip flop, if it receives 0 then it will stay at 0 and if it receives 1 it will toggle
- it will go to one and if at 1 if it receives 0 it will stay at 1 and if it receives 1 it will toggle
and go to 0 ok. This is the other way, other form of representation.
The another representation through timing diagram ok, in all these cases the delays and
other things ok, however, small it might be, is not visible - all this representations that we
495
have discussed so far. So, if we represent the flip flop, the transitions that are happening
for a particular set of inputs and, rather all possible set of inputs excitation - so, through
timing diagram we can show it ok, that we shall discuss through some examples in some
subsequent classes.
(Refer Slide Time: 28:05)
Characteristic equation of a flip flop is a minimized representation of the next state by
considering present input and present state. Excitation table shows in tabular form what as
input is required to move the flip flop from one particular state to other. A don’t care in
excitation table indicates that specific transition will take place irrespective of the variable
under consideration being 0 or 1. And, the change in state of a flip flop for a specific input
can be represented by state transition diagram when - if you look for a pictorial description.
Thank you.
496
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 34
Analysis of Sequential Logic Circuit
Hello everybody. In this class, we shall discuss how to analyse a sequential logic circuit
ok. This is the first discussion on this, so we shall introduce the topic softly. We shall not
take a very complex circuit. In future classes, we shall have discussion on more complex
circuit. So, we have seen various representations of flip-flop in the previous class.
(Refer Slide Time: 00:43)
And we shall make use of some of those representations in the analysis ok.
497
(Refer Slide Time: 00:50)
So, we start with an example and through solving this example we shall learn the
associated technique ok. So, the example that we have taken up, you can see, is a SR
flip-flop best example, right. So, this is a SR flip-flop, this is another SR flip-flop, so you
have named it as A and B ok. So, input has been designated as SA RA instead of Q and
Q bar we are writing A and A bar ok. So, that we understand that this is associated with
flip-flop A and similarly for flip-flop B.
And what you see the circuit has got other logic gates. This is what you are expected to
see in a sequential logic circuit. It will be having combinatorial circuit element, so called
combinatorial circuit elements that is basic gates, right which does not have memory;
and we shall also have these memory elements in the form of flip-flops ok. And, later we
shall see combination of flip-flops by which you know the registers will be part of the
sequential logic circuit and other things ok. So, other building blocks we shall discuss
later.
So, there is some connection, right. So, you have to go through the analysis steps and
figure out what the circuit as a whole does. And in doing it, since it is analysis, we shall
make use of what we’ll see later that truth table and characteristic equation. We are not
looking into excitation table or state transition diagram in its analysis. So, that will be
useful in synthesis part which we shall take up later ok.
498
Further, here we see that of course, this is a clocked flip-flop, right. We consider the
clock cycle time; clock cycle time this is the way the clock cycle is triggering, all right.
So, this clock cycle time is much, much more than the propagation delay of this basic
gates ok. This propagation delays are of the order of nanosecond, 10 nanosecond or so,
ok. And in this flip-flop of course these are the frequencies could be in kilohertz, Hertz
or megahertz, even in all those cases this is not, this delay is not comparable to whatever
is the timing period.
So, if the delay is comparable what will happen that we shall take up later. Right now in
our first discussion on analysis of sequential logic circuit we are considering a scenario
where this propagation delay of basic gates is substantially small. And similarly the
circuit inside the basic gates that comprises of, that goes into the making of this flipflops. So, delay associated with them and delay of the flip-flop is also small ok. So, that
is what we consider.
(Refer Slide Time: 04:16)
So, first we look at representation of different inputs of the flip-flop in terms of the
current state value, right. And in this particular circuit there is no external inputs. So, if
there was external input, we would have represented in the form of, using that external
inputs also. So, we shall take up example where there is external input sometime later.
And also we shall do it for the output, this final output that is getting generated here,
right.
499
So, we see what is happening for SA input. So, if you look at SA input, right this is
nothing but whatever you see here A, right. So, that A the current state value is fed back,
and presented as SA. Is it fine? You can figure it out. So, that is the analysis part, right
you have to look at the circuit diagram and from that you can figure it out. So, S A is An
bar, right.
What about RA? So, this is what we have to see, all the inputs we have to see the you
know, logical connection; logical relation. So, RA you can see this coming from over
here. So, this is the path it is taking, right. So, RA is An; this is fine. Now you have to
look at SB. So, this is SB; what we see it is coming from an AND gate, right. So, this
AND gate is - one input is A and the other input is B bar, so, that is An and Bn bar. So,
that is SB. And what is RB? RB is, RB you can see is that - so, this An this is one is there
another is, this is coming over here, that is Bn, right; so An and Bn, right.
SA = An’
RA = An
SB = An.Bn’
RB = An.Bn
And also you can see the final output X is Bn and An, right. So, final output could have
been taken from here also, if it is so possible ok. Otherwise if it is so drives something
else and also it depends, right. But logical relation of both of them is same for this
particular example; for some other example it could be different, depending on the
requirement; it could be An Bn bar or An bar Bn bar some such thing or whatever. Is it
clear?
X = An.Bn
Now we have understood what is SA RA, SB RB and X ok, how they are logically
connected. So, that is the first step that we do in the analysis.
500
(Refer Slide Time: 07:21)
So, next we come to something which looks formidable now to begin with, but once we
go through the process we’ll see that it is not that difficult to understand what is
happening here. So, it is called state analysis table or state table. So, in this, we begin
with an initial state ok. We are analysing the circuit, so initial state if not otherwise
mentioned; if not otherwise mentioned you can assume it to be 0 0. That means, the
current value of the flip-flop is 0 and 0; is it ok.
Otherwise, it will be mentioned that it is initialized with this, clear. And how we can
make sure that this is 0 0? So, the flip-flop usually will be having an asynchronous clear
- clear input, in some of the flip-flops preset input may also be there, but clear is
available ok. Otherwise also you can drive to the; I mean if it is so possible, by
synchronous clear or preset also you can come to a particular initial stage.
So, it is fairly acceptable - reasonable to assume that the initial state is 0 0 if it is not
otherwise mentioned ok. So, that is what we mean by clock 0. And then with clocking
this circuit will move from one state to another and the corresponding output will get
generated and that is what we have to investigate. Is it ok? So, this is the current state
this is SB RB - the inputs, SA RA - the inputs, this is the - these are the next state, and
this is the output. So, this is how the state table has been configured which is
understandable, right.
501
So, if the current state is 0 0 and we have already seen the equation for SB RB and SA
RA ok. So, what is the current input? So, if it is 0 0, both of them are 0 0 for SB you can
see a An is 0, right, so this is 0 because this is AND logic and here also An is there so
both of them are 0. So, if both of them are 0 for flip-flop B what will be the , so this is
flip-flop B, what will be the next state? So, 0 0 means previous value will be retained, so
Bn is 0. Is it clear?
So, that is what you will see. And when the your, if you look at SA and RA - it is inverse
of An, An bar. So, An is 0, so SA becomes 1, and RA becomes An itself. So, it is 0. So, 1
0, so it will get set. So, this is 0 1; is it clear or not. The first row; only the first row ok.
So, then first clock trigger comes; so, basically Bn plus 1 is clock trigger has happened,
ok. So, the value will become 0 and 1, the flip-flops will move from 0 0 to 0 1. So, when
it moves from 0 0 to 0 1, right. So at the next clock cycle inputs will get changed
accordingly, because the inputs to all these things and even the output is a function of An
Bn and had there been an external input - is a function of that ok. So, here we are
considering only these states, right.
So, for that we have to come to the second row of the state table. So, after first clock
cycle first clock trigger has happened. So, we have come to 0 1 and that 0 1 becomes the
current state, through which the analysis process will continue, with which the analysis
process will continue.
So, if it is 0 1 ok. Now again we shall look at, we shall look at what is happening to this
SB RB. For Bn and An being 0 1, SB is An Bn bar; right An is now 1 and Bn is 0. So,
Bn bar is 1, so 1 and 1 ANDed is 1. And what about RB? RB is An Bn. so, Bn is 0, so 1
and 0. So, this is giving you 1 and this is giving you 0 ok. So, this is 0.
So, 1 0 means then Bn plus 1 will become 1, this part is clear. What about An sorry;
what about SA RA? Now we look at SA RA. This part we have seen, ok. So, SA RA is
An bar and An; An is now 1 ok. So, SA becomes An bar is 0 sorry; SA becomes 0, right
because this is 1 and this is 1, right, because it is An. So, 0 1 means it will become 0. So,
next state, when the clock trigger comes, becomes 1 0 after second clock trigger. So, this
1 0 becomes the current state ok.
502
And this 1 0 then again if you look at SB RB, this is An is 1 and Bn is 0. So, you will see
that An is 0 making it 0 and Bn here also An is 0, so it is 0 0 ok. So, 0 0 means previous
value will be retained. So, this is at 1 ok. And what is happening to SA RA? Because it
was 0 it becomes - An was 0, so SA becomes 1 because it is inverted and this is 0. So, 1
0 means it becomes 1. So, current state becomes, next state becomes 1 1.
And with 1 1 at the input ok; so, we’ll see again if you follow this equation 1 1 as at the
input An is 1 and Bn is 1. So, Bn is 1 means this is 0. So, 1 ANDed with 0, so this is 0
and this is 1 ANDed with 1 this is 1 ok. So, this is 0 1 ok. So, that makes it 0 - An plus 1,
your SB RB. So, that SA RA. So, SA RA - is your this just inverse of it, An is SA is 0
and this is 1, so that makes it 0 ok.
So, that is, next state becomes 0 0. So, when it is 0 0 you come over here you see this is
the first row. So, same thing will come over here and it will keep repeating. And in each
case if you look at the output - output is An Bn. So, whenever the current value is 1 1
the output will be one 1 at that time ok. For the rest of the cases it is 0; is it fine ok.
So, this is the way the state table will evolve.
(Refer Slide Time: 15:57)
So, how will you represent the analysis result? So, you can represent through pictorially,
through state transition diagram. So, in the state transition diagram what we are showing
here is that a this is the current state and this is the output that is generated ok. So, 0 0 is
503
the current state, and output generated at that time is 0; that we have seen in the table,
right. So, next state is 0 1. That means, the when the clock trigger comes, right and this is
0; 1 0 after that then 0; and this 1 1 and at that time output is 1. Next clock again it goes
back to 0 0. And it keeps cycling around this 4 states, ok.
So, this is one way we can visualize what is happening in that circuit after analysis, the
other one is a text description where we say the circuit generates an output 1 at every 4th
clock cycle that is what you have, you can see when it reaches the state B A is equal to 1
1 because that is the way these flip-flops where designated, and repeats these state
transitions 0 0, 0 1, 1 0, 1 1, ok. So, that is the way it continues.
So, analysis - for analysis, a circuit is given. You analyse and you come to a state
transition diagram for a pictorial description of it or text description to English statement
to clearly explain what that circuit does, ok. That is the analysis result.
(Refer Slide Time: 17:43)
Now, in the representation of the flip-flop we said that timing diagram is very useful, but
we did not take up. Now here we can see how timing diagram comes into play.
So, for which we consider that this is the clock and it is getting triggered at negative edge
of the clock, ok. So, whenever a negative edge comes the circuit can trigger, ok; I mean
the flip-flops can trigger, right. So, we start with initial state B and A, 0 0; that is what
we have considered, right. So, when B and A are 0 0, up to this time point what are the
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values of SB and RB? Our SB was B A - A prime B, so this is 0, this was AB so this is 0,
right. And SA and is A bar. So, this was 1 at that time and RA is 0. Is it fine?
So, this is what we can see from the previous circuit if we sorry; here it is An Bn prime,
this is SB is A B prime, ok. So, there is a mistake we have to - please look at it.
So, then what happens at this point when the clock trigger comes, when the clock trigger
comes at this point, ok. So, depending on the values that are presented, so this is 0 and 0,
right. So, the previous value was 0 for B, right, so SB RB is 0 0; SB RB is 0 0. So, it will
continue to become 0. So, it gets the trigger over here, before that it is not supposed to
change. That we discussed before when clock circuit, edge triggered circuit or gated
circuit or so, ok. So, even if the input changes unless the clock trigger comes it is not
going to change.
So, this continuous to 0, ok. How long it will continue till next edge, clock edge comes.
At that time it is you know, it can make a change if - depending on the excitation, all
right. And what happens to A? A is 1 and 0. So, when the clock trigger comes A
becomes - from 0 it goes to 1.
Now, here what I was telling that we can show the delay if it is appreciable which other
representations cannot show. If the delay over here flip-flop delay is comparable to the,
comparable to this you know this clock period sorry; from here to here this is one clock
period, from here to here this is one clock period, then we can show the delay, right here
A is changing we can show it like this, that proportionate delay. That it has become 1,
but after sometime and if the delay is cumulative or this delay is something by which the
circuit can malfunction or can give some undesirable result, that is better manifested
through timing diagram based representation, but not by others, ok. This is the usefulness
of timing diagram based representation. And we shall see such cases in future when we
study other sequential logic circuit, clear.
So, coming back; so B continues with 0 0 and A becomes 0 to 1; is it fine? And it will
remain 0 like this till the next clock edge comes, till the next clock edge comes, negative
edge is triggered, ok. So, when it is at 0 and 1 what happens to the inputs now, ok. So,
again this is A B bar, ok, right. So, this becomes SB becomes A B bar. So, this becomes
1 ok, RB is A B so this is 0; SA is A bar, so this is, this is A is 1 so this becomes 0 and
RA is 0 – ah, RA is 1 because it is A is 1 now. Is it fine?
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So, it is moving with the clock, right synchronous with the clock and it becomes 1 after
that, that causes the changes in SB RB SA and RA. So, small propagation delay will be
there, right. But again this is negligible compared to the clock period, negligible
compared to the clock period, because this logic operations as I said if it is appreciable
then we can show that SB is becoming; after this has changed, like this then from that it
will further small delay and it will be shown in that manner, ok. Otherwise we are
neglecting that part, ok. So, 0 1, so this is 1, this is 0, this is 0 and 1.
Now, clock trigger negative edge comes. So, at that time again circuit can change. Again
let me correct every time, ok. So, this is, ok. So, then what happens 1 0; sorry SB is 1 0.
So, B becomes 1, right and S A is 1 0 all right. So, SA is sorry 0 1 SA RA. So, it
becomes 0. So, from 0 0 it goes to 0 1 then 1 0 and then you can see that it is goes to 1 1
and then again its repeats at 0 0, ok
So, this is the way the timing diagram can be used to show how the circuit moves; I
mean that is through the analysis process. And each time you can show the output over
here and based on the current input, and when both the inputs are 1 1, right you can show
the output is coming 1 1 just after a small propagation delay if propagation delay is
compatible. Fine, right.
(Refer Slide Time: 24:43)
So, we can use characteristic equation also directly, since we already are familiar with
characteristic equation - right, to come up with the analysis result, ok. So, we have seen
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that SA and RA - how it gets represented. And we know the flip-flop equation of SR
flip-flop. So, An plus 1 - we can write it in this manner SA plus RA prime An, right. And
when we substitute SA from here and RA from there and we just simplify, we see that
An plus is An bar - An prime, ok. And that we have actually seen in the previous cases,
in the timing diagram also, that it is just toggling output is - A flip-flop is simply
toggling in every clock cycle, and that we can see from the equation also.
SA = An’
RA = An
An+1 = SA + RA’.An
Substituting,
An+1 = An’ + An’.An = An’
Similarly SB and RB we have seen, right. And we have got flip-flop equation. Now
instead of Qn plus 1, we are writing Bn plus 1; Qn we are writing Bn and if we substitute
and you know, put it into a more compact form by going through the steps of
minimization. So, we see An XOR Bn.
SB = An.Bn’
RB = An.Bn
Bn+1 = SB + RB’.Bn
Substituting,
Bn+1 = An.Bn’ + (An.Bn)’.Bn
= An.Bn’ + (An’ + Bn)’.Bn
= An.Bn’ + An’.Bn + Bn’.Bn
= An.Bn’ + An’.Bn
= An ⊕ Bn
We can have these state table. So, we can - where this is the current state again is reset if
it is not specified you can begin with this current state, right. And then we can look at
this equation, so Bn plus 1 is An XOR Bn, right. An XOR Bn is 0 0. So, it is 0. And
what is An plus 1 it is just inverse of it. So, this is 1.
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So, 0 1 becomes the next state. So, 0 1 this XOR this becomes 1 and An prime, so it will
become just the opposite of it that we already know, we have seen from this equation then becomes - 1 0 becomes the current state XOR is 1 and An - it just gets
complemented so this is 1. So, 1 1 becomes next state. So, 1 1, right XOR 1 1 is 0 only,
and then 1 toggles - becomes 0. So, next state becomes 0 0. So, 0 0 again you come back
to the looping of it cycling of it. So, it is 0 1 and it continues this way, right. And when it
is current state is 1 1 we can see that output is An Bn which is 1, fine.
X = An.Bn
(Refer Slide Time: 27:23)
Finally, we look at one – again, simple example for the first class on analysis of this
circuit, where there is an external input present, ok. So, here is a D flip-flop, clock and
then there is an external input, right. And there is a output that is getting generated in this
manner. So, first step is what; getting the equation at the input of the - for the input of the
flip-flop. Only one flip-flop is used. So, D is XOR - X XOR Qn that we can see, this is
Qn is fed back, right XOR Qn. And what is Y? Output is X ANDed with Qn prime, very
simple, is it ok.
D = X ⊕ Qn
Y = X.Qn’
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Now if we just go by this state table method, we can go by any other method, ok. So,
state table method then we can see the current state we assume to be 0, if not otherwise
specified as I said. And if input could, input could be now either 0 or 1 because it is
coming from outside, we do not know for sure. So, if the input is 0, then 0 XOR 0 is 0,
right which will make D flip-flop whatever is the input that will go as the output. So, this
makes it 0, ok.
But if input was 1; 0 XOR 1 is 1 next value would have been 1, ok. And at that time
since X Qn bar is the final output, so this is X - 1 and Qn bar is 1 so at the time the
output is 1. Now if the state is 1 right and you receive a 0, ok. So, 1 XOR 0 is 1 at the
flip-flop input and then the output will become, right. And instead of 0 if you receive a 1
then 1 1 XOR is 0, right output will be 0. So, this is how the circuit works.
So, this circuit every time from current state to go to the next state it looks at the input.
And based on the input of course, the current state it moves to the next one and generates
output, right. So, for this we are looking at a state diagram representation as the analysis
result, where the state is only 1 state, ok. So, 0 and output is generated based on the
input, directly from the input, ok. So, for this we are showing output not inside the state;
earlier the output was generated solely by the state, ok. So, we showed it inside the state.
Here for input when it is 0, right and the current - this is now 0 right and the current input
is 1; state change will take place in the next clock trigger in the next negative edge, but
when this is happening, right the output is getting generated in this same cycle, clock
cycle itself. So, that shows - that is shown in the state diagram side by side with the
input. So, this is input and this is output, this is the convention more about this kind of
representation, modelling we shall discuss elaborately later, ok.
So, 0 is present, 0 is the current state, input is 0 it will remain at 0, the next value will be
0, output is 0. 1 output is 1 is goes to 1. And then if it is 0, right it will - when it is at 1 it
remains at 1 output is 0 and when it is at 1 it goes to 0 and output is 0.
So, what you can see if you now look at this state diagram, this particular circuit except,
if you ignore this output Y, rest of the thing which is there in this box is nothing but your
T flip-flop, isn’t it. So, in T flip-flop the state transition diagram if we had seen. So, this
part was not there, this part was not there rest of the thing are same, ok.
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So, we analyse the circuit and see that this is how the circuit will behave. And this is the
corresponding text description that its toggles when input is 1. And maintains, otherwise
maintains previous state. And, output is Y, output is 1 when input is received at state 0 is
1, else output is 0. So, that is the analysis result.
(Refer Slide Time: 32:20)
So to conclude: analysis of sequential logic circuit begins with specified initial state.
Combinatorial circuit - logic part is analysed to find out the relationship at flip-flop
terminals, logic relationship and for the output. In the state analysis table all inputs of the
flip-flop at a given state is described and next state is obtained, and that serves as the
input for current state for the next row of the table.
And it can be presented through state diagram - final result or a text description. And
timing diagram based analysis is useful to evaluate the progress of the state and it can
show the effect of propagation delay; when it is comparable it is very much required and
useful. And flip-flop characteristic equation can also be used for analysing the circuit.
And for which some algebraic manipulation is required.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture – 35
Conversion of Flip – Flops and Flip – Flop Timing Parameters
Hello everybody. We have been discussing flip-flops. So, we have seen its truth table,
characteristic equation, excitation table, and also representation through timing diagram
in an analysis problem. So, in today’s class, we shall discuss Conversion of Flip-Flops,
and Flip-Flop Timing Parameters.
(Refer Slide Time: 00:38)
In course of that, we shall also acquaint ourselves with synthesis of sequential logic
circuit. We shall gently introduce ourselves to that. More complex sequential circuit
design, we shall do later ok.
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(Refer Slide Time: 00:56)
So, here when you are talking about conversion of flip-flops, so what actually we are
looking at is a case, a situation, where a circuit has been designed with a particular kind
of flip-flop ok. And in your resource, in your stock or library, you find that a different
kind of flip-flop is available with you ok.
So, one option is to redesign the entire thing using the flip-flop that is available with you
or thinking of a conversion mechanism by which the given flip-flop, the available flipflop can be made to work like a different flip-flop ok. So, if we are looking at D flip-flop
is available with you ok, and you are looking for a T flip-flop made out of it ok. So, one
such circuit we have seen in the analysis class, in the previous class, but let us look at a
formalized method.
So, one way of doing it is that we know the characteristic equation of D flip-flop is Qn
plus 1 is equal to D. So, whatever is presented at D input with the clock trigger, it goes to
the output that we already are, we are familiar ok. So, if we are talking about conversion
of D flip-flop to T flip flop, so we know the T flip-flop equation characteristic equation
to be Qn plus 1 is equal to T Qn prime OR that is plus T prime Qn ok, this is already you
we know.
Qn+1 = D
Qn+1 = T.Qn’ + T’.Qn
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So, if we look at this equation Qn plus 1 is equal to this, and Qn plus 1 is equal to D
right. Then if this input T Qn prime plus T prime Qn, we feed as D ok. Then the D flipflop next clock instant, it will go here at Q, I mean, at the output of Qn plus 1 right. So,
this Qn plus 1 will take the value of D. If D is defined as this one, is it clear ok.
(Refer Slide Time: 03:23)
So, simply we can write D as T Qn prime plus T prime Qn ok.
D = T.Qn’ + T’.Qn
And that in the logic circuit this is a combinatorial logic circuit right, so we can get by
designing it. So, this is your T input, and this is just an XORring. So, basically Q and T
are getting XORed, and it is being available here as D input. And when the clock trigger
comes, whatever is here it will go there ok. So, whatever is here that is this will go there.
So, this is very simple for converting D flip-flop to T flip-flop ok.
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(Refer Slide Time: 04:05)
So, this can be extended to JK flip-flop as well. So, JK flip-flop equation is similar, but it
is J Qn prime plus K prime Qn ok. So, we’ll take D as this one ok, and then we shall just
make it combinatorial circuit, and accordingly we will get it right.
Qn+1 = J.Qn’ + K’.Qn
D = J.Qn’ + K’.Qn
And similarly, for D flip-flop getting converted to SR flip-flop ok. So, the equation is Qn
plus 1 is S plus R prime Qn. So, we can write D as S plus - plus is here OR we know
that, so R prime Qn ok.
Qn+1 = S + R’.Qn
D = S + R’.Qn
So, the circuit will be here, S goes here with it is getting ORed R there is an inverter, a
NOT gate ok, and Qn is coming from here all right. And this is ANDed, and together it
goes here right. So, this block this block entire thing can replace the SR flip-flop,
wherever it is required in your design, in your circuit - its clear.
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(Refer Slide Time: 05:21)
Now, if we are looking at converting other flip-flop to D flip-flop right. So, if we are
looking at SR flip-flop getting converted to D, we have seen before. Otherwise, also we
can figure it out from their equations, the characteristic equation. This is Qn plus 1 is
equal to S plus R prime Qn. And if we consider S as D, and R as D prime which we have
done before, but we can put it in the characteristic equation.
Qn+1 = S + R’.Qn
Consider,
Then,
S=D
R = D’
Qn+1 = D + (D’)’.Qn
= D + D.Qn
= D.(1 + Qn)
= D.1 = D
And in this equation S is put as D, and R as D prime ok. Then we go through the steps,
we can see that Qn plus 1 is becoming D, if that is what is done ok. So, this Qn plus 1 is
D is basically your this D flip-flop equation. So, SR flip-flop all right S and R, this is
your clock right. So, here you put an inverter and you connect, so this is D. So, this
whole block. this whole block this is Q, this is Q bar. This whole block will behave like a
D flip-flop ok.
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(Refer Slide Time: 06:52)
Now, same thing if you follow for JK flip-flop, again you put D and you know, J as D,
and K as D bar all right. So, you can see J as D and K as D bar, and then you go through
the simplification steps. So, you see that it is ultimately becoming D ANDed with Qn
prime OR Qn, which is D only. So, you can get the D flip-flop, just by connecting an
inverter between J and K, and taking the J output as D output. So, the entire block over
here behaves like a D flip-flop ok.
Qn+1 = J.Qn’ + K’.Qn
Consider,
Then,
J=D
K = D’
Qn+1 = D.Qn’ + (D’)’.Qn
= D.Qn’ + D.Qn
= D.(.Qn’ + Qn)
= D.1 = D
Now, if we are looking at converting T flip-flop to a D flip-flop ok. So, now if we look at
the equation, whether we can put an inverter and all, and we can get it, we can see that
the solution is not as trivial as it had been the case before. So, if we you know look very
closely, and go through algebraic manipulation we can arrive at something ok.
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But, we can look at a method which is a generalized method, which we will work for
every such conversion or every such synthesis kind of thing, which will work equally
well for what we have shown here. Here we got by comparing the equation, and by
applying some knowledge about this Boolean algebra ok. So, otherwise also we can
follow a standard synthesis method by which we can arrive at this solution.
So, let us look at this problem of getting a D flip-flop out of T through a synthesis
example, you know synthesis of logic circuit example not going through a algebraic
manipulation process ok. So, to do that, so let us see how we can go ahead.
(Refer Slide Time: 08:47)
So, here what we are doing you see, we have a table here right, which has got four
columns. And here we have got of course these five rows, where data is - four rows,
where data is put ok.
And so the first part of it you see, the one in this color, all right - yellowish color, you see
that it is D flip-flop truth table ok. The flip-flop that we want, truth table of that would be
written, so that is this generalized you know, method we are talking about. So, it will
apply for a any other case, we shall take, we can look at another example of course in the
next slide. So, here we are talking about D flip-flop, so D flip-flop truth table is here. So,
0 all right if Qn is 0, the output will be 0; Qn is 1, output will be 0 that is the way D flip-
517
flop works. So, if D is 1 both for Qn is equal to 0 and 1, output will be 1 - this is ok,
right.
Now, we look at the T flip-flop right. So, this is the D flip-flop that is the way to work.
So, at the time at the T flip-flop input, because inside there is a T flip-flop as a whole the
block T flip-flop plus some additional circuitry, it behaves like a D flip-flop. So, inside
whatever T flip-flop we have put, what should be the input in these cases, four cases that
we have seen in the D flip-flop truth table ok, so that we figure out.
(Refer Slide Time: 10:37)
So, we see that in the first case when D is equal to 0, and Qn is equal to 0 ok, then the
transition takes place from 0 to 0 ok, Qn plus 1 becomes 0 for this combination right So,
for this particular transition 0 to 0 right, what should be the input at T flip-flop. So, we
look at T flip-flop excitation table, so that says it should be 0.
When this is 0, 1 this combination, and next value is 0, it toggles ok. So, for T flip-flop
the input should be 1. For this combination 1 and 0, next value is 1, so that is again 0 to 1
T flip-flop toggles, that is input should be 1. And the fourth combination, when 1 and 1,
then the transition takes place here is 1. So, 1 to 1 T flip-flop should be 0, is it fine. So,
this side we are getting from excitation table putting this color, and this side we are
getting from truth table right. So, we have put them in one common table ok.
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So, now we understand that for this combination D and Qn that is external input and
current state, what should be the T flip-flop current input ok. So, to get equation out of
this. to get a equation out of this what we can put, we can get a get it through a Karnaugh
map I mean simply, so D is over here that is 0 and 1, and Qn is 0 and 1.
(Refer Slide Time: 12:21)
Now, we look at the cases, so 0 0 - T is 0, 0 1 - T is 1, this is the 1, 1 0, this is 1. So, this
is 1, and 1 1, this is 0 right. Now, what we find that this can be get, obtained only by
through two such you know, products terms, so D Qn prime plus D bar Qn ok, this is
what it becomes. So T becomes actually D XOR Qn, D XOR Qn right.
T = D.Qn’ + D’.Qn
So, you could have obtained it by as I said the you know, through an algebraic
manipulation and all. And knowing how XOR function works, XOR of you know XOR
of same function with the same XOR of one function with the same function is giving
you 0 right. And 0 with another variable will be the variable itself ok, one with 1 XOR
with the variable is complement of the variable, and 0 XOR with the variable is the
variable itself.
So, essentially what we are getting here is XOR of XOR, and then the variable ok, so
that if you are knowledgeable about the XOR operations and all. Otherwise, as I said
generally speaking, we can get it for sure by a standard method like this ok. And we can
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verify, so Qn plus 1 over here, we have got in this manner. We know the basic equation
of Q plus 1 sorry that is T Qn prime plus T prime Qn for this particular flip-flop right.
And then we substitute T as what we have got Qn and D XOR right, so that is this
relationship and over here ok. Then we do go through you know steps right, then we can
see that it is nothing but D ok. So, Q n plus 1 eventually becomes D right. So, this is the
way we can see that it is the T flip-flop, and this is D flip-flop. So, this is a simple you
know synthesis problem the steps we know - that truth table, and then this is what is
required for the input to be all those cases, and that is obtained through excitation table
ok.
Qn+1 = T.Qn’ + T’.Qn
= (D.Qn’ + D’.Qn).Qn’ + (D.Qn’ + D’.Qn)’.Qn
= D.Qn’ + (D’.Qn’ + D.Qn).Qn
= D.Qn’ + D.Qn = D
(Refer Slide Time: 14:54)
Now, let us look at another example ok, where we have JK flip-flop required from SR
flip-flop ok. So, given a SR flip-flop two you know two input and we require a JK flipflop. We can do it for any other type that is one type to another, so let us look at this one
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right. So, in this case what we have over here. In the first place as we have mentioned so,
JK flip-flop truth table is it ok. So, the one that we want to be made that truth table will
be put; that is there in the left hand side right. So, 0, 0 and if this is the case input is 0, 0,
0 - 0, 0 and Qn is 0 right. Then next value will be 0 only, and input is 0, 0 and this is 1,
next value is 1, because 0, 0 - the previous value is retained ok.
So, 0 1, irrespective of what is Qn, this is 0, 0. 1 0, irrespective of Qn, this is 1, 1. And
when it is 1 1, it toggles ok. So, 0 becomes 1, 1 becomes 0. So, this we are already
familiar. Now, each. in each of these cases now, for the SR flip flip-flop that is being
used for the design, at its input, what should be present - that we figure it out ok.
(Refer Slide Time: 16:25)
So, here we see a 0 to 0 transition ok. If Jn is 0, Kn is 0, Qn is 0 at that time ok, what
should be present at S and R. Since it is a 0 to 0 transition from SR flip-flop excitation
table, we can write, it should be 0 cross that means either 0 0 or 0 1 - any one of them is
ok. So, this is what should be present clear. So, if it is 0 0, instead of 0, if it was 1 ok,
then what would have been the case, the transition, it would have moved to 1. So, what
should have been present at SR flip-flop input at that time, it should have been X and 0
that is from the SR flip-flop excitation table right.
So, for this combination 0 1 0, J K Qn, then at that time 0 to 0 transition, again 0 X, 0
cross ok; 1 to 0, we need 1 to 0 is 0 1 right 0 1. So, again 0 to 1 ok, so this is 1 0; 1 to 1
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cross 0; 0 to 1, 1 0. And 1 to 0, 0 1. Is it fine? So, for these particular transitions, we
require these ok.
(Refer Slide Time: 17:55)
So, we can now understand that this part is the SR flip-flop excitation table, which is
deciding the entries right. And these part JK flip-flop truth table are deciding the entries.
So, this is this JK flip-flop truth table itself is it ok. Now, with this table in hand ok, we
now move to next step.
(Refer Slide Time: 18:18)
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So, next step would be that representing each of these inputs, each of these inputs Sn and
Rn at a given time as a function of Jn, Kn and Qn ok. So, the current state; current inputs
that is coming from external externally, because we are trying to convert it to a JK flipflop ok, so that is what we are having as current input; and at that time what should be
presented at SR flip-flop input, so that required change in the output Qn, required Qn
plus 1 value appears at the output is it fine.
(Refer Slide Time: 19:19)
So, from that truth table, the truth table, that we had just seen do a mapping from this
part Jn, Kn Qn ok and Sn and then Jn Kn Qn as R n. So, two such Karnaugh maps will
be there, two such relationships will be available ok. So, in one case this is what we get
right 0 0 1 1 cross 0 0 X right. This we can see from - so 0 0 0, you can see for Jn Kn Qn,
it is 0 Sn.
So, you can see it is S n right. Here 0 0 Q n is 1 this is X ok. So, you can see this is X; 0
0 1, this is X. Next is next is 0 and 0 right, you can see 0 0. Next is 1 1 you can see ok, so
this is the way 1 X right, and then 1 0. So, 1 X, and this is 1 0, because this is 1 0, and
this is 1 1 that is the way Karnaugh map is written right, so 0 X, 0 0, 1 X, 1 0.
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(Refer Slide Time: 20:29)
So, this is what you can see this is what you can see over here 0 X, 0 0, 1 X, 1 0 ok. So,
similarly for the Rn value, you can see the mapping is presented X 0, X 1, 0 1, 0 0 ok.
(Refer Slide Time: 20:58)
So, now to have a minimized expression for this right; so, we can see that one group is
required here, so that is coming as Jn remaining constant with value 1, and Qn with value
0, so Jn Qn bar. So, as we can simply write it this way, because we need to cover only
the 1s, that is the largest group possible. And for Rn, we can see that it is Kn remaining
value with 1 and Qn with value 1, so it is Kn Qn ok.
524
So, now we can get the circuit as we have - we see over here. So, this is your basic SR
flip-flop, this is your Q and Q bar right which is generated internally in the SR flip-flop.
So, J and K are the external input ok. So, in one case J is ANDed with Qn bar right the
connection is taken, and fed as S. And in the other case K is ANDed with Qn, and fed as
R ok. And this whole box which you see, the dotted box is your is final circuit, final
converted circuit - fine.
So, any flip-flop that you require which is from the characteristic equation or truth table,
you can, you know directly cannot convert ok, you can go through this synthesis process,
first you write the truth table. And then for the changes that is happening at Qn and Qn
plus 1 for a specific input, you write the input that is required for the flip-flop being used
from the store or library. And then you use the excitation table through Karnaugh map or
any other minimization process you get the combinatorial circuit made, and then finally
you implement it right, fine.
(Refer Slide Time: 22:50)
To end this particular lecture, we just would like to get you know, introduced to another
important concept is that of flip-flop timing parameters, its significance ok. So, as I said
the timing diagram is the key to exhibit how the things happen, work out with respect to
time, which is not very clear from the truth table, excitation table or other form of you
know representation. So, we take help of this timing diagram to discuss, to understand
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the importance of these timing parameters. So, there are quite of few, but we just take up
three important ones.
So, one is called setup time ok. So, this is minimum amount of time data must be present
before the clock trigger arrives ok. So, the clock trigger comes, so if it is a say positive S
triggered, you know kind of thing the it has arrived ok. So, whenever it reaches positive,
it is you know susceptible to change. So, before that some minimum amount of time,
data must be held at a stable value. So, this is called setup time ok. If it does not then, the
output cannot be guaranteed, manufacturer cannot guarantee the output ok. So, this is
one aspect.
And the other thing which comes in association with it, is called the hold time ok. So,
this minimum amount of time data must be held after clock trigger ok. So, clock trigger
has happened, you are not supposed to immediately withdraw the data. So, it must be
held for some time ok. The minimum time that is required you, if you hold it for more
time there is no issue, but certain minimum time it should be held that is called hold time
ok, so that is to ensure or guarantee appropriate output of the flip-flop, appropriate you
know, state change in the flip-flop ok.
And the other thing that is there is called propagation delay right; so, time taken for the
output to change after clock trigger in response to the input. So, basically it goes through
different you know logic gates, and there could be various basic components like you
know stray capacitances, resistances, so charging, discharging. So, all those issues are
there, because the basic gates we have already learned.
So, if you put together all of them ok, so the amount of time that is required for the, for
example here D was 1 so D is after clock trigger becoming - initially it was 0 becoming
1. So, the delay associated is called propagation delay ok. These three terms you take
note of. And if you go through the data sheet, you will see many other such you know,
terms are there timing related which are important ok, but that may occur in certain
instances of time not regularly as it is happening for the setup and hold time and
propagation delay.
For example, if you present an asynchronous clear right or asynchronous preset, so after
certain amount of time, only it will be reflected, it will - the output will get cleared or it
will get preset. So, there is a delay associated with it, but your, it is happening whenever
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it is required not you know regularly. So, those delays, and those parameters, those terms
are also available in the data sheet, if you look at it you can see that there ok.
So, to get an idea about what are the practical values some of the you know ICs or
circuits that are used. So, we take the D flip-flop one from TTL family ok, another from
CMOS family. So, you see that in TTL family the setup time is, these are all in
nanosecond ok. So, minimum time 20 nanosecond, hold time is you know, 55
nanoseconds - so 7474, 74LS74A ok. So, if it is again L means low power, so higher
resistance values ok. So, if it is only Schottky, S for Schottky that we know, we have
seen it in the logic family.
So, then the resistance values will be standard one. So, for which you will see the time
will be relatively less. So, these are you know, just the order that you get it, but for
different families with different realizations, we will be having variation around it ok.
And this propagation delay, so low to high 25 nanosecond ok. And this is 40 nanosecond
is high to low ok; this is the maximum delay that can happen.
And typical frequency of operation because of these delays and all; so that is 33
megahertz ok. And in this case, this CMOS thing, so you can see the setup time is like
this, hold time is approximately 0. In some literature, you will find it is written 0.5
nanosecond. So, this is the propagation delay, it has not been separated in the data sheet
low to high, high to low and f max has been mentioned as 50 megahertz ok.
(Refer Slide Time: 28:53)
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(Refer Slide Time: 28:54)
So, to summarize, conversion of D flip-flop to any other flip-flop is straight forward, if
we consider the characteristic equation. Conversion of SR and JK flip-flop to D flip-flop
can be done by comparison of their characteristics. The conversion of T flip-flop to D
flip-flop can be posed as a synthesis problem. In this, D flip-flop truth table, and T flipflop excitation table are required. And similarly, SR flip-flop can be converted to JK flipflop again though a synthesis problem. And setup time, hold time, propagation delay are
important timing parameters - for their reliable operation we need to take note of them,
and use the flip-flop triggering accordingly.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 36
Register and Shift Register: PIPO to SISO
Hello everybody, we are in week 8 of this particular course and in this class, we shall start
discussion on Register and Shift Register.
(Refer Slide Time: 00:29)
And we shall have a quick recap of what we had in the previous week and then we shall
go in to the new topics.
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(Refer Slide Time: 00:37)
So, if you remember we discussed flip flops in the previous week, its various
representations in the form of truth table, characteristic equation, excitation table, state
transition diagram.
And then we understood the issues that could be there with level triggered flip flop for
which edge triggered flip flop is advisable, which ensures only one transition per clock
cycle. And we also studied asynchronous preset and clear input, how it performs and how
it changes the output or the state without requirement of a clock trigger and which is useful
for initialization and various kind of resetting purposes. And we also looked at analysis of
simple sequential logical circuit and synthesis also from the point of view, conversion of
flip flop from one type to another and mostly we dwelt on flip flop as an individual unit.
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(Refer Slide Time: 01:55)
So, now we start discussion where we look at flip flops as a group ok. So, register is a
group of flip flops that can be used to store binary data and if we think of say a binary
numbers say 1001, if you want to store then we need of course, 4 flip flops ok. So, the
larger the number, larger the information - they will need as many number of flip flops
and together we are say, doing some manipulation. So, it will be a register level
manipulation that we are doing where all the flip flops within that particular group are
addressed simultaneously, are considered simultaneously ok.
So, for 8 bit flip flop, 8 bit register, we’ll be having 8 flip flops and the way we have seen
them, if you want to write something that 8 bit number or 8 bit information and then read
from it then the way we have done it before, we can think of you know, providing a specific
inputs to those flip flops and then reading it from the output ok.
So, directly loading it from the input side the way the flip flop truth table tells us - if it is
D flip flop then, 8 such flip flops 8 such D inputs will be there and the reading will be from
the 8 Q - outputs and if you want Q bar, then Q bar also can be made available. So, that is
the way of you know, writing and reading the way you have seen it before is called parallel
data input and reading is parallel data output.
So, in short parallel input parallel output or PIPO so this we have already seen. And the
data writing is done through clock trigger of course, synchronous with D clocks. So, in
one clock cycle the data is coming to the flip flops outputs and reading we can do as many
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times as we want just by accessing the output values of these flip flops, these 8 flip flops
- is it clear. Now one issue that might come from storing larger number of you know, bits
in the form of a you know, group; the number of input output port or pins that will be
required. So, if it is a 8 bit flip flop so you can imagine, 8 input pins will be required here
– ok. Then 8 output pins will be required here and if you want Q bar then of course, another
8. So, even if we do not consider Q bar so 8 plus 8, 16 then Vcc ground, then clock, then
usually there is asynchronous clear for initialization purpose.
So, you can consider, you can think of how many you know pins will be required and
standard packages you have seen 14 pin, 16 pin and all. So, this is going beyond that – ok.
And so for larger number of bits where we want to store and then we retrieve, these
parallel-in parallel-output may be an issue ok. So, you have to think of alternative and
when you think of those alternatives one idea that comes is to make it serial-in.
So, then comes the discussion or the topic of shift register ok, but then when you talk about
conversion from parallel to serial, time to read or write becomes an issue and the other
issue that comes into consideration is when you are you know, reading it, you are pushing
the data out of this you know shift register, so the data may be lost. So, all the things we
shall discuss in detail in today’s class and to get an idea about how to handle binary
information which is of, consists of larger number of bits clear ok; so, PIPO we have seen.
(Refer Slide Time: 06:29)
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Now, let us look at three other types one is serial in parallel out ok. So, what is happening
here? So, data is coming to the register serially ok. So, one bit at a time. So, to push 8 bit
of information, you need 8 clock cycles ok. So, in each clock 1 data will be pushed. So,
only 1 data input is sufficient, serial data input is sufficient instead of those 8 that were
required and reading is through parallel outputs ok.
So, then you are saving on the data input side number of pins clear; so as many number of
times you want to read you can read it no issue ok. So, this is one particular type ok. The
other type that can be there that data is sent to the register parallel; in one clock cycle all
the data is getting loaded unlike the previous case and then the - the reading part of it, the
first data that is in the endmost flip flop - that is available and then you need another, say
if it is 8 bit, so another 7 cycle to push data out of the flip flops we shall see actual circuit
and other things, we shall discuss elaborately later with examples.
So, that will be required and at that time, since the data is being pushed, so these data as
such on its own will be lost; so that becomes a destructive reading. And the third option is
- the fourth option here other than PIPO, SIPO, PISO parallel in serial out here serial in
parallel out there is serial-in, serial-out. So, that requires a list number of pins. So, data is
you know introduced in the register serially with say 8 clock cycles for 8 bits and data is
read also serially using the clock. So, data will be going out one after another ok.
So, to prevent this data being lost and all, so you can have a feedback kind of mechanism
that we shall see later ok.
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(Refer Slide Time: 09:07)
So, we said that we shall look at the actual circuit that are used ok. So, the first thing that
we see is a PIPO, parallel in, parallel out which we are already familiar with in one single
flip flop form, on one unit of flip flop that you have seen how it works. So, this is IC 74174.
So, this is a 16 pin package you can see – right. And it has got 1, 2, 3, 4, 5, 6 right 6 flip
flops, so 6 bit data you can store here right and for that there are 6 outputs; 6 outputs and
corresponding to that there are 6 inputs. So, whenever clock trigger comes, the clock is
common right and if you look at this inverter here inverter here together then it is a positive
edge trigger. So, whenever the clock trigger comes whatever is the data 6D here comes to
6Q directly. Similarly 5D comes to 5Q, 4D to 4Q and 1D to 1Q right.
And if you are looking for resetting it, clearing it then you can do all the flip flops together
right; so, it is a common clear. So, it is - 2 bubbles here and then a bubble so basically it is
active low - ok. So, if you put a 0 right irrespective of the other values you will see that it
is - it will become reset is it ok. So, the number of pins as you see, as many number of
inputs and as many number of outputs and parallelly it is getting loaded in one clock cycle
and you can do as many times of reading as you want without any issue ok.
Now, there is IC 74175 in which both Q and Q bar outputs are made available say, in some
application you require it – ok, and it is same 16 pin package which is similar to others 14,
16 packages that you are normally used ok. So, then since both Q and Q bar are there, so
you have to sacrifice the number of bits, number of flip flops that you can put inside the
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package ok; so it is a quad. So, 4 D flip flops are there in that particular IC ok. So, this is
the issue with parallel-in parallel-out ok, but it is also useful and you can make use of it
depending on your requirement.
(Refer Slide Time: 11:47)
So, next is the other extend let us see we shall look at a SIPO and PISO also in subsequent
classes ok. So, SISO this is again another practical circuit which is put into use through IC
7491 that we discuss here. So, in this what you see is, it is a 1, 2, 3, 4, 5, 6, 7, 8, 8 bit of
information you can store it here, 8 bit of information. So, Had it been parallel-in parallelout you can imagine 8 plus 8, 16 and so many other things that we discussed before.
But because it is a serial-in serial-out; so, a 14 pin package standard 14 pin package is
sufficient and in that also you can see there are so many of no connection - is not required,
NC stands for no connection ok. So, you have got a clock input common clock which get
is triggering QH and QH bar because there are pins available so you take both the Q and
Q bar as the serial out right.
And additionally you have got A and B where B you can consider as a control input. So,
when B is 1, B is high then whatever is the change in the A that goes to the flip flop I
mean, the flip flop is loaded accordingly, according to the variation in A. And, B is 0 then,
it is all 0 that is coming over there - is it fine, right. And, you see that there is no
asynchronous reset as such - asynchronous clear. So, with B keep kept at 0 control input
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and if you feed the clock then after 8 clock cycle all of them will take the value of 0 is it
fine, understood how this is organized.
(Refer Slide Time: 13:51)
Now, let us look at how this particular circuit can be used for I mean, how such SISO thing
can be used for writing ok. So, here we look at an example where I mean, we can use any
type of flip flop depending on our requirement. So, here we are using JK we shall see
example with SR also, D we have just seen - ok.
So, in JK flip flop what we are doing, we are just making sure that whatever is placed at J,
K will be just opposite of it ok. So, you can see in this timing diagram the serial input that
we are having. So, if you have a J here 0 the corresponding K is 1, 0 0 K is 1, whenever it
has become 1 immediately it has become 0. So, that is ensured you can put an inverter and
all at the - between J and K and feed the data from J ok.
So, that is the idea. So, that is the way you can do it - is very simple right, effectively it
becomes a D flip flop right ok. Now; whatever is there in the serial data input, in the
beginning we consider only the J part of it, K is just a you know inverted version of J. So,
let us consider that there is a 0 present here ok. So, with one clock trigger; so these 0 goes
to this place that is flip flop Q. So, we are naming it Q, R, S, T right. So, Q acquires this
value 0. So, that is how the arrow has been shown - is it fine? And there could be some
value present earlier in these flip flops.
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So, you do not need to bother about that because we have talked about writing a 4 bit data
into this 4 bit shift register through serial input, this is what we want to consider otherwise
it could be 0 or 1 depending on whatever is there ok. So, when you complete the writing
operation that data is lost of course, right. So, next value that we put is 0 at the input clock
trigger comes what will happen? This 0 comes to Q and this Q output is connected to input
of R. So, this 0 now comes to - 0 that was there over here in the next time point it comes
over here - is it ok, right. The other two we are not bothered.
Now, you present 1 at that time. With next clock trigger, 1 comes here right and this 0
comes over here and this 0 comes over here ok. So, S now has got 0, a R has got 0 and Q
has got 1 and before the next clock trigger occurs 0 is presented at the input. What will
happen? So, this 0 will come to Q, this 1 will come to R, this 0 is coming to 0 and this 0 is
coming to 0. So, four clock cycles have elasped and now Q, R and S, T are having value
0 1 0 0; 0 1 0 0 right. So, if you want to store so 0 0 1 0 so you can imagine that first you
have to give 0 then instead of 0 1 0 0 so if it is 0 0 1 0 kind of thing next you have to give
1, then you have to give 0, then you to give 0 ok.
So, this is the way you have to plan your entry of serial data input depending on what you
want to store. Is it clear? And, the example is given through timing diagram right. So, what
is of importance here is the clock edge right. So, it is a negative edge triggered that you
can see this is the negative edge, at which it triggers. So, at that time whatever is the value
that is present at for J so here it is 0.
So, Q ok - Q, R, S, T initially it has been considered - is 0. So, this 0 will be coming here
ok. This is the one that were talking about then its value is 0 here before the clock trigger.
So, this 0 is coming here and this 0 is coming there it is through the timing diagram same
thing ok.
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(Refer Slide Time: 18:37)
Now, before the next clock trigger you see that it has changed and when the clock trigger
comes it is 1 ok. So, this 1 comes here and this 0 comes here and this 0 comes here in the
next clock time period. So, this is way the time is you know, changing right and after that
- before the next clock trigger, 0 is there ok. So, this 0 comes here is already mentioned.
So, this 1 comes here, this 1 ok, this 0 and this 0. So, ultimately 0 1 0 0 at this time point
we shall see in this clock cycle after 1 2 3 4 - 4 clock trigger that is how the writing is
done. Is it fine? Ok.
(Refer Slide Time: 19:43)
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So, now we look at reading of it ok. So, you consider that initially it has been stored with
1 0 1 0 and this is the serial data out ok. So, 1 0 1 0 this is with which the flip flop is
occupied with and then one clock trigger comes. So, at the inputs side it could be anything,
whatever is there that would be post if it is 0 or 1 it will be pushed ok, but we are just doing
the reading operation and as we know that the way if we just read it this way something
else will come here which is not the actual data so that is, that is why it becomes a
destructive reading ok. So, in the first clock pulse this 1 will be coming over here, this Q
is the input to this flip flop ok. So, then now this is a D flip flop based shift register. So,
this 1 comes here and this 0 will come over here and this 1 will come over there ok.
So, in the first before the application of the clock as it is, you can read 0 and then after
application of one clock trigger you can read 1 the information there then one more clock
cycle this 1 will come here and this 0 will come here you can read 0 one here at this signal
data out at the output of T and finally, one more clocks trigger; you can see 1 over here
right. So, this way in this case since already one of the output was available, accessible
through serial data out ok. So, three more clock cycle you have got 0 1 0 1 all the bits read
by this, but in this process now the flip flop except this one which is having the value of
Q, rest of the values are you can say garbage or you can say some something else, but not
the one that your read ok.
So, this is by this you are actually having a destructive reading so that means, the data is
lost and this is shown through the timing diagram ok. So, in this case this 1 0 1 0 you can
see this is you and if you have if you are inputting you know 0 then at the input side then
the finally, the values will become all 0, if this was all 0 the inputted over here then one
more clock cycle all 0’s will be coming and the serial data out that you read over here is
like this is it 1010.
So, first you will read 0 here, then 1, then 0 and then 1 and if you continue to give 0 so 0
will come here.
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(Refer Slide Time: 22:51)
Now, if you are interested in reading the data multiple times not that once you read and
the data is lost ok. So, you may need in an application that you want to read the data
multiple times. It is not the case that you write once, that usually is the case, write once
and read many times; then you need to see that - for parallel-in parallel-out there was no
issue, isn’t it.
So, parallel out you can read it has many times so now, no data data is getting lost, unless
you are reloading it ok, but in serial out we have seen that while you are reading the data
from the output terminal what is being shifted either 0 or 1 or any other value, so original
data is getting lost ok.
So, one way to prevent that and effect multiple time reading is to use an external feedback
ok; so, the one that you see as a connection like this ok. So, what happens in this particular
case? What you are doing actually is every time you are reading something except for the
first case, first case you know you are reading it just like first bit. So, whenever your
reading the next bit say S you are writing this bit back over here, so reading and writing
are happening simultaneously and now you need you know, 4 clock cycles so that you are
back to the data that you are originally started with, ok.
So, if you had originally say 1010 you can read the way we have seen in the previous
examples so 0101 because you are starting with 0 only ok. So, you can complete the
reading what is there in three clock cycle, but then will be having 1 over here and you want
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to get back the number in its original form then you need one more clock cycle. Let us see
how it happens ok. So, this is the original one, 1010 with which you start the reading
process as well as simultaneous writing through a feedback and at that time, since this is
0, this 0 is fed back; this 0 is fed back here ok.
So, with next clock trigger what happens? This 1 comes over here, this 0 comes over here,
this 1 comes over here and you can read this as 1 like the previous case ok. But at that time
what you see, because of the feedback, this 0 information that was in T now is getting
written and it comes to Q ok. So, information of T 0, as 0 is not lost, it is coming back now
you have got 1 0 1 and 0 here earlier this was 1010; now this is 1010 and this. Is it ok?
Another clock at that time, this 1 comes over here.
Next clock, this 0 will be pushed here ok, this 1 will be pushed here right and then this 1
comes to this place at Q and R gets the 0 ok. So, right now this is 1 0 of the previous one
and this is 1 0 which is written back and this 0 is coming over here so again one more
clock cycle, this 1 will be coming and this is, this will be in your red color so this is 0
coming here and this is 1 and this is 0 - is it ok.
And this 1 is fed back here. So earlier in three clock cycle this reading was completed. 0
is originally available at 1 0 1 we have read in three more clock cycles. Now because we
want to read it as many number of times and you want to store the information in 1010
form one more clock trigger, so this 1 comes over here and this 1 is coming back and 1010
you get here ok. So, reading and writing is happening simultaneously. So, this is your non
destructive reading in a shift register where SISO option is only available ok.
Now, if you want that you know, you want to read it this way and also want to write
through external inputs the way you have seen. So, would you like to disconnect or again
connect this serial data input - that is possible or you can think of a you know 2 to 1
multiplexer kind of mechanism by which this input D over here for the first flip flop ok.
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(Refer Slide Time: 27:53)
So, D 1 is a select input. So, when it is 0 say your doing the reading so, that will be your
this T plus when it is 1 you are doing the writing. So, that is the serial input ok. So, you
just need to have a small circuit logic circuit over here by which if you put it in this manner
then it will be external writing when S is equal to 1, so this is serial in and this is external
writing and S is equal to 0 internal writing which is nothing but non destructive reading is it ok?
𝐷𝐷𝑖𝑖𝑖𝑖 = 𝑆𝑆�0 . 𝑇𝑇 + 𝑆𝑆0 . 𝑆𝑆𝑖𝑖𝑖𝑖
Have you understood this part SISO, how it works and how we can make use of it and
PIPO - we have already seen before ok.
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(Refer Slide Time: 28:59)
So, with this we come to the conclusion of today’s class. A register, we have seen that, is
a group of flip flop that can be used to store binary data - one bit of information storage
requires use of one flip flop. Parallel-input parallel-output option for data storage requires
largest number of input ports while serial-in serial-out requires the least - of the four
possible varieties that you have seen. The trade-off associated with serial mode is, I mean
using serial-in serial-out is larger number of like clock cycles required to complete write
and read operation ok.
So, there is the trade-off wherever you go from parallel to serial. Serial-out read operation
on its own is destructive, but if you can put additional circuitry then using feedback which
performs rewriting of the data back to the shift register, then the non destructive reading
can be implemented ok.
Thank you.
543
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 37
Shift Register: SIPO, PISO and Universal Shift Register
Hello everybody, this week we have started discussion on shift register. So, in the last
class we have seen parallel-in parallel-output option for register as well as serial-in and
serial-out ok. So, in today’s class we shall look at serial-in parallel-out, SIPO and
parallel-in serial-out, PISO how are they used and how they look like and also universal
shift register ok.
(Refer Slide Time: 00:47)
So, this is what we are going to discuss today.
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(Refer Slide Time: 00:49)
So, we start with a practical circuit which is used in the IC packages - IC 74164 which is
a serial-in parallel-out shift register I mean, register ok. Register as I said is a group of
flip flops which store binary information that you have seen before and if it uses shifting
option from one flip flop to another where input of one is made - output of one is made
as input of the other; so that is shift register operation ok.
So, if we look at this circuit, it is a 14 pin package ok. So, you have got 1, 2, 3, 4, 5, 6, 7,
8 - so 8 flip flops. So, 8 serial in parallel out so this QA to QH, A, B, C, D, E, F, G, H so
8 outputs are there. So, it can you can read it as many times as you want there is nothing
like destructive reading and all where serial out - reading through serial out is there and
these, but the data is written serially through serial input ok. So, in one you see that these
are the two inputs. So, one of them you can consider as a control input say B. So, in this
is low right. So, this particular input over here will always be low ok.
So, S input we always get low and R is always inverted version of R ok. So, that is the
way we usually store the data right. Effectively this one is D flip flop, it is two of them
are SR flip flop. We do not need additional inverter, isn’t it, to convert it to D because
directly we can connect and then internally and we can get the shift register action
performed - right ok. So, at A is - where B is 1 say the control input is 1 then, A,
whatever is the value of A, the data that you want to put in the registers that is group of
flip flops that will be passed through A and will get to those flip flops through clock
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trigger and this A and B they can interchange their role; one can become the control
input the other can become the data input. And, we have got asynchronous reset which is
active low and common one. We shall say how it works and all, also a common clock ok.
So, this is the way the circuit behaves and now you can understand that, while this is
your serial-in, through one of them and you can read the data out other than parallel data
output through QH also as a serial data out because it is internally connected as a shift
register one is feeding the other. So, if you keep you know, triggering the clock so
whatever is QH is immediately available, after that the QG will become available here,
after one more clock QF will be available here, after another clock QE will be available
here ok.
So, that way also, you can read all of them by triggering of the clock, but it will require
more number of clocks and you already have the option of parallel reading ok, but to
know that it is also possible to serially read it through QH, fine.
(Refer Slide Time: 04:45)
So, let us see how this serial in and asynchronous reset work in this particular IC. So, we
have given an example here. So, this is your clear - right. So, whenever this is
asynchronous reset, so whenever you are giving this clear so it become all reset ok. So,
clock start triggering over here and at every positive edge of the clock; every positive
edge of the clock - you can see from the truth table, it is positive edge triggered and also
you can see from the circuit that this positive edge triggered.
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So, every positive edge of the clock it gets a trigger ok, but as long as you know B is 0,
we consider B as the control input right then, even if A is high the - that is not getting
transferred to the output ok. So, at this positive edge whatever is the value it will remain
the same so that there is no change.
When B becomes high ok, the control input becomes high then, whatever is the change
in A that can go to the flip flops serially one after another. So, you can see this is one
positive edge right and when after you know clock has become, control input B has
become high and at the time at this edge the value over here is 0 for A ok, so QA will get
0 that is what it has got.
So, next clock trigger - before this clock trigger again A is 0 so QA will get 0 and before
this clock trigger you see that value is 1 so now, after that clock trigger QA has become 1
is it fine ok. So, similarly over here this becomes 1 and just before clock trigger you see
it has become 0, so it becomes 0, before this clock trigger this is 1, after that it is all 0 so
there are all 0.
So, this is how it would look like till the next you know, reset comes otherwise it is 0 it is
there, reset comes asynchronous reset immediately irrespective of the clock trigger, you
see the clock trigger comes over here it was here again it comes here, but it becomes - it
will become immediately 0 this effect is not very pronounced, but will see for the other
cases ok.
Now, what happens to QB? So, QA is fed as - output of Q you know A, is fed as input of
B right. So, this 1 up to this, this is 0, 0 so 1 will come over here, 1 will come over here,
0 will come over here and 1 will come over is it ok. So, this is the way it will proceed
and finally, you can see that this is 1101 for QE and after that Q F becomes 1100 like
this and this becomes 1 1 and it could have been you know 0 and 1 unless this
asynchronous reset was; reset was there and similarly for this one.
So, whenever this asynchronous reset occurs all of them become 0, after that when a
clock trigger comes like this, the reset has moved so as long as it is reset this line will
remain 0 ok, after the reset is moved so it is become you know, inactive right it has
become high so next clock trigger is here. So, at this clock trigger, at this clock trigger all
the inputs are 0 right so the outputs are 0 - is it ok.
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So, this is how the serial data-in comes and output you can read from QA to QH
parallelly directly and in the truth table also it is mentioned like this Qxn whatever is the
value – so, QB takes the previous value of QA with the clock trigger ok, QH takes the
previous value of QG just before the last clock trigger whatever the value was - that is
taken. So, this is how to read the truth table and corresponding timing diagram would
appear in this manner and also you understand how asynchronous reset works.
(Refer Slide Time: 09:39)
Now, let us look at the other variety parallel-in serial-out ok. So, again we take up an
actual circuit practical circuit which is in use which is IC 74166 ok. So, in this what you
see, it looks bit complicated slowly your moving into more complicated circuit. The first
one is parallel-in parallel-out, but then you see that. Because it has - it provides little bit
of you know, additional control operation. So, what is it? So, this particular block if you
look at it; so there is a inverter here and there is inverter over there. So, if you put them
into together basically it is a SOP realization that your having ok.
So, these SOP realization, you look at it for SA so this is shift here ANDed with serialin, this is your serial-in, do you get it. Sso shift here ANDed with serial-in I consider, this
shift, forget about the load part of it- ok. And then shift prime, so this is coming over
here the inverter, ANDed with A, that part is understood. So, what does it mean?
SA = Shift.Serialin + Shift’.A
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When a clock trigger comes; when a clock trigger comes at the input of the S flip flop
over here; SR flip flop over here and R is just taking the invert of S. If Shift is equal to 1
serial-in will be going as the input of SA and if Shift is equal to 0 so 0 bar so, this is 1, so
A will be going as input of SA. Is it clear? This part you understand. So, that means, with
clock trigger with Shift is equal to 1, serial-in we come here and Shift is equal to 0 the
value A will get loaded.
Now come to flip flop B so this is SB ok. So, what is happening at the input of it? Shift
whenever it is 1 so, this is the shift is equal to 1 so this thing ok. So, then QA is coming,
QA is coming to the input of SA and when shift is equal to 0, B is coming to the input of
SA ok.
SB = Shift.QA + Shift’.B
So, what does it mean? Whatever was the output of QA becomes output of QB after the
clock trigger. So, it is getting shifted, value of A getting shifted to B ok, flip flop A value
is getting shifted to flip flop B. Is it fine? And, if Shift is equal to 0 then this is getting
loaded by the parallel-in that is there which is B. So, similarly over here you can see is it
ok. So, this is parallel-in serial-out and serial-out is coming, you are taking from finally,
QH ok.
So, you can put it parallel-in just by simply you know loading it using this input control
input to be 0 and then for reading it, since there is no parallel-out available because there
are 8 flip flops then you will require another 8 output pins which is not there ok. So, you
have to read it from here, by triggering the clock which as such will be destructive, but if
you have a feedback and other mechanism that we shared, discussed before, then it will
be non-destructive reading. Is it fine? You understand how it works.
SH = Shift.QG + Shift’.H
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(Refer Slide Time: 13:59)
Now, we look at what is called universal shift register. So, we had seen you know, 4
varieties, parallel-in parallel-out ok. So, this is the one. Then serial-in serial-out in last
class and in today’s class serial-in parallel-out and parallel-in serial-out ok. So, in the
universal shift register, you have all these options available r- ight and of course, when
you make all these options available the sacrifice will be the number of bits you can
handle within a particular package ok.
So, that is another part of it, but if you require a versatile device to do - which can
perform any different operations shift right, shift left and all those things yes, in this
connection you need to remember the universal shift register offers both left-shift and
right-shift ok, so that means, data can have a left shift; that means, if it is A, B, C, D this
is the way the flip flops are organized. So, data can come to QD, then QC, QB and QA
this is way it can be shifted with clock or it can have right shift where data is coming to
QA this and then QA, goes to QB, then QC and QD, is it ok.
So, this is the bidirectional shift that is possible in universal shift register. So, let us look
at again a practical circuit which will help us in understanding how it works and we shall
look at inside circuitry as well. So, you can see this is IC 74194 right. It has got S1 and
S0 two control inputs right, not one - earlier shift / load there is only one control input.
So, these two control inputs, between them offer 4 possible you know, options 00, 01, 10
and 11 ok. So, for 00 we expect certain operation, 01 something else - 10 and 11 right
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and this is depicted in this truth table we shall have more compact and easy to understand
version of it in the next slide which I shall discuss shortly ok.
(Refer Slide Time: 16:35)
So, what else is there? So, parallel-in and parallel-out, you can see this is parallel out
because that option also need to be made available - it is universal shift register all
possible things, then shift left serial input and shift right serial input both the things need
to be - that can have bidirectional shift and other than that you have got clock and
asynchronous reset, active low clear and of course, Vcc and ground and it is a 16 pin
package - is it ok, right.
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(Refer Slide Time: 17:13)
So, let us see the circuit and how the truth table looks like in a compact manner. So, S1 S
naught being 00 then there is no change; no change means whatever is the value it will
be the same right. If there is a 01 it will be right shift, 10 this is left shift and 11 parallel
load because parallel-in - that is possible and parallel-out is always there because you
have seen QA, QB, QC, QD outputs are there.
So, this is the way the control inputs play into the circuit. So, we look at this circuit not
all 4 bits are shown, two ones are shown, but from that you can understand how it works.
So, first of all again the way we have done it for another shift register, another IC; if you
look at this output. So, this is your NOR, that is there is a bubble, there is a bubble so
effectively it is a AND-OR SOP you know, realization that you see here. And if you try
to write it in the form of Boolean equation for A so, this is your QA so this is flip flop A
right.
SA = S1’.S0’.QA + S1’.S0.SRSER + S1.S0’.QB + S1.S0.A
So, this is how it would look like right. So, if you look at this way. So, S1 prime S
naught prime so, S1 is here. So, S1 prime is this one, this line is S1 prime and S naught
prime ok. So, this line is S naught prime and this is your QA, so this is S1 S naught
prime, this is a S1 prime and this is your QA these are the 3 inputs ok. So, that is what
you see as the AND output which is ORd with rest of the inputs ok. Similarly, S1 prime
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and S naught you can see, this is your S1 prime you can see you know dropdown from
here and S naught, there are two inverters over here.
So, this is your S naught and that is ANDed with serial-in, shift right serial in and then
S1 is 1 and S naught is 0 ok; S naught is 0. So, this is the case it happens S1 is 1 here, S
naught is 0 this is the case these two points that is coming downward over here so, this is
this AND gate we are talking about ok.
So, in this, the input is coming from the previous stage. So, that is QA so, it is previous
stage is QB so it is coming from QB and finally, here S1 and S0 both are 1. So, this is the
case this is the AND gate so in this case A is coming over here. Is it clear - right. So, if
this is for happening for SA; for S D you know the other case you can see the first one is
self loading I mean, this its previous value is loaded so that is there no change case. So,
S1 and S0 both being 00, the second case a shift right.
SD = S1’.S0’.QD + S1’.S0.QC + S1.S0’.SLSER + S1.S0.D
So, earlier it was serial in this case it will be QC it is coming from you know it is right
shift. So, QC will be the input of this one right and for S1 being 1 and S naught being 0
right this was QB here so, the it is a left shift operation from QB it was coming to QA,
now there is no other flip flop after this so, basically then you have to consider serial data
in which is for left shift that was there in the IC one of the input ok. So, that is what is
connected here and finally, when both of them are 1, D is directly getting loaded, parallel
load is there is it fine ok. So, this is replicated in the, rest of the cases with the
appropriate values of here. Other things are similar right and this is asynchronous clear
and you know, and clock is common to all of them fine.
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(Refer Slide Time: 22:03)
So, now we understand how this universal shift register works. But one IC that often is
used in the lab is IC 7495 or 7495A. And it is not a universal shift register if you look at
the built-in things that are available unlike the previous one that we just discussed ok, but
we can make it work like a universal shift register by external connection. Since it is
often used in the lab and so I have taken, considered this as a topic of the discussion. So,
let us see how it actually looks like.
And. so this is a 14 pin IC ok. So, 4 bit you know, information can be stored. So, A, B,
C, D is the parallel-in and QA, QB, QC, the QD are the parallel output that you can see
and here you have got one control input, mode control ok. So, when mode is equal to 1 it
is parallel-load and when mode is equal to 0 it is right shift, it is right shift ok.
So, this is the way it has been configured and you can see one - two clocks are there one
clock is for right shift that is there, the other clock over here you see it is written left shift
within bracket load. So, the other clock is actually used for this parallel load which can
be also used for left shift operation. So, how that left shift which is not built-in we shall
see how to get it done ok. So, this is basically what is there and now we look at the
circuit ok.
So, this is again made through SR flip flop and so this is the mode control right, this is
serial input and if you look at just one of them over here. So, when mode is equal to 1 ok.
So, 1 comes here. So, this is your 1 ok, this is 1, this is 0 so another inverter, so this is 1.
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So, this split - this AND gate is now active the other AND gate input will be 0. So, this
will be 0. So, this is again a SOP kind of thing because of two bubbles two NOT gates
are there. So, it is AND-OR SOP realization. So, at the time this is 1 right and D, so D
comes as the input.
(Refer Slide Time: 24:55)
So, it is parallel load that is happening and for the other case when your mode is equal to
0, mode is equal to 0 ok. So you can see that this is your 1 and this is your 0 so, this
AND gate output will be 0 and this is this AND gate, the other AND gate it is taken from
here this inverter output. So, this is your 1 and then at that time QC is coming over here.
So, this is QC right. So, QC will be over here so QC output will go to the QD. So,
basically it is a QC is going to QD. So, similarly if you look at the others QB will go to
QC, QA to QB and for QA there will be serial input in. So, this is the serial input in for
mode is equal to 0 ok. So, this becomes 1- is it ok, right. So, that is your right shift
operation and at that time when mode is equal to 0 right, mode is equal to 0 you can see
that this clock is defunct ok; this clock is defunct - right at that time this is 1, so this
clock is, right shift clock is functional ok, so right shift clock is functional.
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(Refer Slide Time: 26:11)
And when mode is equal to 1, mode is equal to 1. So, this is 0; so this is 0. So, this right
shift clock is nonfunctional ok. So, at that time, this is 1 so this so called left shift or
parallel load clock. So, right now we have seen parallel load only. do not worry about the
left shift part of it ok. So, it is just doing parallel load through this clock at the trigger of
this clock - is it ok.
(Refer Slide Time: 26:43)
Now, let us see this popular IC 7495 how it can be used for left shift also ok. So, for this
we need external wiring ok. So, you see how the external wiring is done. So, you see this
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thing, this is external wire. So, QD; Q D is connected - this wire is going here, it is
coming here and then over here as input to C. So, instead of C, so C is the output parallel
load you know this is input, parallel load input was their C - QC.
So, QD output is now connected as at the input of C externally you connect this wire ok.
Similarly QC is connected to B input. So, parallel load input is there for the flip flop so
B. So, QB is connected to A right and QA is there as the final output ok. So, serial data
in will be coming through D and serial data output will be through QA ok.
So, how it is happening? So, the mode control part we have already seen. So, basically
when it is 1; when it is 1 right so, then this flip flop this AND gate, this AND gate ok,
this AND gate and this AND gate. So, they are active and the other AND gates - these
outputs are all 0, this outputs are all 0 because it is coming from here and this is your 1
ok. So, at that time, at this particular clock so left shift clock - so this is coming here this
is 1 and this is the clock we are talking about so, this is 1, so this is the clock and the
other case this is 0 so, this is not working. So, this is - this AND gate output is always 0.
So OR gate output will be taking this AND gate output.
So, this clock will be the one in consideration. So, at that time you are having your this
QD getting loaded through C, to flip flop C. QC is getting loaded through B to flip flop
B and QB to flip flop A and QA is available as the final output ok. So, this is the way the
left shift operations takes place ok. So, it is not built-in, but it works in that manner ok.
(Refer Slide Time: 29:33)
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So, we got an idea of the register and you know the parallel-in parallel-out and different
kinds you know shift registers that is a SIPO, PISO and SISO in today’s class as well as
the previous class as well as what is in the making of universal shift register. So, last
week, we saw flip flops as individuals and in these two classes we have seen them as a
group storing binary information and we have seen how to read and how to write for
these different configurations and with this we move to next class we shall see the
applications of shift register, other applications of shift register.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture - 38
Application of Shift Register
Hello everybody. We have been discussing Shift Register. In this class, we shall consider
certain Applications of Shift Register.
(Refer Slide Time: 00:25)
.
So, these are the few things that we shall have a look.
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(Refer Slide Time: 00:27)
.
So, the first of all - what we see is as one application of shift register is parallel to serial
conversion that we do through shift register that can be used for converting a parallel
stream of data that is getting generated; for example, in some process say 8 bit data is
generated, samples are generated which is coded, encoded by 8 bits. So, that is generated
one sample means 8 bits are getting generated and it needs to be transmitted to some
other place.
So, one option is to have 8 transmission channels ok, so that at the other side those 8 bits
will be appropriately collected, but having those 8 wires or 8 channels is a bit costly and
if the data rate with which this is generated is such that we can make a parallel to serial
conversion and quickly we can - at a higher rate, we can send it to the other side and
there we can collect it and convert through a serial to parallel conversion, serial input to
parallel output that kind of a shift register – then, we have a this data 8 bit data
appropriately received at the other side.
So, this is one thing that can reduce the cost of transmission by converting parallel data
to serial and having a serial communication between transmitter and receiver and of
course, we need to have an appropriate protocol to find out start of the data, message or
the information and the stop of it, so that next 8 bits again appropriately be picked up,
ok. So, the issue here is trade-off with the time that the rate with which you generate and
the rate with which you transfer, with which you transfer is transfer rate, needs to be as
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many times more depending on number of bits that is getting to converted, clear. So, this
is one thing that you can see on reduction of cost. So, parallel to serial and then, serially
it is pushed out through a shift register.
(Refer Slide Time: 03:01)
.
Next we can use shift register to introduce time delay and the input data stream
somewhere here - IC 7491, we have already seen, this is A, B - is the control input, ok.
When we are keeping it at high, then whatever is the input at A, right. So, at that time
sorry, when B is at low whatever is been put at A, we have to go by this truth table (If B
= L, QH = L. If B = H, QH = A).
So, whatever is the input at A, that is getting transferred to the output after 8 clock delay,
right. So, that is IC 7491. We can have 4 bit shift register then it will be after 4 clock
delay. So, the same variation that you see over here, so that will also be available here. Is
not it – right. And, this clock - the clock time period multiplied by the number of flip
flop units that is there in the shift register will be giving you the total delay between this
input and output and that will give you the time by which the binary data stream is
getting delayed, ok. So, if the clock is of time period - is of 1 microsecond duration, then
by this arrangement we will get 8 microsecond. If there are 4 flip flops in the shift
register, it will be 4 microsecond.
So, if the clock time period is 2 microsecond, in this case it will be 16 microsecond
delay. Is it clear? So, how you can you know, having clock generated which is of
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different time period? One convenient option is that of using IC 555, ok. So, triple five
timer is very much used and this is in astable multi vibrator mode in which are RA and
RB - through RA and RB this capacitor gets charged for which the charging time is
0.693 multiplied with RA plus RB - this is resistance values and capacitance. And for
discharge, discharge happens like this. So, discharging time is 0.693 multiplied by RB
into C. So, total time period is like this.
So, with appropriate choice of RA RB and C you can fix the T value time period and
accordingly the delay can be introduced clear, right. So, next we look at application of a
shift register in sequence generation, ok.
(Refer Slide Time: 05:57)
.
So, here we are thinking about we are - that a particular sequence will be generated
repetitively ok. So, there could be an application where we are looking at a particular
pattern coming say 3 times or 4 times which cannot be random. So, basically that serves
as a pilot or a header or something else to follow, ok. In a random message somewhere a
pattern, like a particular pattern may come, but it is getting repeated number of times it is
unlikely, it is unlikely ok.
So, that could indicate that certain events are to follow or just after that, ok. So, there
could be other applications as well for a sequence getting generated repetitively. So, for
that we can think of a shift register. And a shift register, like a 4 bit shift register over
here - see it is loaded with 1 0 1 1, initially and after the output of it is fed back to the
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input of it the way you see here and if you now clock it, then what will happen this one
will go out right. This one is going out and after that this one will come out and this one
is fed back here after that 0 will come out and after again another clock 1 will come here.
So, another clock. So, this 1 will come up. So, this is the way it will keep circulating and
this pattern 1 1 0 1 will keep getting generated. Is it ok?
Instead of 4 bit if you have got a 8 bit shift register and say we have loaded it with 1 0 0
1 0 0 1 1 0, right. So, again the output of it is feed back as input of this one. So, 0 1 1 0 1
0 0 1 it will - it is getting generated. So, one cycle is getting completed. So, other one
will, the next cycle will start with another 0 and this particular pattern will get repeated
ok. So, a 4 bit you can get 4 bit pattern, 8 bit 8 bit pattern ok, but if you say in some case
you are loading it with say 1 0 1 1 again 1 0 1 1. So, what will happen of course 1 0 1 1
will come in one cycle of 8 twice. So, basically you are generating a 4 bit pattern, ok. So,
if you appropriately load it, then you can get n-bit pattern out of n-bit shift register the
way we have configured it. Is it fine? So, that is what has been mentioned over here.
(Refer Slide Time: 08:43)
.
Now, comes sequence detection. There also shift register can be useful, ok. So, by a
sequence detection what we - what we mean is that identifying a specific pattern from
the incoming bit stream, ok. So, here this is the serial data in the bit still it is coming, and
which is made to go through a shift register and this shift register is used for the pattern
matching sequence detection, and the sequence to be detected we can store it in another
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register, right. So, for example if we want to detect a pattern in the incoming stream 1 0 1
1 we can store it over here in a register, otherwise we can connect it to Vcc. For 0, you
can connect it to ground; 1 again to Vcc and one to Vcc. So, that is hard-wired ok, but if
you want to change the pattern that we want to detect, then again we have to physically
disconnect and connect this Vcc and ground. Alternative is to use a register like this. We
can load the register with another 4 bit number which will be detected for a different
occasion if so required.
So, that is the advantage of having a register in place of hardwiring the bit values that we
want to detect. And here what is happening? So, look at a particular case. The outputs of
this bits that are to be detected they are made to go through XNOR gate each of these are
going through XNOR gate - XNOR gate you know, at the output indicates a equality of
the inputs. So, if 0 0 and 1 1, then the output will be 1. XOR if 0 1 and 1 0, the output
will be 1. So, XNOR is just opposite of it. So, when the input is 0 0 and 1 1, then the
output will be 1. So, that means, it is actually giving the logic for equality equal whether
it is 0 0 or 1 1. In either case the output will be 1 and all these 4 bits when they are equal
this AND gate output will be 1 indicating a match or detection of the specific sequence.
So, the example - in this example at this point of time 1 0 1 1 is to be compared and we
have got 0 1 1 1 in the incoming stream which is stored in this shift register, ok. So, what
we see 1 and 1, this 1 and this 1 - it is compared. So, it is generating 1, this 1 and 1
compared. So, this is generating 1. Now this1 and this 0 will give you 0, this 0 and this 1
it will give you 0. So, this AND gate 1 ok, then this is 1, the rest two are 0. So, the output
is 0.
Next what happens? This 1 one gets here, ok. So, what will be the modified values of
this shift register because it is getting shifted as whole to the right.
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(Refer Slide Time: 12:09)
.
So, now this is 1, this is 0 this is 1 and this is 1 is not it 2. So, all these now - XNOR
gates having same you know, equal values 1 1 here, this 0 0 over here, 1 1 over here. So,
all of them will give you an output which is 1 and the AND gate output will be 1. So,
that is this sequence is detected. So, that is the way we can make use of this shift register
where the incoming this bit stream will pass through a shift register.
(Refer Slide Time: 12:45)
.
Next, we can see use of shift register what is the called, getting ring counter, ok. What is
a counter? Counter keeps count of a particular event. In this case the clock trigger in this
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particular example ok, but it that event that trigger can come from some other place also.
So, when it reaches a specific number, we say the count of something has taken place,
ok. So, if we say counter which is giving a value, modulo value of 8, modulo 8. So, it is
counting 8 and when the count of 8 is completed, an output is triggered - an output signal
is made active. So, that is how the counter works. So, it keeps a count of the input that is
triggering the circuit in certain manner and internally the state change takes place in such
a manner that it gets incremented and when the count, a specific count has been
achieved, an output is activated. Is it clear? So, that is what we understand as a counter
circuit. More about counter we shall discuss next week.
So, when we talk about this shift register as a counter, so we are using the shift register
again you know, in a feedback mode and in this case unlike this sequence generator
where we are putting a specific sequence, we are putting in one example - all of them are
0s and only one value is 1, ok. So, this is how we are starting and then when so that when one, so, this is the case over here. So, this is 1 and all these values are 0 and then
with one clock trigger - clock trigger is getting now counted here as I said. So, what will
happen - this 1 will come over here. So, this is the 1 right and rest of the values will be 0.
So, this 0 pushed here, this 0 is pushed here and this 1 is getting in - it is becoming 1. So,
that is what you can see that rest of the values are 0 - 1, this is 0, this is 0, all of them are
0 and one more clock what will happen.
So, this 1 will come over here. That is what we know as shift register operation, we have
discussed in the previous classes, ok. So, next time, this 1 will come here, right. Next
time - next clock, this 1 will come here and after 8 clock you will see that this 1 is again
appearing over here. Is not it? So, if you have connected an LED or some output action
and also from this point another time when it is getting, it is getting a high input and say
the LED is glowing, then you have, you have - you can very well say that 8 clock trigger
has taken place in between say, count of 8 has been completed, clear and this can be
achieved by any shift register with 8 such flip flop like 74164 you can take and then, the
feedback can be taken from that. You can achieve the way we have achieved a mod 8
counter.
So, in this case the flip flop output directly, the last flip flop output the way we have seen
it, itself indicates the count of 8 has taken place, right.
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(Refer Slide Time: 16:37)
.
So, if we have instead of this one, right so 0 0 0 1 and 0 0 0 1 initially then what will be
the account by this particular shift register. So, 1 is coming here, again 1 will come here
after 4 clock pulses, right. So, it will be a mod 4 counter right, but with this ring counter
arrangement as many number of flip flops if it is n-bit shift register maximum, we can
get a mod 8 – mod n count, ok. So, that is what is mentioned ok, but we can get less you
know depending on how we are initialising the flip flop, clear.
(Refer Slide Time: 17:25)
.
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Next, we look at another type of you know, feedback by which what we get is called
Johnson counter, ok. So, in Johnson counter this is the flip flop right and this is the shift
register. So, the output of it is inverted and sent as input to the first flip flop. Is it clear?
So, serial data out is inverted and fed as input - to the input of serial-in input. Now, if the
arrangement is such, that shift register is such, that inverted output is available at the
serial out, as serial out, then you do not need this extra inverter. So, that inverted output
you can feedback as serially.
So, this is the making of it because of which it is also called switched tail counter or
twisted tail counter, right. Popular name is Johnson counter, but it is also called switched
tail counter or twisted tail because tail is twisted when it is inverted that is that is the
meaning of it.
Now, how this particular circuit works. So, if we initialise it with say 0 0 0 0 then - take
this example. So, this T prime is getting fed back as a serial-in ok. So, 0 is coming here
as 1, right. So, 1 will go as input and rest these three 0s will come here as this three 0s,
clear. So, now it is 0. So, what will be coming as input? Serial in is 1. So, this 1 is
coming here and this 1 is getting in. So, these 1s and these two 0s will be coming as two
0s - still it is 0, what will be fed back is 1.
So, this 1 is coming here. So, three 1s, this is 0 again. Still it is - T is 0. So, what is fed
back is 1 - T prime. So, this 1 is coming here and all three 1s, it is following - these three
1s. These three 1 is coming here as this three 1. So, four 1s have become after that what
will happen. This 1 now fed back as 1 prime which is 0. So, 0 gets in this these are three
1s, then 0 0 gets in. These are two 1s, then 0 0 0 gets in. These are 1 and what next - this
1 will go back. So, it is 0. So, all 0. So, this is all 0 means again it will get repeated. Is it
fine?.
So, what we see, in this case, that we can we are getting the it is getting repeated, the
sequence state is getting repeated after 8 clock pulses, ok. So, it can give a count of 8
clock pulses, right and this is, this is a in that sense, with four such flip flops, 4 bit shift
register we are getting a count of 8. So, modulo number is 8. So, that is the Johnson
counter providing you. So, with n bit shift register, it can be extended. So, if it is 5 bit
shift register or 8 bit shift register, it will be 10 or 16. this count that can be achieved
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OK. Now as I said we the external world needs to know that when that count of 8 or 10
or 16 has been completed, isn't it?
So, it is the internal states that are getting circulated that are getting repeated after 8
clock pulses as we have seen, but the outside world need to know right for that it need to
be what is called decoded and - the states need to be decoded and made available to the
outside world, ok. So, in ring counter, we saw that no other external circuit is required.
The output flip flop directly is made, can be made available to the outside world and
whenever it goes high the means count of 8 has taken place. Is not it? But in this case, if
you consider a similar scenario say T is 0 over here over here over here it is 1, but it is
remaining 1 again. It will become 1 after 4 clock pulses. So, if you only take it from T, it
is not going to work. Similarly, from S from R from Q if you try, in none of the cases
you can see that a modulo count of 8 can be ensured.
But what you can see, what you can see right - that if you take only say Q and T prime Q prime and T prime – that means, both of them are 0, that is occurring again over here,
right. In between in any of these states, it is not your 0 and 0. Is not it? So, if you take a
logic like this and then is this output, it will become 1. Once here again over here after a
count 8 has taken place after 8 clock trigger has taken place. Is it clear? It is possible to
have all these four that means, Q prime R prime S prime T prime right, but that will
require a 4-input gate. So, that is a more complex circuit we are talking about the
minimal requirement. So, earlier no external gate is required. Here we need a gate with
that is 2-input logic gate, and we can see other than this Q and T prime you can have
other combination also.
Y = Q’T’
So, for example this 1 0 ok. Q is 1 and R is 0. So, this is again occurring over here. So,
once it occurs right, it will again occur after 8 clock pulses. So, that could also be a
decoding logic. Is it clear? So, decoding logic for Johnson counter as you have seen in
this case requires a two input logic gate.
Y = QR’
Now interestingly you can work out, it is for 4 bit shift register, you can work out for 5
bit shift register, 8 bit shift register, any other and for Johnson counter you will see that
every case what you would be requiring a, only a 2-input logic gate - more than that is
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not required, more than that is not required OK. With a two input logic gate, even for 5
bit or 8 bit shift register working in Johnson counter mode giving you modulo 10, 16 or
whatever I mean depending on that number twice the shift register siz,e a 2-input logic
gate is sufficient for decoding, ok.
So, this is the way we can see that it works and you can think of other kind of
initialisation also and we can see that it is - it progresses in this manner, ok.
(Refer Slide Time: 25:55)
.
So, with this we come to the conclusion of this class. What we have seen is that parallel
to serial conversion at transmitter end, serial to parallel conversion at receiver end help in
reducing number of transmission channels and shift register comes useful there because
after parallel to serial conversion then the data is made serially out and their lies its
utility. And you also saw that serial data can be appropriately delayed by selection of
clock period and also the size of the shift register used, Ok. If n bit shift register and
clock of T time period is used, then nT is this delay in this case.
With serial data out fed back directly as serial data in which shift register can generate up
to n-bit long pattern repeatedly, repetitively. So, there you can use shift register as
sequence generator
And shift register can be used as sequence detector also to identify a specific pattern in
the incoming bit stream where we are doing a bit by bit comparison, XNOR gate is used
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and XNOR gate outputs are going to a multi input AND gate and that AND gate output
is if, when it goes high that means, the pattern is detected.
And n-bit shift register in ring counter configuration can act as a modulo-n counter and
in Johnson counter configuration as modulo-2n counter. And for ring counter
configuration we do not need any decoding logic, extra decoding logic, but for Johnson
counter we need 2-input logic gate for decoding purpose.
Thank you.
571
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 39
Linear Feedback Shift Register
Hello, everybody. In the last class we saw certain application of shift register and there
we saw that a feedback of the serial-out as serial-in can give rise to Sequence generation
Ring counter, Johnson counter. We shall look at what is called Linear Feedback Shift
Register in this particular class and its different uses.
(Refer Slide Time: 00:37)
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(Refer Slide Time: 00:45)
.
So, by linear feedback shift register what we actually mean that the shift register outputs,
it is say length 8, you will consider x1 x2 x3 like up to say x8, ok.
So, it is going to a block where there is a feedback function and that feedback function is
generating an output, and that output is getting fed as serial-in. And when we say linear,
so this general case, linear means this function has got a linear relationship, the equation
that you are having is a linear relationship, ok. So, in this case we write it in this manner
C1 x1 plus C2 x2 to C8 x8 and these coefficients are either 0 or 1, this is a binary world.
So, it is 0 or 1. So, 0 means there is - this value is not used, ok. So, in another sense,
there is no tap from this shift register output to this feed feedback function generation
logic, ok. So, that is not there.
y = C1x1 + C2x2 + C3x3 + C4x4 + C5x5 + C6x6 + C7x7 + C8x8
And if there is 1 present that means, that particular tap is present. So, that is how this Cis are defined, either 0 or 1 - tap is present or tap not present. And this plus is the sum
operation which is obtained through XOR. So, this is the way the circuit is developed
and if we look at an example, so y is x1 plus x2 plus say, x7, right. What does it mean?
y = x1 + x2 + x7
So, x1 x2 and x7 - so, these three taps are used, these three taps are used and they are
these three inputs are summed up here. These three outputs of this shift register is
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summed up here and fed as input to the - input y as serial in. For example, if the flip
flops - this shift registers is initially loaded with this value 1 0 0 1 1 0 1 1 ok, then x1 x2
and x7 are these values, the ones in the bold, right.
Then y will be 1 XORed with 0 XORed with 1. So, the value is 0. So, 0 will fed back.
So, with clock trigger what will happen? So, this 0 will come here. So, everything else
will get shifted 1 0 0 1 1 0 1 will come over here. So, at that time your x1 x2 x7 are the
ones in the bold. Again here 0 1 0, so 0 1 0; so, now the value is 1. So, next value - 1 will
be getting in, and rest of the values will be shifted, and when we say non-linear that
means other than sum operations. So, this is x1 AND x2, then sum x7. So, these are the
things that come under non-linear feedback which we are not discussing here; our topic
is Linear Feedback Shift Register.
y = x1x2 + x7
(Refer Slide Time: 04:11)
.
So, what we have seen that is redefined in a manner by which we introduce the term
feedback polynomial. So, in this, instead of x1, x2 up to x8, we represent the output of
this shift register of length 8 as x to the power 1, x to the power 2, x to the power 3, x to
the power 4 etcetera up to x to the power 8 as if you know, each one of them is delayed
by 1 unit. So, delayed by 1 unit – d, delayed by 2 units d into d - d square. So, d cube, d
4. So, this is the idea, ok. So, in this sense you have got x to the power 8 up to here, right.
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And the input to it, it is not delayed. It will come to the output after one clock trigger.
Isn't it? So, this input is represented as x to the power 0 or 1, x to the power 0 or 1.
f(x) = 1 + C1x1 + C2x2 + C3x3 + C4x4 + C5x5 + C6x6 + C7x7 + C8x8
So, this 1 you will see in the polynomial that the function is you know, getting
represented and usually in many cases since it is length 8, requirement is of - that of
length 8. So, x to the power 8 is also, would be visible. If it is of length n, so x to the
power n is also expected to be there, but there could be another way the polynomial can
be generated without that and in between wherever the connection is there; that means,
these Ci values are 1 – the tap is there otherwise it is 0, right. So, for n bit shift register
with the degree we say will be of n; 8 bit here - the degree is 8 and these are some
examples and if it is x8 x7 and x1, ok. So, x8 x7 and x1, so x 8 x 7 and 1 is this 1. So,
what does it mean actually?
f(x) = x8 + x7 + x4 + x2 + x + 1
f(x) = x8 + x7 + x2 + x + 1
f(x) = x8 + x7 + 1
So, these two are getting XORed and fed as input. So, this is the meaning of this
polynomial. Is it ok? Tap from bit 7 and 8 are XORed and fed as serial input to bit 1.
(Refer Slide Time: 06:47)
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Now, such an arrangement can give rise to, can generate pseudo random sequence.
Sequence generator we have seen - where we had seen a particular length if it is 8 bit, it
is you know, 8-bit long it was, right. Here we see what happens when we connect in a
particular manner; so here that is 4 bit shift register. So, this 4 bit shift register, this S and
T are XORed and is fed as serial-in. So, in terms of polynomial, feedback polynomial
just now we have defined, this is x to the power 3 and this is x to the power 4, and this
and this input is 1. So, we will be representing this as x to the power 4 plus x to the
power 3 plus 1, clear.
f(x) = x4 + x3 + 1
This arrangement can be re-written as this the meaning is the same, ok. So, if this thing
happens, then let us see how the - with clock, these states will evolve and what will be
the serial-in in each case. So, it is - if it is initialised with say 0 0 0 0, what’ll happen? If
it is all 0 0 0 0 - so, 0 0 XORed output is 0, ok. So, this 0 will be fed in. So, again next
value will be 0 0 0 0; so it will remain locked. So, it is not to be initialised with 0 0 0 0.
So, let us consider instead of all getting cleared, all was pre-set ok. All the flip flops
where preset and it was initialised with 1 1 1 1. If there was no preset option, then it was
serially or parallelly loaded, but somehow we have initialized the shift register with a
value 1 1 1 1 ok. Then what will happen? These S and T are XORed, 1 and 1 is XORed.
So, serial-in will be 0; so, next value will be 0 1 1 1.
After that, this 1 and 1 again this 1 and 1 XORed, it is 0. So, again 0 comes and the rest
of the things get shifted; so it is 0 0 1 1. So, then this 1 1 again 0; so this is 0 0 0 1. Now
0 and 1, this is 1; so this is 1 0 0 0. So, this way you will continue, you can work it out.
And, you can see, you can see - unlike the sequence generator which was of you know,
length 4, in this case this output which is the - you know you can take as final output of
it, continues up to a length which is 15.
After that, again it starts repeating. After that. it again it starts repeating and the numbers
you can see you here these 0s and 1s, it is what is known as pseudo random, ok. It is not
exactly random in the sense because it will repeat after some time and if you have
number of these n bit shift register, the value of n is large then of course you can
understand that the length will be very large.
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(Refer Slide Time: 10:07)
.
And the formula that is used for such case is the maximum length that is possible is 2 to
the power n minus 1, 2 to the power n minus 1. All these 0 0 0 0 - that particular state is
not acceptable, ok; rest of the things are getting, these rest of the things are getting
circulated, ok. So, with a higher value of n you can understand that these will get
repeated after a long value, this sequence will be very long, and almost equal probability
of 0s and 1s that is present in this particular sequence, clear.
So, this is one particular way you can generate pseudo random sequence using shift
register, and you require minimum you know, hardware you know, additional hardware
and you can move very fast, ok; these things can be done in very fast manner.
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(Refer Slide Time: 11:11)
Now, it is to be noted that the feedback that you take - any kind of feedback will not give
maximal length, ok. So, for example, again for a the 4 bit shift register, we are talking
about instead of x 4 and x 3 if it is x 3 and x 2, they are XORed and fed as serial-in, so,
the corresponding polynomial is x3, x to the power 3 plus x to the power 2 plus 1 and we
initialize it with say, 1 1 1 1, then this serial in is 0. So, 0 1 1 1 and that way you
continue.
f(x) = x3 + x2 + 1
We shall see that over here it becomes 1 1 1 0, ok. After that again this 0 comes over
here, this is T ok, this is Q R S T, this T comes here. So, it becomes 0 1 1 1 1. So, this 0 1
1 1 again repeats here. Of course, after that it will, repetition will start. So, 1 2 3 4 5 6 7.
So, this cycle length becomes 7. Earlier, when it was taken from x 3 and x 4, x to the
power 3 and x to the power 4 and it was 1, it was maximal length that was 15 possible 0
0 0 0 0 was ruled out, ok. So, it will remain locked. So, this is to be noted.
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(Refer Slide Time: 12:53)
And that gives us - brings to the discussion of discussion on primitive polynomials. So,
not all polynomials will give us maximal length. So, the one that gives us the maximal
length are called, is called primitive polynomial, ok.
So, the example that you can see; so these are the polynomials that requires minimal
number of minimal number of XOR gates for a given degree; so, provided a table. So,
for degree 2, 3, 4, 6, 7 ok, so x to the power n plus x plus 1 that will give a primitive
polynomial; this is not the only one. I shall tell more about it shortly. So, but this will
give you a primitive polynomial, right. So, for example if it is a 7, so x to the power 7
plus x plus 1, 1 is the input that is coming here. So, 7th flip flop and the 1st flip flop
output right, XORed together and fed as input, it will give a maximal length and
maximum maximal length will be 2 to the power 7 minus 1.
So, that is how it is there. So, for 5, x to the power 5 plus x to the power 2 plus 1; so, 8 9
10, so this is what has been arrived at after checking with different combinations. Now,
in each of these cases when you look at it - right, and what you can find that the
necessary condition - it is not sufficient; when you look at it, right and what you can find
that the necessary condition - it is not sufficient, but it is required that number of taps are
even ok. Number of taps x to the power n and x. So, x that is x to the power 7 and the 1st
flip flop and 7th flip flop; 5th and 2nd; 8th 6th 5th and 1st ok. So, 9th and 4th; 10th and
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3rd ok. So, we have shown it up to say 10 degree, but you can extend and you see that
always the number of taps are even.
And the other important thing is the tap numbers are co-prime like 7 and 1, 5 and 2, 8 6 5
1, 9 4, 10 3 relatively between them, ok. There is no common divisor other than 1 ok. So,
that is a necessary condition, but it is not a sufficient condition. The other thing
important here is - if the tap sequence of n bit linear feedback shift register generating
primitive polynomial is in n, m, l, k and 0 - n means that if it is a degree 8, the last flip
flop, so that is n and 0 is the input that is coming here to x to the power 0. So, n and 0 are
there and in between these are the different taps. Then if that gives a primitive
polynomial, then n minus n, n minus m, n minus l, n minus k, n minus 0 right which the
first one will give you 0 and the last one will give you n. So, basically they do remain,
ok.
And other value is just n minus the other one, the particular tap number ok. That will also
give a primitive polynomial that will also give a maximal length sequence and pseudo
random number getting generated of the particular length. For example, in this case if x
to the power 5 plus x square plus 1 is a primitive polynomial, then n minus n is x to the
power 5 minus 5, 5 minus 2 and 5 minus 0, right. So, x to the power 5 plus x to the
power 3 plus 1 is also a primitive polynomial. So, if you take it from 5 and 3, XOR it and
feed it as input, that will also generate maximal length. In this case, 2 to the power 5
minus 1 long sequence, which will repeat pseudo random sequence.
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(Refer Slide Time: 17:29)
.
So, what we had discussed so far constitutes external feedback, ok. So, there can be
linear, there can be internal feedback also if provision is there by which these
polynomials can be generated and implemented, ok. So, internal - using internal
feedback if we are implementing the polynomial x to the power 4, x to the power 3 plus
1 which was maximal length in case of the external feedback which you have already
investigated, so then how it would look like. So, x to the power 4 and x to the power 3,
they are XORred and fed as input to the flip flop over here and of course, x to the power
4, this is coming over here as 1, x to the power 0.
f(x) = x4 + x3 + 1
So, this is how it would look like with internal feedback and with this internal feedback
again if you look at an initialisation which say 1 1 1 1 right and then, you can see for first
few cases you can examine. So, here S and T are XORed. S and T are XORed 1 and 1.
So, the output is 0; so S and T, so this output is 0. So, 0 will be fed back here. So, next
clock right this is becoming 0. And this was 1 - 1 is fed back here 1. And these other two
1s are getting pushed, ok. This two 1 is getting pushed here, this 1 is coming over here
and 1 1 XORed is 0. So, that is getting 0. Is it ok? So, next this 0 will come over here
like this, right. This two 1 are getting pushed over here and now 1 and 0 XORed is 1, ok.
So, this 1, this 1 XORed 0 is coming over here. So, this is the way it will evolve and if
you progress, you can see that it is coming to four 1s again after 15 clock trigger, after 15
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clock pulses, ok. So, this also x to the power 4 plus x to the power 3 plus 1 gave
maximum length for external feedback. For internal feedback also we see that it is giving
maximal length. But in this case this pseudo random sequence that is getting generated is
1 0 1 0 1… so, whatever you see over here and for the other case we saw something else,
ok.
So, that number getting generated and fed as you know, serial-in could be different, but
maximum length is there for both the cases, ok. So, this is one important thing. We take
note of that. Primitive polynomial for external feedback also works as maximal,
primitive polynomial for internal feedback and generates pseudo random sequence, clear.
(Refer Slide Time: 20:51)
Now, we look at again, this particular arrangement, configuration. Earlier it was actually
involving only from internal state values and the feedback that is getting generated.
Now, the feedback is there. In addition, we are putting an external input, and would like
to see if it is of any use. Yes it is of important use in error control as error control code
generation, and this is used in what is called a Cyclic Redundancy Check code, CRC
code ok. So, I shall take you through an example and see how it is useful. So, the
polynomial here used is x to the power 3 plus x plus 1, right. So, that means this is 1 2 3.
So, this one this one, first one it is fed back, this x 3 x 1. So, this is through internal
feedback this is fed here and this one that is coming over here that is getting XORed with
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the incoming data stream which we call as say, message which we want to code. Is it
clear?
g(x) = x3 + x + 1
So, x 3 plus x XORed here going here and 1 is coming over here which is now getting
XORed with the incoming data stream, right. Now the message that we are having, let us
consider, it is a 7 bit message. These flip flops are initially all cleared, right in this
register shift register, and to this 7 bit long message we append three 0s, we append three
0s signifying the values that are present here, signifying the initial values of these shift
registers, ok. Now, this is the input data stream 7 bit and 3 appended with three 0s, ok.
So, now how this particular circuit evolves with time, with clock pulses?
D1 = Sin ⊕ Q3
D2 = Q1 ⊕ Q3
D3 = Q2
Qn+1 = Dn
So, this is the clock pulse 0, this is serially so initial value is 1. So, this is the 1 that you
see in here. So, these are all three 0s ok. Then what happens? This 1 and 0 right. This is
0. So, D1 is serial in and XORed with Q3, serial in XORed with Q3, D2 is - D2 is this
one, Ok. Q1 and Q3 getting XORed and D3 is just whatever is Q2 output that is going as
Q2.
And always we know for D flipflop whatever is the Dn and that is becoming Qn plus 1 –
next clock value, ok. So, we can examine it in this manner. So, the first case serial in is 0
- serial in is 1 and Q 3 is 0. So, the value is 1, right. So, what will go to Q1 in the next
clock is 1 ok, then Q3 and Q1 XORed is 0, Q3 and Q1 XORed is 0. So, next clock it
becomes 0 and what Q3 will get, Q3 will get whatever is there in D3, D3 gets Q2. So,
this is the 1 that will be there. So, the next value will be 1 0 0. After that 1 comes as the
serial input. So, 1 and 1 sorry, 1 and - serial in and Q3, so 1 and 0; so 1 comes here, then
Q1 and Q3, right. So, 1 and 0, so this is 1.
So, 1 comes here in the next clock and Q2 comes to Q3, in the next clock. So, that
becomes 1 1 0, then 0 comes here. So, that way it continues and you include these 0s
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also, ok. So, 0 to 9. So, 10 clock pulses are there. Once we complete this 10 clock pulses
right, the value over here what we see is 0 1 0 that is the remainder, ok. So, that
remainder now we attach as check bits to this 7 message bits, ok.
If the message bit was less than that, then or more than that we’ll continue accordingly,
but always we’ll be in our scheme of things; these three 0s, these three 0s will be there
right. So, now this is what is getting transmitted, right. This message bits are getting
transmitted. At the receiver end, what we’ll, what will you do? So, receiver end now
these bits, whatever is there will be given as input. The circuit will be the same and it
will be initialized with 0 0 0, and we will publish in the same manner, exactly the same
manner the way it has progressed at the transmitter end. And at the receiver end, when if
every bit is appropriately received, no error is there, then the remainder will become 0 0
0, ok. If the remainder is anything other than 0 0 0 ok, then that means there is error here,
there is an error here in the incoming stream, ok.
And this CRC code is especially useful for detecting burst error. Bust error means
because the noise and all more than one bits, consecutive bits have got have become
wrong ok, error has got into consecutive bits. So, this is the CRC code generation and
then, it is - at the receiver side its detection and this is the way the check bits are coming
and there this shift register is useful.
(Refer Slide Time: 27:43)
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There are many applications of LFSR. So, here I have listed a few and majority of them
from its ability to generate pseudo random sequence. If the counter does not require
states to be like 0 0 0 1, 0 0 1 0 that kind of you know, these sequential numbers you
know, increment is not required - any kind of states can be there and then, a fast counter
can be made of sufficiently long length.
So, that is - with n bit we can go up to 2 to the power n minus 1. And the other use of it is
in test pattern generation of which can be used for testing the faults in application
specific integrated circuits. Scrambling is another use of LFSR output. The pseudo
random sequences can XORed with the message bit and the resultant signal pattern
would look more noise like, and the reverse can be done at the receiver end to get back
the original message. And it is used in cryptography also where the initial seed from
which the pseudo random sequence is generated can serve as a cryptographic key and
can be used for encryption first and at the receiver side for decryption. And you have
already seen its use in error control code, the cycle redundancy check, the check bits –
the way it has been placed and CRC 16 is one popular such thing, CRC 32 is also there.
For example, x to the power 16 plus x to the power 15 plus x square plus 1 could be one
such polynomial and it can detect up to 16 burst error and many other types of errors.
g(x) = x16 + x15 + x2 + 1
(Refer Slide Time: 29:43)
.
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So, with this we conclude. We have seen that LFSR can be used - and to generate through primitive polynomials pseudo random sequences of sufficiently long length and primitive poly polynomials need to have even number of pairs and tap indices need
to be relatively prime. This is a necessary condition, not sufficient - and CRC code is
useful for error control, as error control code and LFSR can be used in cryptography and
scrambling, test pattern generation and many other areas, ok.
Thank you.
586
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & E C Engineering
Indian Institute of Technology, Kharagpur
Lecture - 40
Serial Addition, Multiplication and Division
Hello everybody, in this class we shall look at use of shift registers in Serial Addition,
Multiplication and Division ok; that means, in arithmetic circuit building. We have seen
them - this addition, multiplication and division in combinatorial logic related discussion
and there we told that there are other ways, other way to do it and one is using sequential
logic based implementation.
(Refer Slide Time: 00:43)
So, we shall see how it can be done using shift register.
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(Refer Slide Time: 00:51)
So, we begin with serial addition so, in serial addition what we have is this shift register two shift registers we are putting one is your register A - and register B. So, in this the
addend and augend they are put and when you are clocking it then this is going serially
out, coming serially out. And the way it is put the most significant bit is this side and
least significant is bit is the other side. So, this here so, if it is A 7 then this is A naught
so, this is the LSB and this is the MSB. Similarly this is B 7 and this is B naught so, this
is the way initially it is put right.
What else, so, instead of - if we are talking about 8 bit addition in commutatoral logic
context we have seen that eight adder units are required. Here we are using only one
adder unit the one that you see here right and we are using it successively. In every clock
cycle it is doing a one bit addition right and the carry output of it that is generated here is
stored in a D flip flop and this is fed back here for use it in the next bit addition. And the
sum bit that is getting generated that is coming as serial-in and is stored in register A.
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(Refer Slide Time: 02:43)
What happens to states here, register B? The serial-in that is there we can put another
number so, if you are looking for consecutive addition of A plus B plus C plus D more
than two numbers so, we can make C enter at that time through this particular serial-in
ok. So, after 8 clock pulses what will happen? That A plus B result will be stored here
with carry and then by that time C is already loaded here. So, with another 8 clock pulse,
A plus B plus C will be generated so, this is the way it will go on, is it clear. So, we can
see one example.
(Refer Slide Time: 03:37)
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For example, we have two numbers say one, four 0 1010 so, this is A and this is B
initially loaded and Q is 0 and when after 1 clock pulse what will happen. So, 1 and 0 it
is getting added so, that is 1 right. So, this 1 will be after 1 clock pulse because it is fed
back here, it will come over here right since carry generated is 0 10 it is there is no carry.
So, Q will be 0 only so, 0 will be coming here right and for B after 1 clock pulse; after 1
clock pulse the next number or some other value you know, which is of no significance
will come here. So, if it is the next number if it is 0, 0 will be there or 1, it will be 1,
otherwise we say it is do not care, we do not care.
So, next clock pulse what will happen? Within this, because it is a combinatorial logic 1
plus 1 which is 0 is generated and carry generated as 1. So, this is 0 and carry generated
as 1 with in the same clock cycle, but we need the clock trigger for this 0 to come over
here. So, next clock trigger so, this 0 that is generated will come over here this 1 will get
pushed right everything will get pushed so, 1 0 is coming over here ok. Now this carry
which was at this input with the trigger will come over here and it is there and for B
another such input will come ok. So, this way it will keep doing it and after 8 clock
pulses, the addition will be completed. Is it fine?
And here we can see this snapshot of it so, A 7 to A 2, after 2 clock pulses where it is.
So, B 7 to B 2 is here so, these are A 2, B 2 and C 1 that is the carry of the previous
clock - previous addition, previous bit number one – A 1 and B 1 addition is over here
and S 2 is entering with the clock, next clock 3, S 2 will enter here ok. And these two
places the next number or some junk value or would not care which value are entering in
this particular place right.
So, earlier we are doing it at one go here we require 8 clock seconds to complete
addition. So, this is the difference between parallel addition using combinatorial logic
and serial addition using sequential logic ok. So, there it was faster, but requiring more
hardware. Here it is slower - it requires more time ok, but it is if it is - the clocking is
sufficiently fast then you know, it will be done in real time ok.
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(Refer Slide Time: 06:45)
So, next we look at serial multiplication ok, in serial multiplication what we are having?
First, let us get familiarized with the hardware that we are using. So, the two factors to
generate the product so, one is x3 x2 x1 and x naught right and the other one is y3 y2 y1
and y naught right.
And in addition to that we are using a 7 bit adder, note that it is a 7 bit adder and a
register which is 8 bit long. So, we are giving an example of 4 bit and 4 bit multiplication
right, so it can be extended for other cases. So, this is a latch right, this is a shift register
the arrow direction shows that gradually it will be shifted ok. So, first we’ll you know,
multiply with y3, you will get the partial product which will get added, then again we
will multiply with y2 and these AND gate outputs will be giving you the bitwise
multiplication y2 multiplying these x3 to x naught.
We shall see one example of course, right and the other important point to be noted here
of course, the m initially is loaded with 00000000, is that the m naught to m6 these
values after addition is coming here as m1 to m7. Please note this part ok. So, inherently
in the structure we are having a one left shift - left shift occurring. The arrangement is
such that, the wiring is such that a left shift is occurring when we are loading the addition
result.
Now, this 7 bit addition for which 7 bits are taken from here and this AND bank the first
is not required we shall see an example why it is not required. So, this 3 AND output will
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be going to the adder and the for the rest of the cases we will be having 0’s, so that both
side we are having 7 bit - is it fine. So, this is the hardware part of it and this shifting and
loading are not happening in the same clock edge. So, when shifting is happening not at
that time loading is happening.
So, when shift happens at the negative edge right after that this combinatorial circuit
does its operation with whatever propagation delay is required, result is available, next
positive edge it gets loaded - so that the whole thing gets completed in one clock cycle
itself ok, but it is in this manner. And the example that we shall take is the one which we
have seen before that is 1101, in our combinatorial logic circuit discussion for multiplier,
and we saw that this was the result and corresponding decimal value was 143 right. We
shall see that example in the next slide ok.
(Refer Slide Time: 10:21)
So, this circuit in a bit smaller form - placed it here for easier understanding and we start
with this x3 x2 x1 and x naught, it is always there 1101. And y3 y2 this will be coming
getting shifted over here. So, first the y3 will be considered so, y 3 ANDed with 1101.
So, the AND output, the AND output over here, what will be those values? 1101 only. Is
it ok? This AND output is 1101 - it’s clear. M output initially is all 0’s right and out of
this all 0’s 8 bits this ones in the blue the seven one ok.
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x3x2x1x0 : 1101
y3y2y1y0 : 1011
So, that will - that are getting fed back at the adder input ok. So, this is the - this seven
will be there right. And other adder input is what? This one is not used this is coming
directly as per the circuit diagram you can see to the m naught and the rest three; that
means, 110 ok. So, this 110 and rest four are 0; rest four are 0; rest four are 0 and this is
110 that is this seven bits are going for as A and B for the adder, is it clear right.
So, what is the result? So, this 1 is coming directly as 1 right and the other cases so, this
is 0 this is 1 and this is 1 and rest are 0 and after the clock trigger what is happening,
what is getting fed here, what is getting loaded here? So, this m naught this 1 is getting
directly loaded here and the adder output will be coming at m 1 to m 7. So, 0000110. Is it
fine? Understood? Right.
So, now this is the value of m right, this is the value of m. It is getting shifted negative
edge so, it is becoming, what is the output for the AND gate all 0 right. m output is now
here whatever is the output next clock cycle in the beginning this is the output of the M
and which of that is going as adder input the m naught to m6, m naught to m6 - right. So,
this is going as adder input in the blue right. And to which what is getting added? This 3
bits so, these are all 0’s in this case and rest all 0 and this 0 is directly coming.
So, what will be the corresponding addition result? This is there, addition result ok. So,
what effectively you see that it is just getting shifted when you are multiplying with 10 in
this particular case, it is getting - the first one is getting multiplied properly and then it is
just getting shifted by the, for the case of the 0, by 1 - ok. So, that is the inherent shifting
that is happening we are not doing any shift register based shifting - is not required and
we are saving on clock cycles and also the complexity of the circuit is reduced.
So, after that what we are getting? The value of this shift register becomes 000 - this m
register becomes 00011010 ok. So, 00011010 and now again its getting shifted so, this 1
will come, y1 will come. So, what is the AND gate output? 1101 and out of that this 1
will come directly and 110 appended with four 0’s is the 7 bit adder’s B input. And for
the A input, this m naught to m6 is coming here m naught to m6, then if you add this is
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1; then 1 plus 1 is 0; 1 plus that carry is 1; 0 carry is 1; 0 carry is 1 - 0 and then we have
got a 1.
So, this is your m register which is - which will be taking the value after clock 3 right.
So, this will be now coming here in the next clock cycle and this is the input this m
naught to m6 - 7 bits will go as adder input right and here again y naught is 1 so, this is
1101 right, this 1 is coming directly over here and 110 and four 0’s that is participating
in the addition. So, what we get this is 1; this is 1; this is 1 and this is 1 and this three 0’s
and 1. So, after clock trigger this is the adder output this is the value that we get so this 1
is 128 and this four 1s 15 – 143, ok.
So, this is the way we can see that you know we can - through this partial product and
shift we can get the multiplication term. So, his is the same example we had seen before
you can compare the result and you can you perform it by hand also.
(Refer Slide Time: 16:29)
Now, we shall look at division. For the division we shall just implement the circuit that
we had used for combinatorial logic circuit, its sequential version ok. So, for which I
have brought that particular unit cell based architecture, the array we had used ok. So, if
you remember fine, otherwise please revisit that particular lecture. I believe it is lecture
number 30 ok - week 6 last lecture, then it will be clearer to you how this division takes
place. So, we have taken up this example which is there in the right hand side. So, the
same example, I mean we can see in that particular lecture module also.
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So, the - this is the dividend, this is the divisor, this is the quotient and this is the
remainder and we had seen how it actually is getting calculated through this and how we
can arrive at these numbers. So, this dividend D6 D5 D4 D3 - these bits are taken first,
right and then gradually D2 D1 D naught are added; added means it comes into the
consideration. This is important because in next circuit, sequential logic based circuit, we
also see that initially, D6 D5 D4 D3 are there - these 4 bits, then D2 D1 D naught are
there. So, this is 7 bit getting divided by 4 bit - this is a specific example. So, you can
extend it for 8 bit and other cases.
And in every case see this d3 d2 d1 and d naught ok, that is participating in the
subtraction process either the subtraction result is going to the output or this x is going to
the output because of the multiplexing - 2 to 1 multiplexer it is there. So, it is the borrow
out which is deciding it. And borrow out inverted is the quotient that is getting generated
and finally, the remainder will come over here. Is it ok? And these are the quotients and
this quotient is also available here at this side.
So, here also you get this quotient. In the right hand side also you get the quotient. We
had in that example we had taken it from the left hand side, but we could have taken
from this output also. Is it fine? So, this is what we had done in that particular class.
So, now we see how it is getting implemented there. So, D6 D5 D4 D3 we shall begin
with then D2 D1 D naught will get appended sequentially right and every time d3 d2 d1
d naught will be in consideration q3 q2 q1 q naught will be generated through the borrow
and finally, the remainder will be there ok. So, this is the thing that we take note of and
this is how the serial division takes place ok.
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(Refer Slide Time: 19:51)
So, first of all you can see this D naught to D 6 that was there. In addition there is
another bit we have put. So, it is 8 bit register ok. So, out of this 8 bit I mean, basically
we are dividing into a 4 bit register parallel in parallel output kind another is a 4 bit shift
register.
So, D naught to D3 is a 4 bit shift register and this one is a parallel-in parallel-out
register ok. And this is just a latch or a parallel-out register which could be serial-in
parallel-in depending on the requirement - once it is loaded it is not I mean, the output is
always being used. Is it fine? And these are the unit cell one bank of it is only required
because it is sequentially used - right. So, how it works? How it implements the one that
we had seen - the circuit, the combinatorial circuit.
So, here in this particular case so, in the beginning D6 D5 D4 D3 you see this is the
output this is taken from here right and D7 is also there first of all in the beginning D7 is
not of consequence. So, D6 D5 D4 D3 that is being used right and it goes through that
particular block and the whatever is generated this q this output, it is also generated
through here so, this is made available. This is, this is a combinatorial logic block - is not
it.
Now with the clock, what happens? This quotient q naught comes over here right and D2
takes place of D3 right and now this D6 D5 D4 and I mean, what is you know, the
particular value that comes over here from the unit cell - either this one or the subtraction
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value as per the logic, that will be there with that D3 - the D2 also comes into
consideration.
So, these three values 1 2 3 and D 2 comes into consideration and in each case d3 d2 d1
d naught is there next time again this; this; this; this will be coming into consideration
and D1 also comes in to picture. So, this is how it progresses. Same thing is implemented
in the same manner. The example that you had seen you can just put over here and with
the clock you can see it moves from - exactly the same manner and the same result will
be found at the end, right.
And as we had mentioned in the previous case, here also this 1 and 5 could use halfsubtractor instead of full subtractor. Again I say that we are following the division
paradigm that we had used in the combinatorial logic circuit based divider circuit
discussion. So, please refer to that and then come back, here it will be easier for you to
follow.
(Refer Slide Time: 23:43)
So, with this we come to the conclusion of this particular class. So, what you have seen?
Serial addition uses an adder circuit adder unit successively where consecutive bits are
presented from shift register and the carry part of it can be handled by a D flip flop.
In serial multiplayer realization, one of the factors is shifted through a shift register and
one bank of AND gates and the adder block is used successively. In storage of adder
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result, one left shift is made so, the storage part is made in such a manner, intelligent
manner, that we do not require an any separate you know, shifting that we see in the
multiplication process ok.
So, in serial divider realization the one that we had seen we have a unit cell based
approach where one bank of unit cell comprising of subtractor and multiplexer is used in
a successive manner ok. And these unit cells in the divider circuit receive the dividend
bits through a register and shift register where shift register introduces the lower 4 bits
and the remainders are stored in the higher bits that is D7 to D6 D5 D4 the way you have
seen and D3 to D naught now is the placeholder for the quotient ok. So, with this we
conclude the discussion on shift register.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 41
Asynchronous Counter
(Refer Slide Time: 00:27)
Hello everybody. We are in week-9 of this course. In this week, we shall discuss counter.
So, we begin with a discussion on Asynchronous Counter, which we shall take up in this
particular class. Before that we shall have a quick recap of what we discussed in week-8.
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(Refer Slide Time: 00:33)
So, if you remember we discussed shift register, and there we noted that the number of
bits in the register defines how many information can be stored, digital information can
be stored. And we discussed various configuration of it - parallel input parallel output,
serial input parallel output, parallel input serial output, and serial input serial output.
And we noted that serial in and serial out give the option of having less number of input
output pins, but the time required for data write and data read is more. And we also noted
that for serial data out, the way we read the data, in such case as such is destructive. But,
if we feed the data back, then it will be the data can be re-stored, rewritten in the shift
register.
And we saw a various application of shift register serial-to-parallel, parallel-to-serial
conversion, and then using that - for a serial-to-serial communication which reduces the
number of transmission channel required that is required. Then sequence generator,
sequence detector, ring counter, Johnson counter, introducing delay of appropriate or
required time.
And then we discussed at length linear feedback shift register, and its various use. And as
pseudo random number generator, it has various use in - from cryptography to many
different places. And we also saw a cyclic redundancy check generation, and also
detection, any error in that code that is code word for any especially, it was useful for
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burst error checking, so that kind of use also we have seen. And finally, we saw use of
shift register in efficient realization of adder cum subtractor, multiplier, divider ok.
(Refer Slide Time: 02:51)
With this we discuss - we start discussion on counter. So, counter - what is a counter?
Counter keeps record of the number of times a particular event has occurred ok, so it
keeps a count, so the way I mean, the name itself can give us an idea. And to note how
the - how many such event has taken place. So, the counter circuit with the memory
element in it, it advances its state one by one ok. And one particular state is associated
with one specific count. So, there is a uniqueness in this particular thing. So, a specific
state is associated with one count.
And if this advancing of state is in sequential order ok, so 0000 to 0001, then 0010 so on
and so forth. Then if it is advancing, it is increasing, then it is up counter. And if it is
decreasing, the other way it happens - it is called down counter ok. But, as I said, the
basic idea is you need to have a unique state. So, it is not necessary that it is always need
to be in that manner. So, it could be any random, but unique state, so but as many
number of state as many count that is required here. So, that is also possible in that case,
it is random or irregular sequence will be there.
And the way the events trigger all the flip-flops that is there in the counter design in the
make of the counter, it can happen that the trigger is going to each of the flip-flop. And
simultaneously each of the flip-flop can get triggered, so that is called synchronous -
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synchronously it is happening, so that is called synchronous counter. And if the trigger,
the external trigger that is coming that is going to one of the flip-flop, then that flip-flop
in turn triggers the next and so on and so forth ok.
As if the effect of the one is going past, you know to the other through a rippled manner,
so that is called ripple counter, also it is because how it is happening in different point of
time, so that is why, it is called not exactly in a same - synchronous with the external
trigger, it is also called asynchronous counter ok. A modulo-n or mod-n encounter has
got n different states ok, so the number that is the way it is associated.
And after n such trigger after the count of n, it comes back to its initial value. And if
there are m flip-flops used for counter design, of course 2 to the power m need to be
greater than or equal to n ok. And usually in most of the applications, the discussion that
we have, clock is given as input trigger, but it could be some other signal also. And modn counter is also called divided-by-n counters, so we shall soon see that the output of the
counter effectively will be having the rate of change of the signal, which is original
signal that is the clock or the input trigger divided by the modulo number - ok.
(Refer Slide Time: 06:27)
So, with this basic understanding of how counter works - a counter is supposed to work,
we look at asynchronous up counter. We begin our discussion with asynchronous up
counter ok. So, for that we are having a circuit made up of JK flip-flop, we could have
some other flip-flop as well, but JK flip-flop we have taken it up ok. So, what you see
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here that both the inputs of each of the JK flip-flop is connected to 1, tied to Vcc that
means 1.
So, each of the flip-flop when they get the trigger ok, the clock at the negative edge of it
ok, this is negative edge triggered all of you can see that. So, it is supposed to toggle ok,
so that is for sure. Now, let us see how things move. So, the clock is given here only to
the first flip-flop - right, as I was saying that is it is asynchronous. So, the clock is not fed
to each of the flip-flop, only the first flip-flop is getting the clock right, then what will
happen? After the negative edge, so initially all the flip-flops are initialized with the
values at 000 ok.
So, after the negative edge comes, as you see the timing diagram, it will toggle it will
become 1 another negative edge comes ok, so this flip-flop will become 0 right. So, then
again 1 0 1 0 1 0 and 1, so this is the way it will continue - is it clear. So, this is how the
first flip-flop will work right. We’ll discuss about second and third little later. So, the
clock is directly connected, the external trigger which is getting counted - how many
clock cycles or how many negative edge of the clock occurring, that is going directly to
the flip-flop A. And the flip-flop A is toggling in each of the negative edge in each clock
cycle right, at these points a, b, c, d, e, the way you have seen it - is it fine.
Now, what happens, this flip-flop B is getting a feel, getting an idea about the triggering
through A, not directly from the clock. So, whenever A changes, A output A
uncomplemented output A is connected as clock to flip-flop B. So, whenever A changes
from high to low right, so a trigger comes that is something as a clock right. Now, for
every two change in the clock, you can see A changes by one, these two cycles - these
are the two cycles, then A changes by, there are two negative edges here, then there is
one negative edge of the clock ok.
So, for every two such clock trigger, you get one trigger out over here for flip-flop B ok.
So, it is coming via A right, it is coming as you know kind of - the effect is rippling
through flip-flop A to coming to flip-flop B right. So, at the negative edge of the A flipflop output right, the B flip-flop will toggle that is the idea. So, B is remaining 0, 0 over
here for these time instances. So, only at time instant b, when it gets a negative edge, it
goes - it toggles, so it goes from 0 to 1.
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And how long will it remain in 1? As long as next negative edge from A comes here,
because A is fed as clock. So, next negative edge A comes at d, you can see here right.
So, at the time from 11, it comes to 0. So, next negative edge will come at f, so it goes
from 0 0 to 1 1, and this way it goes on is it fine ok. Now, let us look at C, what happens
to C? C is getting trigger from B ok. So, similarly whenever B goes from high to low that
time this C is triggered, and triggered in the sense - its both the inputs are 1, so it will
toggle. So, let us see when B is going from high to low, so B is going from high to low at
d. And again at h right, so these are the instances 1 to 0, and again 1 to 0.
So, C is changing, C is remaining 0 0 0 0 ok, because it does not get any trigger right
though flip-flop A has got triggered in every clock cycle, B has got trigger in every two
clock cycle, C has not got triggered up to this only in the fourth clock cycle, you can see
a, b, c, d right, it is getting a trigger ok. And at that time since it is toggling, it goes from
0 to 1. And it remains at 1, till next negative edge of B comes, and it goes from 1 to 0,
and this way it continues - is it fine. So, this is what is happening to the flip-flops right.
Now, by this what have you achieved in terms of you know count? So, if you now look
at the values of C, B, A, if you read it in this manner C MSB, C is your MSB, and A is
your LSB, if you read it this way. So, 0 0 0, 0 0 1, you can read in each of this clock
cycle right up to a. From a to b, it is 0 0 1; b to c, it is 0 1 0; c to d, it is 0 1 1 ok.
So, these are the you know, clock cycles. And 0 1 1, 1 0 0, 1 0 1, 1 1 0, 1 1 1 right, what
is it in binary (converted to decimal) 0 to 7 you have come, then again it is 0 0 0 ok. So,
you have got these states if you put it in the in the tabular form 0, 1, 2, 3, 4, 5, 6, 7, and
again it is coming to 0 right. So, what is it, it is nothing but up count, the number is
sequentially increasing - right. And it is a modulo 8 counter, because 8 distinct states are
there.
Now, if you look at the output of flip-flop A right, you can see for every two changes in
clock one changes happening here. So, clock cycle - the period of, time period of A one
period of A is just half of sorry twice that of the clock period right two clock periods are
consumed in one cycle of A. So, frequency wise for every two, you know cycle one
cycle of A is seen, so the frequency of A is half of it, then half of the clock. Frequency of
B, one-fourth, and frequency of C that is the last flip-flop over here, you are having a
frequency which is divided by 8. So, you can see that divided by 8, it is a modulo 8
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counter, because 8 sets are there. So, you can get up to I mean if you from the last output
a divided by 8 count – ok, output.
(Refer Slide Time: 14:05)
So, far so good we have got a up counter, modulo 8 up counter by a very simple
mechanism - the output of one is fed as clock to the next flip-flop, and each flip-flop is
togglong. Now, in these, what was not visible in the previous case that is the timing
diagram, that we are trying to show by stretching the diagram somewhat ok, and
introducing the time delay associated with each flip-flop transition ok.
So, let us see what is it, so this is the clock right. So, clock has got a negative edge over
here. Now, flip-flop A is changing, but it will take a propagation delay which is defined
here as t suffix p right. So, after that time only, A will go up. Similarly, A will go down
here after that propagation time of propagation delay tp, right - is it fine, so that will
happen in every case.
Now, flip-flop B. So, flip-flop B is not fed by the clock directly, it is fed by the flip-flop
A right. So, when flip-flop A changes, after that one more propagation delay, which is
required inside flip-flop B for its output to change that will be there. So, from the clock clocking instant over here the negative edge, B changes change of B will take place
change of A required that is one propagation delay plus change of B that is required.
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So, two propagation delay will be there within this, so that is what is shown here. So, two
propagation delay will get involved. And for C, what will happen? C is not again fed by
clock, triggered by clock - it is triggered by B. So, B is taking two propagation delay
from the clocking instant, so it will take another propagation delay. So, three propagation
delay will come into picture, is it clear.
So, this way you can see in this arrangement, the propagation delay are cumulative right.
And if you are having a very fast clocking right, then this propagation delay, when they
add it up for an n-bit counter right, and becomes comparable with the time period of this
particular clock ok, then there can be problem ok.
So, this addition, when it goes - extend beyond this time period, then what will happen,
within this time period over here never this 1 0 0 will occur. So, for example over this is
the way you see 0 1 1, then 1 0 0 right. So, this is the corresponding clock cycle ok. So,
0, 1, 2, 3, 4, this is the fourth clock cycles after you know starting from 0 ok. So, 1, 2, 3,
4 right, so this is - the fourth clock edges have come right. But, if it extends beyond this,
so fifth clock edge will come and 1 0 0 is not shown, so that is what is something comes
as a cause of concern. So, this is one issue with this kind of you know arrangement right.
Another is what you can see after 0 0 0, this is 0 0 1, after that 0 1 0 is supposed to come
in up counter. But, momentarily you can see for a small duration 0 0 0 is there, because
A has changed, but B is taking one more propagation delay to change ok. Similarly, over
here after 0 1 1, you are expecting 1 0 0 to come 1 0 0 right. But, momentarily you can
see that 0 1 0 is there, and then 0 0 0 is there right, after that 1 0 0 is coming right. So,
this can cause glitch in the circuit ok, so this is something which one need to be careful
about ok. And we shall see solutions and many other things later, but this is something
which we taken not in asynchronous counter in this discussion, this part of the
discussion.
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(Refer Slide Time: 18:37)
Now, we look at asynchronous down counter ok. So, asynchronous up counter we have
seen, so a synchronous down counter again we look at modulo-8 counter. These are three
flip-flops up to, with these three, 2 to the power 3 maximum modulo 8 counter is
possible. So, in this what is done, you can see the circuit input side remains the same,
flip-flops will toggle ok. Clock is given to the first flip-flop right.
And over here instead of A, A bar is fed as clock to the next flip-flop B. B bar is fed as
clock to the next flip-flop that is C - is it fine, ok. So, by this what happens, so initial
state is 0 0 0, and A will toggle in every clocking, negative edge of the clock that is for
sure, this is the first flip-flop right, so that is 0 1 0 1 that is what you see for A, which is
ok, which is similar to what we had seen before.
Now, because of A bar fed as clock what happens, so this will change at negative edge
right. So, A is going from in this particular place, A is going from high to low ok, sorry
A is going from here low to high. So, what will happen to A bar, A bar will go from high
to low, is not it. If you plot A bar alongside ok, A is going from high to low. So, A bar
will go from - A is going from low to high, so A bar will go from high to low. So, there
is a negative edge. There is a negative edge over here which will trigger it, trigger it
means it will toggle, so B will go from then 0 to 1, is it fine.
Now, when B goes from 0 to 1, B goes from 0 to 1 right, B bar what happens to B bar? B
bar will go so that was A bar before, now B bar will go from high to low 1 to 0, so that
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will also trigger that will trigger C. So, C will go from 0 to 1 is it clear, because it is just
opposite of it right. Whenever there is a positive edge for A ok, there is a negative edge
for A bar. Similarly, for B bar and C bar is not fed anywhere, so it would have been for C
bar also ok, if there was a flip-flop D right.
So, at positive edges of A, B, actually transition are happening ok, because for the
subsequent flip flops, because A bar and B bar are fed as clock. So, these positive edges
over here, so 0 0 0, it becomes 1 1 1 right. Next, this A is changing right, and A is
changing over here, it is going from high to low. And it is high to low means, A bar is
going from low to high, so no change right, understood.
Again A is going from low to high here, so output will go for - A bar will go from high
to low. So, here A bar is going from high to low, so there is a change in B, so it is
coming from - going from 1 to 0. So, this is the way, it continues. So, what you can see 1
1 1, after that 1 1 0, after that 1 0 1 ok. Again, B goes from low to high here, so (B bar)
high to low will be in this particular place.
So, C changes over here ok. And C does not change when B bar goes from high to low,
because B bar is what is fed here unlike the previous case. So, this way you can see 1 1
1, this way if you read MSB to LSB C to A 1 1 0, 1 0 1, 1 0 0, 0 1 1 ok, and these are the
counting states. right - is it fine. And it is up to - going up to 0 0 0 right, 0 0 1 and then it
is 0 0 0, after that again 1 1 1 will get loaded right. So, it is mod 8 down counter.
(Refer Slide Time: 23:47)
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Now, one important thing to be noted here; so, you have taken out put A, B, C right.
Now, if inverted output is also available, please understand this part. If this counter
circuit also allows you inverted output to the outside world that means, A bar, B bar, and
C bar ok. So, what the reading for C bar B bar A bar would have been in these cases. Can
you identify?
So, for example this was 0 0 0 right, after that it has gone to 1 1 1 ok. So, 1 1 1, and then
1 1 1 inverted it is 0 0 0 only ok, so after that it is 1 1 0. So, 1 1 0 is your what - inverted
is 0 0 1, then 1 0 1. So, 1 inverted will be 0, C bar will be 0, this is 1, this is 1 0 1 - 1 0,
and this is 0. So, just invert of this. And initially when it was 0 0 0, it would have been
initially it was 1 1 1 we are writing that. So, this way it will continue.
So, what is it, it is up counter only, up counting. So, the inverted outputs complemented
outputs will if available will give you up count while the standard one, uncomplemented
outputs are giving you down counter for A bar and B bar fed as clock to the subsequent
flip flops right.
So, similarly in the previous arrangement the up counter, we had seen - had we the
option of taking the output from C bar B bar A bar, then output there would have shown
down count ok. So, this we again take a note.
(Refer Slide Time: 25:31)
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Now, having understood how up counter and down counter works in asynchronous
counter ok; so, can you have one circuit ok, which can both work as up counter and
down counter. And depending on our requirement, we can make it work like a up
counter, and for another use, we can make it work like a down counter. So, here is a
circuit. So, the flip-flops A, B, C are there, the inputs are 1 1 that means, for every
clocking available here, it will trigger ok, it will sorry toggle ok, it will go to the other
value. If it is 0, it will go to 1; 1, it is it will go to 0 ok.
Now, we have put an additional input M, so M can be considered as mode control input.
So, M is 0 what happens, let us see for this particular circuit right. So, M is 0, you can
see M here, this is two AND gate and one OR gate. So, it is more likely to I mean, it is
the way the 2-to-1 multiplex circuit you have seen, but in a different context right.
So, M is equal to 0, this means this is equal to 1 right, this is equal to 1, and this is equal
to 0. So, 0 means, these AND gate output is 0, irrespective of what is there in the other
output ok, because for AND gate 0 is a forcing input. And since, it is 1. For this AND
gate, whatever changes in A, that will go here right. And for OR gate 0 is a non-forcing
input. So, whatever change is occurring, it will come here. So, effectively M is equal to
0, A is coming here. Similarly, B is coming here right. And if A comes and B comes, the
way we have seen the circuit, it is up counter only.
(Refer Slide Time: 27:25)
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Instead of this, if M is equal to 1, this is 0, so this is 0, and this is 1 right, so this is 0, and
this is 1. So, what is happening at that time? A bar is going to the clock of B flip-flop,
and B bar is going to the clock of C flip-flop, right. So, what is this arrangement, if you
are taking output from A, B, C, the uncomplemented you know, output of each of the
flip-flop ok, so then it is acting like a down counter.
So, M is equal to 0 up counter, M is equal to 1 down counter, this is the way we can
make it work in one circuit both the things are there right. So, while it is counting, it has
counted up to a particular level value, then you are changing M, then again it will start
counting in the opposite direction. So, it has count say, counted in the up count mode 0,
1, 2, 3, 4, 5 ok, and then you have made it 1, so it will start down counting ok.
(Refer Slide Time: 28:29)
So, finally we would like to see one standard IC, which gives this asynchronous up count
ok. So, IC 7493 is one such IC, which has got actually if you look at inside the circuit, a
mod 8 counter over here, and the mod 2 counter ok, two such units are there in this
particular IC. So, this is clock B, and this is clock A right.
If you do not bother about clock A right, if you just feed the outside clock two clock B,
then what will happen? This circuit will behave like a mod 8 up counter, you can see this
QB is going to the flip-flop QC is going to the flip flop. So, it is not complemented
output, it is - uncomplemented output is going. So, it will be behaving like a up counter
all right, so this part is mod 8 up counter, and this part is mod 2 counter right.
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Now, instead of QD, if you are just looking at QB and QC, then these are mod 2 and
mod 4 right, you will get a count of that thing you have seen that before, that it is a
divided by 2 over here, divided by 4 over here, and divided by 8 over here ok, so that is
the 1. But, as a whole three flip-flops are there, 8 unique states - increasing order. So, it
is a mod 8 up counter, if you take it as a whole right.
Now, if you make an, if you make an external connection from QA to clock B over here
right, and feed the clock here external clock here, then what will happen? So, now forget
about this one it is not there, it is directly connected. So, instead of three flip-flops, now
we are having four flip-flops. So, in the earlier circuit timing diagram, we stopped at A,
B, and C. Then there will be a D coming over there right, so that D will change for every
negative edge of C ok. And that will, one full cycle of it will occur for 8 plus 8, 16 cycles
of the clock right. So, it will become a mod 16 counter ok, because - here when you are
feeding the clock, so if you can if you remember the circuit. So, this is your clock, so
negative edge ok.
So, the QA is changing over here, and then again over here, and then again over here
right. So, this is halved, so this is divided by 2, and this is divided by 8 right, so together
it is divided by 16. So, modulo 16 count that is what we will get right, is it clear. So,
extending what we had discussed before, for three flip-flops to four flips-flops, right.
Additionally, here you can see there are two other inputs which are R01 and R02. If both
of them are high both of them are high, then what will happen? This is NAND gate, so it
will become low.
And you can see that there will be a synchronous clear, asynchronous reset right ok, it is
required for initialization and for some other purposes that we shall discuss later. And,
any one of them low ok, then the normal count operation will take place up count
operation will take place right. And why 2, why not 1, 1 would have been sufficient more
on that will be revealed in the subsequent discussion on the counter ok. There is a
specific reason to put this thing, some such thing ok, which is helpful in certain context.
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(Refer Slide Time: 32:53)
So, to summarize counter keeps a record of the number of times a particular event has
occurred by advancing its state which is unique for each count. And for modulo-n
counter, n different states are there. And if m flip-flops are there, then with those m flipflops, we can go up to 2 to the power m modulo number. Asynchronous counter, the
clocking of consecutive flip-flops are not by - not from the same clock or the external
trigger, it is done through a rippling effect from one flip-flop to another.
In up counter the counting states sequentially go up, and in down counter it is
sequentially coming down ok. And if you have the option of taking the output from the
inverted outputs, then the counter of opposite kind can be available. And in
asynchronous counter, important thing is that you have seen the propagation delay is
cumulative for which I mean, if this cumulative delay is of the order of the clock time
period, then a count can get missed. And also it can, it can give glitch, in between values
may come up ok, which can cause problem. And up-down counter can be made where
one - same circuit can give both up count as well as down count by suitable choice of
control input.
Thank you.
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Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 42
Decoding Logic and Synchronous Counter
Hello everybody, in this week, we are discussing counter. In the last class, we had seen
asynchronous counter. We had seen up counter; we had seen down counter; we had seen
up and down counter put into one particular circuit. And also we looked at one particular
IC. Today’s class we shall look at decoding logic, what it is and how it is useful in
counter design context and also we shall discuss synchronous counter, up counter, down
counter and up-down counter.
(Refer Slide Time: 00:47)
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(Refer Slide Time: 00:53)
Decoding logic, why decoding a counter state is important? So, for example, we consider
the mod-8 up counter asynchronous up counter that we had taken up in the previous class
ok. So, the counter has got 3 flip-flop, JK flip-flops each one of the input is having 1 and
1; that means, whenever the clock trigger comes to its input, it toggles ok.
And so the counting state as we had seen before, in the last class moves from 0 0 sorry
this is the output, 0 0 0 to 0 0 1, then 0 1 0, then 0 1 1, then 1 0 0, then 1 0 1, 1 1 0, 1 1 1,
and again it comes back to 0 0 0, and it continues. This we have already seen in the last
class, we discussed this.
Now, this is happening internally. If we look at all the three inputs, we can understand
that a counting of a specific number of a clock or the trigger has happened ok. But to the
external world if we want to know that a count of 7 has taken place, do we need to
sample all three of them, and figure it out or we can make a logic, an output, a separate
output available which will go high whenever the count of 7 takes place ok. So, that we
do not need an additional thing where we need to look at all three values; and from that
infer whether a count of 7 has taken place or not or count of 5 has taken place or some
such thing.
So, in this example we are showing that a count of 7 has taken place that can be
understood by having a three input AND gate over here where A, B, C are connected in
this manner. And when all of this A, B, C are high as is the case over here in 7th you
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know after the 7th point ok, so 7th clock cycle if we have consider these as 0th ok, then
the output will go high for one clock period. Is it clear? Right.
So, this one this output is 1, that means, 7 clock edges starting from 0 has taken place 1,
2, 3, ok, 1, 2, 3, 4, 5, 6 and 7, 7 clock clocking, 7 triggering has happened Is it clear? So,
this will again go high, when another 7 (i.e. 111) occurs right. So, this is the utility of
having a decoding circuit by which we can figure out whether that particular count has
taken place or not ok.
(Refer Slide Time: 04:11)
Now, if we extend it, if we extend it, instead of say 7 (i.e. 111), if we are interested in
decoding whether a count of 5 (i.e. 101) has taken place or not ok. So, what shall I do?
So, we shall put a output gate, where the in input of which will be C is the MSB here, C
is you know changing with a frequency which is less than that of A and that of B right.
So, when C is 1, B is 0, and A is 1, right that indicates that a count of 5 has taken place,
that means, five clock edges have come starting from 0. Is it ok, right?.
So, similarly 0, 1, 2, 3, 4, 5, 6, 7 - 7 we have already seen. So, depending on our
requirement, we can put this you know decoding logic at the output of the counter. And
accordingly this output will go high, whenever the count value in the counter reaches that
one and it remains high for one clock period.
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So, in this example, you can see since this 0 will go high here again that is A bar, B bar,
C bar, all of them are 1 at this point; and again when it comes over here right,
1, this decoding, decoder output ok, this logic gate output, so C B both are 0, and A is 1
right. C is 0, C is 0, B is 0 and A is 1, so that is the occasion when it will go high, so that
is the case when this is happening right this is going high here and again going high here.
So, after every 8 clock cycle, it will happen.
Now, similarly for the other cases. Is it clear, right?. So, in the circuit, in this place
instead of 3 input AND gate, we shall put one of this connection right. And we can take
wherever A bar is there, we will be to take it from the in inverted output instead of A the
way it has been shown here right.
Now, instead of say mod 8, if we had a mod 16 counter right, so to have a count of say in
that case if 15 or 14 depending on that requirement, so we need, we would have required
a four input logic gate. So, depending on in you know the number of the count value the
mod 16 mod 32, whether a it will be 4-input 5-input, accordingly the number of input for
the decoding circuit will increase.
(Refer Slide Time: 07:05)
Now, we look at what happens - one specific issue related to glitch that we discussed, we
introduced in the last class regarding discussion related to asynchronous counter - the
effect of propagation delay. So, in the previous diagram, we did not consider it. Now, we
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are considering it. So, this is the time ok; this is the clock. And here it is A; here it is B;
here it is C ok.
And we had seen in the previous class, this is the clock edge, this one this blue line you
can see, and A is getting triggered right. And after one proper propagation delay, A;s
value is changing from 1 to 0, because it is toggling in every clocking edge, negative
edge of the clock right. Now, B gets triggered from A; clock of B flip-flop is actually fed
by fed by A, sorry this one ok, this part I shall discuss it later right.
So, after the negative edge of the clock, so another propagation delay is required for B to
change state, and B will toggle every time A changes from high to low ok. Similarly, for
C. So, there is a - there are three propagation delays. So, this we have seen in the last
class. So, this is the way A B C you know changes its value right, and the propagation
delays are cumulative right.
Now, consider that we are looking for a count of 6. So, then the decoding logic required
is C B A bar right. Say A bar is the complemented output of flip-flop A so it is changing.
Whenever A is going high, it is going low and vice versa, so that is what is there in A bar
ok, A bar wave form all right. And this will go high right when this is 0, this is 0, and A
is sorry this is 1, C is 1, B is 1, and A is 0, that is A bar is 1 ok. So, this is happening
where - when it is reaches the count of, reaches the count of 6 ok. So, this is the case C is
1, B is 1, and A is 0, so A bar is 1 ok. So, this three are 1, at that time A bar B and C, and
the output will go high right that is what you see right.
And of course, this AND gate, there will be small propagation delay which has not been
shown here which is less compared to this flip-flop propagation delay so, but there will
be small delay over here ok. But the idea here is that the output will go high, when these
three are 1 1 and A is 0 that is A bar is 1 all right.
Now, moving forward, after 1 1 0, there is 1 1 1. And after 1 1 1, there is a it should be 0
0 and 0, this is the value that is expected all right. But because of the propagation delay
all right, after 1 1 1 you can see for a small duration it still remains - is remaining at 1 ok.
B as - B is 1, but A has already change from 1 to 0. So, for a small time, for the duration
of the propagation delay, you have got 1 1 0. After that B has changed right, but A has
already changed, but C has not yet changed. So, for a small time 1 0 0 is there; and after
that only you are getting the 0 0 0 right.
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Now, whenever these 1 1 0 is there ok, so this logic decoding out, decoder output will go
high for a brief period ok. So, this is the glitch that you can see. And if this output is
feeding, another counter or another say, sequential logic circuit which is you know
counting, the number of trigger that is happening number of changes happening here
right. So, it will get a wrong message that a count of 6 has taken place. Again a count of
6 has taken place just after 1 clock cycle which is wrong right. So, this is something
which is the, which is a problem with a synchronous circuit, and we need to think of
getting around, solving this problem addressing this problem right.
So, one way to solve this problem is to associate the clock and increasing the number of
input to the decoding gate to - by 1. So, there were three inputs, now you are making it
four inputs. So, when you associate the clock and of course, clock period is considered
much larger right, than this propagation delay. Then what is happening over here, so this
is getting ANDed right. So, this propagation delay is occurring when the clock is there in
the low value all right, you can see this is where the clock is changing. So, the change is
initiated when clock is going from high to low ok, it is negative edge triggered. So, this
is the time clock is remaining at low.
When you are ANDing it with the clock, then this glitch goes away ok. Of course, we are
not considering clock to be so fast that this delay and delay is so much that delay is
coming when the clock is again becoming high right, so that is ruled out ok. So,
propagation delay and the number of flip-flops considered and the clock period are such
that it is occurring, the glitch is occurring when the clock is low ok. So, then the glitch
can get removed right. So, this is one way of handling this problem.
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(Refer Slide Time: 13:13)
Now, this brings up, brings us to the discussion on synchronous counter ok. So, in the
synchronous counter, this accumulated delay and resulting glitch, these aspects are not
there ok. In the synchronous counter, all the flip-flops are getting triggered by the same
clock, by the same clock ok. Now, we see here in this case two diagrams, two
arrangements ok. So, this is one circuit, this is another circuit I mean there giving you
will give you the same result.
So, in the first circuit what you see is that each of the flip-flop has got 1 and 1, 1 and 1, 1
and 1. So, all of them can toggled right, all of them can toggle whenever they get the
clock right. And you can see this clock is fed here to flip-flop A. This clock is again fed
here through an AND gate, we’ll come to that AND gate part later, and this is also fed
here. So, effectively the clock is being available to all the three flip-flops right which will
make it a synchronous counter right.
So, of course, there is no AND logic here. So, every lock trigger, it toggles, flip-flop A
toggles the way you know we expect to be the case, the least significant bit part of it in a
CBA configuration. So, A is toggling at every place 0 1, 0 1, 0 1, more about these boxes
etcetera we shall discuss later in this diagram, in this table, all right.
Next for flip-flop B, clock has come right, but clock will - clock has come up to this, but
clock will go - is allowed to go to this place only when A is high because of the AND
logic right. So, only when A is high, only when A is high right, so B will get the clock
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for which it will trigger, it will sorry it will toggle ok. And when A is 0 like this case,
when A is 0 initialised with 0 0 0, A is 0, clock has come here as well as here, but the
clock has not advanced to this point right for which A has toggled, but B has not toggled.
You can see A has toggled but B has not toggled ok.
So, when A is 1 right, that means the next you know clock cycle right, then this is 1 and
the clock has come. So, according to the clock at the negative edge of the clock, it will
toggle, so it has become 0 1. So, then again A has become 0. So, when A becomes 0
right, so this clock is not available it is coming up to the AND gate input right. So, it will
remain at the same value, input is - because in that clock cycle there is not toggling
happening. So, this is remaining 1 1. And this continues that way it is 0 0 1 1 0 0 1 1,
again it will go, becomes 0 0, so that is for flip-flop B.
And for flip-flop C, what is happening, for flip-flop C clock again has come right, but
when A and B any one of them is 0 right, this output is 0. And when both of them are 1,
that is it has reached 1 1 right. It has reached 1 1, then only the clock is allowed to come
over here and trigger the flip-flop C ok. And this flip-flop C is getting triggered, and the
output is - its value changes from 0 to 1. Again it will change when both of them are 1,
and it will - value will change to 0 ok.
So, the value 1 1 or 1, it is made available in the previous clock trigger itself right. So,
that way it this is not contributing to the delay ok. In the way that this flip-flop this is not
actually triggering. A output is not triggering, it is only the clock is triggering, A output
is just ensuring that the clock is made available, so that way it is behaving like a
synchronous counter ok.
Now, let us look at the other circuit ok. So, in this the clock is directly fed to each of the
flip-flop right. The first flip-flop is toggling at every instance right.
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(Refer Slide Time: 18:15)
And next flip-flop, when A is 0, the output will remain 0 0 no change. When A is 1 right
like this case, when A is 1 right, then this will both of them are 1 J and K. So, it will
toggle. So, the output will become - from 0, it will go to 1 right. So, next clocking
instance, it is 0 all right, so it will get a 0 here, so no toggling right. Again it will get a 1
over here so that will make it change from 1 to 0 for B, and similarly it continues, right.
And for flip-flop C, what happens right, this is when both A and B are 1 right, then J and
K both of them are 1 as is the case over here, then only when the clock comes, it triggers
ok, it toggles. So, it becomes 0 to 1. So, every clock instance, it gives gets a trigger, but
the value if it is 0, it will not change; if it is 1, it will toggle fine. So, this is the way these
3 flip-flops behave, and resulting you know, values for CBA are 0 0 0, 0 0 1 to 1 1 1, and
then 0 0 0. So, what is it, it is a up counter and it is synchronous ok, clear.
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(Refer Slide Time: 19:47)
And because of this if you look at the timing diagram, if you look at the timing diagram
what is happening? In this case, so this is your clock right this is the negative edge of the
clock, A is changing at every clock the way you have seen. So, basically this A, after one
propagation delay it changes right. So, it is moving like this ok and what about B right.
So, B is changing again with the edge whenever A is 1, this is A is 1, then only B will
change when the clock trigger comes ok.
So, clock trigger has come B has changed because A is 1 – right, clear. So, it will change
after one propagation delay only. So, A has changed, the A value has taken - from 0 to 1,
after one propagation delay; 1 to 0 - one propagation delay. B has gone from 0 to 1 after
one propagation delay, right. So, there is no accumulated delay from A to B like
asynchronous, right. Again B will change when A is 1, then the clock is you know, at the
clock trigger it will change from 1 to 0 and so on and so forth. And what about C, C will
change you have seen, when both B and C are 1.
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(Refer Slide Time: 21:11)
So, this and this when both of them are 1 right at the clock trigger, it changes all right.
And it changes after one propagation delay only right. So, this has become 0 to 1. Again
it occurs in this place when both of them are 1, it has gone from 1 to 0, so that way you
have got the timing diagram, where the flip-flops are all changing at the same clock
trigger and the values are available after one propagation delay, right. And because of
which, because of which if we have got a decoding, the way we were decoding
asynchronous up counter say 1 1 0 right and in this case so A bar is just following A the
complemented output.
(Refer Slide Time: 21:53)
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So, at this time this is 1 1 1, this three one right. So, at that time this output will be 0. So,
the propagation delay associated with this AND gate has not been shown in this diagram,
but there will be small propagation delay as was the case for the last timing diagram.
And it will remain high for one clock period right. So, this is the way it can - the count of
6 can be decoded right.
(Refer Slide Time: 22:23)
Now, let us look at synchronous down counter ok, like we had asynchronous down
counter following asynchronous up counter. Now, we have synchronous down counter
right. In asynchronous down counter, we remember that A bar was given as input ok, and
then B bar was given as input you know to the next flip-flop the clock and all right. So,
here we would be following the same logic right. So, first we look at the sequence ok,
the down count sequence, then we can see what would be the corresponding circuits. So,
down count consequence is if you start from 0, then it goes to 7 we are talking about mod
8 counter only right, but it can be extended to mod sixteen and other values.
So, 7, 6 - 1 1 0, 5 - 1 0 1, 4 - 1 0 0, 0 1 1, 0 1 0, 0 0 1, 0 0 0 again it is 1 1 1. So, this
way it repeats - is not it, so that is your down count ok. So, first if we look at A, A is
toggling at every you know, a clocking, clock cycle, at all clock edge. So, this is how A
is connected. Both of the - both the inputs are 1 is fine right.
Now, when B is changing? B is changing you can see when this 0 black underline is
there. Whenever there is A 0 ok, with the clock trigger A - as value 0, A as value 0 right
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- with the clock trigger right, we see that it is changing right. Again A has 0 - with the
clock trigger, it is changing right. So, this is changing from 0 to 1, this is changing from
1 to 0, again 0 to 1 and so on and so forth right.
Now, to make change happen in a flip-flop we need 1 1 at the input right, just in the
toggle mode for a JK flip-flop. So, for 0, it is changing. So, instead of A, we’ll put - if we
put A bar that means, that will make whenever A is 0, 1 1 fed as the input to J and K, and
with the clock it will toggle. So that is the way the connection has been made here, clear.
So, similarly for C to change, C to change what we see that - follow this brown underline
when both of B and A are 0, it is changing. Again 0 0, it is changing right; again 0 0 it is
changing right. And both of the A and B 0 0 means A bar and B bar are 1, so that way
right we can take this A bar and B bar ANDed and put them together, and we can get a
output, we can get a circuit like this ok, so that will give you a synchronous down
counter all right.
And like what we discussed in the previous asynchronous case, previous class
asynchronous up and down counter, instead of A, B, C, if you take output if so possible
from A bar, B bar, C bar, the output will be just opposite A B C, if it gives down count A
bar B bar C bar will be giving you up count ok. And similarly in the previous case also,
for up counter design, if you take the output from the inverted terminal, complemented
terminal, it will be giving you a down count.
(Refer Slide Time: 26:05)
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Now, we can move to a synchronous up and down counter, right. So, again there can be
two arrangement. So, in one arrangement this there are two clocks, one is a count up. So,
when we are giving the clock through this, then the countdown clock is 0 ok. So,
countdown clock is 0, this input is 0 right whenever we are feeding clock here right. So,
this A is coming over here - this is the first circuit, first arrangement that we have seen in
the discussion related to up counter; and its corresponding counterpart is coming here for
the down counter right. So, this is coming, so basically then A ANDed with this clock is
fed here right, and this will be 0 because this is 0.
Similarly, the A and B ANDed with the clock will come here, and this is this output will
be 0 and so on, and it will continue right. And if we have, if you are looking for down
count, then you want to feed the clock through A bar B bar, A bar B bar here, A bar B
bar C bar over here right, so that is what we will do.
(Refer Slide Time: 27:17)
And we will put this to be 0 and this is the clock that will be fed here right. And in the
other arrangement, again similar to the asynchronous up down counter, we can have a
mode control input right when if it is 0 all right.
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(Refer Slide Time: 27:35)
So, then this is 1 and this is 0 all right and all this AND gates outputs will be 0 0 0 right,
and then A is fed to J-K input and in this case A and B ANDed is fed to the J-K input
here, this is your this is your A right. So, this is A, B and of course, M bar is there with it
right. And this is your A B is already there, A B C and M bar is there right. So, we can
have a three input AND gate also like the one that you had seen before, in this case
instead, here we are only having in all the cases because we are feeding the AND logic,
AND gate output of the previous stage; so, every case we have got a 2-input gate.
But remember in this case there is a small you know, accumulation of delay right,
because this gate, this gate – these delay get accumulated, so that issue may come up if
you are clocking it too fast right; so, that need to be taken care of ok. Otherwise, it is like
that, only one propagation delay. But, then too many, for a larger number of, you know
bit associated, flip-flop associated in the counter design then the fan-in could be an issue
if we go for multi input AND gates.
And this arrangement only we are having 2-input AND gates, but the thing is that there is
accumulation of delay before clocking of course, right not after clocking right. So, a flipflop has changed, so after that the delayed value will make the appropriate clocking
available to the next flip-flop ok, so that we need to take note of. And for M is equal to 1,
we know that the down counter, A bar B bar C bar, these are the ones that will be fed
here. So, this is how we can design a synchronous up-down counter.
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(Refer Slide Time: 29:51)
So, with this we conclude quickly. A decoding gate connected to the outputs of a
counter, is activated only when a counter content is equal to a given state. For optimal
use of number of flip-flops in counter design n bit counter requires n input logic gate for
decoding. So, for mod 8, we have seen that 3-input logic gate will be required; for mod
16, 4-input and so on and so forth. So, decoding gates strobed by clock can remove
propagation delay related glitch in asynchronous counter.
In synchronous counter, every flip-flop is triggered simultaneously which avoids the
accumulation of delay and possible glitch. Unlike asynchronous counter, additional logic
gates are required in synchronous counter. So, in asynchronous counter, we have seen
that output of one flip-flop is fed as clock to the next flip-flop. Here we are putting some
additional logic gates in the synchronous counter circuit. And, design of synchronous up
down counter is analogues to asynchronous counter, but where we are feeding for up
count certain input and for down counts certain other input, and the intermediate logic or
the box is 2-to-1 multiplexer, the way it works ok.
Thank you.
629
Digital and Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 43
Cascading: mod-2, 3, 5 to Mod 6, 10, 1000 Counter
Hello everybody. In the last two classes, we have discussed synchronous and
asynchronous counters, up and down counters with modulo number-8 and we had seen
how it works even for modulo number 16 right. And we can of course understand that
how it will work for modulo number 4 also ok, though the basic circuit that we had
discussed for 8 and one example we had seen for 16 right.
(Refer Slide Time: 00:52)
So, this is - where the modulo number was on in the integer power of 2. So, in today’s
class, we shall look at some other modulo number like modulo-3 counter, modulo-5
counter and then we shall look at the effect of cascading.
I mean if we cascade one counter with the another counter, we can get a modulo number
which is if you just multiply them, then whatever the value, that modulo number will
come up ok. So, we shall look at such arrangement ok.
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(Refer Slide Time: 01:19)
So, we begin with mod-3 counter ok. So, let us see the circuit of one mod-3 counter
right, so it is made up of JK flip-flop right. And it is synchronous the clock is fed here
right. And in this B bar is fed here as J input of A flip-flop ok. And A output is going as J
input of B flip-flop all right. And K input for both the flip-flops are connected to logic
high ok, very simple circuit the you can see all right.
Now, let us see how this circuit behaves; how this circuit behaves ok? So, initialised with
0 0, so this is the clock right. So, 0 0 then at that time your JB - KB and KA is always 1,
this is permanently connected to 1, all right. So, JB is A, so A is 0 means, JB is 0 right.
And what about JA? JA is B bar, B is 0 all right. So, this is 1 ok. JA is B bar all right, it
is fed back like this ok, so this is 1.
So, after the clock trigger, what will happen? So, this is 0 1 right JB - so it will remain at
0, and this is 1 1, it will toggle from 0, it will come to 1, is it clear. From 0 0, we have
come to 0 1. We are analysing a sequential circuit right. Now, when it is like this, so JB
now, because A has become 1 right, so JB is 1, KB is always 1, JA since B is still 0, B is
still 0, it remains at 1 and this is 1 right.
So, next clock trigger, both the flip-flop toggle. So, 0 becomes 1 and 1 becomes 0 right,
this is the case. After that what happens, JB is A means, the 0, this 0 comes here and JA
is B bar, so B is 1, so it is 0. So, this is 0 1 and this is 0 1 ok. So, it will - after clock
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trigger what will happen, so both of them will get 0. So, we are having 0 0, 0 1, 1 0, 0 0
ok, this is visible in the timing diagram also.
So, once it goes to 0 0, the cycle will continue. Cycle will repeat, after 0 0. After 0 0, 0 1
will come and 1 0 will come ok. So, this is the mod-3 counter that you can see. And in
this case; in this case if you take the output from flip-flop B ok, so every 3 clock pulses,
it will remain high for one clock period -is not it.
So, regarding the decoding logic and all, this B flip-flop output directly gives you the
output that a count of 3 has taken place and it will remain high for one clock cycle right.
So, we do not need any separate circuit for that ok, is it clear. So, if we put this thing as a
mod-3, you know block like this right with in which we know that this is the circuit, this
is the way the circuit behaves ok. So, 0, 1, 2, again 0, 1, 2, this is way the count goes on.
(Refer Slide Time: 04:42)
If that is the case, then let us see if we connect a mod-3 and mod-2, mod-2 you all know
right 2, 4, 8, 16 right. So, mod-2 means only one flip-flop at its output, it is divided by 2
right, so that is mod-2 counter.
So, if mod-3 and mod 2 put together, what happens ok? So, there are two arrangements.
In the first arrangement, first we are putting the mod-3 ok. And the B flip-flop which is
going high and remaining high only for 1 clock period for every 3 clock pulses ok, so
that is, that B output is fed as clock to the next flip-flop - that is the mod-2 counter right.
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So, in this case, what happens? In this case, this is your A and B, which is changing as 0
0, 0 1, 1 0 right. After that again 0 0 from the previous discussion on the previous slide
right 0 0, 0 1, 1 0, right a count of 3 has taken place again 0 0, 0 1, 1 0, again 0 0, 0 1 ok,
1 0, because count of 3 has taken place, so it is repeating right.
Now, every time B goes from high to low. So, B goes from high to low over here, B goes
from high to low here, B goes from high to low over here. So, this Q which is written as
C here ok, it toggles ok. So, it toggles means, so C was 0 - initialised with 0, so it
becomes 1. So, it will remain 1, till it gets next negative edge of B right, over here. Then
again it will be become 0 and then it will continue - is it fine.
Now, if you look at these 3 flip-flop outputs together C, B, A ok, the unique states they
define for these clock pulses that is fed over here ok, then what are those unique states?
So, put together you can see 0 0 0, 0 0 1, 0 1 0, 1 0 0, 1 0 1, 1 1 0, then again 0 0 0, 0 0 1
comes right - is it fine. This what you see, if you read it along this line C, B, A this way
right.
So, you have got 1, 2, 3, 4, 5, 6 6 unique states, unique states after which it repeats. So,
what does it mean? It is a mod 6 counter right, according to the definition of modulo
number of the counter. See it is a mod 6 counter and what are the counting states 0, 1, 2,
4, 5, 6 again 0, 1, 2, 4, 5, 6. So, this is the way it will continue, is it fine.
Now, for a mod 6 counter given the mod-3 counter was giving you 0, 1, 2 and then again
0 right, you may think that can we get a mod 6 counter, which is 0, 1, 2, 3, 4, 5, so 6
unique states the count value, then again it becomes 0 ok. So, this arrangement does not
give you, the previous arrangement see it gives you 0, 1, 2, then 4, 5, 6 ok, 3 is missing
right. There are 6 unique, unique states, but it is missing.
Now, if you put the mod-2 counter, before the mod-3 counter, then let us see what
happens ok. Since, we have already defined A and B, mod-3 counter here as A and B, so
we are just keeping it Q right. Otherwise, you write C also, but to avoid, so in this case it
is you know the order is different it is A, B, C. So, it will be B, A,Q ok, so, this is the
MSB to this is your MSB ok, and this is your LSB.
The clock is fed here the one, it will change faster as compared to the others actually is
your LSB right. So, and the MSB changes slower, so B will be the one like this. So,
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coming back to this discussion mod-2, before mod-3. So, this Q changes in every clock
negative edge right these negative edges, it is changing 0 1, 0 1, it is toggling right. Now,
for this mod-3 counter, forget about this clock for the time being. So, this is the clock,
this Q is now fed as clock here, at it is negative edge, it will behave like a mod-3 counter
right. So, it will give you, so this is one full clock cycle for this particular mod-3 counter.
This is another full clock cycle, this is another full clock cycle. So, 0, 0 1 - 0 0, 0 1, 1 0,
again 0 0, 0 1, 1 0, this is the way it will continue right. So, one clock cycle, full clock
cycle for Q which is fed here as clock is two clock cycles over there, so that is why, you
can see 0 0 is there for two clock cycles; and 1 1 again for two clock cycles like this ok,
because this Q is a divided by 2 ok, in terms of the frequency compared to clock - right.
Now, if you do the reading from B, A, Q, as I said MSB is your B and A this is Q. So, 0
0 0, 0 0 1, 0 1 0, 0 1 1, 1 0 0, 1 0 1 and then again 0 0 0 is coming ok, so that is the way
you have to read the data, then you can see 0, 1, 2, 3, 4, 5 again 0, 1, 2 right. So, it is up
counter without skipping any counting value right. So, this is the way, you can get mod 6
counter by cascading mod-3, after that mod-2; and also mod-2, after that mod-3 ok and
the counting states value will be like these in each of the cases.
(Refer Slide Time: 11:10)
Now, let us look at mod-5 counter - one arrangement, again there could be many
different way, it can be made. So, there could be other than JK flip-flop other circuit as
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well right, even with the JK flip-flop there could be different arrangements. So, this is
one arrangement ok.
So, in this what you can see that KA, KB, KC right, all of them are permanently
connected to Vcc right. JA is connected to C bar; JA is connected to C bar, you can see
right. JB is also connected to 1 right, but Clock B is fed by A ok. How that happens, how
that effects and all that we shall see in the timing diagram ok.
And JC is fed by A AND B, A AND B fine. So, this is the initial circuit that we see. And
then we shall examine, how it behaves like a mod-5 counter right. So, here the A flipflop will toggle ok, whenever these the inputs are 1 and 1, so that is the case in the
beginning, when this C is equal to 1, I mean initialized with all 0 0 0 ok, this all are 0, so
this is 1 right.
So, what I have written here, this - in this notation. So, these are the J and K ok and flipflop JK inputs are shown for each before clocking. so this one is there right and this is
permanently connected ok. So, then A will toggle right, so A will toggle means, A will
become - from 0 it will become 1 right. Now, when A goes from 0 to 1, this flip-flop
does not get the trigger. This flip-flop will get the trigger, whenever A goes from 1 to 0
at the negative edge of it, because it is an negative edge clock, negative edge triggered,
right.
So, you can see for B flip-flop, there is no trigger. B flip-flop trigger is for these brown
marks ok. These brown you know lines that is there which is associated with the negative
edge of flip-flop A output, flip-flop A output right. So, B flip-flop at that time will
remain at 1 1 only input will remain at 1 1 only and the value will remain 0 for this clock
cycle as well, because it has not got any clock trigger.
What happens to C right, C it is - input is AB, A AND B, so the input is 0 right and KC
is 1. So, this is always 1, so this is 0 1, so the out value will remain 0, this fine. So, after
1 clock pulse right what we can see, the values are 0 0 1. So, this is 1, this is 0 and this is
0 right. So, then this is 1 fed back here, so this will again toggle.
So, from 1 it will become 0 right, so that is what has happened ok. And when it toggles,
these gets a negative edge, so B becomes - from 0 it becomes 1, so that is what you have
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seen, what you see over here ok. So, this is 0, this is 1 and for this flip-flop, the input is
still 0 1 for which this is 0 ok.
Next again since C is still 0, so A will again toggle that is what has happened, so it has
become 1 right. And unless the negative edge of clock comes, so A comes - B will not
change. So, B is remaining at 1 all right. And C, before that it is only 0 and 1, because
this A was 0, so it is remaining at 0. Now, at this point of time, what you can see that A
is 1 and B is 1, so, this JC is getting 1 1.
So, then the next clock trigger - what happens. Next clock trigger - C becomes, C is
always getting the clock all right becomes 1 right. And before clocking of course C bar
was 1, so A has toggled right. And there is a negative edge, so for which it has also
toggled for which it has become 0, B has become 0.
Now, at this point of time since C has become 1, so C bar is 0, you can see the input of
flip-flop A is 0 1, so it will, this output will remain 0 ok. And this output is also 0,
because it is no negative edge ok. And at that time A and B, both of - here this AND
input for which it is 0 and this is 1. So, this next the output C 0, so, we are coming back
to 0 0 0 right.
So, now if you look at the timing diagram and now these values, counting states. So, this
is 0 0 0 right, 0 0 1, 0 1 0, 0 1 1, 1 0 0 and then again 0 0 0, ok. So, this is what you can
see over here right. Again it comes back to 0 0 0, so what is it 5 counting states, and it is
sequentially increasing ok. So, it is a mod-5 counter clear right. So, as I said there can be
other arrangement also, this is one arrangement.
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(Refer Slide Time: 17:05)
Now, what we expect to see the cascading, and getting mod-10 counter and like what we
saw for mod 6 counter, where mod-3 and mod-2 were put together one after another. So,
here mod-5 and mod-2 will be put together one after another and we shall get mod-10
count, that is what we expect right. And again there could be two arrangement mod-5
first, mod-2 later and mod-2 first, mod-5 later. So, these are two possible arrangements.
So, we shall examine them.
(Refer Slide Time: 17:42)
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And before that, we also take note that here C output is remaining at high for one clock
period, in this particular arrangement ok. And, so this can directly give you, this
signalling that a count of 4 that is from 0 to 4 that has taken place 1 0 0 state has
occurred right.
So, coming back, so mod-5 followed by mod-2 ok. So, in this case the A, B, C, this the
first one, this three are mod-5 counter, so 0 0 0, 0 0 1, 0 1 0, 0 1 1, 1 0 0 ok, then our
again 0 0 0 is coming and so on and so forth right.
And at the negative edge of C; C is fed as clock here, it will toggle, flip-flop D will
toggle ok, so that is what is happening at the negative edge of C, you can see that D has
changed value. So, this is the negative edge of C. So, from 0, it was initialized with 0, it
has become 1. Again the negative edge of C will come here. After the A, B, C, the mod-5
counter has gone through 5 clock cycles right, 5 clock edges. So, again at that time it is
coming from 0 1 to 0 and this is the way it continues ok.
Now, if you look at this state values, so 0 0 0 0 together that means, you are reading D,
C, B, A together ok. So, this is - in every case you put the 0 - 0, then after that 1, so this
is 0 0 1, then this is 1 and this way it will continue.
So, the first 5 values you can see 0, 1, 2, 3, 4, after that what has come 1 three 0’s, 1 0 0
1 ok. So, 1 three 0 is nothing but 8, and this is 9 right. So, these are unique ten states 0, 1,
2, 3, 4, 8, 9, 10, 11, 12 unique 10 states right. But, the count value if you convert from
binary to decimal and you know, in that manner. So, these are 0, 1, 2, 3, 4, 8, 9, 10, 11,
12, again 0, 1, 2, 3, 4, 8, 9, 10, 11, 12, so this is the way, it will continue ok. But, this is a
mod 10 counter because of 10 unique states that are there right.
And again if we for a you know mod-10 counter, the we would expect that number will
be 0 to 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, the way binary coded decimal are represented ok. For
that what we need to do, similar to what we had done for mod 6 counter. So, we shall
place the mod-2 counter first ok, followed by mod-5 counter ok.
So, now this mod-2 counter, we are naming it as A ok. And these we are naming, at this
mod-5 counter, as BCD right and so, this A is changing at every clock trigger right. And
after that this A is effectively feeding as clock sorry this is not this one, if there was
another like here. So, feeding as clock to the these 3 flip-flops BCD ok, the mod-5
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counter, and at this clock edge it will change from you know 0, 1, 2, 3, 4, 5 ok. So, this is
the way it will go on, right.
So, now if you look at the state values, so 0 0 0 0, then 0 0 0 1, 0 0 1 0 ok, 0 0 1 1, 0 1 0
0 ok, then 0 1 0 1, then 0 1 1 0, 0 1 1 1, then 1 0 0 0, 1 0 0 1 and finally 0 0 0 0. So, 1 0 0
1 means 9, after that again 0 has come ok. See you got 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and then
0, 1, 2, again it repeats. So, this is mod-10 counter, but where the numbers are
sequentially increasing and there is no such jump like from 4 to 8. So, this is called BCD
counter, and this is called bi-quinary counter, 5-2 counter ok so, 5-2 right.
(Refer Slide Time: 22:48)
So, would like to see one IC 7490 ok, where we have a mod-10 counter implemented ok.
So, IC 7490 A is one such IC right. And this IC has got a mod-5 counter over here right,
and a mod-2 counter right. And you can see there are 2 clocks, this is one clock and this
is another clock. This clock is associated with mod-2 counter and this clock is associated
with mod-5 counter right.
Now, when you want to make it work like a - so we can make it work like individual
mod-5 and individual mod-2 counter. So, for mod-2 give input here, output here; mod-5
we give input here, and we take the output from QD right. All three of them are giving
the counting states, but that a count of 5 as taken place the final signalling, if you
required you know in certain sense that decoding of 1 0 0, we can take it from here right.
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So, but if you want to work them, work it as a mod-10 counter, we have to cascade one
after another right. So, the cascading can be done, again one of the two ways that we
have mentioned. So, if we want a BCD counter made out of it, so mod-2 counter should
be first. And then mod 5 counter will be following.
So, at that time clock will be fed here right, the external clock which is getting counted
or external event that - trigger of which is getting counted. And this QA need to be
connected over here ok, then the circuit will behave like a mod-10 counter BCD counter
right. And instead if we want Bi-quinary counter, then the clock will be fed here the
external clock will be fed here and this QD will be connected to clock A. Is it fine?
Right.
Now, comes there are two other inputs, two sets of other inputs you can say, this is R01
and R02 right, so when any one of them is low ok. So, this proper count is happening, I
shall discuss it later. So, when both of them are high, then this output is low, this output
is low and it will be cleared all of them will be cleared, ok. So, the all the output will
become low ok, when both of them are high; irrespective of what is happening over here
right.
Now, when irrespective of what is happening means, one of them remaining low ok,
please understand that. So, when both of them are high ok, if one of them this R9; R9
means it is setting 9, so that I will come later. So, one of these inputs is remaining low,
irrespective of what is happening to the other input, the output will be, all this things will
be asynchronously cleared, right.
And when these two are high, these two are high, irrespective of what is happening at
these places right. So, these particular 4 flip-flops will be loaded with 9 high, low, low,
high, QD, QC using pre-set and clear. So, all of them have got a pre-set and clear input
right - these two are not required, because thy will be only getting the clear value 0. So,
these two flip-flops have got both pre-set and clear ok. So, this will be having your what
is that called - 9 will get loaded right.
And when any one of them are low, then for both the cases, the normal count will happen
based on the clocking arrangement that we are having either BCD or bi-quinary. If we
are looking for mod-10 counter, otherwise normal mod-5 or mod-2 counter, it will work.
Is it fine? Ok.
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Again we shall discuss in next class or subsequent classes why these two inputs and an
internal logic gate has been put in this manner. At that time, it will be clear. So, right
now if we just need to clear it, you can connect one wire and we can you know feed it to
both of them and we make it high, it will become clear ok. Later on, we will see how
these two inputs and this internal logic gate will be helpful in subsequent classes.
(Refer Slide Time: 28:05)
Finally, we can extend the way we were cascading circuits to get higher modular number
from 6 to 10. Now by connecting modulo 10 counter in cascade like this 7, 4, 9, 0 three
of them, one after another ok. What we can get, we can get a modulo 100 sorry not 100,
this is 1000 ok, please take a note of this modulo 1000 counter 0 to 999 ok, the count is
possible right.
So, whenever this changes by 10, it gets a clock, I mean every time changes, there will
be a negative edge available and similarly over here and similarly over here, so that way
we can get a modulo 1000 counter available by cascading right. If we cascade two of this
thing, not this one is say there, so it will get modulo 100 ok, 10 and 10 right - is it fine.
641
(Refer Slide Time: 29:27)
So, with this we conclude today’s class, mod-3 and mod-5 counters we have seen require
2 and 3 flip-flops. And the way we have designed them is 0, 1, 2, 0 for mod-3 counter
and when we have we are cascading it, we can get depending on whether mod-3 is there,
before mod-2 or mod-2 is there before mod-3, we can get 0-1-2-4-5-6-0 or 0-1-2-3-4-5-0.
Similarly, for mod-5 counter, we have the states counting states 0-1-2-3-4 in our, in that
circuit that you have seen. And when mod-5 and mod-2, we are putting them one after
another in the cascaded circuit. Depending on mod-5 is before or mod-2 before, we have
got bi-quinary arrangement or a BCD arrangement BCD count happening ok. And 3
mod-10 counter in cascade gives mod-1000 counter ok.
Thank you.
642
Digital Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 44
Counter Design with Asynchronous Reset and Preset
Hello everybody. In this class, we shall look at Counter Design using Asynchronous
Reset and Preset.
(Refer Slide Time: 00:33)
We have been seeing in our earlier classes that some of the ICs; counter ICs are having
internal AND gate logic AND gate and there are two inputs to it. And we told that, from
the truth table, they can be used for resetting purposes.
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(Refer Slide Time: 00:50)
And in IC 7490, we had seen that there can be a preset of 1001 as well; again there is an
internal AND gate.
So, we actually were surprised why such thing is there, why that internal AND gate is
there why not only one pin. So, it will be clear from today’s discussion that how a
asynchronous reset can be used to get different kind of modulo number and those
internal, those inputs and the internal AND gate can come useful in this particular
context. So, that will require, that will eliminate the requirement of additional external
AND gate and placing another IC, taking more space, wiring and other things. So, those
can be prevented.
So, let us see IC 7490A with that we are looking at. So, it is we are already familiar with
this circuit this IC. It is a mod-10 counter and if we connect it appropriately; that means,
mod 2 followed by mod 5, then it acts like a BCD counter. So, BCD counter means it
goes from 0000, 0001 up to 1001 that is 9, decimal equivalent 9, then again it goes to
0000 so that we - that is what we know, we have seen in the previous class right. So, the
IC 7490, this particular BCD counter has been connected in this manner ok. So, clock is
fed to mod-2 counter and QA output is fed to, as clock to mod-5 counter and these are
the ABCD or the QA QB QC QD, these are the outputs ok
So, the count in that particular counter with clocking as given here will go on as I have
mentioned here 0 0 0 0 to 1 0 0 1 and then again 0 0 0 0 ok. This we are already familiar
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with. Now, if you are connecting QB and QC output 8 and 9, output one of them is going
to 2 another is going to 3 right. So, if you do that, what will happen? So, these are R01
and R02 ok. So, these asynchronous reset input, internally there is an AND gate ok. So,
when both of them are high, when both of them are high, then what happens? This
particular outputs are asynchronously reset, this counter is asynchronously reset; that
means, immediately after a short time of that propagation delay of the internal AND gate
all the values gate 0 this QA QB QC QD all of them acquire the value 0 ok.
So, the counter is having a short, very short duration - some number associated with this
and then it goes to 0 0 0 0 ok. So, with the count happening 0 0 0 0, 0 0 0 1 that way
what is the first instance when these two become 1 1? So, that it goes to 0 0 0 0; again it
goes on counting similarly, I mean the way the clock gets triggered. If we follow the
counting sequence we can see that 0 0 0 0, then 0 0 0 1, 0 0 1 0, 0 0 1 1 you will note that
QC and QB are fed ok.
So, this is your QC and this is your QB. After that 0 1 0 0, 0 1 0 1 and then comes 0 1 1
0. So, this is the first time in this counting sequence as you see that QC and QB both of
them are becoming 1 ok. And when both of them are becoming 1 immediately; that
means, after that short propagation delay which is much, much you know, less than the
time period of the clock ok. So, what is happening? It is immediately going to 0 0 0 0.
So, in that particular clock cycle, you are effectively having for larger duration,
effectively you are having 0 0 0 0 so; that means, you are back to this particular number
this particular state. Is it fine?
So, what are the then unique states for which the clock period, during the clock period
the counter holds a specific value? So, these are the ones - 0 0 0 0 to 0 1 0 1 ok. After
that it again goes to 0 0 0 0, for very small duration staying at 0 1 1 0 ok. So, effectively
you are having 0 1 2 3 4 5 and again back to 0 right; so, 6 unique states ok. So, this is
called, this is behaving like a mod-6 counter and if you had required to do this by
external connection, then we would have required a 2-input AND gate and then that
output would have been fed to one of the input.
So, that additional circuitry, wiring and you know putting another IC 7408, powering it
and all those things are not required and that need is eliminated. Now having noted this,
that 0 0 0 0 to you know 0 1 0 1 and the value where with which, wherever it goes, then
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you know that and 0 0 0 0 stays together in this particular mode ok. So, if QD and QA
right; this is QD and this is QA right if they are sent here instead of QC and QB right.
QC and QB were sent; now, we are sending QD and QA to this asynchronous reset.
What will happen then?
So, it will go from 0 0 0 0 to first time whenever it goes to both of them QD and QA
become 1 that is 1 0 0 1, immediately it gets reset. So; that means, for a very short
duration it will be there and then 0 0 0 0 will be there right. So, effectively you are
having 0 to 8; 1 0 0 0 and in this particular clock cycle 0 0 0 0 is again getting, again
appearing because of this asynchronous reset. So, effectively you are having 0 to 8; that
means 9 unique states. So, it behaves like a mod 9 counter ok. If you want a mod 8
counter so, what is the first occasion when you know - this is how, this is the count so, 0
0 0 0. So, 1 0 0 0 this is your - this is the time when you want to reset it ok.
So, before that you had 0 1 1 1 right. You want 1 0 0 0 and 0 0 0 0 at one particular clock
cycle. This is the one with which you want to reset it ok. So, 1 has not come before 1 is
coming for the first time right. So, 1, QD you can feed to just take a wire and connect to
both of them; that is fine internally it is getting ANDed both the input are 1. So, that way
you can get mod 6, that way you can get mod 8, that way you can get mod 9 right. But, if
you want to get a mod 7 right, then the first time it is happening it is 0 1 1 1 ok.
Now, with two inputs ok, it is not possible because if you give just these two, then it is
mod 6 ok. First time it will occur when 0 1 1 0 and if you want to give these two inputs
right that will also occur when it is 3 and if you want to give QC and QA that occurs
when it is 5, isn’t it. So, you need all the 3 inputs I mean, this QC QB QA for which you
will be needing an external gate in this particular arrangement, is it fine ok. But
otherwise, you can see that for the other cases, we are having this you know other
modulo number obtained by just connecting wires in this manner.
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(Refer Slide Time: 09:38)
Now, we shall look at something which is, where the use of fixed preset which is there
with 7490A that we shall exploit for this modulo number design.
So, here we had seen that when R91 and R92 - R9 means it is setting a value 9, 1 0 0 1
ok. So, when this 6 and 7 earlier we have kept at ground because these are the ones that
we are using right. So, if we keep 2 and 3 ground and these 6 and 7 where R91 and R92
are there ok; so, if both of them are high, then what happens? 1 0 0 1 this is 1 0 0 1 gets
loaded, isn’t it? 1 0 0 1 gets loaded instead of 0 0 0 0 it is now will be having a value 1 0
0 1. So, we take note of this from the truth table and then we go forward.
So, what has been done here? What you can see is that the it is again a BCD counter
right 2 and 3 now is kept at ground. So, there is no resetting happening; no asynchronous
resetting happening. Asynchronous preset can occur if right condition appears otherwise,
it will be normal count as it was in the previous case. So, if you are having, in the
previous case 0 1 1 0 - the same thing right; so, 0 1 1 0 means QB and QC - first time it
is occurring in the counting sequence say if you have you have started from 0 0 0 0 the if
you have started from there it goes on and then when first time it is occurring here and
then it is getting what? 6 and 7.
So, R 91 and R 92 internally it is AND gate is there. So, both of them are high. So, 1 0 0
1 will be appearing. Very short duration it will be there after that 1 0 0 1 will be there.
So, primarily this particular state is 1 0 0 1 having the value counted value 1 0 0 1 except
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for that small propagation delay associated with the internal AND gate ok. So, this 1 0 0
1 right when it gets loaded after that what will happen? It is normal count, usual count.
So, after 1 0 0 1, 0 0 0 0 will come then 0 0 0 1 will come and that way it will continue
after again when it comes 0 1 1 0 it will again get preset, again it will get preset, that
fixed preset it will occur. So, the counting sequence, counting states, unique states are 1
0 0 1, 0 0 0 0 and then it goes on up to 0 1 0 1 and then again it goes back to 1 0 0 1.
So, you have got now 6 unique states sorry, 7 unique states 1 2 3 4 5 6 and 1 0 0 1 got
added right; so, 7 unique states. So, what is it? It is a mod 7 counter right. So, mod 7
counter also - you can get it without any additional gate and all if you use the fixed
preset part of it. Is it fine? And there can be other uses as well, right. Now we look at
another IC where some such preset is there, but that is variable preset.
(Refer Slide Time: 13:12)
Here, there was a fixed preset. So, here we have got variable preset; that means, we can
load numbers other than 1 0 0 1. 1 0 0 1 is possible and any other number that we shall
see how it works. So, this is IC 74193 ok. So, IC 74193 interestingly has got various
features.
So, first of all it is a synchronous 4 bit up down counter. So, it can count both in the up
direction; that means, 0 1 2 3 4 and also in the down direction; that means, 15 14 13 12
etcetera and for this, you have got two clock input right. So, when one of them is active,
the other one should be inactive. So, if it is other one - need to be held at logic high,
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why? You can see there is an OR gate, then it is going to the input. So, if it is at high,
then this output is low. So, then other input of the OR gate to which the other clock is
being fed, so, that clock will take over the output and accordingly the clocking will take
place. Is it fine?
So, that clock input, the one that is not used, will be kept at high, right. And other thing
that is important here we know that this QB QC QD QA the uncomplemented outputs
will take role when we are going for up counting and complemented outputs, they will be
participating when we are going for down counting ok. So, basically the number of - they
need to be ANDed. And, depending on count-up or count-down whether ABC for here or
A prime B prime C prime that will be fed here and similarly A B or prime B prime or A
prime that is the thing that will come here. So, these are the things that we already know
from synchronous up-counter down-counter design. So, those things are over here. The
other thing important in this particular IC is that there is a load input, there is a clear
input that is reset. So, all of them get reset 0 0 0 0.
So, this is a single input ok. So, there is no such facility available that two inputs are
there and all and you will see that it is not required because of this variable preset that is
there. So, we can get a different kind of modulo number easily. So, this is a single input
clear all right and then there is a load input ok. So, whenever it is activated,
asynchronously whatever number is there DCBA that will come to QD QC QB and QA,
respectively without the need of the clock. So, immediately it will come after the these
gate delays and all. So, it will get transferred to the output ok.
So, this is a parallel-in getting loaded, asynchronously getting preset. So, this is variable
because DCBA value can be different right. So, the idea is if you are basically putting a
1, then you are presetting it; if you putting a 0, you are resetting it is clearing it the
corresponding flip flop so, similarly for other bits right. So, other than this, you have got
a carry output and borrow output here. So, whenever the number is increasing say, 0 1 2
3 4 going to say 15 in count-up mode then it has reached 15 and it is going to say 0; next
cycle ok, next clock cycle.
So, it has reached 15, the clock has gone low that it is a positive edge triggered ok. So,
you can see here is a inverter and here is a inverter. So, effectively it is a positive edge
triggered right so, with two inverter from here from this side from the input side ok. So,
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whenever the counter clock input goes low in the second half of it right and the value is
15, then at that time the carry output will be active ok; only for that small duration as
long as this clock input is remaining low. And borrow output will be happening in the
other direction when it is getting - the count is from 4 3 2 1 0.
So, when it goes to 0; that means, all of them are 0 and countdown clock is at logic low
in the second half of the clock cycle. at that time it will be active otherwise they will not
be active and this is the count-up count-down the sequence that we can see is it ok. So,
we shall see its performance with timing diagram that will make it more clear.
(Refer Slide Time: 18:29)
So, this is the timing diagram, I am talking about. So, you see, initially the counter may
have some value QA QB QC QD over here by right. So, whenever you are giving a clear
– right; so, all of them are getting cleared, asynchronously cleared. So, you can see that
all of them are cleared right. So, after that clear input is taken away, is inactive - right.
So, clear is a you can see is active high- right and then in ABCD all right, these are the
data that is input of it. So, at the input you are putting a value D is 1, C is 1, B is 0 and A
is 1 – right; and whenever you give load which is active low, you make it low, what will
happen? Earlier it was remaining cleared ok. So, whenever you do that this QD QC QB
QA, they take these values.
So, now they become 1 1 0 1 right. So, that is what has been shown here as 13 getting
loaded right. So, the clock in these cases when it was happening clocks were at logic
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high ok. So, then the OR gate output was 0. So, basically there is no change, clock was that is no clocking happening right. Now, the clock countdown up that is remaining at
high so; that means, it is inactive, it is not playing any role in the clocking and count up
has started clocking, ok. And what what you can see? In the positive edges, it is - QD QC
QB QA, the values start changing right I mean, get triggered. So, after 13 at the positive
edge, what will happen? It will go to 14, after that it will go to 15, after that it will go to
0, 1 2 and so on, 3. But what you are doing just to show that how counting happens, to
illustrate that ok.
So, after that you consider that count up has remained high ok. So, no more clocking; so,
no more state change, it is remaining at 2 and countdown was also high. So, it is
remaining at there is no even countdown clock also. So, it is remaining at that particular
value ok. So, what you can see here 0 - 0 0 1 0 that is 2. Then what happens? Count up
remains at high and countdown starts clocking ok. So, at its positive edge what will
happen? So, from 2 it will go to 1 then 0, then 15, then 14, then 13.
So, that is how it works. So, I understand that with this illustration, there is more clarity
about how this clocking and counting takes place and along with the parallel load and
clear ok. The other thing is that you can see when it is at fifteen and clock is at logic low
ok. From the logic circuit also you can see that happening. So, the carry is remaining low
for this half clock cycle duration and similarly, borrow is for when it is 0 and for this half
cycle duration. Is it fine?
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(Refer Slide Time: 22:12)
Now, let us see how it helps in getting different modulo number ok. So, we have seen
this particular state transition diagram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 again 0 1 2.
This is the standard mod-16 counter; states are 0 to 15. Is it fine - right? Now we
consider that we have put an external gate ok; QA QB QC QD they are connected. So, it
is a 4 input NAND gate and so its output will be low when both of, all of them are 1
because for NAND gate any input is low means output is high.
So, all of them are 1, it becomes low as soon as all of them are 1, it will become low and
this is sent to what, this is sent to your parallel load that is asynchronous preset input
which is active low ok. Now for different condition, different data input we’ll be having
different data now getting loaded whenever this parallel load occurs-ok; asynchronously
within the same clock period right, after the whatever this small propagation delay is
there with the basic gate right. So, if you have got your DCBA data input at that time is 1
0 0 1, what will happen?
Whenever this reaches 15 immediately within that clock cycle the way we had discussed
it for 7490 right 9 gets loaded because it is now variable preset. So, now, it is 1 0 0 1 like
before, but we have now put external values 1 0 0 1 separately. Earlier it was preset it,
you need not to do it for 7490. 1 0 0 1 was internally getting loaded, getting preset ok.
So, it will go to 9. So, 9 10 11 it is in up count mode all right, it will, if you are putting it
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in up count mode, so, 9 10 11 12 13 14 again as soon as it reaches 15 a asynchronous
reset. So, 15 and 9 are together in 1 clock cycle right and then again it will go on.
So, you have got 9 10 11 12 13 14, a mod-6 counter available with you right and had it
been a down counter, if you have exchanged the role of the clock. One of the clock is
now - countdown clock is active and count up clock is held at logic high, then what
would have happened?. So, after 15 loaded is 9 ok; I mean immediately within, the 15
and 9 together. So, then 9 8 7 6 5 4 3 2 1 0 again 15 right and at that time again, it will
get loaded immediately, this 9 will get loaded. So, how many unique states are there? 9 8
7 6 5 4 3 2 1 0 and 15 and 9 are together. So, you can see that the unique states are 1 2 3
4 5 6 7 8 9 10. So, it is a mod-10 counter.
Now instead of 1 0 0 1, you could have loaded any other thing. And in up-count mode
and down-count mode, there could have been different modulo numbers available
depending on your requirement ok. So, if you are, instead of say 1 0 0 1, if you are
loading say 0 1 1 0 ok, I mean this 0 1 1 0. Then what will happen? So, instead of 9, you
are loading 6 you are; instead of 9 you are loading 6. So, from 15, it is coming over here
ok; so, 6 7 8 9 10 11 12 13 14 15and 6 together; so, 1 2 3 4 5 6 7 8 9 ok.
So, mod-9 count will be there and similarly over here, it will go in this direction and
again it will get loaded see 15 and 6. Together it will give you mod 7, 7 unique states
right. So, this is the way with variable preset, you can have different kind of such things.
(Refer Slide Time: 26:47)
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Now, to end this particular class, we shall have a look at one simple example of getting a
digital clock using a multiple you know, counter and an arrangement to calibrate it to set
the time right. So, what you see over here is - this is the 1 hertz clock which you know
how to design using a triple 5 timer or if you have any other arrangement some stable,
you know, astable multi vibrator generator that also you can use ultimately what you
need at the input is a 1 hertz.
So, every 1 second there is a trigger coming ok. So, this is going to the seconds, this is
going to the - seconds is feeding to the minutes and minutes is feeding to the hours. So,
every 60 seconds so it is a - you can have a mod 6 and mod 10 together right and another
could be your what is it called - for minutes also a mod 60 and for hours you need a mod
12 ok. So, this will be the unit decoding; that means, 1 0 - 0 to 9 and then, this is 0 to 5
the tens place ok. So, 59 then it will go to 0 0; 0 to 59 - 00 to 59 then it will go to 00 and
at that time when it reaches that 59 to 60; that means, mod 60 counter 1 clock trigger
comes over here.
Similarly, for count of 60, one clock trigger comes over here. So, this is the way the
cascaded counter that we have discussed before, the same thing in a bigger framework
ok. So, that is one part of the story, the other one is what you see the switches that are
there so to calibrate or to set the initial timing right, you first disengage this one the reset
seconds right, then what you can do If you if your current time is say 350 ok? So, you
can you can put this one, you just connect this one. This press this one depress this one.
So, basically this will get connected. So, now clock is feeding here. So, every one second
there will be a change here in this hour count ok, every one second because now 1hertz
clock is now feeding it directly. So, whenever it reaches 3, you stop there right.
So, after that you put it over here I mean remove the depression. So, it will come back it
you know there is a spring load by which it is coming back it is appropriate switching
mechanism all right. Then you go to minutes so, if it is 50 again you wait if its initial
value was 30, then you have to wait for 20 seconds 20 such call you know things will be
there and it will come coming here and then you release it. So, it is set, the minute part is
set and then you engage it, then the counting starts ok. Is it fine? So, this is the way, we
can have a digital clock in place and it is how you initialize it, set the time correct.
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(Refer Slide Time: 30:23)
So, with this we conclude using asynchronous reset counting state 0 can be enforced
early and in a clock cycle, in which a specific count is reached ok - so, 0 0 0 0 will be
there whenever that particular number count value reaches. These helps in getting a
modulo number of one’s choice, but a glitch occurs because this state causing reset
appears for a short duration.
So, in the final class on this counter, the next class we shall see that what could be
alternate arrangement by which we can get this glitch removed or we can have a different
kind of counter design paradigm. The internal 2-input AND gates are useful in counter
ICs to effect asynchronous reset to obtain different modulo numbers that we have seen
IC 7490A provides a fixed asynchronous reset of 1 0 0 1 along with an asynchronous
reset to set the modulo numbers. 74193 - we have got variable preset which offers a lot
of flexibility and also you have seen that a digital clock can be made using counters
when we can have a mechanism to initialize it.
Thank you.
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Digital and Electronic Circuits
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 45
Counter Design as a Synthesis Problem and Few Other Uses of Counter
Hello everybody, we are in the last lecture of this counter topic. In earlier lectures we
have seen how to design Counter with different modular numbers using asynchronous
reset and a preset. And in that we have seen that there is a small glitch that is possible
because of the reset precedes going to the next state and asynchronous reset ensures all
zero or a preset value appearing in the same clock cycle.
So, in this particular class, we shall see how synchronous counter with different modulo
number can be designed and that design can be considered as a synthesis sequential logic
circuit design problem. And we shall see that those kind of glitch will not occur, it does
not require to go to next state. Straight away the next valid state in the sequence as per
the modulo number, if n unique states are there, those n unique states will be appearing
one after another.
(Refer Slide Time: 01:35)
And we shall also look at some specific application other than the ones that you have
seen before ok.
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(Refer Slide Time: 01:39)
So, we start with an example where we are taking mod-6 counter ok. So, in the mod 6
counter, we are having six unique states and we are considering up counter for this
discussion. And this counter has got the six states 000, 001, the one that you can see,
010, 011, 100 and 101 after that again it goes to 000. And we consider, of all the flip
flops, JK to be the one by which we would like to design it - right.
So, for JK flip flops, since it is a synthesis problem, for design, we shall refer to its
excitation table. So, this is the extension table right. So, if the flip flop current state is 0
and next state is also 0 as per this transition diagram, then at the input what should be
present 0 cross; 0 1 - 1 cross should be present; 1 0 - cross 1 should be present; and 1 1 cross 0 should be present. Cross 0 means one of 00 or 10; either way it is fine, ok.
One of these two combinations either 00 or 10 that will ensure 1 1 transition, 1 to 1
transition for J K flip flop, ok. So, this we already know from our earlier discussion on
flip flop. Then we shall follow the standard synthesis process. So, once we have this state
transition diagram, we shall go to the state table and we shall use the excitation table for
getting different input combinations for different states.
So, 0 0 0 is the initial state over here like right. So, for that the next state is 0 0 1. So,
what will be the corresponding input for Cn changing to Cn plus 1 - 0 cross from here; B
n is also changing to B n plus 1, that is 0 to 0 - so, 0 cross; and An changing from 0 to 1,
so, it is 0 to 1 transition - so, 1 cross. Is it clear?. We are just recollecting and what we
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had done before in simple synthesis example in earlier classes, so, this is the first row.
Similarly the second row: after 0 0 1, it has to go to 0 1 0 ok.
So, this is 0 1 0 and corresponding transition 0 to 0 - 0 cross; 0 to 1 - 1 cross; and 1 to 0,
1 to 0 you can see over here, 1 to 0 - cross 1. Is it clear? Second row is also clear, ok. So,
third row, third row 0 1 0 to 0 11 . So, 0 0 - 0 cross; 1 to 1, 1 to 1, this line - cross 0; and
then 0 to 1 - 1 cross ok, 0 to 1 – 1 cross. So, with this if you proceed, we will come to 1 0
1 right.
Now, after 1 0 1 in earlier design that was a module 8 counter, a standard counter and it
was going to 1 1 0 and we were doing an asynchronous reset so that 1 1 0 and 0 0 0 are
occurring in the same clock cycle for a very small duration 1 1 0 was there. Now in this
design after 1 0 1, we are going straight away to, straight a way to 0 0 0. Here it should
be 0 right it should be 0 right. So, 1 to 0; it should be cross 1 so, that is your cross 1; 0 to
0 - so, this is your 0 cross; and 1 to 0, 1 to 0 - so, this is your cross 1. Is it clear? So, this
was a typo error. Is it fine?
1 to 0 right that is your, I am doing it once more again. So, this will be; this will be 0; 1
to 0, this is your transition - cross 1. So, that is your cross 1; 0 to 0, 0 to 0 -this is your 0
cross; and 1 to 0, 1 to 0 again cross 1. So, this is cross 1 is it clear. So, from 1 0 1, we are
directly going to 0 0 0 right. So, this is the thing that we are doing in designing a modulo
number, modulo-6 counter using standard synthesis, design problem ok -the way we
solve it, sequential logic circuit design problem.
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(Refer Slide Time: 07:01)
Next, what is the next stop, next step? So, next step is from those inputs - that state table,
we are writing the equation, corresponding equation, for individual inputs. So, JC KC JB
and KB right, and we have already noted in the previous case - as JA and KA, if you
look at the previous one ok. So, 1 cross, cross 1, 1 cross 1, and so on. So, that is the
thing, that is being represented here and rest of the things are taken from here to the next
this Karnaugh map based this simplification. So, all of them are this 1 or cross so, we can
consider all of them as 1, then it becomes the simplest possible. So, that way you can
consider each one of them as 1 ok.
So, in the corresponding table, you can understand that this is 1 cross 1 cross then 1 cross
and this two are 1 1 0 and 1 1 1 - we can consider them as cross. So, all of them can be
put together. So, this is your 1 fine. For other cases, we are just substituting the values
taking the values from those columns and remember this 1 1 0 and 1 1 1 those were not
there - those last two possible. With three flip flops, eight possible states are there. So, 1
1 0 and 1 1 1 we did not consider, right. It it is not a valid state - is not it. So, we consider
for those two cases, cross cross. So, this is cross cross; that means, it does not matter
because it is supposed, it is considered that it will never go to those states.
So, it is initialized with one of the valid states, this counter is initialised with one of the
valid states. Later on we shall see if it is not the case then what will happen. So, that we
shall take up little later. So, over here ok. Accordingly we do not have any compulsion of
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if there was a 1 or something 0 considering, treating it accordingly ok. Now we can
consider them as don’t care and depending on that we will get a minimized circuit ok.
So, these are the corresponding equation right and once this equations are obtained from
there, we can get the circuit right. Is it clear?
(Refer Slide Time: 09:30)
So, this is the standard sequential synthesis, logic synthesis problem. We look at how this
particular circuit, how this particular circuit behaves when 1 0 1 comes here - over here
and then with the clock trigger how it goes to 0 0 0 without any glitch or so, alright. So, 1
0 1 so this is 1 right and this is at 0 and this is at 1 right.
And when this is 1 and this is 0 and this is 1 so, what are the corresponding inputs of this
flip flop? So, JA KA is always 1 that we have noted, is not it. And this JB is we have
found from the previous Karnaugh map based simplification is Cn bar An. So,
accordingly the circuit has been drawn ok. So, Cn bar because it is 0 so, together it is 0
ok. And what is An? A n is 1. So, this is 0 1 fine. What about JC KC?
So, JC is Bn An right so, An is 1, but Bn is 0. So, this input is 0 right. And what about
KC? KC is An - An is coming over, this is 1 right. So, for A flip flop you have got 11;
for B flip flop, you have got 0 1 at the input and for C flip flop, you have got 0 1 at the
input, right. Now when the clock trigger comes, what will happen? Now when the clock
trigger comes, you will have 11 - it toggles. So, it will become 0 from 1 to 0; 0 1 for this
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J K flip flop 0 1, if it is the input then it will be 0 only right and here also it is 0 - so, it
will be 0 only.
So, with the clock edge, all of them go to 0 0 0 unlike the asynchronous reset based
modulo-6 counter where we have got 1 1 0 and at that times with this value it was getting
reset and the output was obtained I mean, the next state was obtained as 0 0 0 for longer
duration of the time. Is it fine? Right. And this is the decoding of the counter. So, this
part is understood, right.
(Refer Slide Time: 12:12)
Now we look into the case for the two states 1 1 0 and 1 1 1 which we did not actually
consider in our design process right. So, in this particular case, this is the circuit diagram
we are having. Suppose it is you know, initialised with or because of some noise or some
surge it goes to one of those two states. So, if it goes to 1 1 1 - 11 1 and then, you can
consider the you know, calculate the input for each of the flip flops right and with a next
clock trigger, you can see that it is coming to 0 0 0.
And then with clocking, it will keep circulating like this as per this state transition
diagram and mod-6 counter will be there, after that. And had it been initialised or had
gone to the other invalid state which is 1 1 0 with a clock trigger, it would have come to
1 1 1 and then to 0 0 0 ok.
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So, this is what happens for this particular circuit, but this is happening just like that. But
there could have been another I mean, there could have been other possible cases where
if it is 1 1 0 with clocking right, it remains at 1 1 0 only, right. With 1 1 1 it is remaining
at 1 1 1. Or 1 1 0, it is going to 1 1 1 or from 1 1 1 it is coming back to 1 1 0. That
means, it is getting trapped into the invalid states only and it is never coming back to,
coming to one of the valid states ok.
That also could have been a possibility because we got this way that it is not getting
trapped ok, but it was not by design; not by design right. Just see that it has happened in
that manner. But in another design, there remains a possibility that it could be locked in
one of these cases; or if there is a modulo-5 counter there could be three invalid states - it
could be locked in one of those three states also or you know, keep circulating there. So,
this is something which we should think of avoiding in a counter design right.
(Refer Slide Time: 14:39)
So, for that what you need to do? We need to explicitly consider them in the design
process right. And how you can consider? So, there could be multiple ways. So, in this
example what we see is that for one of - for any of these invalid states, it goes - 1 1 0 or
1 1 1 - in the next clock trigger it comes to one of the valid state which is the 0 0 0.
After that it will continue to count modulo-6 the way, it was designed I mean, it is
already designed alright. So, for this, then these two unused states which we did not
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consider in the earlier design and there was a don’t care option in the Karnaugh map
based simplification of the design equation. So, they now get into picture right.
So, 1 1 0 are getting 0 0 0 and corresponding C B A flip flop inputs are like this and 1 1
1 it is also 0 0 0 and these are the corresponding inputs from the J K flip flop excitation
table right. Now other than those six, these two also are getting considered right. So, to
explicitly get around or avoid that getting trapped into the what is that called, unused
states, right.
(Refer Slide Time: 16:14)
So, now the design equation becomes little bit more complex in the sense now, these earlier these two cases; it was always don’t care. So, we had greater flexibility in
deciding the equations. So, corresponding equations have now become like this, all right.
So, you can see that earlier these equations right. For example, JA; JA was all 1, JA was
1 because this was a don’t care right. Now there is a 0 over here ok. You cannot treat this
as a 1. So, accordingly it has become Cn bar plus Bn.
So, we are sacrificing some of the design flexibility and how that becoming little bit
more complex, but the benefit is that there is no lock-out kind of situation ok, so, no
getting trapped into the unused state.
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(Refer Slide Time: 17:25)
So, that is what you can see that this is the - this was the earlier circuit and now with
those design equations for inputs, this is the modified circuit, where the invalid states
going to valid 0 0 0 at next clock trigger. And this is what is expected also. Is not it?
Right.
(Refer Slide Time: 17:55)
Now, let us look at another aspect of the design. So, we had been discussing this up
counter. Again similarly down counter is possible and it is also possible that we can have
these counting states - they need not be regular in the sense that it is in increasing mode
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you know, always the number is increasing one after another by a value of 1 or getting
decremented by 1, right. So, it is not necessary that it need to be like that. We just need
as many number of unique states ok. And that can also be considered in the design
process right.
So, here is one such you know, modulo-4 counter where the numbers are not 0 0, 0 1, 1 0
1 1, again 0 0 it is not like that what is it? 0 0 after that 1 0 then 1 1, 0 1 and then 0 0.
One good thing about it what you can see here that only one bit is changing which could
be useful in some consideration, in some cases right.
So, in two counting states, one after another, one bit is changing its value all right, but
otherwise the significance - the corresponding decimal equivalent 0 2 3 again 0. So, in
that sense it is irregular, it is not 0 1 2 3 0 or the down count the way we have seen that 3
2 1 0 and again 3 is not like that right - so, that sense.
And what else is there in this particular example? So, we had used JK flip flop right
earlier, now we are considering D flip flop. So, with D flip flop also you can design the
counter. So, let us see how. Since it is D flip flop so, D flip flop excitation table will be
put to use. So, this is 0 to 0, then 0 should be input; 0 1 - 1 should be at the input; 1 0 - 0
should be at the input; and 1 1 - 1 should be at the input. Is it fine? So, this is the way the
excitation table of D flip flop we have seen in earlier classes related to flip flop, alright.
So, now 0 0 to 1 0, 0 0 to 1 0. Then 0 1; if it is 0 1, then it goes to 0 0; if it is 1 0, it goes
to 1 1 and if it is 1 1, it goes to 0 1. So, you need to be take note of this thing that it is not
coming one after another 0 0 to 0 1 and it is just incrementing in that manner.
So, you need to be careful about this aspect in the design process not to make mistake
when we map it to Karnaugh map, right. And then D flip flop is - whatever is the next
value that is the input ok, 1 0 1 0 so, 1 0 1 0 - 0 0 1 1 so, 0 0 1 1. So, accordingly you
have got your this Karnaugh map entry and these are the equations. Is it fine? Right.
So, with these equations, we can get the circuit made, right and the circuit will behave
like a mod-4 counter with counting states 0 0, 1 0, 1 1, 0 1 again 0 0 fine right.
So, these are example with mod 4, it can be done for mod 8, mod 6, mod 4, 5 whatever,
right and whenever we are using a modulo number which is not integer power of 2, with
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flip flops that can have some invalid states unused states, it is better that we take care of
it, but putting them into the design consideration to avoid any kind of locking.
(Refer Slide Time: 22:01)
Now, we had seen counters getting used for you know of course, the counting number of
pulses and all and then digital clock where the seconds, minutes and hours you know this
count was getting incremented using different kind of you know counter.
So, mod 6, mod 10 together giving seconds and also to minutes and then mod 12 for the
hour count, all those things we have seen before as use of counter. Those were the
standard uses, right. There can be few other uses of counter where we can see that
counter can be used for in this example, sequence generator.
How is it? So, the counter - sequence generator we had seen before using shift register,
mostly shift register and linear feedback shift register also, alright and that is also another
version of a shift resigister. And here as a counter what we do – say, we are looking for a
8 bit long sequence which gets repeated, right.
So, we are then having a mod-8 counter with us. So, this can be extended to 16 bit long
sequence. So, then will be having a mod 16 counter. So, 0 0 0, 0 0 1, 0 1 0, 0 1 1, 1 0 0, 1
0 1, 1 1 0, 1 1 1 and then again 0 0 0 is coming, right. And for each of this count as the
clocking occurs so, whatever the sequence output, sequence generator as a sequence
generator - the output that you consider in the right hand side.
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So, say, we want to generate 0 1 0 0 1 1 0 1 again 0 1 0 0 1 1 0 1 or that is repetitively.
So, now, this becomes a combinatorial logic circuit problem. So, if the count is 0 0 0, the
counting state the output will be 0. If the counting state is 0 0 1, output will be 1, 0 1 0
output will be 0. And this counter is keep ticking you know, keep repeating itself. So,
this 0 will again come over here when 0 0 0 comes this 1 will come again here when the
counting state is 0 0 1. So, this is the way we map it, right.
So, we have to ensure a logical connection between Y and C B A right. So, C B A - is
independent variable and Y is the dependent variable. So, for which we are having a,
trying to get a relationship ok. So, C B A 0 1 and B A is 0 0, 0 1, 1 1 and 1 0. So, you
just put it 0 1 0 0 - 0 1 0 0; 1 1 0 1 - 1 1 0 1, right and then we write the Karnaugh map
equation right. So, B prime A; C B prime plus C A. So, this is the combinatorial logic
that we will get right.
So, how then this circuit will be made? So, clock will be given which is generating the
sequence right to a - that clock goes to a mod-8 counter right. So, that has got three states
C B A right which is now fed to the combinatorial logic. Within this combinatorial logic
box, we have got this equation, alright. So, basically this you can take in complemented
output if it is available or inverter, then AND gate and OR gate ok.
Together you will get it so, this is finally, is it fine – right. As I said, if it is mod 16, then
we have to have you know 4-bit counter; any other depending on the counting sequence
whether its 12 bit sequence generated, sequence we want to generate repetitively. So, it
will be a mod-12 counter, right.
That is the way we have to move. And another example with which we end this class is
that what you see over here is a 8-to-1 multiplexer, ok. Again this example can be
extended to 16-to-1 and cases. And this 8-to-1 multiplexer will be having 3 select inputs
right. And multiplexer does what - many to one. So, depending on select inputs, one of
the inputs gets connected to the output - is not it; so, that is the idea. So, if you place 0 0
0, D naught will be connected right. So, with 0 0 0 over here right D naught and Y is
connected - the rest of the things are not contributing to the Y.
So, that is the way multiplexer works right. Now you can see there this input is, selection
inputs are fed from the, from a mod-8 counter alright which is your C B A; C B A you
have seen here and a clock is fed to this counter, so, 0 0 0, 0 0 1 and so on and so forth
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so, this is the clock right. So, when the clock is giving a count say 0 0 0 the first count
first clock right so, then D naught whatever is the D naught value that will go over here
right. Next is 0 0 1 whatever is the D1 value that will go here. If D1 value is 0, it will go
as 0; next clock 0 1 0 whatever is the D2 value, ok.
If it is 0, it will remain 0. So, then 7 – 1 1 1 – D7 will go here again 0 0 0 - D naught will
come over here. Is it clear, is this is understood? So, this parallel set of data. Now is
placed serially in a consecutive clock period right by this arrangement. Now if somebody
read this one this Y synchronised with this clock and this count value that is there. So,
when this value is 0 0 0 in the first clock cycle, it will read D naught then he will read D
1.
So, this is D naught read this is D1 read this is D2 read and this is D3 read and so on and
so forth and then D7. So, what was parallel now you can see, it is in serial manner you
are able to read it and it is time-multiplexed means it is appearing in different point of
time. So, this is was full 8 clock cycle within which this is getting read. So, this is in a
way you can say it is a - parallel-to-serial conversion is happening and the data is able to
be read through a time-multiplexed manner. So, this is another interesting example of
you know, using mod-8 counter in combination with a multiplexer.
So, if it is a 16 to 1 you know, 16 such parallel data read to be read by 1 output line in
different point of time, then this would be 16 to 1 multiplexer and then it will be a mod16 counter, is not it. So, you just need extension of that.
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(Refer Slide Time: 29:43)
So, with this we come to the conclusion.
(Refer Slide Time: 29:44)
So, what we have understood is that sequential logic circuit design concept can be
applied to synchronous counter design for different modulo numbers and such design can
avoid the glitch which otherwise is seen for asynchronous reset based counter design.
Lock out is possible when unused states are not considered and the counter remaining
trapped in that ok.
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So, it is better to avoid it by explicitly considering it in the design steps and of course, JK
flip flop, T flip flop we have seen before and also SR flip flop for counter design, but we
are know that D flip flop also can be used right for design. And the corresponding
excitation table can be used for this design process. And the counters can have various
other applications – the one that we have seen is parallel to serial conversion together used together with a multiplexer; or sequence generation where a combinatorial logic
was used in addition ok. So, with this we conclude.
Thank you.
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Digital Electronic Circuits.
Prof. Goutam Saha
Department of E & EC Engineering
Indian Institute of Technology, Kharagpur
Lecture – 46
Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model
Hello everybody, we are in week 10 of this particular course. In the previous class we
had seen, previous week we had seen counter design; different aspects of counter.
(Refer Slide Time: 00:27)
So, we shall begin with a quick recap of that and whatever we had done, the designing
aspect of it, the counter circuit if you remember that, with clock trigger it was moving
from one state to another and output was generating - output was generated based on
how it was getting decoded ok. A general type of Sequential Logic Circuit Design will
also consider an external input ok.
So, in this class we shall consider that circuit design, sequential circuit design where the
external input will also be there. And we shall take two routes; one is called Moore
model based route another is Mealy model based route.
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(Refer Slide Time: 01:20)
And so let us see. Before that quick recap. We had seen that counter records number of
times a particular event has occurred by advancing state which is unique ok. And the
states could be, can be sequentially going up, called up counter and can come down then
it is called down counter. And in asynchronous sequential - asynchronous counter we
had seen that the consecutive flip flops are triggered through rippling ok.
So, one flip flop output is triggering the next flip flop clock ok. So, that way there is a
delay between the triggering of consecutive flip flops. And this delay is cumulative ok,
which can cause issue in certain cases. Decoding is very important and later on we had
seen that for certain cases there could be glitches and that, glitches need to be removed
for sequential logic operation. Synchronous counter - we had seen that all the clocks are
getting triggered at the same time, by the same clock edge in edge-triggered counter and
we had seen cascaded counter. If mod 2 is cascaded with mod 3, then mod 6 counter was
there and 2 and 5, mod 10 counter was there.
So, in general, you can see that m with n, it will be m multiplied by n, that will be the
mod value ok. And the order of this cascading is also important that is what we had seen.
So, mod 2 mod 5 if you put one after another then you get BCD counter. If you have
mod 5 first and then mod 2 then it is Biquinary counter ok. And to get different kind of
modulo number we can use asynchronous reset, but that can offer glitch and we can have
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standard sequential logic circuit design concept applied for counter design where this
glitch can be removed ok.
(Refer Slide Time: 03:43)
And as I said, in this class we are looking at more general approach for sequential logic
circuit design not specifically tied, being tied with - counter was a specific case; so, this
is a more general case, in which we have got input to the circuit, sequential logic circuit
and it is generating certain output and inside the circuit tthere is an advancement of state;
changes one after another ok.
So, these are the three important things right, These primary inputs where we are seeing
primary input. There, there will be certain input which will be generated inside the
circuitry ok; by those can be considered you know intermediate input ok. And
accordingly there will be intermediate output. So, these primary inputs that is coming
from the external world all right, they are effecting changes in the state ok, but it is not
effecting change in the output that is made available to the outside world.
So there is no direct connection, you can see, the primary output that is generated from
combinatorial logic is developed from the state or the memory elements or the flip flops
or the registers ok. These memory elements or flip flops or the state get influenced by
this primary input of course, so, indirectly it effects (output), not directly, right. So, that
is what you see in Moore model that the primary outputs are generated solely from the
states ok. Whereas, the state, the change of the state that occurs based on certain logic,
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certain input that are presented before the flip flops, at the input of the flip flops. So, that
is generated, that is generated through primary inputs and the previous state the current
state, so, together they derive - they drive the next state ok. So, that is certain logic,
combinational logic will be there by which you are generating the next state value. So,
this is a general block diagram level representation of Moore model ok.
So, output will be generated solely from the states. So, whenever state change takes place
after that, as long as that state remains so; that means, that for that clock period the
output will become available would remain available ok; and it is synchronized with the
clock. So, state, clocking, state change, output available after whatever this
combinatorial logic propagation delay is there, is it clear.
So, that is how Moore model works right. So, primary input for changing the state
together with the current state; and this state only defining the primary output. Now we
had seen such circuit before, Moore model we have seen before, if you remember though
it was not explicitly a primary input as such, but if you remember the up down counter this is a section of it just we have taken 2 bit counter so mod 4 right.
So, there was an external inputs say M and M, you could change any time. So, if you
keep M is equal to 0 right at any given state, so state is 0 0. So, it is up count mode; so M
is equal to 0 it was going to 0 1 ok; and M is equal to 1 it was going to down count mode
1 1.
So, that is the way state transition diagram would be written ok. Then M, if it is at 0 1, M
is equal to 0, it will go to 1 0 - up count and if it is 1 it is down count, so from 0 1 it will
go to 0 0. So, this is the way you can these 4 states you can see for 0 it is going from 0 0,
0 1, 1 0, to 1 1. And for 1, it will go from 0 0 to 1 1 to 1 0 to 0 1 and go back - going
back to 0 0, right.
So, in this particular case what we had seen that output can be generated since it is a mod
4 counter a count of you know 11 sorry, 1 1 has taken place. So, this is 1 and this is 1 in
we are discussing it, writing in binary ok. So, when both of them are 1 then the output is
1. So, it is solely derived from the flip flop outputs. So, flip flop outputs defining the
state. So, M is not directly affecting the output ok.
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So, of course, it is a case of a Moore model right and here we write the output alongside
the state value within the state ok. So, this each circle defines the state, so 0 0 the output
is 0; 0 1 output is 0; 1 0 output is 0 and 1 1 output is 1 - is it clear ok. So, this is one
thing, but still we are analyzing it; we shall look at the synthesis part later ok. So, this is
the objective of today’s class we shall come to that.
(Refer Slide Time: 09:34)
Mealy model - from the discussion we had on Moore model you can expect that Mealy
model will be related to it, but somewhat different. Yes, in this of course, the primary
input and the current state ok – together, the current state together they have a part of the
combinatorial logic ok, which will be deciding the next state this is similar to Moore
model.
So primary input and current state values together through a combinatorial logic is
defining the next state inputs and next state is obtained ok. But another part of the
combinatorial logic is also taking primary input and the current state and generating the
primary output; the primary output again what I mean by this is the output that is made
available to the external world ok.
So, secondary input or secondary output these are internally generated intermediate
values within the logic circuit. So, I am not talking about that. So, this one, the primary
outputs now is having input also from primary input ok. Earlier in Moore model, it was
only from the memory or the state values flip flop values is it clear, that is the difference.
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Now it looks ok, I mean what is a big deal about it, but when you go forward we shall
see that this has got you know lot of significance, right now what we can understand
what we can understand is that, the output need will not be synchronized with the clock
ok.
So, whenever input changes, in between a clock cycle if the input changes, so output will
be changing ok. Because if such is the logic, such is the combinatorial logic right
because it is derived from input also right; any glitch, any transient value in the input will
go directly to this output ok. Now if these are certain issues associated with it which one
can consider disadvantage or you know problematic, the other issue is that if you look at
the response time ok.
So, whenever input changes, output can respond immediately, after whatever this
combinatorial logic propagation delay. For Moore model, if input changes accordingly
the state will change and then state will generate the output ok. So, some amount of time
is required in between for the clock getting triggered - so depends on the clock period ok.
And also because current state and primary input together can generate output, number
of states required, which will be clearer later, maybe less which can effect less amount of
hardware ok.
So, these are certain things, pros and cons of two models right, and accordingly two kind
of you know, finite state machine - Moore machine or Mealy machine can be developed
ok. And each one has its own as I said advantage disadvantage; accordingly depending
on our requirement we shall be using it, clear.
And have we seen some such circuit before? Mealy model based circuit? Yes, we had
seen. This is also from our - this second part of the discussion sequential logic based
circuit, one of the earlier classes. So, there we had seen one such circuit ok.
So, there if you see that if this is X, the external input. So, this is connected directly to
the output generating combinatorial logic over here - this AND gate and this is Q bar,
right. So, what does it say? The corresponding state transition diagram is this - we have
analyzed before. So, I am not doing it again. So, you refer to that particular class in the
beginning of the sequential logic circuit part, that particular week 7 ok. So, week 7 you
can see it, right.
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So, here whenever this input is at state 0 sorry, the flip flop is at state 0 ok, the circuit is
at stage 0. So, at that time if a 1 comes right immediately the output is getting generated,
output is getting generated as high ok, otherwise the output remains 0 ok. So, 0 and 0
here means it is 1. So, this 1 and whenever it becomes 1, it does not depend, need to
depend on the clock. So, that is why it is called not synchronized with the clock right.
But again the response is - immediately it can respond. So, now let us look at because we
are now look into the synthesis design aspect of it.
(Refer Slide Time: 14:44)
So, for that we take up we one problem which we first define - very simple problem,
something which you had seen before in a different context; a sequence detector right.
Did not we see it for the shift register and other application? In those cases we have seen
sequence detector right. So, here we are seeing it in a different point of view. So, the
sequence to be detected is very simple 1 1 0 ok. So, first bit should be 1 second bit
should be 1 and third bit should be 0; as soon as it is done, then the output will say,
output of this circuit will say that this sequence, this bit pattern has been detected ok. So,
it will go to 1 otherwise it will remain 0. Is it clear?
So, if it is shift registered based or register based – well, then three such flip flops will be
required. And we’ll push it and then we will be having a XNOR kind of logic circuit
which we had seen before ok. So, here let us see whether we require 3 flip flops or less
ok. So, now for that the first step required is defining the states ok. So, the problem -
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now we are breaking into sub problems ok. So, these are the - this is what needs to be
done ok.
So, for that the circuit should move from one state to another. So, we initialize the circuit
with a state say a ok, which means that none of the bit in the prescribed sequence is
correctly decoded which is reasonable, is not it ok. Because the circuit is just reset, is just
- you have begun, you have begun to sample the input data stream ok. Now if you
receive 1 bit correctly, so you say the circuit moves from state a to state b. So, that is b; 2
bits detected correctly c; 3 bits detected correctly d ok.
So, a is no bit; b is 1 bit; c is 2 bits and d is 3 bits detected correctly. Is it fine? And these
are the, this is the requirement 3 bits are detected correctly right. And whenever you go
to state d; so Moore model it will generate output, so that is the idea ok. Now we need
the state transition diagram, and once we have the state transition diagram - state table
and all, and those journey we shall - we know that part, we shall see later.
So, first let us see what would be the state transition diagram for this one. So, here is the
state transition diagram. So, you begin with state a, this 0 means no output, output is 0.
Of course, no bit is detected - output should be 0. So, that part we shall take, discuss
later. So, first is a; now when it is at a input data stream is coming it can - it can be 0, it
can be 1, both are possible, is it ok. So if 0 comes, then it will stay at a and if it 1 comes
right it has to go to state b because b refers 1 bit is correctly decoded.
So, first bit decoded - is properly decoded, out of 1 1 0 ok; so it goes to b. When it is at b
if it receives 1 then second bit is correctly detected. So, it goes to c so that is your c that
is what is happening here. But after getting 1 if it receives 0 then what it has to do? It has
to do all over again this (1 0) 1 1 0 right. So, after receiving 1 if it receives 0 it just needs
to restart the process so; that means, it has to go back to state a which signifies that no