CONTENT
➢ General Diagram of
Microcomputer and CPU
➢ Architecture and Features
of 8086
➢ Memory Addressing
➢ Assembly Instruction Set of
8086
➢ Buffering
➢ Memory Interface
➢ I/O Interface
➢ Subroutines
➢ Delay Time
➢ Sheet 1
➢ Sheet 2
➢ 1st Term Midterm
2017/2018
➢ Sheet 3
➢ Sheet 4
➢ Sheet 5
➢ Sheet 6
➢ 2nd Term Midterm
8086
MICROPROCESSOR
[NOTES] - VERSION
3.0
Helwan University
Faculty of Engineering - Helwan Branch
3rd Computer Engineering
2017/2018
This is not an official
document, it’s just some
personal notes haven't been
verified officially.
8086 Microprocessor [Notes] - Version 3.0
Version Updates
➢ From Version 2.0 to Version 2.0.2:
•
•
Correct the PPI control lines on the draw for Q.2 and Q.3 at Sheet 6.
From (MR & MW)
To (IOR & IOR)
Correct part of program for Q.1 and Q.2 at Sheet 6.
From (SHR 01H /*\ JC EVEN)
To (MOV AH, AL /*\ SHR AH, 01H /*\ JNC EVEN)
➢ From Version 2.0.2 to Version 3.0:
•
•
•
Refine Sheets (5,6) Solutions with:
- Obtaining the Concept of odd and even addresses of I/O ports.
- Adding second solution using Memory Full Decoding Approach for problems
that has memory mapped I/O Ports.
Adding more explanation about Memory Interface and I/O Interface.
Adding explanation about Subroutines and Delay Time.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
References
A. The Intel Microprocessors Architecture Programming And
Interfacing - 8th Edition
B. ]‫محمد ابراهيم العدوي‬.‫د‬.‫المعالجات الدقيقة [أ‬
C. 8086 Microprocessor [Tutorials Point]
D. “Intel 8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/80861” Data Sheet
E. Memory Addressing of 8086(CS502)
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8086 Microprocessor [Notes] - Version 3.0
Table of Contents
Version Updates ........................................................................................................................................... 1
Table of Contents ......................................................................................................................................... 3
General Diagram of Microcomputer and CPU............................................................................................. 5
Architecture and Features of 8086 .............................................................................................................. 7
❖
Architecture of 8086......................................................................................................................... 7
❖
Features ............................................................................................................................................ 7
❖
General-Purpose Registers Vs Special-Purpose Registers............................................................... 8
❖
Functional Units of 8086 .................................................................................................................. 8
❖
Execution Unit (EU) ...................................................................................................................... 8
❖
Bus Interface Unit (BIU) ............................................................................................................... 9
Memory Addressing ................................................................................................................................... 11
❖
Addressing Modes .......................................................................................................................... 11
➢
Direct Addressing Mode............................................................................................................. 11
➢
Register Indirect Addressing Mode ........................................................................................... 11
➢
Based Addressing Mode ............................................................................................................. 11
➢
Indexed Addressing Mode ......................................................................................................... 11
➢
Base-Indexed Addressing Mode ................................................................................................ 11
➢
Base-Indexed with Displacement Addressing Mode ................................................................ 11
Assembly Instruction set of 8086 .............................................................................................................. 12
➢
Data Transfer Instructions: (MOV, PUSH, PUSHF, POP, POPF) ..................................................... 12
➢
Arithmetic Instructions: (ADD, ADC, SUB, SBB, CMP, INC, DEC, MUL, DIV) ................................. 12
➢
Logical Instructions: (AND, OR, XOR, NOT) ................................................................................... 13
➢
Execution Transfer Instructions: (JMP, CALL, RET, RETF) .............................................................. 14
➢
Iteration Instructions: (LOOP) ........................................................................................................ 15
➢
I/O Port Transfer Instructions: (IN, OUT) ...................................................................................... 15
➢
Shift Operations Instructions: (SAR, SAL, SHR, SHL) ..................................................................... 15
➢
Rotate Operations Instructions: (ROR, ROL, RCR, RCL) ................................................................. 16
❖
General Assembly Instructions Notes: (Due to Dr. Maher Mansour) .......................................... 17
Buffering ..................................................................................................................................................... 18
❖
Latch................................................................................................................................................ 18
❖
Buffers............................................................................................................................................. 18
➢
Normal Buffer (Single Input) ...................................................................................................... 18
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8086 Microprocessor [Notes] - Version 3.0
❖
➢
Tri-State Buffer ........................................................................................................................... 19
➢
Bi-Directional Buffer ................................................................................................................... 20
Buses Buffering of 8086 ................................................................................................................. 21
Memory Interface ...................................................................................................................................... 23
❖
Memory Types ................................................................................................................................ 23
❖
8086 Memory Interface.................................................................................................................. 23
I/O Interface ............................................................................................................................................... 26
❖
I/P Port............................................................................................................................................ 26
❖
O/P Port .......................................................................................................................................... 26
❖
PPI ................................................................................................................................................... 26
❖
Generating Port CS (Chip Select): .................................................................................................. 28
❖
Mapping .......................................................................................................................................... 28
Subroutines ................................................................................................................................................ 29
Delay Time .................................................................................................................................................. 30
Sheet 1 [8086]: 8086 MCU Architecture .................................................................................................... 32
Sheet 2 [8086]: Assembly Language .......................................................................................................... 36
Task [8086] ................................................................................................................................................. 47
1st Term Midterm 2017/2018 ..................................................................................................................... 48
Sheet 3: Microprocessor Buffering ............................................................................................................ 51
Sheet 4: Memory Interfacing with the Intel 8086 CPU ............................................................................. 54
Sheet 5: I/O Interfacing with the Intel 8086 CPU ...................................................................................... 63
Sheet 6: Intel 8086 CPU Microcomputer ................................................................................................... 80
2nd Term Midterm 2017/2018 .................................................................................................................... 88
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8086 Microprocessor [Notes] - Version 3.0
General Diagram of Microcomputer and CPU
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
❖ External Buses: used to control memory and I/O.
• Address Bus: used to request a memory location or I/O device.
• Data Bus: used to transfer data between the microprocessor and its
memory and I/O spaces.
• Control Bus: used to control memory and I/O spaces and requests reading
or writing of data.
❖ Memory locations:
Memory locations are actually 8-bits in width. So whenever 16-bit data is
accessed two consecutive 8-bit memory location. Using concept of LittleEndian format.
• Little-Endian format: The least significant byte is always stored in the
lowest-numbered memory location, and the most significant byte is stored
in the highest.
❖ I/O Ports:
Like Memory, I/O ports are actually 8-bits in width. So whenever 16-bit port is
accessed two consecutive 8-bit ports are actually addressed.
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8086 Microprocessor [Notes] - Version 3.0
Architecture and Features of 8086
❖ Architecture of 8086
❖ Features
• Data Bus (Size): (16-bit Internal/External) Microprocessor.
• Address Bus: 20-bit.
• Memory: can access up to 1 MByte of memory.
General laws:
Memory Space(Size) = (2^Address Bus) [unit of memory location width(capacity)]
Memory Capacity = Memory Space * Memory Location Capacity
[bit]
= (2^Address Bus) * Memory Location Capacity
[bit]
• I/O: can access (2^16 = 64K) I/O’s.
• Pipelining: supports pipelined architecture, it uses 2 stages of pipelining
Fetch Stage and Execute Stage.
▪ Pipelining means fetching the next instruction while the current is
executed.
▪ Fetch Stage can prefetch up to 6 bytes of instructions and store them in
the queue (cache).
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
❖ General-Purpose Registers Vs Special-Purpose Registers
• General-Purpose(Multipurpose) Registers:
Include AX, BX, CX, DX, BP, DI, and SI.
These registers hold various data sizes (bytes or words) and are used for
almost any purpose, as dictated by a program.
For some instructions maybe, a multipurpose register has a special
purpose, but is generally considered to be a multipurpose register.
• Special-Purpose Registers:
Include IP, SP, and FLAGS, and the segment registers include CS, DS, SS,
and ES.
These registers are used for a certain purpose only.
❖ Functional Units of 8086
8086 Microprocessor is divided into 2 functional units
• Execution Unit (EU)
• Bus Interface Unit (BIU)
❖ Execution Unit (EU)
➢
➢
➢
➢
➢
➢
• Its function is to control operations on data using the instruction decoder
and ALU.
• It gives instructions to BIU stating from where to fetch the data and then
decode and execute those instructions.
ALU: handles all arithmetic and logic operations.
General purpose registers (Ax, Bx, Cx, Dx):
▪ Each register is 16-bit and consist of 2 8-bit register like (AH, Al).
• AX (Accumulator register): used with I/O and arithmetic operations.
• BX (Base Index register): sometimes holds the offset address of a location
in the memory.
• CX (Counter register): holds the count for various instructions.
• DX (Data register): holds a part of data used in I/O and some arithmetic
(DIV & MUl) operations.
SP (Stack Pointer register): point to the top of the stack.
BP (Base Pointer register): point to somewhere in the stack.
SI (Source Index register): used in addressing.
DI (Destination Index register): used in addressing.
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8086 Microprocessor [Notes] - Version 3.0
➢ Flag Register (9 Flags): indicate the condition of the microprocessor and
control its operation.
o Conditional Flags: changes its status according to the result of the last
arithmetic or logical instruction executed.
• CF (Carry flag)
• AF (Auxiliary flag): (half-carry) carry given by D3 to D4 is AF flag.
• ZF (Zero flag)
• SF (Sign flag)
• PF (Parity flag): when the lowest 8-bit contains even number of 1’s the
flag is set. else the flag is reset.
• OF (Overflow flag): system capacity is exceeded.
o Control Flags:
• IF (Interrupt flag): interrupt enable/disable flag.
• TF (Trap flag): used for single step control allows to execute one instruction
at time for debugging.
• DF (Direction Flag): used in string operation. When it is set the string bytes
are accessed from the higher memory address to the lower and vice-a-versa.
(selects either the increment or decrement mode for the DI and/or SI registers
during string instructions)
❖ Bus Interface Unit (BIU)
• It takes care of all data and address transfers on the buses for EU like:
writing/reading data, fetching instructions and sending address.
➢ Instructions Queue(Cache): store up to 6 bytes of prefetched next
instructions.
➢ IP (Instruction Pointer register): point to the next instruction in a section of
memory defined as a code segment. That will be fetched to be executed by
the EU.
➢ Segment registers (CS, DS, SS, ES): used by the microprocessor to access
memory locations. [Note: our registers are 16-bit but the address bus is 20bit, so we have used segmentations]
• CS (Code Segment): for memory locations where the executable program
is stored. Works with [IP].
• DS (Data Segment): for memory locations that deals with data. Works with
[BX, SI, DI].
• SS (Stack Segment): for memory locations that related to the stack. Works
with [SP, BP].
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8086 Microprocessor [Notes] - Version 3.0
• ES (Extra Segment): for memory locations that deals with extra destination
data (Arrays, Strings). Works with [SI, DI].
▪ Calculating the absolute (actual) address:
SegmentRegisterValue:RegisterValue(OffsetAddressValue)
EX:
89AB:F012 ->89AB*10
-> 89AB0 (SegmentRegisterValue * 10Hex)
F012
-> 0F012
----- +
98AC2 (The Absolute Address [20-bit])
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8086 Microprocessor [Notes] - Version 3.0
✓ Before we get into the Assembly Instruction set let’s first know how
we can using and write address in our Instructions.
----------------------------------------------------------------------------------------------Memory Addressing
▪ To access the content of a memory location having its address we write
the instruction operand like that: [address]
▪ The address can be only consisting of any combination from (BX, BP, SI, DI,
or a direct displacement 8-bit/16-bit)
➢ Note we can’t use (BX) and (BP) together.
➢ Note we can’t use (SI) and (DI) together.
✓ Note: memory location is 8-bit so when we store or read a 16-bit data it use
two sequential locations the first for the lowest 8-bit and the second for the
highest 8-bit.
❖ Addressing Modes
•
•
•
•
•
•
➢ Direct Addressing Mode
[displacement] like [1111H]
➢ Register Indirect Addressing Mode
[BX] or [BP] or [SI] or [DI]
➢ Based Addressing Mode
[BX/BP + displacement 8-bit/16-bit] like [BX + 082H]
➢ Indexed Addressing Mode
[SI/DI + displacement 8-bit/16-bit] like [BX + 0082H]
➢ Base-Indexed Addressing Mode
[BX/BP + SI/DI]
➢ Base-Indexed with Displacement Addressing Mode
[BX/BP + SI/DI + displacement 8-bit/16-bit] like [BX + SI + 04H]
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8086 Microprocessor [Notes] - Version 3.0
Assembly Instruction set of 8086
✓ Notes:
- “Memory” word refer to: [address]
- “REG” word refer to: (AX, AL, AH), (BX, BL, BH), (CX, CL, CH), (DX, DL, DH),
SI, DI, SP, BP
- “SREG” word refer to: CS (read only), DS, SS, ES
- “immediate” word refer to an immediate data: 1111H
- We can’t use IP register.
- If we use chars as immediate data, it will be converted to its ASCII Code.
Like (‘A’) will be (41H)
➢ Data Transfer Instructions: (MOV, PUSH, PUSHF, POP, POPF)
• MOV operand1, operand2 ~ operand1 = operand2
Flags unchanged (C, Z, S, O, P, A)
Operand1 and Operand2 may be:
REG, memory
SREG, memory
memory, REG
memory, SREG
REG, REG
REG, SREG
SREG, REG
memory, immediate
REG, immediate
• PUSH operand1 ~ SP = SP – 2, SS:[SP] = operand (Push 16-bit into stack)
• POP operand1 ~ operand = SS:[SP], SP = SP + 2 (Pop 16-bit from stack)
Operand1 may be:
REG
SREG
memory
• PUSHF NO Operand ~ Push the flag register to stack
• POPF NO operand ~ Pop the flag register from stack
➢ Arithmetic Instructions: (ADD, ADC, SUB, SBB, CMP, INC, DEC, MUL, DIV)
• ADD operand1, operand2 ~ operand1 = operand1 + operand2
• ADC operand1, operand2 ~ operand1 = operand1 + operand2 + CF
• SUB operand1, operand2 ~ operand1 = operand1 - operand2
• SBB operand1, operand2 ~ operand1 = operand1 - operand2 - CF
• CMP operand1, operand2 ~ operand1 - operand2 (update flags only)
Conditional Flags changed (C, Z, S, O, P, A)
Operand1 and Operand2 may be:
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8086 Microprocessor [Notes] - Version 3.0
•
•
•
•
REG, memory
memory, REG
REG, REG
REG, immediate
memory, immediate
INC operand1 ~ operand1 = operand1 + 1
DEC operand1 ~ operand1 = operand1 – 1
Conditional Flags changed (Z, S, O, P, A)
Conditional Flags unchanged (C)
Operand1 may be:
REG
memory
MUL operand1
(Unsigned Multiply)
If operand1 refer to 8-bit ~ AX = AL * operand1
If operand1 refer to 16-bit ~ (DXAX) = AX * operand1
Conditional Flags changed (C, O) CF=OF=0 if high section of result is zero.
Conditional Flags unchanged (Z, S, P, A)
Operand1 may be:
REG
memory
DIV operand1
(Unsigned Divide)
If operand1 refer to 8-bit ~ AL = AX / operand1
AH = reminder
If operand1 refer to 16-bit ~ AX = (DXAX) / operand1
DX = reminder
Conditional Flags unchanged (C, Z, S, O, P, A)
Operand1 may be:
REG
memory
➢ Logical Instructions: (AND, OR, XOR, NOT)
• AND operand1, operand2 ~ operand1 = operand1 AND operand2
• OR operand1, operand2 ~ operand1 = operand1 OR operand2
• XOR operand1, operand2 ~ operand1 = operand1 XOR operand2
Conditional Flags changed (Z, S, P, A)
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8086 Microprocessor [Notes] - Version 3.0
Conditional Flags set to 0 (C, O)
Conditional Flags unchanged (A)
Operand1 and Operand2 may be:
REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
• NOT operand1 ~ operand1 = NOT operand1
Flags unchanged (C, Z, S, O, P, A)
Operand1 may be:
REG
Memory
➢ Execution Transfer Instructions: (JMP, CALL, RET, RETF)
• JMP operand1 ~ jump to label/address(operand1)
(Unconditional Jump)
Flags unchanged (C, Z, S, O, P, A)
Operand1 may be:
label
immediate 4-byte address segment:offset
(conditional Jump) JFlag/JCondition operand1
Flags unchanged (C, Z, S, O, P, A)
Operand1 may be only:
label
like: (JZ (jump if ZF=1), JNZ (jump if ZF=0)), (JS, JNS), (JC, JNC), (JA, JNA), (JO,
JNO), (JP (PF=1), JPE (even) (PF=1), JPO (odd) (PF=0) ), JNP (PF=0))
(JE, JNE), (JL, JNL), (JLE, JNLE), (JG, JNG), (JGE, JNGE)
• CALL operand1 ~ Push IP into stack then transfer to the called address
If it's a far call, then code segment is pushed to stack as well.
Operand1 may be:
label
immediate 4-byte address segment:offset
procedure name
• RET No operand ~ Pop IP from stack and use to return for caller
• RETF No operand ~ Pop IP&CS and use to return for caller (Return form far)
• IRET No operand ~ (Interrupt Return) Pop IP&CS&FR from stack
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8086 Microprocessor [Notes] - Version 3.0
➢ Iteration Instructions: (LOOP)
• LOOP operand1 ~ Decrease CX, jump to label if CX not zero
(Unconditional Loop)
Flags unchanged (C, Z, S, O, P, A)
Operand1 may be only:
Label
➢ I/O Port Transfer Instructions: (IN, OUT)
• IN operand1, operand2(Port Number)
~ Input from operand2(port) into operand1(AL/AX).
Flags unchanged (C, Z, S, O, P, A)
Operand1 and Operand2 may be:
AL, immediate 8-bit(byte)
AL, DX
AX, immediate 8-bit(byte)
AX, DX
• OUT operand1(Port Number), operand2
~ Output from operand2(AL/AX) into operand1(Port).
Flags unchanged (C, Z, S, O, P, A)
Operand1 and Operand2 may be:
immediate 8-bit(byte), AL
immediate 8-bit(byte), AX
DX, AL
DX, AX
➢ Shift Operations Instructions: (SAR, SAL, SHR, SHL)
• SAL operand1, operand2
• SHL operand1, operand2
~ shift arithmetic/logic operand1 left by number of shifts = operand2
Shift all bits left, the bit that goes off is set to CF
Zero bit is inserted to the right-most position
EX: 11100000b after 1 shift will be 11000000b, CF=1
• SAR operand1, operand2
~ shift logic operand1 right by number of shifts = operand2
Shift all bits right, the bit that goes off is set to CF
The Sign bit is inserted to the left-most position (has same value as
before shifting)
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8086 Microprocessor [Notes] - Version 3.0
EX: 11100000b after 1 shift will be 11110000b, CF=0
• SHR operand1, operand2
~ shift logic operand1 right by number of shifts = operand2
Shift all bits right, the bit that goes off is set to CF
Zero bit is inserted to the left-most position
EX: 11100000b after 1 shift will be 01110000b, CF=0
Flags changed (C, O), OF=0 if operand1 keeps its original sign.
Flags unchanged (Z, S, P, A)
Operand1 and Operand2 may be:
memory, immediate
REG, immediate
memory, CL
REG, CL
➢ Rotate Operations Instructions: (ROR, ROL, RCR, RCL)
• ROR operand1, operand2
~ Shift all bits right, the bit that goes off is set to CF
and the same bit is inserted to the left-most position
EX: 11100000b after 1 rotate will be 01110000b, CF=0
• ROL operand1, operand2
~ Shift all bits left, the bit that goes off is set to CF
and the same bit is inserted to the right-most position
EX: 11100000b after 1 rotate will be 11000001b, CF=1
• RCR operand1, operand2
~ Shift all bits right, the bit that goes off is set to CF
and the previous value of CF is inserted to the left-most position
EX: 11100000b, CF=1 after 1 rotate will be 11110000b, CF=0
• RCL operand1, operand2
~ Shift all bits left, the bit that goes off is set to CF
and the previous value of CF is inserted to the right-most position
EX: 11100000b, CF=1 after 1 rotate will be 11000001b, CF=1
Flags changed (C, O), OF=0 if operand1 keeps its original sign.
Flags unchanged (Z, S, P, A)
Operand1 and Operand2 may be:
memory, immediate
REG, immediate
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8086 Microprocessor [Notes] - Version 3.0
memory, CL
REG, CL
❖ General Assembly Instructions Notes: (Due to Dr. Maher Mansour)
• If an instruction that we know in 8086 needs two operands. It
may be given with only one operand and the other operand will
be Al or AX.
EX:
AND Al,05H ~ AND 05H
AND Ax,0506H ~ AND 0506H
• It’s preferred to write the immediate value of a port number like:
(immediate) instate of immediate
EX:
IN AL, (00H)
OUT (00H), AL
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8086 Microprocessor [Notes] - Version 3.0
Buffering
❖ Latch
Latch is an electronics component that works on coping the data form the
input at a certain moment and hold it on the output. Like: D-Flip Flop
LE
1
0
Q
D
Q(t-1)
❖ Buffers
Buffer is an electronics component that works on coping the data form the
input and represent it on the output with isolation between I/P and O/P.
➢ Normal Buffer (Single Input)
has only one I/P as the data I/P without control Lines.
Non-Inverting Buffer
I/P
O/P
0
0
1
1
Created By: M. El-Moughazy
Inverting Buffer
I/P
O/P
1
0
0
1
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8086 Microprocessor [Notes] - Version 3.0
➢ Tri-State Buffer
has two inputs as a data input and a control input.
This control line controls the buffer to work on buffering the input data or to
make the O/P high impedance.
Control I/P
Line
0
0
0
1
1
1
Active High
NonInverting
Inverting
Buffer
Buffer
0
High
Impedance
High
Impedance
0
High
Impedance
High
Impedance
1
1
1
0
Created By: M. El-Moughazy
Active Low
NonInverting
Inverting
Buffer
Buffer
0
1
1
0
High
Impedance
High
Impedance
High
Impedance
High
Impedance
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8086 Microprocessor [Notes] - Version 3.0
➢ Bi-Directional Buffer
Using two Tri-State Buffers constructing one bi-directional buffer and
control the direction using a control line
Like Active High Non-Inverting Bi-directional Buffer:
DIR(AB/BA) OE
0
0 A&B High Impedance
0
1
A = B, (A  B)
1
0 A&B High Impedance
1
1
B = A, (B  A)
So, depending on the type of the two Tri-State buffers can construct:
Active High Non-Inverting Bi-directional Buffer
Active High Inverting Bi-directional Buffer
Active Low Non-Inverting Bi-directional Buffer
Active Low Inverting Bi-directional Buffer
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8086 Microprocessor [Notes] - Version 3.0
❖ Buses Buffering of 8086
▪ Latched Uni-Directional Buffer: the latch use to hold (save) last value and the
buffer to avoid short circuit on buses and to provide additional power to the
value transferred.
Has two pins:
- OE (O/P Enable): is active low allow the buffer to transfer the value else
its O/P will be high impedance.
- LE (Latch Enable): is active high allow the latch to get a new value to hold
it.
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8086 Microprocessor [Notes] - Version 3.0
▪ Bio-Directional Buffer: this buffer allows the value to transfer in two directions
using “DIR” pin to choose which direction will be active.
Has two pins:
- OE (O/P Enable): is active low allow the buffer to transfer the value else
its O/P will be high impedance.
- DIR (Direction): choose the direction for which the buffer works
according to its value.
▪ There is a time multiplexing between Data and Address buses (AD0 – AD15)
▪ DEN (Data Enable): is active low pin indicates that the multiplexing lines have
data at that moment.
▪ DT/R (Data Transmit/Receive): high value indicates that the data is
transmitting from the micro, low value indicates that the data is receiving to
the micro.
▪ ALE (Address Latch Enable): is active high indicates that the multiplexing lines
have address at that moment.
▪ BHE (Byte High Enable): is active low indicates that the higher byte of data
bus is used.
▪ A0 (Least Bit of Address Bus): is active low to indicates that the least byte
of data bus is used.
▪ IO (Input Out): is active low indicates that the Data bus is dealing with the IO
devices at that moment.
▪ RD (Read): is active low indicates the current operation is reading using data
bus.
▪ WR (Read): is active low indicates the current operation is writing using data
bus.
▪ Control Bus: (all are active low)
o MW: Memory write
o MR: Memory Read
o IOW: IO write
o IOR: IO read
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8086 Microprocessor [Notes] - Version 3.0
Memory Interface
❖ Memory Types
RAM
ROM
Random Access Memory
Random Only Memory
Volatile
Non-Volatile
SRAM
DRAM
ROM
PROM
EPROM EEPROM UVEPROM
Static RAM
Dynamic
Programable Erasable Electrical Ultra-Violet
RAM
ROM
PROM
EPROM
EPROM
fabricated
fabricated
using
using
Latches
Capacitors
Don’t need
Need
Refreshment Refreshment
Circuit
Circuit
❖ 8086 Memory Interface
Memory locations are actually 8-bits in width. So whenever 16-bit data is
accessed two consecutive 8-bit memory location. Using concept of Little-Endian
format.
The address space is physically connected to a 16-bit data bus by dividing the
address space into two 8-bit banks of up to 512K bytes.
o Even Bank: is connected to the lower half of the 16-bit data bus (D0 – D7)
and contains even address bytes. when A0 bit is low, the bank is selected.
o Odd Bank: is connected to the upper half of the 16-bit data bus (D8 – D15)
and contains odd address bytes. when BHE (Byte High Enable) is low, the
bank is selected.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Data can be accessed from the memory in four different ways.
They are:
1. 8 - bit data from Lower (Even) address Bank.
2. 8 - bit data from Higher (Odd) address Bank.
3. 16 - bit data starting from Even Address.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
4. 16 - bit data starting from Odd Address.
Is accessed using two bus cycles.
During the first bus cycle the lower byte with the odd address is accessed.
(A0=1, BHE = 0)
During the second bus cycle the upper byte with the even address is
accessed. (A0 = 0, BHE = 1)
Full(Absolute) decoding VS Partial Decoding:
1. Full decoding: The decoding in which all available address line (20 lines)
are used for decoding to generate a unique address range.
2. Partial decoding: The decoding in which only minimum needed address
line are used for decoding to generate an addresses range. resulting
multiple addresses ranges refer to the same Locations range.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
I/O Interface
Like Memory, I/O ports are actually 8-bits in width. So whenever 16-bit port is
accessed two consecutive 8-bit ports are actually addressed. And divided into
Even and Odd banks.
❖ I/P Port
❖ O/P Port
❖ PPI
Refer to Peripheral Programmable Interface
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8086 Microprocessor [Notes] - Version 3.0
• Consist of 2 Groups: Group A (Port A + Port C Higher-nibble) and Group B
(Port B + Port C Lower-nibble)
• Consist of 3 Prots Programable as I/P or O/P Ports as dedicated by the
Configuration Word
• Has Configuration Word Register (CWR) that receive the CW to be
decoded with the PPI-Control Unit
• PPI-A0 and PPI-A1 two accessing selection lines
PPI-A1
PPI-A0
Access
0
0
Port A
0
1
Port B
1
0
Port C
1
1
CWR
Preferred to connect PPI-(A1, A0) to Address Bus-(A2, A1)
And connect PPI-(D7-D0) to Data Bus-(D7-D0) or Data Bus-(D15-D8) according to
the address (even or odd). [Can’t use Address Bus-(A0)]
• PPI Pregaming:
Send the control word to CWR.
1st mode of programing to configure ports
D7
D6
D5
D4
D3
D2
Mode Selection
Port A
Port C
Mode Selection
of Group A
0→
Higherof Group B
00 → Mode 0
Output
nibble
0 → Mode 0
1
01 → Mode 1
1→
0→
1 → Mode 1
1X → Mode 2
Input
Output
1→
Input
D1
Port B
0→
Output
1→
Input
D0
Port C
Lowernibble
0→
Output
1→
Input
Notes: (Due to Dr. Maher Mansour) [The Default Mode to Use
for Groups A & B is Mode 0]
2nd mode of programing (BSR) Bit Set Rest Mode
Used to set or rest the values of port C bits
D7
D6
D5
D4
D3
D2
0
X
X
Created By: M. El-Moughazy
X
D1
Used to Select the target bit
D0
0 → Rest
1 → Set
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8086 Microprocessor [Notes] - Version 3.0
❖ Generating Port CS (Chip Select):
There are different ways to decode the address and control lines to generate
the Chip Select Line for an I/O Port. Like:
1. Using NAND Gate: [ Fixed Single Port Number]
2. Using Comparator: (Compare the Address Bus with a presented Port
Number) [ Changeable Sigle Port Number]
3. Using Decoder (DeMux): [may use to generate multiple chip select lines
for consecutive port numbers]
❖ Mapping
Isolated I/O [I/O Mapped I/O]
Use IN & OUT Instructions
Use IOR & IOW Control Lines
Ports Addressing limited to 16-bit
(A15-A0) [and Address Bus-(A19A16) forced to be zero’s]
64 K I/O Ports
Port address can be the same
address as a memory location
Memory addressing range doesn’t
affected by I/O addressing range
Memory Mapped I/O
Use MOV Instruction
Use MR & MW Control Lines
Ports Addressing can be 20-bit
(A19-A0)
Port address can’t be the same
address as a memory location
I/O addressing range is part from
Memory addressing range
Notes:
- If Port Address is larger than 16-bit. Memory mapped approach
must be used.
- Preferred to use Memory Full decoding approach, when using I/O
Memory Mapped I/O.
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8086 Microprocessor [Notes] - Version 3.0
Subroutines
A subroutine is a special program perform a specific task that can be
called for execution from any point in a program.
Proper Subroutine:
- Is only entered with a CALL and exited with an RTE
- Has a single Entry point.
- Has a single Exit point.
Elements of subroutine:
-
Save Information to Stack if needed (PUSH, PUSHF)
Body. Group of instructions perform the task.
Restore Information from Stack if needed (POP, POPF)
Return to Caller (RET, RETF)
Example:
; Main
MOV AL,05H
.
CALL XX
HLT
XX:
PUSH AX
MOV AL, 04H
.
POP AX
RET
We can use nested subroutines but must be careful about going into
infinite loop of calls.
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8086 Microprocessor [Notes] - Version 3.0
Delay Time
Subroutines can be used to perform software delay function.
Instructions - Clock Numbers Table:
Instruction
Number of Clocks
MOV REG, Immediate
4
LOOP Label
17/5
NOP
3
DEC REG
3
JNZ Label
16/4
JMP Label
15
CALL Label
19(near) OR 28(far)
RET
16(near) OR 26(far)
Delay Time = Total NO. of Clocks * Clock Cycle Time
Delay Time = Total NO. of Clocks * (1 / Rate)
Example:
; Main:
.
CALL DELAY
.
HLT
DELAY:
MOV CX, Immediate
LOOP0:
NOP
LOOP LOOP0
RET
; 19 CLK
; 4 CLK
; 3 CLK
; 17/5 CLK
; 16 CLK
Delay Time = [19 + 4 + (3+17) * Immediate – (17-5) + 16] * (1 / Rate)
By neglecting the clocks of CALL & RET:
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Delay Time = [4 + (3+17) * Immediate – (17-5)] * (1 / Rate)
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8086 Microprocessor [Notes] - Version 3.0
Sheet 1 [8086]: 8086 MCU Architecture
1. Draw a block diagram for any microcomputer system containing a CPU, ROM,
RAM, an input port and an output port. (illustrate signal names and directions
on the diagram).
-
2. The 8086 CPU is a 16-bit Microprocessor, what does this mean?
- That means it has 16-bit Data Bus.
3. What is the relation between Number of address lines in the Address Bus and
Memory Space?
- Memory Space = (2^ Number of Address lines)
4. The 8086 CPU has 20-bit Address Bus, what is the maximum Memory capacity
that can be connected to the 8086 CPU?
- According to General laws:
(as we know that each memory location in 8086 is only 1 Byte)
Memory capacity = (2^Address Bus) * Memory Location Capacity
Memory capacity = (2^20) * 8 = 8 Mbit
5. How many address lines we need to address the whole range of the following
memories?
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8086 Microprocessor [Notes] - Version 3.0
a. 2 KB (KB: Kbytes).
- 2^ Number of Address lines = 2 * 1024 = 2^ 11
Number of Address lines = 11 line
b. 64 KB.
- 2^ Number of Address lines = 64 * 1024 = 2^ 16
Number of Address lines = 16 line
c. 1 MB.
- 2^ Number of Address lines = 1 * 1024 * 1024 = 2^ 20
Number of Address lines = 20 line
6. Explain briefly the function of the following registers:
a. IP.
- IP (Instruction Pointer register): point to the next instruction in a section
of memory defined as a code segment. That will be fetched to be executed
by the EU.
b. SP.
- SP (Stack Pointer register): point to the top of the stack.
c. FR.
- Flag Register (9 Flags): indicate the condition of the microprocessor and
control its operation.
Conditional Flags (C, Z, S, O, P, A): changes its status according to the result
of the last arithmetic or logical instruction executed.
Control Flags (I, T, D).
7. State names of the general-purpose registers available in the 8086 CPU.
- AX (AL, AH), BX (BL, BH), CX (CL, CH), DX (DL, DH), SI, DI, BP.
8. What are the Indexing Registers, and what are they used for?
- SI (Source Index register), DI (Destination Index register), BX (Base Index
register)
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8086 Microprocessor [Notes] - Version 3.0
Used for Addressing like:
Indexed Addressing Mode:
• [SI/DI + displacement 8-bit/16-bit] like [BX + 0082H]
Base-Indexed Addressing Mode:
• [BX/BP + SI/DI]
Base-Indexed with Displacement Addressing Mode:
• [BX/BP + SI/DI + displacement 8-bit/16-bit] like [BX + SI + 04H]
9. State functionality of the following flags:
Due to the result of the last arithmetic or logical instruction executed
a. CF (Carry Flag).
- CF = 0 if the result doesn’t send a carry
CF = 1 if the result sends a carry
b. PF (Parity Flag).
- PF = 0 if the result lowest 8-bit contains odd number of 1’s
PF = 1 if the result lowest 8-bit contains even number of 1’s
c. ZF (Zero Flag).
- ZF = 0 if the result doesn’t = 0
ZF = 1 if the result = 0
d. SF (Sign Flag).
- SF = 0 if the result is (+)
SF = 1 if the result is (-)
e. OF (Overflow Flag).
- OF = 0 if the system capacity doesn’t be exceeded
OF = 1 if the system capacity is exceeded
10. State names of the Segmentation Registers available in the 8086 CPU.
- CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES (Extra Segment)
11. Find the actual memory addresses of the instructions having the following
CS:IP combinations:
a. CS = 1000H, IP = 2000H.
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8086 Microprocessor [Notes] - Version 3.0
- 10000H + 2000H = 12000H
b. CS = 1A00H, IP = B000H.
- 1A000H + B000H = 25000H
12. Find the actual memory addresses for these register values, Given that, CS =
0200H, DS = 1544H, SS = 5000H:
a. IP = 2350H.
- CS:IP → 0200H:2350H → 02000H + 2350H = 04350H
b. BX = 1300H.
- DS:BX → 1544H: 1300H → 15440H + 1300H = 16740H
c. SP = FFF0H.
- SS:SP → 5000H: FFF0H → 50000H + FFF0H = 5FFF0H
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Sheet 2 [8086]: Assembly Language
1. Write an 8086 assembly program to save the HEX numbers 01H, 02H, 03H,
04H, and 05H to memory locations 7101H, 7102H, 7103H, 7104H, and 7105H
respectively.
-
; THIS SOLUTION ~ N.3-B SOLUTION (SEE ALSO NO.3-A AND -C )
MOV CX,05H
MOV BX,7105H
L:
MOV [BX], CL
DEC BX
LOOP L
RET
2. Write an 8086 assembly program to add the value 05H to the contents of each
of the registers BL, CL, DL. Assuming BL=11H, CL=22H, DL=33H.
-
MOV BL,11H
MOV CL,22H
MOV DL,33H
ADD BL,05H
ADD CL,05H
ADD DL,05H
RET
3. Repeat question 1 for memory locations 0100H, 0101H, and 0102H
a. Using direct addressing.
-
MOV [0100H],00H
MOV [0101H],01H
MOV [0102H],02H
RET
b. Using indirect addressing.
-
MOV CX,0002H
MOV BX,0102H
L:
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8086 Microprocessor [Notes] - Version 3.0
MOV [BX],CL
DEC BX
DEC CL
JGE L
RET
c. Using relative addressing.
-
MOV BX,0002H
L:
MOV [BX+0100H],BL
DEC BX
JGE L
RET
4. Write an 8086 assembly program to add the two numbers 23F9H and 9A35H,
and save the result at memory locations 7100H, 7101H, and 7102H.
-
MOV AX,23F9H
ADD AX,9A35H
MOV [7100H], AX; SAVING THE MAIN VALUE 16-BIT IN 7100H&7101H
MOV AX,0000H
ADC AX,0000H
MOV [7102H], AL; SAVING CARRY BECAUSE WE HAVE ONE EXTRE MEMORY “7102H”
RET
5. Write an 8086 assembly program to add the two numbers F3A56BH and
78B6A9H, and save the result at memory locations 7100H, 7101H, 7102H, and
7103H. *
-
MOV AX, 0A56BH; SPLIT THE 24-BIT NUMBER ON TO (BLAX)
MOV BL,0F3H
ADD AX,0B6A9H
ADC BL,78H
MOV [7100H], AX; SAVING THE FIRST 16-BIT OF THE ANSWER TO 7100H&7101H
MOV [7102H], BL; SAVING THE NEXT 8-BIT OF THE ANSWER TO 7102H
MOV BL,00H
ADC BL,00H
MOV [7103H],BL ; SAVING CARRY BECAUSE WE HAVE ONE EXTRE MEMORY “7103H”
RET
6. Write an 8086 assembly program to calculate the summation of the contents
of each memory location from 7101H to 7105H, with its corresponding contents
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8086 Microprocessor [Notes] - Version 3.0
in memory locations 710AH to 710EH, then save the results in memory locations
7110H to 7114H, respectively. *
-
MOV BX,0004H
L:
MOV AL,[BX+7101H]
ADD AL,[BX+710AH]
MOV [BX+7110H],AL
DEC BX
JGE L
RET
7. Write an 8086 assembly program to contentiously read content of memory
location 7100H, and check its content: - if it is zero, put 1 in register BL. - if it is
negative, put 2 in register BL. - if it is positive, put 4 in register BL.
-
L:
MOV AL,[7100H]
CMP AL,00H
JZ LZERO
JS LNEGATIVE
MOV BL,04H ; IT’S POSITIVE
JMP L
RET
LZERO:
MOV BL,01H
JMP L
LNEGATIVE:
MOV BL,02H
JMP L
RET
8. Write an 8086 assembly program to perform a cyclic displacement on the
contents of registers AL, BL, and CL.
-
MOV DL,CL
MOV CL,BL
MOV BL,AL
MOV AL,DL
RET
9. Repeat question 8 with the contents of memory locations FE50H to FE52H
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8086 Microprocessor [Notes] - Version 3.0
a. Using direct addressing.
-
MOV AL,[0FE52H]
MOV AH,[0FE51H]
MOV [0FE52H],AH
MOV AH,[0FE50H]
MOV [0FE51H],AH
MOV [0FE50H],AL
RET
b. Using indirect addressing.
-
MOV BX,0FE52H
MOV AL,[BX]
; BX = 0FE52H
L:
; FIRST LOOP
; SECOND LOOP
; BX = 0FE51H
; BX = 0FE50H
MOV [BX],AH
; BX = 0FE52H
; BX = 0FE51H
DEC BX
; BX = 0FE51H
; BX = 0FE50H
CMP BX,0FE50H
; LOOP
; OUT
DEC BX
MOV AH,[BX]
INC BX
JG L
MOV [BX],AL ; BX = 0FE50H
RET
c. Using relative addressing.
-
MOV BX,0FE50H
MOV AL,[BX]
L:
MOV AH,[BX+01H] ;
MOV [BX],AH
INC BX
CMP BX,0FE52H
JL L
MOV [BX],AL
RET
d. Which addressing mode fits best? Why?
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8086 Microprocessor [Notes] - Version 3.0
- relative addressing special in the case of many locations because it has
less number of instruction
10. Write an 8086 assembly program to multiply the contents of register BL by
the contents of register BH, and save the result in AL. Don’t use the “MUL”
instruction.
-
MOV AL,00H
CMP BH,00H
JG L
RET
L:
ADD AL,BL
DEC BH
JG L
RET
11. Draw a flowchart and write an 8086 assembly program to divide the contents
of register BL by the contents of register BH, save the result in AL, and the
remainder in AH. Don’t use the “DIV” instruction. (Assume that BL > BH, BH≠ 0)
-
;IF YOU NEED TO UNDERSTAND THE CONSEPT SEE :
; http://www.bbc.co.uk/skillswise/factsheet/ma12pape-l1-f-division-using-repeated-subtraction
; Assume that BL > BH, BH != 0
MOV AL,00H ; INTIAL RESULT = 0
MOV AH,BL ; INITIAL REMINDER = ALL THE BIG NUMBER
L:
SUB AH,BH
INC AL
CMP AH,BH ; IF THE REMINTER STILL CONTAIN VALUE MOR THAN THE LOW NUMBER
JGE L
RET
12. Write an 8086 assembly program to calculate the factorial of an integer in the
accumulator, assuming that the result can reside in one byte register. Send the
result to register BX.
MOV CX,AX
MOV AX,01H
L:
MUL CL
LOOP L
MOV BX,AX
RET
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
13. Within the address range 1900H 191FH. Determine the content of BL, BH,
and DL registers in which: BL = Number of Positive values. BH = Number of
Negative values. DL = Number of Zero values.
-
MOV BL, 00H ; INITIALIZE THE COUNTER
MOV BH, 00H ; INITIALIZE THE COUNTER
MOV DL, 00H ; INITIALIZE THE COUNTER
MOV SI,191FH
L:
CMP [SI],00H
JZ LZERO
JS LNEGATIVE
INC BL
LX:
; IT’S POSITIVE
DEC SI
CMP SI,1900H
JGE L
RET
LZERO:
INC DL
JMP LX
LNEGATIVE:
INC BH
JMP LX
RET
14. Write an 8086 assembly program to always check the content of the input
port 35H. If the content is positive, put it in memory location 7200H. While if
negative, put it on output port 03H.
-
L:
IN AL,(35H)
CMP AL,00H
JG LPOSITIVE
JS LNEGATIVE
JMP L
RET
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8086 Microprocessor [Notes] - Version 3.0
LPOSITIVE:
MOV [7200H],AL
JMP L
LNEGATIVE:
OUT )03H(,AL
JMP L
RET
15. On a production line system of one factory the products are conveyed using
moving belts. At the end of the belt, product packaging takes place. Each package
contains 12 products. There is a photo cell near the end of the belt (connected to
bit7 of port 55H) that generates a positive logic signal when a product passes in
front of it. Write an 8086 assembly program to control the belt-motor (bit 0 of
port 00H) so as to stop it when product count reaches 12 to allow for the packing
process. When packaging is completed a worker may restart the belt-motor
manually through a switch (connected to bit1 of port 00H).
; FIRST SOLUTIOUN (LIKE THE IDEA OF N.16-FIRST SOLUTION)
; USE (BL) TO STORE THE LAST READ OF I/P SENSOR
; USE (CL) AS OUR COUNTER
START:
MOV AL,01H
OUT )00H(,AL ; RUN THE BELT-MOTOR
MOV CL,00H
MOV BL,00H
L:
IN AL,(55H)
AND AL,80H
ROL AL,01H
; ROTATE TO AVOID THE OVERFLOW IN CALCULATION (signed numbers)
CMP AL,BL
MOV BL,AL
JNL L
; THE LAST ARITMATIC OPERATION WAS “CMP”
INC CL
CMP CL,0CH
JL L
MOV AL,00H
OUT (00H),AL
LSWITCH:
IN AL,(00H)
AND AL,02H
CMP AL,00H
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8086 Microprocessor [Notes] - Version 3.0
-
JZ LSWITCH
JMP START
RET
; SECOND SOLUTIOUN
; USE (CL) AS OUR COUNTER
START:
MOV AL,01H
OUT (00H),AL ; RUN THE BELT-MOTOR
MOV CL,00H
L:
IN AL,(55H)
SHL AL,01H
JNC L
STILLINPULSE:
IN AL,(55H)
SHL AL,01H
JC STILLINPULSE
INC CL
CMP CL,0CH
JL L
MOV AL,00H
OUT (00H),AL ; STOP THE BELT-MOTOR
LSWITCH:
IN AL,(00H)
AND AL,02H
CMP AL,00H
JZ LSWITCH
JMP START
RET
16. In mid-town there is a garage that can hold a maximum capacity of 200 cars.
There are two photo-cells, one at the entrance and the other at the exit point,
each of which generates a positive pulse signal when a car passes in-front of it.
Write an 8086 assembly program to control one big red light to show the driver
whether there is an empty place for his car, or the garage is full. Assuming that: Entrance photo-cell is connected to bit0 of input port 00H. - Exit photo-cell is
connected to bit1 of input port 00H. - The Red (Full) Light is connected to bit0 of
output port 00H.
; USE (CL) AS OUR COUNTER
; USE (BL) AND (BH) TO STORE THE CURRENT READ OF I/P SENSORS
; USE (DL) AND (DH) TO STORE THE LAST READ OF I/P SENSORS
;(AT THE PULSE END "CURRENT READ < LAST READ" )
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8086 Microprocessor [Notes] - Version 3.0
-
MOV CL,00H
MOV BX,00H
MOV DX,00H
MOV AL,00H
OUT (00H),AL
L:
MOV DL,BL
MOV DH,BH
IN AL,(00H)
MOV BL,AL
AND BL,01H
MOV BH,AL
AND BH,02H
CMP BL,DL
JL LENTRANCE
LENTRANCERET:
CMP BH,DH
JL LEXIT
JMP L
RET
LENTRANCE:
INC CL
CMP CL,0C8H
JZ LFULL
JMP LENTRANCERET
LFULL:
MOV AL,01H
OUT (00H),AL
JMP LENTRANCERET
LEXIT:
DEC CL
MOV AL,00H
OUT (00H),AL
JMP L
RET
;THE SECOND SOLUTION
; USE (CL) AS OUR COUNTER
; USE (BL) TO STORE THE LAST READ STATE OF I/P SENSORS
; LAST --> CURRENT
; 00 --> ** 0 --> * ~ -----; 01 --> 00 1 --> 0 ~ IN
; 01 --> 10 1 --> 2 ~ IN
; 01 --> 11 1 --> 3 ~ -----Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
; 10 --> 00
; 10 --> 01
; 10 --> 11
; 11 --> 00
; 11 --> 01
; 11 --> 10
; SO:
; 1 --> 0 ~ IN
; 2 --> 0 ~ OUT
; 2 --> 1 ~ OUT
; 1 --> 2 ~ IN
; 3 --> 2 ~ IN
MOV CL,00H
MOV BL,00H
MOV AL,00H
OUT (00H),AL
L:
MOV BL,AL
IN AL,(00H)
AND AL,03H
CMP AL,00H
JZ LX0
CMP AL,01H
JZ LX1
CMP AL,02H
JNZ L
CMP BL,01H
JZ LENTRANCE
CMP BL,03H
JZ LENTRANCE
JMP L
LX1:
CMP BL,02H
JZ LEXIT
JMP L
LX0:
CMP BL,01H
JZ LENTRANCE
CMP BL,02H
JZ LEXIT
JMP L
RET
LENTRANCE:
2 --> 0 ~ OUT
2 --> 1 ~ OUT
2 --> 3 ~ -----3 --> 0 ~ IN+OUT (CAN TAKE NO ACTION)
3 --> 1 ~ OUT
3 --> 2 ~ IN
; IF CURRENT STATE IS 0
; IF CURRENT STATE IS 1
; IF CURRENT STATE IS 2
; IF 1 --> 2
; IF 3 --> 2
; IF 2 --> 1
; IF 1 --> 0
; IF 2 --> 0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
INC CL
CMP CL,0C8H
JZ LFULL
JMP L
LFULL:
MOV AL,01H
OUT (00H),AL
JMP L
LEXIT:
DEC CL
MOV AL,00H
OUT (00H),AL
JMP L
RET
17. Draw the schematic diagram and write an 8086 assembly program to
continuously read 8 input switches and control 8 output LEDs. So that if a switch
is LOW, then its corresponding LED is OFF, and if the switch is HIGH, then its
corresponding LED is ON, and so on. The 8 switches are on input port 00H The 8
LEDs are on output port 05H
L:
IN AL,(00H)
OUT (05H),AL
JMP L
RET
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8086 Microprocessor [Notes] - Version 3.0
Task [8086]
1. In the range 1900H to 1A00H, Find the Max. & Min. Numbers and their
address. Store Min. value at AL and its address at SI, Max. value at AH and its
address at DI.
- MOV BX,1900H
MOV SI,1900H
MOV DI,1900H
MOV AL, [SI]
MOV AH, [DI]
L:
INC BX
CMP [BX], AL
JL MINFOUND
MINFOUNDRET:
CMP [BX], AH
JG MAXFOUND
MAXFOUNDRET:
CMP BX,1A00H
JL L
RET
MINFOUND:
MOV AL, [BX]
MOV SI, BX
JMP MINFOUNDRET
MAXFOUND:
MOV AH, [BX]
MOV DI, BX
JMP L MAXFOUNDRET
RET
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
1st Term Midterm 2017/2018
1.
a) Compare between general-purpose and special-purpose registers in a
microprocessor.
- General-Purpose(Multipurpose) Registers:
Include AX, BX, CX, DX, BP, DI, and SI.
These registers hold various data sizes (bytes or words) and are used for
almost any purpose, as dictated by a program.
- Special-Purpose Registers:
Include IP, SP, and FLAGS, and the segment registers include CS, DS, SS, and
ES.
These registers are used for a certain purpose only.
b) What is the function of each of the following:
- IP.
- IP (Instruction Pointer register): point to the next instruction in a section of
memory defined as a code segment. That will be fetched to be executed by
the EU.
- SS.
- SS (Stack Segment): for memory locations that related to the stack. Works
with [SP, BP].
- DI.
- DI (Destination Index register)
Used for Addressing like:
Indexed Addressing Mode:
o [SI/DI + displacement 8-bit/16-bit] like [BX + 0082H]
Base-Indexed Addressing Mode:
o [BX/BP + SI/DI]
Base-Indexed with Displacement Addressing Mode:
o [BX/BP + SI/DI + displacement 8-bit/16-bit] like [BX + SI + 04H]
c) Explain:
I. The function of BIU.
- Bus Interface Unit (BIU): It takes care of all data and address transfers on
the buses for EU like: writing/reading data, fetching instructions and
sending address. Contains Instructions Queue(Cache), IP, CS, DS, SS, and ES.
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8086 Microprocessor [Notes] - Version 3.0
II. The MUL instruction.
- it’s an Arithmetic Instructions for Unsigned Multiply
MUL operand1
If operand1 refer to 8-bit ~ AX = AL * operand1
If operand1 refer to 16-bit ~ (DXAX) = AX * operand1
Conditional Flags changed (C, O) CF=OF=0 if high section of result is zero.
Conditional Flags unchanged (Z, S, P, A)
Operand1 may be:
REG
memory
2.
a. Write an assembly program:
I. To always invert the most two bits in the input port 25H.
- L:
IN AL,(25H)
XOR AL,11000000B
JMP L
RET
II. To put the maximum value of the data stored in memory locations
A2BC to A3AE in the output port 37H.
- MOV BX,0A2BCH
MOV AL,[BX]
L:
INC BX
CMP AL,[BX]
JL MAXFOUND
MAXFOUNDRET:
CMP BX,0A3AEH
JL L
OUT (37H),AL
RET
MAXFOUND:
MOV AL,[BX]
JMP MAXFOUNDRET
RET
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
b. Determine the task of the following program:
XX: IN AL,(0F5H)
MOV BH,AL
AND 02H
~ AND AL,02H
JZ YY
MOV AL,BH
MOV [B102H],AL
JMP XX
YY: MOV AL,BH
OUT (0C3H),AL
JMP XX
- To always check the D1 (bit-1) in the read of the input port F5H, if it is 0
send the read of the port to the output port C3H, else save the read of the
port to the memory location B102.
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8086 Microprocessor [Notes] - Version 3.0
Sheet 3: Microprocessor Buffering
1. What is meant by buffering?
- Buffering means passing an input through to output with providing
additional power to the value transferred allows a signal to drive more
inputs than it would by itself.
2. When do we need to apply buffering to microprocessor lines?
-
To avoid short circuit on buses (Data and Address) [To isolate address and data buses
from each other]and to provide additional power to the value transferred.
3. The input ports are built using tri-state buffers, why?
- To avoid short circuit on Data Bus with the outside environment and
control passing the values to data bus only when the port been accessed.
4. Discuss the types of tri-state buffers.
- Active High Tri-State Buffer
Active High Inverting Tri-State Buffer
Active Low Tri-State Buffer
Active Low Inverting Tri-State Buffer
5. Explain with sketching how address bus along with tri-state buffers are used
to prevent data collision on the data bus
6. Draw a logic circuit to get the Microprocessor 4 control lines (MEMR,
MEMW, IO𝑅 and IOW) out from the Intel 8086 CPU output lines (M/IO, RD
and WR).
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8086 Microprocessor [Notes] - Version 3.0
7. Draw a complete block diagram to show how the Intel 8086 CPU buffering is
done to prepare its buses for interfacing.
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8086 Microprocessor [Notes] - Version 3.0
8. Fill each empty field in the following table with the number of times the
corresponding control line in its column is asserted (activated) during
execution cycle.
Control Line
Instruction
MOV AL, 89H
MOV [0E100H], AL
MOV AX, [E100H]
IN AL, (00H)
OUT (00H), AL
MEMR
MEMW
IOR
IOW
BHE
1
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
1
1
9. What is meant by time multiplexing between data and address buses in the
intel 8086 microprocessor? And why?
- There are 16 shared lines between Data and Address buses (AD0:AD15)
using time multiplexing and controlled by (ALE and DEN) to indicate the
lines carry data or address.
- To Minimize the number of pins and chip area.
10. What is the control line that the intel 8086 microprocessor provides to
isolate address and data buses from each other? Draw a block diagram to
show how this control line is used for this purpose.
- Address Latch Enable (ALE): Active High,
Data Enable (DEN): Active Low.
Diagram included in Question No.7 Answer
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8086 Microprocessor [Notes] - Version 3.0
Sheet 4: Memory Interfacing with the Intel 8086 CPU
1. Show how to connect 4 KB EEPROM Memory on 2 chips to the Intel 8086
CPU.
- Solution using Memory Partial Decoding Approach
2 Chips (1 Even and 1 Odd)
4 KB = 212 B → Total Used Address Lines = 12 Line (A11-A0)
4 KB / 2 = 2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
Chips
4 KB
EEPROM
A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Address (HEX)
X
X
0
0
0
XX000
X
X
F
F
F
XXFFF
2. Show how to connect 64 KB EEPROM to the Intel 8086 CPU using memory
chips of 2 KB.
-
Solution using Memory Partial Decoding Approach
64 KB / 2 KB = 32 Chips (16 Even and 16 Odd)
64 KB = 216 B → Total Used Address Lines = 16 Line (A15-A0)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
Chips
A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Address (HEX)
X
Created By: M. El-Moughazy
0
0
0
0
X0000
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8086 Microprocessor [Notes] - Version 3.0
64 KB
EEPROM
X
F
F
F
F
XFFFF
3. Show how to connect 128 KB EEPROM to the Intel 8086 CPU using memory
chips of 4 KB.
- Solution using Memory Partial Decoding Approach
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8086 Microprocessor [Notes] - Version 3.0
- 128 KB / 4 KB = 32 Chips (16 Even and 16 Odd)
128 KB = 217 B → Total Used Address Lines = 17 Line (A16-A0)
4 KB = 212 B → 12 Address Lines (A1:A12) for each chip
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
128 KB
EEPROM
(XXX0) bin
0
0
0
0
XXX00000000000000000
(XXX1) bin
F
F
F
F
XXX11111111111111111
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8086 Microprocessor [Notes] - Version 3.0
4. Show how to connect 256 KB memory to the intel 8086 CPU by using
memory chips of 2 KB and 4 blocks.
- Solution using Memory Partial Decoding Approach
Block Size = 256 KB/4 Blocks = 64 KB/Block
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8086 Microprocessor [Notes] - Version 3.0
256 KB = 218 B → Total Used Address Lines = 18 Line (A17-A0)
64 KB = 216 B → 16 Address Lines (A0:A15) for each block
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
IN Each Block 64 KB/2 KB = 32 Chips → (16 Even and 16 Odd)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
1st
Block
(XX00) bin
0
0
0
0
XX000000000000000000
(XX00) bin
F
F
F
F
XX001111111111111111
2nd
Block
(XX01) bin
0
0
0
0
XX010000000000000000
(XX01) bin
F
F
F
F
XX011111111111111111
3rd
Block
(XX10) bin
0
0
0
0
XX100000000000000000
(XX10) bin
F
F
F
F
XX101111111111111111
4th
Block
(XX11) bin
0
0
0
0
XX110000000000000000
(XX11) bin
F
F
F
F
XX111111111111111111
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
5. Show how to connect 16 KB EEPROM and 16 KB RAM to the intel 8086 CPU,
using 8KB EEPROM chips and 8KB RAM chips. And draw the corresponding
memory map. - Solution using Memory Partial Decoding Approach
- 16 KB/8 KB = 2 Chips (1 Even and 1 Odd)
8 KB = 213 B → 13 Address Lines (A1:A13) for each chip
(16 KB + 16 KB) = 215 B → Total Used Address Lines = 15 Line (A14-A0)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
X
(X000) bin
0
0
0
XXXXX000000000000000
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8086 Microprocessor [Notes] - Version 3.0
16 KB
EEPROM
X
(X011) bin
F
F
F
XXXXX011111111111111
16 KB
RAM
X
(X100) bin
0
0
0
XXXXX100000000000000
X
(X111) bin
F
F
F
XXXXX111111111111111
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8086 Microprocessor [Notes] - Version 3.0
6. Show how to connect 16 KB EEPROM and 4 KB RAM to the intel 8086 CPU,
using 8KB EEPROM chips and 2KB RAM chips. And draw the corresponding
memory map.
- Solution using Memory Partial Decoding Approach
EEPROM:
16 KB/8 KB = 2 Chips (1 Even and 1 Odd)
8 KB = 213 B → 13 Address Lines (A1:A13) for each chip
RAM:
4 KB/2 KB = 2 Chips (1 Even and 1 Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
USE A14 to separate between EEPROM and RAM
(16 KB + 4KB) <= 215 B → Total Used Address Lines = 15 Line (A14-A0)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
16 KB
EEPROM
X
(X000) bin
0
0
0
XXXXX000000000000000
X
(X011) bin
F
F
F
XXXXX011111111111111
4 KB
RAM
X
(X100) bin
0
0
0
XXXXX100000000000000
X
(X100) bin
F
F
F
XXXXX100111111111111
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Sheet 5: I/O Interfacing with the Intel 8086 CPU
1. Show how to connect the intel 8086 CPU with the following:
a. 2KB EEPROM.
b. I/P port (00H).
c. O/P port (05H).
-
Solution using Memory Partial Decoding Approach
2 KB EEPROM (1 KB Even and 1 KB Odd)
2 KB = 211 B → Total Used Address Lines = 11 Line (A10-A0)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
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8086 Microprocessor [Notes] - Version 3.0
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
2 KB
EEPROM
X
X
(X000) bin
0
0
XXXXXXXXX00000000000
X
X
(X111) bin
F
F
XXXXXXXXX11111111111
2. Show how to connect the intel 8086 CPU with the following:
a. 2KB EEPROM.
b. 2KB RAM.
c. I/P port (F3H).
d. I/P port (E6H).
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8086 Microprocessor [Notes] - Version 3.0
- Solution using Memory Partial Decoding Approach
2 KB EPPROM (1 KB Even and 1 KB Odd)
2 KB RAM (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
(2 KB + 2 KB) = 212 B → Total Used Address Lines = 12 Line (A11-A0)
I/P Port (F3H) → (11110011) BIN
O/P Port (E6H) → (11100110) BIN
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address
(HEX)
2 KB
EEPROM
X
X
(0000) bin
0
0
XX000
X
X
(0111) bin
F
F
XX7FF
2 KB
RAM
X
X
(1000) bin
0
0
XX800
X
X
(1111) bin
F
F
XXFFF
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
3. Show how to connect the intel 8086 CPU with the following:
a. 4KB EEPROM.
b. 4KB RAM.
c. I/P port (A327H), using I/O mapped approach.
d. O/P port (05H).
- Solution using Memory Partial Decoding Approach
4 KB EPPROM (2 KB Even and 2 KB Odd)
4 KB RAM (2 KB Even and 2 KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
(4 KB + 4 KB) = 213 B → Total Used Address Lines = 13 Line (A12-A0)
I/P Port (A327H) → (1010001100100111) BIN
O/P Port (05H) → (0101) BIN
Chips
A19-A16
A15-A12
A11-A8
4 KB
EEPROM
X
(XXX0) bin
0
0
0
XXXXXXX0000000000000
X
(XXX0) bin
F
F
F
XXXXXXX0111111111111
4 KB
RAM
X
(XXX1) bin
0
0
0
XXXXXXX1000000000000
X
(XXX1) bin
F
F
F
XXXXXXX1111111111111
Created By: M. El-Moughazy
A7-A4 A3-A0
Address (BIN)
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8086 Microprocessor [Notes] - Version 3.0
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8086 Microprocessor [Notes] - Version 3.0
4. Show how to connect the intel 8086 CPU with the following:
a. 4KB EEPROM.
b. 2KB RAM.
c. I/P port (1222H), using memory mapped approach.
d. O/P port (1223H), using memory mapped approach.
- 1st Solution using Memory Partial Decoding Approach
EEPROM:
4 KB (2 KB Even and 2KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
RAM:
2 KB (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
USE A12 to separate between EEPROM and RAM
(4 KB + 2 KB) <= 213 B → Total Used Address Lines = 13 Line (A12-A0)
I/P Port (1222H) → (0001 0010 0010 0010) BIN
O/P Port (1223H) → (0001001000100011) BIN
USE A13 to separate between Memory and I/O Ports
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
4 KB
EEPROM
X
(XX10) bin
0
0
0
XXXXXX10000000000000
X
(XX10) bin
F
F
F
XXXXXX10111111111111
2 KB
RAM
X
(XX11) bin
0
0
0
XXXXXX11000000000000
X
(XX11) bin
F
F
F
XXXXXX11111111111111
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
- 2nd Solution using Memory Full Decoding Approach
EEPROM:
4 KB (2 KB Even and 2KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
RAM:
2 KB (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
USE A12 to separate between EEPROM and RAM
(4 KB + 2 KB) <= 213 B → Total Used Address Lines = 13 Line (A12-A0)
I/P Port (1222H) → (0001 0010 0010 0010) BIN
O/P Port (1223H) → (0001001000100011) BIN
Chips
A19-A16
A15-A12
A3-A0
Address (HEX)
4 KB
EEPROM
0
(0000) bin
0
0
0
00000
0
(0000) bin
F
F
F
00FFF
2 KB
RAM
0
(0001) bin
0
0
0
01000
0
(0001) bin
F
F
F
01FFF
Created By: M. El-Moughazy
A11-A8 A7-A4
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8086 Microprocessor [Notes] - Version 3.0
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8086 Microprocessor [Notes] - Version 3.0
5. Show how to connect the intel 8086 CPU with the following:
a. 4KB EEPROM.
b. 4KB RAM.
c. PPI chip at base addresses 30H.
- Solution using Memory Partial Decoding Approach
4 KB EEPROM (2 KB Even and 2 KB Odd)
4 KB RAM (2 KB Even and 2 KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
USE A12 to separate between EEPROM and RAM
(4 KB + 4 KB) = 213 B → Total Used Address Lines = 13 Line (A12-A0)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
4 KB
EEPROM
X
(XXX0) bin
0
0
0
XXXXXXX0000000000000
X
(XXX0) bin
F
F
F
XXXXXXX0111111111111
4 KB
RAM
X
(XXX1) bin
0
0
0
XXXXXXX1000000000000
X
(XXX1) bin
F
F
F
XXXXXXX1111111111111
PPI:
Base Address (30H) → (00110000) BIN
PPI-A1 → A2 PPI-A0 → A1
Port A
Port B
Port C
CWR
0
0
1
1
Created By: M. El-Moughazy
0
1
0
1
Address (Hex)
30
32
34
36
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8086 Microprocessor [Notes] - Version 3.0
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8086 Microprocessor [Notes] - Version 3.0
6. Show how to connect the intel 8086 CPU with the following:
a. 4KB EEPROM.
b. 4KB RAM.
c. Two PPI chips:
i. One PPI at base addresses 50H
ii. One PPI and base address 2100H, using memory mapped approach.
st
- 1 Solution using Memory Partial Decoding Approach
4 KB EEPROM (2 KB Even and 2 KB Odd)
4 KB RAM (2 KB Even and 2 KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
USE A12 to separate between EEPROM and RAM
(4 KB + 4 KB) = 213 B → Total Used Address Lines = 13 Line (A12-A0)
USE A13 to separate between Memory and I/O Ports
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
4 KB
EEPROM
X
(XX00) bin
0
0
0
XXXXXX00000000000000
X
(XX00) bin
F
F
F
XXXXXX00111111111111
4 KB
RAM
X
(XX01) bin
0
0
0
XXXXXX01000000000000
X
(XX01) bin
F
F
F
XXXXXX01111111111111
1st PPI:
Base Address (50H) → (01010000) BIN
PPI-A1 → A2 PPI-A0 → A1
Address (Hex)
Port A
0
0
50
Port B
0
1
52
Port C
1
0
54
CWR
1
1
56
2nd PPI:
Base Address (2100H) → (0010000100000000) BIN
PPI-A1 → A2 PPI-A0 → A1 Address (Hex)
Port A
0
0
2100
Port B
0
1
2102
Port C
1
0
2104
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8086 Microprocessor [Notes] - Version 3.0
CWR
1
Created By: M. El-Moughazy
1
2106
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
- 2nd Solution using Memory Full Decoding Approach
4 KB EEPROM (2 KB Even and 2 KB Odd)
4 KB RAM (2 KB Even and 2 KB Odd)
2 KB = 211 B → 11 Address Lines (A1:A11) for each chip
USE A12 to separate between EEPROM and RAM
(4 KB + 4 KB) = 213 B → Total Used Address Lines = 13 Line (A12-A0)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address
(HEX)
4 KB
EEPROM
0
(0000) bin
0
0
0
00000
0
(0000) bin
F
F
F
00FFF
4 KB
RAM
0
(0001) bin
0
0
0
01000
0
(0001) bin
F
F
F
01FFF
1st PPI:
Base Address (50H) → (01010000) BIN
PPI-A1 → A2 PPI-A0 → A1
Address (Hex)
Port A
0
0
50
Port B
0
1
52
Port C
1
0
54
CWR
1
1
56
nd
2 PPI:
Base Address (2100H) → (0010000100000000) BIN
PPI-A1 → A2 PPI-A0 → A1 Address (Hex)
Port A
0
0
2100
Port B
0
1
2102
Port C
1
0
2104
CWR
1
1
2106
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8086 Microprocessor [Notes] - Version 3.0
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8086 Microprocessor [Notes] - Version 3.0
Sheet 6: Intel 8086 CPU Microcomputer
1.
a. Design a microcomputer has the following:
i. Intel 8086 CPU.
ii. 2KB EEPROM.
iii. 2KB RAM.
iv. I/P port (70H).
v. O/P port (33H).
b. Write an intel 8086 assembly program to read i/p port (70H) and check its
content. If the content is odd, put it on o/p port (33H). if the content is even,
put it in memory location 0100H.
-
Solution using Memory Partial Decoding Approach
2 KB EPPROM (1 KB Even and 1 KB Odd)
2 KB RAM (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
Use A11 to separate between EEPROM and RAM
(2 KB + 2 KB) = 212 B → Total Used Address Lines = 12 Line (A11-A0)
I/P Port (70H) → (01110000) BIN
O/P Port (33H) → (00110011) BIN
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (HEX)
2 KB
EEPROM
X
X
(0000) bin
0
0
XX000
X
X
(0111) bin
F
F
XX7FF
2 KB
RAM
X
X
(1000) bin
0
0
XX800
X
X
(1111) bin
F
F
XXFFF
Program:
START:
IN AL, (70H)
MOV AH, AL
SHR AH, 01H
JNC EVEN
ODD:
OUT (33H), AL
RET
EVEN:
MOV [0100H], AL
RET
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8086 Microprocessor [Notes] - Version 3.0
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8086 Microprocessor [Notes] - Version 3.0
2.
a. Design a microcomputer has the following:
i. Intel 8086 CPU.
ii. 2KB EEPROM.
iii. 2KB RAM.
iv. PPI chip at base address 70H.
b. Write an intel 8086 assembly program to configure the PPI chip in part (a)
such that port A is input, while ports B and C are output. Then read port A forty
[40] times and check its content. If the content is odd, put it in port B. if the
content is even, put it in port C.
- Solution using Memory Partial Decoding Approach
2 KB EPPROM (1 KB Even and 1 KB Odd)
2 KB RAM (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
Use A11 to separate between EEPROM and RAM
(2 KB + 2 KB) = 212 B → Total Used Address Lines = 12 Line (A11-A0)
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address
(HEX)
2 KB
EEPROM
X
X
(0000) bin
0
0
XX000
X
X
(0111) bin
F
F
XX7FF
2 KB
RAM
X
X
(1000) bin
0
0
XX800
X
X
(1111) bin
F
F
XXFFF
PPI:
Base Address (70H) → (01110000) BIN
PPI-A1 → A2 PPI-A0 → A1 Address (Hex)
Port A
0
0
70
Port B
0
1
72
Port C
1
0
74
CWR
1
1
76
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Program:
START:
MOV AL, 90H; CWR → (10010000) BIN
OUT (76H), AL
MOV CX, 028H; 28H → 40 DEC
STARTOFLOOP:
IN AL, (70H)
MOV AH, AL
SHR AH, 01H
JNC EVEN
ODD:
OUT (72H), AL
EVEN:
OUT (74H), AL
LOOP STARTOFLOOP
RET
3.
a. Design a microcomputer has the following:
i. Intel 8086 CPU.
ii. 2KB EEPROM.
iii. 2KB RAM.
iv. PPI chip at base address BF20H.
b. Write an intel 8086 assembly program to configurated the PPI chip in part
(a) such that ports A and B are inputs, while port C is output. Then read the two
ports A and B and send the larger value to port C, while the smaller value to
memory location 2100H.
- Solution using Memory Partial Decoding Approach
2 KB EPPROM (1 KB Even and 1 KB Odd)
2 KB RAM (1 KB Even and 1 KB Odd)
1 KB = 210 B → 10 Address Lines (A1:A10) for each chip
Use A11 to separate between EEPROM and RAM
(2 KB + 2 KB) = 212 B → Total Used Address Lines = 12 Line (A11-A0)
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address
(HEX)
2 KB
EEPROM
X
X
(0000) bin
0
0
XX000
X
X
(0111) bin
F
F
XX7FF
2 KB
RAM
X
X
(1000) bin
0
0
XX800
X
X
(1111) bin
F
F
XXFFF
PPI:
Base Address (0BF20H) → (1011111100100000) BIN
PPI-A1 → A2 PPI-A0 → A1 Address (Hex)
Port A
0
0
BF20
Port B
0
1
BF22
Port C
1
0
BF24
CWR
1
1
BF26
Program:
START:
MOV AL, 92H; CWR → (10010010) BIN
MOV DX, 0BF26H; LOAD CWR ADDRESS
OUT DX, AL
MOV DX, 0BF22H; LOAD PORT B ADDRESS
IN AL, DX
MOV BL, AL;
PORT B READ IN BL
MOV DX, 0BF20H; LOAD PORT A ADDRESS
IN AL, DX;
PORT A READ IN AL
MOV DX, 0BF24H; LOAD PORT C ADDRESS
CMP AL, BL
JGE ALARGER
BLARGER:
MOV [2100H], AL
MOV AL, BL
OUT DX, AL
RET
ALARGER:
OUT DX, AL
MOV [2100H], BL
RET
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
NOTE: TO SOLVE USING MEMORY MAPPED USE A12 TO SEPARATE BETWWEN MEMORY AND
I/O as Memory Partial Decoding Approach OR USE Memory Full Decoding Approach.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
-
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
2nd Term Midterm 2017/2018
1. Show how we can:
a. Buffer the 8086 microprocessor buses.
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
b. Cover the 8086-memory range using 64 KB RAM chips.
- 1 MB / 64 KB = 16 Chips (8 Even and 8 Odd)
64 KB = 216 B → 16 Address Lines (A1:A16) for each chip
1 MB = 220 B → Total used address lines 20 (A19-A0)
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
2. Show how we connect 8086 microprocessor with the following:
• Two 8 KB EPROM chips
• O/P Port (3D)
• I/P Port (A2DE0)
st
- 1 Solution using Memory Partial Decoding Approach
Chips (1 Even and 1 Odd)
8 KB = 213 B → 13 Address Lines (A1:A13) for each chip
(8 KB + 8KB) <= 214 B → Total used address lines 14 (A13-A0)
O/P Port (3D) → (00111101) BIN
I/P Port (A2DE0) → (1010 0010 1101 1110 0000) BIN
Use A14 to separate between Memory and I/O Ports
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (BIN)
16 KB
EEPROM
X
(X100) bin
0
0
0
XXXXX100000000000000
X
(X111) bin
F
F
F
XXXXX111111111111111
- 2nd Solution using Memory Full Decoding Approach
Chips (1 Even and 1 Odd)
8 KB = 213 B → 13 Address Lines (A1:A13) for each chip
(8 KB + 8KB) <= 214 B → Total used address lines 14 (A13-A0)
O/P Port (3D) → (00111101) BIN
I/P Port (A2DE0) → (1010 0010 1101 1110 0000) BIN
Chips
A19-A16
A15-A12
A11-A8
A7-A4
A3-A0
Address (HEX)
16 KB
EEPROM
0
(0000) bin
0
0
0
00000
0
(0011) bin
F
F
F
03FFF
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
Created By: M. El-Moughazy
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8086 Microprocessor [Notes] - Version 3.0
3. Compare between:
• Microprocessor and Microcontroller
Microprocessor
Microcontroller
Chip contains only the processor
Chip contains processor and all the
components of a computer (Memory,
I/o, ...)
Need other components to make
Stand alone
working system
More Flexibility
Less Flexibility
More components count in system
Less components count is system
• CISC and RISC Computers
RISC
Stands For
Reduced Instruction Set
Execution
one cycle
Time
Speed
Faster
Number of
Minimum Instruction
Instructions
Instruction
Fixed
Format
Created By: M. El-Moughazy
CISC
Complex Instruction Set
multiple cycles
Slower
Large Number of Instructions
Variable
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