VHDL and HDL Designer Primer
Instructor: Jason D. Bakos
VHDL (Appendix B in Textbook)
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HDL => VHDL / Verilog
VHDL more verbose, better for team projects
Not case-sensitive
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VHDL => “VHSIC Hardware Description Language”
VHSIC => “US DoD Very-High-Speed Integrated Circuit”
DoD project
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Used to describe behavior of digital logic
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Document behavior of ASICs from suppliers
Alternative to manuals
Extensions for analog
High-level programming language, subset of Ada
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Also looks like Pascal
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IEEE standards: 1987, 1993, 2000, 2002
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First came the language…
…next came simulators…
…then came synthesizers (FPGA and ASIC)
VLSI System Design 2
VHDL
• By its nature, VHDL is
– Self-documenting
– Allows for easy testbench design (simulators, instruments)
• Any VHDL code may be simulated
• Only some VHDL codes may be synthesized
– Depends on packages, data types, and constructs
• VHDL descriptions (programs) have structure similar to C++
• Each design (component) is made up of
– Entity section
• Component interface (I/O)
• Analogous to C++ header (public methods only)
– Architecture section
• Contains behavior (implementation)
• Can have multiple architectures for any entity
• Example: different types of adders with consistent interfaces
VLSI System Design 3
Entity / Architecture
library ieee;
use ieee.std_logic_1164.all;
entity buffer is
port (
a:in std_logic_vector(3 downto 0);
y:out std_logic_vector(3 downto 0)
);
end;
architecture my_hypernifty_buffer of buffer is
signal int_a : std_logic_vector(3 downto 0);
begin
int_a <= not a;
y <= not int_a;
end;
VLSI System Design 4
Data Types
• In this course, you will only use 2 data types
– std_logic
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Represents a bit signal
Enermerated type: (1, 0, X, U, Z, -)
1, 0 are logic values
X is “don’t know” – unassigned or shorted (double-driven) signals
U is “unassigned” – special for un-initialized FF/register/memory
Z is “high-impendence” – for tristated/floating outputs
- is “don’t care” – for outputs, helps synthesizer minimize logic
• Use ‘1’ to represent scaler
– std_logic_vector
• Array of std_logic
• Represents a “bus” signal
• Use “11” to represent scaler
VLSI System Design 5
Sequential vs. Concurrent Semantics
• Problem:
– Programming languages with sequential semantics:
• Assume B=0, C=5
A = B
print
print
B = C
print
print
+ C
A (output is 5)
B (output is 0)
A (output is 5)
B (output is 5)
– Hardware is concurrent
• Each line of code executes concurrently (no ordering)
A = B
print
print
B = C
print
print
+ C
A (output is 10)
B (output is 5)
A (output is 10)
B (output is 5)
• Example:
– A <= B OR C when D=‘1’ else C OR D;
– E <= A + B;
• How is this synthesized?
VLSI System Design 6
Structural vs. Behavioral VHDL
• Structural VHDL
– Resembles a netlist
• Defines instantiated components
• Interconnects
– May contain library subroutine calls, operators, mux behavior
– Can be directly (and easily) synthesized
• Behavioral VHDL
– Defines how outputs are computed as function of inputs
– Use a “process”
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Looks like a programming language
Internally has sequential semantics
Sensitivity list
Process block implements concurrent assignment
May contain variables
Constructs: if-then, for-loop, while-loop, inf-loop
Difficult to synthesize
Not synthesizable: timed waits, file I/O, some loop structures
VLSI System Design 7
Constructs in Structural VHDL
• Concurrent assignment statement
[output] <= [function of inputs] after [delay] when [condition] else
[function of inputs] after [delay] when [condition] else
…
[function of inputs];
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Example:
out <= A and B when sel=“00” else
A or B when sel=“01” else
A nor B when sel=“10” else
A xor B;
sel <= “00” when (C or D)=“0101” else
“10”;
VLSI System Design 8
Priority
out <= A
A
A
A
and B when sel=“00” else
or B when sel=“01” else
nor B when sel(1)=‘1’ else
xor B;
• What’s the problem with the above statement?
VLSI System Design 9
Constructs in Process VHDL
• if-statement
if a=“01” then
y <= b;
elsif a=“11” then
y <= not(b)+1;
else
y <= “0000”;
end if;
• Loops
loop
<statements>
end loop;
for i in 0 to 15 loop
<statements>
end loop;
while <condition>
<statements>
end loop;
VLSI System Design 10
Example process
-- right-shift arithmetic for 8-bit signed integer
rsa: process (a, shamt)
variable fill : std_logic_vector(1 downto 0);
variable temp : std_logic_vector(4 downto 0);
begin
for i in 0 to 3 loop
fill(i):=‘1’ and a(3);
end loop;
if shamt(0)=‘1’ then
temp := fill(0) & a(7 downto 1);
end if;
if shamt(1)=‘1’ then
temp := fill(1 downto 0) & temp(7 downto 2);
end if;
if shamt(2)=‘1’ then
out <= fill(3 downto 0) & temp(7 downto 4);
end if;
end process;
VLSI System Design 11
Memory
• Memory is inferred:
-- 8-bit rising-edge register with asynchronous reset
reg8 : process(d, clk, en, rst)
begin
if rst=‘1’ then
q <= “00000000”;
elseif en=‘1’ and clk’event and clk=‘1’ then
q <= d;
end if;
end process;
VLSI System Design 12
HDL Designer
• Allows for rapid VHDL development
– graphical design entry
– generated VHDL
– automated design flows
• Views
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Block diagram
State machine
Truth table
Flow chart
VHDL view (combined or architecture-only)
Symbol
VLSI System Design 13
Libraries in HDL Designer
• A library is a collection of components
– Components have one or more views (implementations)
• Block diagram, truth table, flow chart, state machine, VHDL
architecture
– Each view has representations:
• Graphics, VHDL, simulator netlist, synthesis netlist
CPU_lib
library
component
view
representation
block diagram 1
graphics
ALU
CPU
control_unit
block diagram 2
VHDL arch
state diagram
gen. VHDL
sim. binary
synth. netlist
VLSI System Design 14
Libraries in HDL Designer
• Libraries are stored in four subdirectories
\ALU_lib
\hds
source directory
\hdl
HDL directory
\work
simulation directory
\ls
synthesis directory
/libraries
\CPU_lib
– For each library you use or create, library mappings
to these directories must be specified
– The mappings for your set of libraries are stored in
your project file
• Lives in your group directory
VLSI System Design 15
Projects
• Projects are a collection of library mappings
Project
tutorial
Library
ALU_Lib
Component
ALU
Src (hds)
HDL
Downstream
Downstream
(graphical view)
(generated)
(compiled for sim)
(compiled for synth)
VLSI System Design 16
Projects, Libraries, Files
Shared
Project
ieee
ALU
ALU_Lib
src files
hdl files
CPU
COELib
sim files
CPU_Lib
synth files
VLSI System Design 17
HDL Designer GUI
VLSI System Design 18
Block Diagram Editor
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Block Diagram Editor
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Flowchart Editor
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Lookup Table Editor
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State Machine Editor
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VHDL Editor
VLSI System Design 24
Components
• Library components can be
instantiated in other
designs
– Shown as green blocks
• For bottom-up design
– Libraries also contain
“blocks”
• Attached to the design they
were created in
• Shown as blue blocks
• For top-down design
– Embedded blocks –
embedded into block
diagram
• Shown as yellow blocks
• Embeds behavior into structure
VLSI System Design 25
Sequential Logic
• Combinational logic
– Output = f (input)
• Sequential logic
– Output = f (input, input history)
– Involves use of memory elements
• Registers
VLSI System Design 26
Finite State Machines
No
missile
detected
• FSMs are made up of:
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input set
output set
states (one is start state)
transitions
No locked
on
Standby
missile
detected
Fire=no
Target
Fire = no
• FSMs are used for controllers
miss
hit
Locked
on
Launch
Fire= yes
Input alphabet {missile detected, locked
on, hit, miss}
Output alphabet{fire}
VLSI System Design 27
Finite State Machines
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Registers
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Output logic
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Hold current state value
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Encodes output of state machine
• Moore-style
– Output = f(current state)
»
• Mealy-style
Output values associated with
states
– Output = f(current state, input)
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Output values associated with
state transitions
Outputs asynchronous
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Next-state logic
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Synchronous state machines transition on
clock edge
RESET signal to return to start state
(“sanity state”)
Note that state machines are triggered
out-of-phase from the input and any
memory elements they control
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Encodes transitions from each state
Next state = f(current state, input)
VLSI System Design 28
Example
• Design a coke machine controller
– Releases a coke after 35 cents entered
– Accepts nickels, dimes, and quarters,
returns change
– Inputs
• Driven for 1 clock cycle while coin is entered
• COIN = { 00 for none, 01 for nickel, 10 for
dime, 11 for quarter}
– Outputs
• Driven for 1 clock cycle
• RELEASE = { 1 for release coke }
• CHANGE releases change, encoded as COIN
input
VLSI System Design 29
Example
• We’ll design this controller as a state diagram view in
FPGA Advantage
Add new state
(First is start state)
Add new hierarchical
state
Add new transition
Note: transitions into and out of a
hierarchical state are implicitly ANDed
with the internal entrance and exit
conditions
VLSI System Design 30
Example
• Go to state diagram properties to setup the
state machine…
VLSI System Design 31
Example
• Specify the output values for each state in the state
properties
VLSI System Design 32
Example
• Specify the transition conditions and priority in the transition
properties
VLSI System Design 33
Example
VLSI System Design 34
Example
VLSI System Design 35
State Machine VHDL
• Let’s take a look at the VHDL for the FSM
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Enumerated type: STATE_TYPE for states
Internal signals, current_state and next_state
clocked process handles reset and state changes
nextstate process assigns next_state from
current_state and inputs
• Implements next state logic
• Syntax is case statement
– output process assigns output signals from
current_state
• Might also use inputs here
VLSI System Design 36
Types
ARCHITECTURE fsm OF coke IS
-- Architecture Declarations
TYPE STATE_TYPE IS (
standby,
e5,
e10,
e25,
e30,
e15,
e20,
e35,
e50,
e40,
e55,
e45
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE ;
SIGNAL next_state : STATE_TYPE ;
VLSI System Design 37
“clocked” Process
---------------------------------------------------------------------------clocked : PROCESS(
clk,
rst
)
---------------------------------------------------------------------------BEGIN
IF (rst = '1') THEN
current_state <= standby;
-- Reset Values
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
END IF;
END PROCESS clocked;
VLSI System Design 38
“nextstate” Process
---------------------------------------------------------------------------nextstate : PROCESS (
coin,
current_state
)
---------------------------------------------------------------------------BEGIN
CASE current_state IS
WHEN standby =>
IF (coin = "01") THEN
next_state <= e5;
ELSIF (coin = "10") THEN
next_state <= e10;
ELSIF (coin = "11") THEN
next_state <= e25;
ELSE
next_state <= standby;
END IF;
WHEN e5 =>
IF (coin = "10") THEN
next_state <= e15;
ELSIF (coin = "11") THEN
next_state <= e30;
ELSIF (coin = "01") THEN
next_state <= e10;
ELSE
next_state <= e5;
END IF;
WHEN e10 =>
…
VLSI System Design 39
“output” process
---------------------------------------------------------------------------output : PROCESS (
current_state
)
---------------------------------------------------------------------------BEGIN
-- Default Assignment
change <= "00";
release <= '0';
-- Default Assignment To Internals
-- Combined Actions
CASE current_state IS
WHEN standby =>
change <= "00" ;
release <= '0' ;
WHEN e5 =>
change <= "00" ;
release <= '0' ;
WHEN e10 =>
change <= "00" ;
release <= '0' ;
WHEN e25 =>
change <= "00" ;
release <= '0' ;
WHEN e30 =>
change <= "00" ;
release <= '0' ;
WHEN e15 =>
change <= "00" ;
release <= '0' ;
…
VLSI System Design 40
Hierarchical States
hstate1
VLSI System Design 41
Testbenches
• “Harness” for a component
• Interface matching
– Inputs  Outputs
• Allows
– Stimulation of input signals
– Output signal checking
• ASSERTs
• Waiting/branching based on outputs
– Debugging with waveforms
• Testbench component
– Block diagram
• Tester component
– Typically a flowchart
VLSI System Design 42
Testbenches
• Advantage over ad hoc methods
– Ex. do-files
• Allows simulation of inputs, but no output checking
• Testbench code reveals interface specification and
functionality (“self documenting”)
• Reproducible
– Can use same testbench for multiple
implementations/generations of a component
– Can generate or utilize data file to share tests
between simulation and hardware testing
VLSI System Design 43
Testbenches
• A test procedure is a methodology for testing a design
– Sequence of steps
– Testing aspects of a design’s functionality
• Example: ALU
– Test each type of operation with different inputs
– Along with asserting inputs/operations, can also verify correctness of output
values
– Also, use if-then-else semantics
VLSI System Design 44
Testbenches
• Facilities in HDL Designer
– Easy creation of tester/testbench
– Flowchart view is natural choice for implementing a test
bench
• Mirrors test procedure in a graphical representation
– VHDL support for testbenches
• ASSERT/REPORT/SEVERITY clause
– Can use boolean operators here
• Testbench operates in simulation
VLSI System Design 45
Testbenches
• Simple testbench example
• Drive inputs
• Wait for combinational logic
• Wait for clock edges
• ASSERT/REPORT/SEVERITY
• Repeat
VLSI System Design 46