Sir Syed University of Engineering & Technology (SSUET)
Computer Engineering Department
Digital System Design (CE-304)
Semester: 6th
Batch: 2020
LAB FILE
Course Teachers:
Lab Teachers:
Engr. Maqsood Jan Mohammad
Engr. Maqsood Jan Mohammad
1
TABLE OF CONTENT
Lab #
1
2
3
Topic
Page #
Introduction to HDL & Verilog. Develop, implement &
simulate AND, OR and NOT gates by using Gate Level
Modeling
Develop, implement & simulate Full Adder & Half Adder
through Schematic & Gate Level Modeling
12
Develop, implement & simulate Flouting point multiplication and
57
40
division through Data Flow Modeling.
4
Develop, implement & simulate 4-bits Ripple Carry Adder &
4-bits Subtractor
65
5
Develop, implement & simulate 2x2 multiplier and 4x4
multiplier
71
6
Develop, implement & simulate 8x8 Dadda Wallace Tree
74
7
Open ended lab
78
8
Develop, implement & simulate Sequence Detector by using
Finite State Machine – Moore Machine
79
9
Develop, implement & simulate Sequence Detector by using
Finite State Machine – Moore Machine
85
10
Reproduce and implement basic gates by using FPGA Kit.
89
11
Reproduce and implement Half Adder by using FPGA Kit.
104
12
Reproduce and implement Full Adder by using FPGA Kit.
106
13
Reproduce and implement Ripple Carry Adder by using FPGA
Kit.
108
14
Open Ended Lab
110
2
Annexure C
SSUET/QR/118
(Form Ia)
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric Guideline for Hardware Based Lab
Course Name (Course Code),
Semester, Batch
Name of Student:
Roll No.
Criteria
Exceeds Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory
(<50%)
Can’t set up the
experiment even
with assistance
Able to setup
experiment
independently with
complete understanding
of each step
Able to setup
experiment
independently with
adequate
understanding of
each step
Can setup major part
of the experiment
with assistance
Procedure
Able to follow the
procedure completely
with simplification or
develop alternate
procedure
Able to follow the
procedure
completely
Able to follow major Unable to follow
part of the procedure the procedure
with errors or
omissions
Experimental
Results
Able to achieve all the
desired results with
alternate ways to
improve measurements
Able to achieve all
the desired results
Able to achieve
most of the desired
results with errors
Unable to achieve
the desired results
Extremely alert to
practice safety measures
in laboratory procedures
Fairly alert to
practice safety
measures in
laboratory
procedures
Rarely alert to
practice safety
measures in
laboratory
procedures
Poorly alert about
safety measures in
laboratory
procedures
Laboratory manual has
no grammatical and/ or
spelling errors.
Laboratory manual
has very few
grammatical/
spelling errors.
Laboratory manual
has multiple
grammatical/
spelling errors.
All sections of the
report are
technically accurate.
Few sections of the
report contains
technical errors.
Laboratory
manual has several
grammatical/
spelling errors and
sentence
construction is
poor. All sections
of the report
contains multiple
technical errors.
Experimental
Setup
Safety
Laboratory
Manual
All sections of the
report are very well
written and technically
accurate.
3
SSUET/QR/118
(Form Ib)
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric -Laboratory Manual
Course Name (Course Code),
Semester, Batch
Name of Student:
Roll No.
Description & Score
Lab
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
Experimental Setup
(
)/0.1
Procedure
(
)/0.5
(
Results
)/0.2
(
Safety
)/0.1
Lab Report
( )/0.1
(
Score
)/1.0
TOTAL SCORE
Overall Score:
(Obtained Score / Total Score) x 5
out of 5
Examined by:
(Name and Signature of concerned lab instructor
4
SSUET/QR/118
(Form IIa)
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric Guideline for Software Based Lab
Course Name (Course Code),
Semester, Batch
Name of Student:
Roll No.
Criteria
Exceeds Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
Unsatisfactory
(<50%)
(50%-69%)
Software
Handling
Able to use software
with its standard and
advanced features
without assistance
Able to use software
with its standard and
advanced features with
minimal assistance
Able to use
software with its
standard features
with assistance
Unable to use the
software
Able to program/
simulate the lab tasks
without errors
Able to program/
simulate lab tasks
with errors
Unable to
program/simulate
Able to achieve all the
desired results with
alternate ways
Able to achieve all the
desired results
Able to achieve
most of the
desired results
with errors
Unable to
achieve the
desired results
Laboratory manual has
no grammatical and/ or
spelling errors.
Laboratory manual has
very few grammatical/
spelling errors.
All sections of the
report are very well
written and technically
accurate.
All sections of the
report are technically
accurate.
Laboratory
manual has
multiple
grammatical/
spelling errors.
Laboratory
manual has
several
grammatical/
spelling errors
and sentence
construction is
poor.
Programming/ Able to program/
simulate the lab tasks
Simulation
with simplification
Results
Laboratory
Manual
Few sections of
the report contains
technical errors.
5
SSUET/QR/118
[Form-IIb]
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric-Laboratory Manual
Course Name (Course Code),
Semester, Batch
Name of Student:
Roll No.
Lab
Description & Score
1.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
2.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
3.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
4.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
5.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
9.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
10.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
11.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
13.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
14.
Software Handling
(
)/0.2
Programming/ Simulations
(
)/0.5
(
Results
)/0.2
Lab Report
(
)/0.1
(
Score
)/1.0
6.
7.
8.
12.
TOTAL SCORE
Overall Score:
out of 5 Examined by:
(Obtained Score / Total Score) x 5
(Name and Signature of concerned lab instructor)
6
SSUET/QR/118
(Form IIIa)
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric for Subject Project
Course Name (Course Code),
Semester, Batch
Name of Student:
Roll No.
Criteria
Project
Demonstration
Project results
Project Report
Viva
Exceeds
Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory
(<50%)
Able to
demonstrate the
project with
achievement of
required objectives
having clear
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are fully
functional, if
applicable.
Able to demonstrate
the project with
achievement of
required objectives
but understanding of
project limitations
and future
enhancements is
insufficient.
Hardware and/or
Software modules
are functional, if
applicable.
Able to
demonstrate the
project with
achievement of a*t
least 50% required
objectives and
insufficient
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are partially
functional, if
applicable.
Able to
demonstrate the
project with
achievement of
less than 50%
required
objectives and
lacks in
understanding of
project limitations
and future
enhancements.
Hardware and/or
Software modules
are not functional,
if applicable.
Able to achieve all
the desired results
Able to achieve
most of the desired
results with errors
Unable to achieve
the desired results
Project report has no
grammatical and/ or
spelling errors.
All sections of the
report are very wellwritten and
technically accurate.
Project report has
very few
grammatical/
spelling errors.
All sections of the
report are
technically accurate.
Project report has
multiple
grammatical/
spelling errors.
Few sections of the
report contains
technical errors.
Project report has
several
grammatical/
spelling errors and
sentence
construction is
poor.
Able to answer the
questions easily and
correctly across the
project.
Able to answer the
questions related to
the project
Able to answer the
questions but with
mistakes
Unable to answer
the questions
Able to achieve all
the desired results
with alternate ways
to improve
measurements
Score
Obtained
Total Marks
7
SSUET/QR/118
(Form IIIb)
Sir Syed University of Engineering & Technology, Karachi
Computer Engineering Department
Rubric for Lab Exam
Course Name (Course Code),
Semester, Batch
Name of Student:
Criteria
Roll No.
Exceeds
Expectations
(>=90%)
Meets Expectations
(70%-89%)
Developing
(50%-69%)
Unsatisfactory Score
(<50%)
Obtained
Able to present full
knowledge of both
problem and solution.
Able to present
adequate knowledge of
both problem and
solution
Able to present sufficient
knowledge of both
problem and solution
No or very less
knowledge of
both problem
and solution
Able to answer the
questions easily and
correctly across the
project.
Able to answer the
questions related to
the project
Able to answer the
questions but with
mistakes
Unable to
answer the
questions
Performance
Viva
Total Score
Final Lab Assessment
Criteria
Score Obtained
Laboratory Manual
Subject Project (If any)
Lab Exam
Total (50)
Examined by:
(Name and Signature of concerned lab instructor
8
LAB PLAN
Session:
Fall 2020
Course Title:
Digital System Design
Course Code:
CE -304
Credit Hours:
3+1
6th
Semester:
Lab Objectives:
These labs provide the concepts and fundamentals of hardware descriptive language and FPGA.
The objective of the lab is to give working knowledge of Verilog and implementing different
system design on it. This will be accomplished by using Xilinx ISE Design suit. The first section
of labs focuses on different modeling method in Verilog. The final section introduces FPGA kit.
The students will not only learn to implement various system design on Xilinx, but how digital
system design are implemented on FPGA kit.
`
Lab Contents:
Introduction to HDL and Verilog, installation of Xilinx ISE Design suit, implementation and
simulation different basic gates through gate level modeling, half adder and full adder through
gate level and schematics: Introduction to data flow modeling, implement and simulate different
type of adders multiplexers demultiplexers, multiplier, divider through data flow modeling:
introduction to behavioral modeling and finite state machines, implement and simulate mealy
and moore machine concept: introduction to Spartan 3E FPGA Kit.
Learning Outcomes:
At the completion of the course, the student will:
Mapping of CLOs and PLOs
CLO
No.
PLOs
Blooms Taxonomy
4
Implement different types of adders,
subtractor, multiplier, divider and (FSM)
Finite State Machines on Xilinx Software
PLO_5
(Modern Tool Usage)
C3(applying)
5
Follows & implement different types of
adders on Spartan 3E FPGA Kit.
PLO_3
(Design/Development
of Solutions
P3
(Guided Response)
Course Learning Outcomes
9
RELATIONSHIP BETWEEN ASSESSMENT TOOLS AND CLOS:
Assessment
Tools
CLO1(12.5)
60.7% (20)
Final Exam
Lab
Assessment
Lab Project
CLO-2(33)
-
-
CLO3(34.5)
CLO-4(15)
CLO-5(5)
-
-
66.7% (8)
100%(2)
86.95%
(30)
-
33.3%(10)
GRADING POLICY:
Assessment Tools
Percentage
Project
15
Lab File
15
Lab tests
20
TOTAL
50
Administrative Instructions:
•
According to institute policy, 75% attendance is mandatory to appear in the final
examination but 100% will be expected. Approved leaves will not be considered towards
attendance.
•
Every student should bring lab manual in each lab.
•
Every student is expected to be in lab before schedule starting time.
•
In any case there will be no rescheduling and makeup of labs.
Lab Contents
Lab No
Topics
Corresponding
CLO’s
1
to HDL & Verilog. Develop, implement & simulate AND,OR and
NOT gates by using Gate Level Modeling
CLO_4
2
Develop, implement & simulate Full Adder & Half Adder through
CLO_4
10
Schematic Introduction & Gate Level Modeling
3
4
Develop, implement & simulate Floating point multiplication and
division through Data Flow Modeling.
Develop, implement & simulate 4-bits Ripple Carry Adder & 4bits Subtractor
CLO_4
CLO_4
Develop, implement & simulate 2x2 multiplier and 4x4 multiplier
5
CLO_4
Develop, implement & simulate 8x8 Dadda Wallace Tree
6
CLO_4
Open Ended Lab
7
ClO_4
8
Develop, implement & simulate Sequence Detector by using Finite State
Machine – Moore Machine
CLO_4
9
Develop, implement & simulate Vending Machine by using Finite State
Machine – Mealy Machine
CLO_4
Reproduce and implement basic gates by using FPGA Kit.
10
CLO_5
Reproduce and implement Half Adder by using FPGA Kit.
CLO_5
11
Reproduce and implement Full Adder by using FPGA Kit.
12
13
14
CLO_5
Reproduce and implement Ripple Carry Adder by using FPGA Kit.
CLO_5
Open Ended Lab
CLO_4
11
LAB #1
Introduction to Verilog Language, Gate Level Modelling and Example.
Modules
Module Declaration
A module is the principal design entity in Verilog. The first line of a module declaration
specifies the name and port list (arguments). The next few lines specifies the i/o type (input,
output or inout, ) and width of each port. The default port width is 1 bit.
Then the port variables must be declared wire, wand, . . ., reg . The default is wire. Typically
inputs are wire since their data is latched outside the module. Outputs are type reg if their signals
were stored inside an always or initial block.
Syntax
module module_name (port_list);
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
... statements ...
endmodule
Example
module add_sub(add, in1, in2, oot);
input add; // defaults to wire input
[7:0] in1, in2; wire in1, in2; output
[7:0] oot; reg oot;
... statements ...
endmodule
add
in1
oot
8
add_sub
in28
8
Module Instantiations
Module declarations are templates from which one creates actual objects (instantiations).
Modules are instantiated
Syntax for Instantiation
Example
inside other modules, and each
module_name
instance_name_1 (port_connection_list), // MODULE DEFINITION
instantiation creates a unique
instance_name_2 (port_connection_list),
object from the template. The
......
module and4(a, b, c);
exception is the top-level module
instance_name_n (port_connection_list);
input [3:0] a, b;
which is its own instantiation.
output [3:0] c;
assign c = a & b;
The instantiated module’s ports
endmodule
must be matched to those defined
in the template. This is specified:
(i) by name, using a dot(.) “
.template_port_name (name_of_wire_connected_to_port)”.
(ii) by position, placing the ports in exactly the same positions in the port lists of both the
template and the instance.
12
// MODULE INSTANTIATIONS
wire [3:0] in1, in2;
wire [3:0] o1, o2;
/* C1 is an instance of module and4 C1 ports referenced by
position */ and4 C1 (in1, in2, o1);
/* C2 is another instance of and4. C2 ports are referenced to
the declaration by name. */
and4 C2 (.c(o2), .a(in1), .b(in2));
Parameterized Modules
You can build modules that are parameterized and specify the value of the parameter at each
instantiation of the module.. Primitive gates have parameters which have been predefined as
delays.
Syntax
module_name #(1st_parameter_values,
2nd_parm_value, ...)
instance_name(port_connection_list);
Example
// MODULE DEFINITION
module shift_n (it, ot);
// used in module test_shift.
input [7:0] it; output [7:0] ot;
parameter n = 2;‘
// default value of n is 2
assign ot = (it << n);
// it shifted left n times
endmodule
// PARAMETERIZED INSTANTIATIONS
wire [7:0] in1, ot1, ot2, ot3;
shift_n
shft2(in1, ot1),
// shift by 2; default
shift_n #(3) shft3(in1, ot2); // shift by 3; override parameter 2.
shift_n #(5) shft5(in1, ot3); // shift by 5; override parameter 2.
Synthesis does not support the defparam keyword which is an alternate way of changing
parameters. Here the instance name is associated with a parameter in a defparam statement.
Syntax
defparm instance_name.parameter
= parameter_value;
module_name instance_name
(port_connection_list);
// PARAMETERIZED INSTANTIATIONS
wire [7:0] in1, ot1, ot2, ot3;
defparm shft3.n=3, shift5.n=5;
// shift by 2; default
shift_n shft2(in1, ot1),
shift_n shft3(in1, ot2); // shift by 3; override parameter 2.
shift_n shft5(in1, ot3); // shift by 5; override parameter 2.
13
Lexical Tokens
Verilog source text files consists of the following lexical tokens:
White Space
White spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a
statement can extend over multiple lines without special continuation characters.
Comments
Comments can be specified in two ways (exactly the same way as in C/C++):
Begin the comment with double slashes (//). All text between these characters and the
end of the line will be ignored by the Verilog compiler.
Enclose comments between the characters /* and */. Using this method allows you to
continue comments on more than one line. This is good for “commenting out” many lines code,
or for very brief in-line comments.
Example
a = c + d;
// this is a simple comment
/* however, this comment continues on more
than one line */
assign y = temp_reg;
assign x=ABC /* plus its compliment*/ + ABC_
Numbers
Number storage is defined as a number of bits, but values can be specified in binary, octal,
decimal or hexadecimal
Examples are 3’b001, a 3-bit number, 5’d30, (=5’b11110), and 16‘h5ED4, (=16’d24276)
Identifiers
Identifiers are user-defined words for variables, function names, module names, block names
and instance names. Identifiers begin with a letter or underscore (Not with a number or $) and
can include any number of letters, digits and underscores. Identifiers in Verilog are casesensitive.
Operators
Operators are one, two and sometimes three characters used to perform operations on variables.
Examples include >, +, ~, &, !=.
14
Verilog Keywords
These are words that have special meaning in Verilog. Some examples are assign, case, while,
wire, reg, and, or, nand, and module. They should not be used as identifiers.
Gate-Level Modelling
Primitive logic gates are part of the Verilog language. Two properties can be specified,
drive_strength and delay.
Drive_strength specifies the strength at the gate outputs. The strongest output is a direct
connection to a source, next comes a connection through a conducting transistor, then a resistive
pull-up/down.
Delays: If no delay is specified, then the gate has no propagation delay; if two delays are
specified, the first represent the rise delay, the second the fall delay; if only one delay is
specified, then rise and fall are equal. Delays are ignored in synthesis. The parameters for the
primitive gates have been predefined as delays.
Basic Gates
These implement the basic logic gates. They have one output and one or more inputs. In the gate
instantiation syntax shown below, GATE stands for one of the keywords and, nand, or, nor, xor,
xnor.
Syntax
GATE (drive_strength) # (delays)
instance_name1(output, input_1,
input_2,..., input_N),
instance_name2(outp,in1, in2,..., inN);
Delays is
#(rise, fall) or
# rise_and_fall or
#(rise_and_fall)
Example
and c1 (o, a, b, c, d); // 4-input AND called c1 and
c2 (p, f g);
// a 2-input AND called c2.
or #(4, 3) ig (o, a, b); /* or gate called ig (instance name);
rise time = 4, fall time = 3 */
xor #(5) xor1 (a, b, c); // a = b XOR c after 5 time units
xor (pull1, strong0) #5 (a,b,c); /* Identical gate with pull-up
strength pull1 and pull-down strength strong0. */
15
Data Types
Value Set
Verilog consists of only four basic values. Almost all Verilog data types store all these values:
(logic zero, or false condition)
(logic one, or true condition)
x (unknown logic value)
x and z have limited use for synthesis.
(high impedance state)
Wire
A wire represents a physical wire in a circuit and is used to connect gates or modules. The value
of a wire can be read, but not assigned to, in a function or block. A wire does not store its value
but must be driven by a continuous assignment statement or by connecting it to the output of a
gate or module. Other specific types of wires include:
wand (wired-AND);:the value of a wand depend on logical AND of all the drivers connected to
it.
wor (wired-OR);: the value of a wor depend on logical OR of all the drivers connected to it.
tri (three-state;): all drivers connected to a tri must be z, except one (which determines the
value of the tri).
Syntax
wire [msb:lsb] wire_variable_list;
wand [msb:lsb] wand_variable_list;
wor [msb:lsb] wor_variable_list; tri
[msb:lsb] tri_variable_list;
Reg
Declare type reg for all data objects on the left hand side of expressions in initial and always
procedures, or functions. A reg is the data type that must be used for latches, flip-flops and
memories. However it often synthesizes into leads rather than storage. In multi-bit registers, data
is stored as unsigned numbers and no sign extension is done for what the user might have
thought were two’s complement numbers.
Input, Output, Inout
These keywords declare input, output and bidirectional ports of a module or task. Input and
inout ports are of type wire. An output port can be configured to be of type wire, reg, wand,
wor or tri. The default is wire.
16
Syntax
input [msb:lsb] input_port_list; output [msb:lsb] output_port_list; inout [msb:lsb] inout_port_list;
Example
module sample(b, e, c, a);
input a;
// An input which defaults to wire.
output b, e;
// Two outputs which default to wire
output [1:0] c; /* A two-it output. One must declare its
type in a separate statement. */
reg [1:0] c;
// The above c port is declared as reg.
Integer
Integers are general-purpose variables. For synthesis they are used mainly loops-indices,
parameters, and constants. They are of implicitly of type reg. However they store data as signed
numbers whereas explicitly declared reg types store them as unsigned. If they hold numbers
which are not defined at compile time, their size will default to 32-bits. If they hold constants,
the synthesizer adjusts them to the minimum width needed at compilation.
Syntax
integer integer_variable_list;
... integer_constant ... ;
Example
integer a;
assign b=63;
// single 32-bit integer
// 63 defaults to a 7-bit variable.
Parameter
Parameters allows constants like word length to be defined symbolically in one place. This
makes it easy to change the word length later, by change only the parameter.
Syntax
parameter par_1 = value,
par_2 = value, ..... ;
parameter [range] parm_3 = value
Example
parameter add = 2’b00, sub = 3’b111;
parameter n = 4;
parameter [3:0] st4 = 4’b1010;
...
reg [n-1:0] harry; /* A 4-bit register whose length is
set by parameter n above. */
always @(x)
y = {{(add - sub){x}}; // The replication operator Sect. 5.8.
if (x) begin
state = st4[1]; else state = st4[2];
end
17
Operators
Arithmetic Operators
These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y)
operators.
Operators
+ (addition)
(subtraction)
* (multiplication)
/ (division)
% (modulus)
Example
parameter n = 4;
reg[3:0] a, c, f, g, count;
f = a + c;
g = c - n;
count = (count +1)%16;
//Can count 0 thru 15.
Relational Operators
Relational operators compare two operands and return a single bit 1or 0. These operators
synthesize into comparators.
Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However
for integers -1< 6.
Operators
<
<=
>
>=
==
!=
(less than)
(less than or equal to)
(greater than)
(greater than or equal to)
(equal to)
(not equal to)
Equivalent Statement
Example
if (x = = y) e = 1;
e = 0;
else
e = (x == y);
// Compare in 2’s compliment; a>b
reg [3:0] a,b;
if (a[3]= = b[3]) a[2:0] > b[2:0];
else
b[3];
Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands.
Operators
~
(bitwise NOT)
& (bitwise AND)
|
(bitwise OR)
^
(bitwise XOR) ~^
or ^~(bitwise XNOR)
Example
a
a(0
b(0)
module and2 (a, b, c);
input [1:0] a, b;
output [1:0] c;
assign c = a & b;
endmodule
c(0
2
a(1)
b
b(1)
c(1)
2
18
Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for
single bit operands. They can work on expressions, integers or groups of bits, and treat all values
that are nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements
since they work with expressions.
Operators
!
(logical NOT)
&& (logical AND)
|| (logical OR)
Example
wire[7:0] x, y, z;
// x, y and z are multibit variables.
reg a;
...
if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero.
else a = !x;
// a =0 if x is anything but ze
19
Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a single-bit value.
These are the unary (one argument) form of the bit-wise operators above.
Operators
&
(reduction AND)
|
(reduction OR)
~& (reduction NAND)
~|
(reduction NOR)
^
(reduction XOR) ~^
or ^~(reduction XNOR)
Example
module chk_zero (a, z);
a
input [2:0] a;
output z;
3
assign z = ~| a; // Reduction
NOR endmodule
a(0)
a(1)
z
a(2)
Shift Operators
Shift operators shift the first operand by the number of bits specified by the second operand.
Vacated positions are filled with zeros for both left and right shifts (There is no sign
extension).
Operators
<< (shift left)
>> (shift right)
Example
assign c = a << 2;
/* c = a shifted left 2 bits;
vacant positions are filled with 0’s */
Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector.
Operators
{ }(concatenation)
Example
wire [1:0] a, b; wire [2:0] x;
wire [3;0] y, Z;
assign x = {1’b0, a}; // x[2]=0, x[1]=a[1], x[0]=a[0]
assign y = {a, b}; /* y[3]=a[1], y[2]=a[0], y[1]=b[1],
y[0]=b[0] */
assign {cout, y} = x + Z; // Concatenation of a result
20
Conditional Operator: “?”
Conditional operator is like those in C/C++. They evaluate one of the two expressions based
on a condition. It will synthesize to a multiplexer (MUX).
Operators
Example
assign a = (g) ? x : y;
(cond) ? (result if cond true):
(result if cond false)
assign a = (inc = = 2) ? a+1 : a-1;
/* if (inc), a = a+1, else a = a-1 */
Operator Precedence
Table shows the precedence of operators from highest to lowest. Operators on the same level
evaluate from left to right. It is strongly recommended to use parentheses to define order of
precedence and improve the readability of your code.
Operator
Name
[ ]
bit-select or part-select
( )
Parenthesis
!, ~
logical and bit-wise NOT
&, |, ~&, ~|, ^, ~^, ^~
reduction AND, OR, NAND, NOR, XOR, XNOR;
If X=3’B101 and Y=3’B110, then X&Y=3’B100, X^Y=3’B011;
+, -
unary (sign) plus, minus; +17, -7
{ }
concatenation; {3’B101, 3’B110} = 6’B101110;
{{ }}
replication; {3{3'B110}} = 9'B110110110
*, /, %
multiply, divide, modulus; / and % not be supported for synthesis
+, -
binary add, subtract.
<<,
>>
shift left, shift right; X<<2 is multiply by 4
<, <=, >, >=
comparisons. Reg and wire variables are taken as positive numbers.
= =, !=
logical equality, logical inequality
= = =, != =
case equality, case inequality; not synthesizable
&
bit-wise AND; AND together all the bits in a word
^, ~^, ^~
bit-wise XOR, bit-wise XNOR
|
bit-wise OR; AND together all the bits in a word
&&,
logical AND. Treat all variables as False (zero) or True (nonzero).
logical OR. (7||0) is (T||F) = 1, (2||-3) is (T||T) =1,
||
(3&&0) is (T&&F) = 0.
?:
conditional. x=(cond)? T : F;
Verilog Operators Precedence
21
Operands
Literals
Literals are constant-valued operands that can be used in Verilog expressions. The two common
Verilog literals are:
(a)String: A string literal is a one-dimensional array of characters enclosed in double quotes(“
“).
(b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.
Number Syntax
n’Fddd..., where
n - integer representing number of bits
F - one of four possible base formats:
b (binary), o (octal), d (decimal),
h (hexadecimal). Default is d.
dddd - legal digits for the base format
Example
“time is”// string literal
267 // 32-bit decimal number
2’b01 // 2-bit binary
20’hB36F// 20-bit hexadecimal number
‘o62 // 32-bit octal number
Wires, Regs, and Parameters
Wires, regs and parameters can also be used as operands in Verilog expressions.
Bit-Selects “x[3]” and Part-Selects “x[5:3]”
Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively, from a
wire, reg or parame-ter vector using square brackets “[ ]”. Bit-selects and part-selects can be
used as operands in expressions in much the same way that their parent data objects are used.
Syntax
variable_name[index]
variable_name[msb:lsb]
Example
reg [7:0] a, b;
reg [3:0] ls;
reg c;
c = a[7] & b[7];
// bit-selects
ls = a[7:4] + b[3:0]; // part-selects
22
Function Calls
The return value of a function can be used directly in an expression without first assigning it to a
register or wire var-iable. Simply place the function call as one of the operands. Make sure you
know the bit width of the return value of the function call.
Syntax
function_name (argument_list)
Example
assign a = b & c & chk_bc(c, b);// chk_bc is a function
. . ./* Definition of the function */
function chk_bc;// function definition
input c,b;
chk_bc = b^c;
endfunction
23
Lab Task 1:
Develop and implement different logic gates (AND, OR, NOT, XOR) using Gate Level
Modeling in Verilog.
Object:
1. To Develop, Implement and Simulate AND gate using Verilog Gate Level Modelling.
2. To Develop, Implement and Simulate OR gate using Verilog Gate Level Modelling.
3. To Develop, Implement and Simulate XOR gate using Verilog Gate Level Modelling.
Theory
1. AND Gate:
The AND gate is a basic digital logic gate that implements logical conjunction - it behaves
according to the truth table to the right. A HIGH output (1) results only if all the inputs to
the AND gate are HIGH (1). If none or not all inputs to the AND gate is HIGH, a LOW output
results.
Input A
Input B
Input C
0
0
0
0
1
0
1
0
0
1
1
1
Equations:
A.B=Z
Or
AB=Z
Block Diagram:
24
2. OR Gate
The OR gate is a digital logic gate that implements logical disjunction – it behaves according
to the truth table to the right. A HIGH output (1) results if one or both the inputs to
the gate are HIGH (1). If neither input is high, a LOW output (0) results.
Input A
Input B
Input C
0
0
0
0
1
1
1
0
1
1
1
1
Equation:
A+B=C
Block Diagram:
3. XOR Gate
The XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital
logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An XOR
gate implements an exclusive or; that is, a true output results if one, and only one, of the inputs
to the gate is true
Input A
Input B
Input C
0
0
0
0
1
1
1
0
1
1
1
0
25
Equations:
A⊕B=C
Where,
A ⊕ B = AB’ + A’B
Block Diagram:
Steps Of Performance:
1. Entering the Design
Figure #1
26
Select either File New Project or click on the New Project tab. The New Project Wizard
dialog box will appear. Specify the directory in which you want to store the project in and name
the project In the Top-Level Source Type section select Schematic and click Next. Another
New Project Wizard dialog box will appear prompting you for device, synthesis and simulation
settings for the project.
Figure #2
In this dialog box verify the following settings:
• Family = Spartan3E.
• Device =XC35100E.
• Package = VQ100.
• Speed Grade = -4.
• Synthesis Tool = XST (VHDL/Verilog).
• Simulator=ISim (VHDL/Verilog).
• Generated Simulation Language = VHDL.
If the information is correct click Next.
27
Figure #3
The following window will appear which is about the Project Summary. Now click
Finish.
28
Figure #4
We will enter a design using a structural or RTL description using the Verilog HDL. You can
create a Verilog HDL input file (.v file) using the HDL Editor available in the Xilinx ISE Tools
(or any text editor).
Click New Source in the New Project Wizard to add to one new source to your project. Type in
the file name counter. Select VHDL Module as the source type in the New Source Dialog box.
Verify that the Add to Project checkbox is selected. Click Next.
29
Figure #5
You will be asked for the module’s port names/types. While you can use this dialog to create the
port names, we will manually add them later within the Verilog file itself. You can skip this step
and click on the Next button.
30
Figure #6
31
The following window will appear which is about the Summary. Once you click on
Finish, the source file will be displayed in the sources window in the Project Navigator
Figure #7a (for XOR gate)
Figure #7b (for OR gate)
Figure #7c (for AND gate)
32
The Verilog source code template generated shows the module name, the list of ports and also
the declarations (input/output) for each port. Combinational logic code can be added to the
verilog code after the declarations and before the endmodule line.
To implement the design, double click the Implement design option in the Processes window.
If everything is done successfully, a tick mark will be placed before the Implement Design
option.
Figure #8a
Figure #8b
33
Figure #8c
The schematic diagram of the synthesized verilog code can be viewed by double clicking View
RTL Schematic under Synthesize-XST menu in the Process Window.
2. Simulating the Circuit
We can now proceed to a simulation of the circuit designed. This can be done by creating
a new source file called a text fixture file.
34
Figure #9
In the Sources window (top left corner) right click on the file that you want to generate the test
bench for and select ‘New Source’ ,Provide a name for the test bench in the file name text box
and select ‘Verilog test fixture’ among the file types in the list on the right side as shown in
figure 9.
35
Figure #10
This window is about associating a module to a test bench. Click on Next to proceed.
36
Figure #11
The following window will appear which is about the Summary. Now click Finish.
37
Figure #12
The Xinlinx tool detects the input and output of the module that you are going to test and
assigns them the initial values. In order to test the gate completely we shall provide all the
different input combinations. #100 is the time delay for which the input has to maintain the
current value. After 100 unit of times have elapsed the next set of values can be assign to the
inputs
38
Figure #13a (AND gate)
Figure #13b (OR gate)
Figure #13c (XOR gate)
Now we can run the simulation. double click on simulate behavioral model. This brings up the
simulation window as shown in the figure.
39
LAB #2
Lab Task #1 :
Object:
Develop, implement & simulate Half Adder through Schematic & Gate Level Modeling.
Theory:
Half Adder
A half adder is a type of adder, an electronic circuit that performs the addition of numbers. The
half adder is able to add two single binary digits and provide the output plus a carry value. It has
two inputs, called A and B, and two outputs S (sum) and C (carry). The common representation
uses a XOR logic gate and an AND logic gate.
Input A
Input B
Sum
Carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Equations:
S= A ⊕ B
C=A.B
Block Diagram:
40
Steps Of Performance:
1. Entering the Design
Figure #1
Select either File New Project or click on the New Project tab. The New Project Wizard
dialog box will appear. Specify the directory in which you want to store the project in and name
the project In the Top-Level Source Type section select Schematic and click Next. Another
New Project Wizard dialog box will appear prompting you for device, synthesis and simulation
settings for the project.
41
Figure #2
In this dialog box verify the following settings:
• Family = Spartan3E.
• Device =XC35100E.
• Package = VQ100.
• Speed Grade = -4.
• Synthesis Tool = XST (VHDL/Verilog).
• Simulator=ISim (VHDL/Verilog).
• Generated Simulation Language = VHDL.
If the information is correct click Next.
42
Figure #3
The above window will appear which is about the Project Summary. Now click Finish.
43
Figure #4
Click on the New Source button. In the new dialog box that appears, select Schematic from the
list of file types and enter the file name. The default location is the current project directory and
can be left as it is. Ensure the Add to Project box is selected and click the Next button.
44
Figure #5
Verify the information in the next dialog box and click Finish.
45
Figure #6
We are now ready to start working with the schematic editor. The Schematic Editor window
will have appeared within the project navigator interface at the completion of the last step in the
previous section.
We will now insert logic gates into our schematic. Select the Symbols tab in the Options toolbar
and a list of symbol categories will appear on the left hand side of the Project Navigator
window. Select Logic from this list and a list of simple logic gates will be shown in the lower
Symbols scroll box.
Schematic Diagram:
Figure #7
46
For the half adder, we will require a 2 input XOR gate and a 2 input AND gate. To add a simple
logic gate to the circuit, left-click to select a symbol from the Symbols list, drag the cursor to the
pallet wherever you want the symbol to be placed, and left-click again to drop the gate in the
schematic. You can also find a symbol by typing a name into the symbol name filter.
Figure #8(a,b,c,d)
Go back to regular cursor mode (Select Mode Icon) and double left-click on an I/O marker.
When the I/O marker’s object properties dialog box appears, select the Nets category and enter a
meaningful value for the Name field of the I/O marker. The finished dialog box should look
similar to the above pictures
Press Apply and then OK.
Repeat this process for all IO (i.e., Enter “a,b” as inputs and “Sum” and “Carry” as outputs). The
finished circuit should look similar as shown in the next picture.
2. Simulating the Circuit:
We can now proceed to a simulation of the circuit designed. This can be done by creating
a new source file called a text fixture file.
47
Figure #9
In the Sources window (top left corner) right click on the file that you want to generate the test
bench for and select ‘New Source’ ,Provide a name for the test bench in the file name text box
and select ‘Verilog test fixture’ among the file types in the list on the right side as shown in
figure 9.
48
Figure #10
The following window will appear which is about the Summary. Now click Finish.
49
Verilog Test Fixture
Figure #11
The Xilinx tool detects the input and output of the module that you are going to test and
assigns them the initial values. In order to test the gate completely we shall provide all
the different input combinations. #100 is the time delay for which the input has to
maintain the current value. After 100 unit of times have elapsed the next set of values can
be assign to the inputs.
50
Verilog Module Code
Figure #12
Now we can run the simulation. Double click on simulate behavioral model. This brings up the
simulation window as shown in the figure.
51
Lab Task #2:
Object:
Develop, implement & simulate Full Adder using schematic & Gate Level Modeling.
Theory:
Full Adder
A full adder is a digital circuit that performs addition. Full adders are implemented with logic
gates in hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit.
The adder outputs two numbers, a sum and a carry bit. The term is contrasted with a half adder,
which adds two binary digits.
Input A
Input B
Cin
Sum
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Equations:
S = A ⊕ B ⊕ Cin
Cout = AB + Cin (A ⊕ B)
52
Block Diagram:
Schematic Diagram:
53
Verilog Module Code:
54
Verilog Test Fixture:
55
Waveform:
56
LAB#3
To design, implement & simulate Flouting point multiplication and division through Data Flow
Modeling.
Representation of Floating-Point Numbers:
Single-precision numbers are stored in 32 bits: 1 for the sign, 8 for the exponent, and 23 for the
fraction. The exponent is a signed number represented using the bias method with a bias of 127.
The term biased exponent refers to the unsigned number contained in bits 1 through 8 and
unbiased exponent (or just exponent) means the actual power to which 2 is to be raised. The
fraction represents a number less than 1, but the significand of the floating-point number is 1
plus the fraction part. In other words, if e is the biased exponent (value of the exponent field) and
f is the value of the fraction field, the number being represented is
The primary reason why the IEEE standard, like most other floating-point formats, uses biased
exponents is that it means nonnegative numbers are ordered in the same way as integers. That is,
the magnitude of floating-point numbers can be compared using an integer comparator. Another
(related) advantage is that 0 is represented by a word of all 0’s. The downside of biased
exponents is that adding them is slightly awkward, because it requires that the bias be subtracted
from their sum
Floating-Point Multiplication:
The simplest floating-point operation is multiplication, so we discuss it first. A binary floatingpoint number x is represented as a significand and an exponent,
x = s* 2e.
57
The formula
(s1 *2e1) • (s2 *2e2) = (s1 • s2) *2e1+e2
Shows that a floating-point multiply algorithm has several parts. The first part multiplies the
significands using ordinary integer multiplication. Because floating point numbers are stored in
sign magnitude form, the multiplier need only deal with unsigned numbers (although we have
seen that Booth recoding handles signed two’s complement numbers painlessly). The second part
rounds the result. If the significands are unsigned p-bit numbers (e.g., p = 24 for single
precision), then the product can have as many as 2p bits and must be rounded to a p-bit number.
The third part computes the new exponent. Because exponents are stored with a bias, this
involves subtracting the bias from the sum of the biased exponents
Rules of floating point multiplication
S0: Add the two exponents e1 and e2 and subtract the bias once
S1: Multiply the mantissas as unsigned numbers to get the product, and XOR the two sign bits to
get the sign of the product
S2: Normalize the product if required
S3: Round or truncate the mantissa
58
Verilog module code:
59
RTL Schemetic:
60
Verilog Test Fixture:
Wave:
61
Floating-Point DIVISION:
Floating-point division is an important operation in scientific computing and multimedia
applications. This paper presents and compares two division algorithms for an times86
microprocessor, which utilizes a rectangular multiplier that is optimized for multimedia
applications. The proposed division algorithms are based on Goldschmidt's division algorithm
and provide correctly rounded results for IEEE 754 single, double, and extended precision
floating-point numbers.
It is similar to multiplication.
To do the unsigned division on the mantissas (don’t forget the hidden bit)
subtract TRUE exponents
The organization of a floating point adder unit and the algorithm is given below
Rules for division




Check for zero
Subtract the exponent and add 127
Divide the mantissas and determine the sign of the result
Normalize the resulting value, if necessary
Verilog module code
62
Verilog Test Fixture File:
63
Wave:
64
LAB #4
Lab Task 1:
Develop, implement and simulate a 4-bit ripple carry adder using 4 full adders.
THEORY
4 BIT RIPPLE CARRY ADDER
Arithmetic operations like addition, subtraction, multiplication, division are basic operations to
be implemented in digital computers using basic gates like AND, OR, NOR, NAND etc. Among
all the arithmetic operations if we can implement addition then it is easy to perform
multiplication (by repeated addition), subtraction (by negating one operand) or division (repeated
subtraction).
Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical
circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a Cin,
which is the Cout of the previous adder. This kind of adder is a Ripple Carry Adder, since each
carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced
by a half adder. The block diagram of 4-bit Ripple Carry Adder is shown here below -
Circuit Diagram
DESIGN ISSUES:
The corresponding boolean expressions are given here to construct a ripple carry adder. In the
half adder circuit the sum and carry bits are defined as
sum = A ⊕ B
65
carry = AB
Verilog Module Code:
Verilog Test Fixture Code:
66
Waveform:
67
Lab Task 2:
Develop, implement and simulate a 4 bit subtractor using 4 full adders.
THEORY
4 BIT SUBTRACTOR
By using full–adder, binary subtraction can be performed by following the standard rule from
arithmetic: A – B = A + (–B). We just need to negate one of the inputs to the full–adder and
we have a subtractor. How do we do that?
All modern Arithmetic Logic Units implement integer arithmetic using the two’s–complement
form. Thus we need to build a two’s–complement negator. As an aside, we note that it is
possible to build an adder/subtractor for other formats, but that these designs are quite complex.
It is the simplicity of the standard two’s–complement unit that lead to its being the standard.
Remember the rule for negating an integer in two’s–complement arithmetic: take the one’s–
complement and add one. As an expression, this is as follows:
In order to get the negative of the number, all we need to do is add 1 to it. Of the several ways
this could be done, the best way is to set the carry–in of the units full–adder to 1.
Circuit Diagram
Consider the case when A#/S = 0. This indicates that addition is to take place. This signal
is fed into the exclusive OR gates feeding the right inputs of the adders, passing the plain form
of the B input. This feeds the units carry–in; the result is A + B + 0, or just A + B.
Now consider the case when A#/S = 1. This indicates that subtraction is to take place. This
is fed into the exclusive OR gates, passing the one’s complement of B into the right inputs of
the adder. The signal feeds the units carry–in, thus the result we get is
.
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Verilog Module Code:
Verilog Test Fixture Code:
Waveform:
69
Lab Task 3:
To develop, implement and simulate an Open-Ended Lab. Some of the sample question are given
below:
Sample Questions





To design 8-bits Ripple Carry Adder
To design 16-bits Ripple Carry Adder
To design Half Adder using NOR gate
To design Half Adder using NAND gate
To design Full Adder using Half Adder
70
LAB 5
Lab Task 1:
Develop, implement and simulate a 2x2 Multiplier
THEORY
MULTIPLIER
Multiplication involves the use of addition in some way to produce a product p from a
multiplicand x and multiplier y such that:
p=x·y
High speed multipliers are typically classified into two categories. The first, known as parallel
multiplication, involves the use of hardware to multiply am-bit number by a n-bit number to
completely produce a n+m product. Parallel multipliers can also be pipelined to reduce the cycle
time and increase the throughput by introducing storage elements within the multiplier. On the
other hand, serial or sequential multipliers compute the product sequentially usually utilizing
storage elements so that hardware of the multiplier is reused during iteration.
DESIGN ISSUES:
P0 = a0b0
P1 = a1b0 + a0b1
P2 = a1b1 + c1
P3 = c2
71
Verilog Module Code:
Verilog Test Fixture Code
72
Waveform:
Lab Task 2:
Design a 4x4 Multiplier.
73
LAB #6
LAB OBJECTIVE:
To Develop, Implement and Simulate 8x8 Dadda Wallance Tree.
THEORY:
Dadda wallance Tree is used to perform multiplication. It performs multiplication much faster
than any other technique. The two well-known fast multipliers are those presented by Wallace
and Dadda. Both consist of three stages. In the first stage, the partial product matrix is formed. In
the second stage, this partial product matrix is reduced to a height of two. In the final stage, these
two rows are combined using a carry propagating adder. In the Wallace method, the partial
products are reduced as soon as possible. In contrast, Dadda's method does the minimum
reduction necessary at each level to perform the reduction in the same number of levels as
required by a Wallace multiplier. It is generally assumed that, for a given size, the Wallace
multiplier and the Dadda multiplier exhibit similar delay. This is because each uses the same
number of pseudo adder levels to perform the partial product reduction. Although the Wallace
multiplier uses a slightly smaller carry propagating adder, usually this provides no significant
speed advantage. A closer examination of the delays within these two multipliers reveals this
assumption to be incorrect.
Developing 8x8 Dadda Wallace Tree takes 8 bit values as input and generates 16 bit output.
74
Sourse code:
75
76
Simulating the Design
Now we have to create the test fixture module to check the working of Dadda Wallance Tree.
Timing Diagram:
77
Laboratory Exercise 07
Open-Ended Lab
Title:
1. Objective:
2. Hardware/Software Required
3. Diagram
4. Methodology
5. Observation Table
6. Results
7. Conclusion
78
LAB#8
Develop, implement and Simulate Moore Machine using behavioral modeling
Finite State Machine
A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), finite automaton,
or simply a state machine, is a mathematical model of computation. It is an abstract machine that
can be in exactly one of a finite number of states at any given time. The FSM can change from
one state to another in response to some external inputs; the change from one state to another is
called a transition. An FSM is defined by a list of its states, its initial state, and the conditions for
each transition.
Moore’s Machine:
Moore machine is an FSM whose outputs depend on only the present state.
A Moore machine can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −
 Q is a finite set of states.
 ∑ is a finite set of symbols called the input alphabet.
 O is a finite set of symbols called the output alphabet.
 δ is the input transition function where δ: Q × ∑ → Q
 X is the output transition function where X: Q → O
 q0 is the initial state from where any input is processed (q0 ∈ Q).
State Diagram And State Table of MOORE Machine:
Next State
Present
state
Output
Input
=0
Input
=1
a
b
c
x2
b
b
d
x1
c
c
d
x2
d
d
d
x3
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Lab task:
To develop a sequence detector using Moore FSM
1011
input=00010101100011
output=000000001000
Verilog Code:
module Sequence_Detector_MOORE_Verilog(sequence_in,clock,reset,detector_out
);
input clock;
input reset;
input sequence_in;
outputreg detector_out;
parameter
Zero=3'b000,
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One=3'b001,
OneZero=3'b011,
OneZeroOne=3'b010,
OneZeroOneOne=3'b110;
reg [2:0] current_state, next_state;
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <= Zero;
else
current_state <= next_state; end
always @(current_state,sequence_in)
begin
case(current_state)
Zero:begin
if(sequence_in==1)
next_state <= One;
else
next_state <= Zero;
end
One:begin
if(sequence_in==0)
next_state <= OneZero;
else
next_state <= One;
end
OneZero:begin
if(sequence_in==0)
next_state <= Zero;
else
next_state <= OneZeroOne;
end
OneZeroOne:begin
if(sequence_in==0)
next_state <= OneZero;
else
next_state <= OneZeroOneOne;
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end
OneZeroOneOne:begin
if(sequence_in==0)
next_state <= OneZero;
else
next_state <= One;
end
default:next_state <= Zero;
endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin
case(current_state)
Zero:
One:
detector_out <=0;
detector_out <=0;
OneZero:
detector_out <=0;
OneZeroOne:
detector_out <=0;
OneZeroOneOne:
default:
detector_out <=1;
detector_out <=0;
endcase
end
endmodule
Verilog Test Fixture for the Moore FSM Sequence Detector:
module tb_Sequence_Detector_Moore_FSM_Verilog;
// Inputs
reg sequence_in;
reg clock;
reg reset;
// Outputs
wire detector_out;
// Instantiate the Sequence Detector using Moore FSM
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Sequence_Detector_MOORE_Verilog uut (
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out)
);
initialbegin
clock =0;
forever #5 clock =~clock;
end
initialbegin
// Initialize Inputs
sequence_in =0;
reset =1;
// Wait 100 ns for global reset to finish
#30;
reset =0;
#40;
sequence_in =1;
#10;
sequence_in =0;
#10;
sequence_in =1;
#20;
sequence_in =0;
#20;
sequence_in =1;
#20;
sequence_in =0;
// Add stimulus here
end
endmodule
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Wave form
84
Lab #9
Mealy Machine:
A Mealy Machine is an FSM whose output depends on the present state as well as the present
input.
It can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −
 Q is a finite set of states.
 ∑ is a finite set of symbols called the input alphabet.
 O is a finite set of symbols called the output alphabet.
 δ is the input transition function where δ: Q × ∑ → Q
 X is the output transition function where X: Q × ∑ → O
 q0 is the initial state from where any input is processed (q0 ∈ Q).
State Diagram And State Table of Mealy Machine:
Next state
Present
state
input = 0
input = 1
State
Output
State
Output
→a
b
x1
c
x1
b
b
x2
d
x3
c
d
x3
c
x1
d
d
x3
d
x2
Lab Task:
To design, implement and simulate vending machine using mealy machine concept
Verilog CODE:
module Mealy(open,clk,reset,n,d);
output open;
inputclk,reset,n,d;
reg open;
reg [1:0] state;
reg [1:0] nextstate;
regnextopen;
parameter zero=0,five=1,ten=2;
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parameter fifteen=3;
always@(n or d or state)
case(state)
zero:begin
if(n)begin
nextstate=five;nextopen=0;
end
else if(d)begin
nextstate=ten;nextopen=0;
end
else begin
nextstate=zero;nextopen=0;
end
end
five:begin
if(n)begin
nextstate=ten;nextopen=0;
end
else if(d)begin
nextstate=fifteen;nextopen=1;
end
else begin
nextstate=five;nextopen=0;
end
end
ten:begin
if(n)begin
nextstate=fifteen;nextopen=1;
end
else if(d)begin
nextstate=fifteen;nextopen=1;
end
else begin
nextstate=ten;nextopen=0;
end
end
fifteen:begin
if(!reset) nextstate=fifteen;
elsenextstate=zero;
nextopen=1;
end
endcase
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always@(posedgeclk)
if(reset ||(!n && !d))begin state<=zero;open<=0;end
else begin state<=nextstate;open<=nextopen;end
endmodule
TextFixtureCODE:
moduleMealy_tf;
// Inputs
regclk;
regreset;regn;reg d;
// Outputs
wire open;
// Instantiate the Unit Under Test (UUT)
Mealy uut (
.open(open),
.clk(clk),
.reset(reset),
.n(n),
.d(d));
parameter PERIOD=100;
always begin
clk=1;
#(PERIOD/2)
clk=0;
#(PERIOD/2);
end
initial begin
reset = 1;n = 0;d = 0;
#100;reset=0;n=1;d=0;
#100;n=0;d=1;
#100;n=1;d=0;
#100;n=0;d=0;
end
endmodule
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Wave Form:
88
Lab #10
Lab Task1
Object:
Reproduce and implement basic gates (AND, OR, XOR) by using FPGA Kit.
Introduction:
FPGA is a semiconductor IC (Silicon chip) where a large majority of the electrical functionality
inside the device can be changed. Each FPGA has configurable logic blocks, connected with
reconfigurable wiring circuitry. There is up to 10,000 of these logic blocks in any given FPGA.
Spartan-3E FPGA Starter Kit:
89
Steps Of Performance:
Step#1
Entering the Design
Figure #1
Select either File New Project or click on the New Project tab. The New Project Wizard
dialog box will appear. Specify the directory in which you want to store the project in and name
the project In the Top-Level Source Type section select Schematic and click Next. Another
New Project Wizard dialog box will appear prompting you for device, synthesis and simulation
settings for the project.
90
Figure #2
In this dialog box verify the following settings:
• Family = Spartan3E.
• Device =XC35100E.
• Package = VQ100.
• Speed Grade = -4.
• Synthesis Tool = XST (VHDL/Verilog).
• Simulator=ISim (VHDL/Verilog).
• Generated Simulation Language = VHDL.
If the information is correct click Next.
91
Figure #3
The following window will appear which is about the Project Summary. Now click
Finish.
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Figure #4
We will enter a design using a structural or RTL description using the Verilog HDL. You can
create a Verilog HDL input file (.v file) using the HDL Editor available in the Xilinx ISE Tools
(or any text editor).
Click New Source in the New Project Wizard to add to one new source to your project. Type in
the file name counter. Select VHDL Module as the source type in the New Source Dialog box.
Verify that the Add to Project checkbox is selected. Click Next.
93
Figure #5
You will be asked for the module’s port names/types. While you can use this dialog to create the
port names, we will manually add them later within the Verilog file itself. You can skip this step
and click on the Next button.
94
Figure #6
The following window will appear which is about the Summary. Once you click on
Finish, the source file will be displayed in the sources window in the Project Navigator
Figure #7
95
Step#2
Simulate the circuit
We can now proceed to a simulation of the circuit designed. This can be done by creating a new
source file called a text fixture file.
Figure #8
In the Sources window (top left corner) right click on the file that you want to generate the test
bench for and select ‘New Source’ ,Provide a name for the test bench in the file name text box
and select ‘Verilog test fixture’ among the file types in the list on the right side as shown in
figure 9.
96
Figure #9
This window is about associating a module to a test bench. Click on Next to proceed.
97
Figure #10
The following window will appear which is about the Summary. Now click Finish.
98
Figure #11
Step#3
Implementation



Select Implementation
Double click on Configure Target Device from process: HA window
Wait until ISE iMPACT (0.87xd) window appear
Figure # 12
99
Step#4

Double click on Boundary Scan
A message appears on the window
Figure # 13


Right click on Add Device or initialize JTAG chain
Select Initialize chain option from the list
100
Figure # 14





Select e.g HA bit
Click bypass
Again bypass
Ok
A message Identify Succeed appear on the screen
Figure # 15
101
Step#5



Right click on colored IC
Select program option
A message Program Succeed appear on the screen
Figure # 16
Step#6
Verify the result on SPARTAN-3E starter board
Figure #13a (AND gate)
102
Figure #13b (OR gate)
Figure #13c (XOR gate)
103
Lab #11
Object:
Reproduce and implement Half Adder by using FPGA Kit.
Implementation
Step#1



Select Implementation
Double click on Configure Target Device from process: HA window
Wait until ISE iMPACT (0.87xd) window appear
Step#2








Double click on Boundary Scan
Right click on Add Device or initialize JTAG chain
Select Initialize chain option from the list
Select file e.g RSflipflop bit
Click bypass
Again bypass
Ok
A message Identify Succeed appear on the screen
Step#3



Right click on colored IC
Select program option
A message Program Succeed appear on the screen
Step#4
Verify the result on SPARTAN-3E starter board
104
Waveform
105
Lab #12
Object:
Reproduce and implement Full Adder by using FPGA Kit.
Implementation
Step#1



Select Implementation
Double click on Configure Target Device from process: HA window
Wait until ISE iMPACT (0.87xd) window appear
Step#2








Double click on Boundary Scan
Right click on Add Device or initialize JTAG chain
Select Initialize chain option from the list
Select file e.g RSflipflop bit
Click bypass
Again bypass
Ok
A message Identify Succeed appear on the screen
Step#3



Right click on colored IC
Select program option
A message Program Succeed appear on the screen
Step#4
Verify the result on SPARTAN-3E starter board
106
Waveform:
107
Lab #13
Object:
Reproduce and implement Ripple Carry Adder by using FPGA Kit.
Implementation
Step#1



Select Implementation
Double click on Configure Target Device from process: HA window
Wait until ISE iMPACT (0.87xd) window appear
Step#2








Double click on Boundary Scan
Right click on Add Device or initialize JTAG chain
Select Initialize chain option from the list
Select file e.g RSflipflop bit
Click bypass
Again bypass
Ok
A message Identify Succeed appear on the screen
Step#3



Right click on colored IC
Select program option
A message Program Succeed appear on the screen
Step#4
Verify the result on SPARTAN-3E starter board
108
Waveform:
109
Laboratory Exercise 14
Open-Ended Lab
Title:
1. Objective:
2. Hardware/Software Required
3. Diagram
4. Methodology
5. Observation Table
6. Results
7. Conclusion
110