A Workshop on ASIC & FPGA
Design Flow
Agenda
Agenda
The two days workshop provides in depth coverage to Embedded system on Zynq FPGA using the Xilinx
Vivado software and ASIC Design flow using Mentor Graphics tools.
Objectives
After the completion of this training program the participants will be able to:
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Understand why FPGAs are preferred over Embedded system design
Describe the Xilinx Vivado design flow
Explain the features of Xilinx Zynq architecture
ASIC design flow using Mentor Graphics Pyxis tool
Course Highlights
The training program delivers the following key concepts to the participants:
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Introduction to Vivado design flow
Embedded system design flow on Zynq
Advanced Zynq Architecture
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Full custom design flow using Pyxis tool
Pre-requisites:
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Concepts of digital design
Familiarity with HDL (VHDL or Verilog)**
Basic awareness on Xilinx FPGA design flow
Fundamental of MOSFET
** Not Mandatory
Schedule
Day 1:
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Introduction to Embedded System Design using Zynq
Lab 1: Simple Hardware Design
o
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Create a Vivado project and use IP Integrator to develop a basic embedded system for a
target board.
Zynq Architecture
Extending the Embedded System into Programmable Logic
Lab 2: Adding Peripherals in Programmable Logic
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o Extend the hardware system by adding AXI peripherals from the IP catalog.
Adding Your Own IP Peripheral
Lab 3: Creating and Adding Your Own Custom IP
o
Use the Manage IP feature of Vivado to create a custom IP and extend the system with
the custom peripheral.
Day 2:
Morning Session:
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An overview of VLSI flow (Full & Semi Custom flow).
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Introduction to Mentor Graphics tools relating to VLSI Design flow.
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Demonstration of Schematic Design entry with ADK Library.
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Creating the stimulus (Test Bench) and performing the Simulation
Afternoon Session:
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Physical design concepts using pyxis layout
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Physical Verification using Calibre & Post Layout Simulation using ELDO.
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Demonstration of physical layout and physical verification using Mentor Graphics Pyxis tool
Lab infrastructure needed
1. Xilinx Vivado System Edition
2. Xilinx FPGA Development Kits
a. Zed board
Terms and Conditions:
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Minimum of 20 Participants is required to run a program.
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Course materials will be provided.
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Validity of proposal is ONE month.