MENTOR: Mr. Minh Cao
MEMBER OF GROUP 2
 Nguyễn Văn Tuấn Đức
 Nguyễn Trọng Phúc
 Lê Quang Vinh
TOPICS OF GROUP 2
Present STA : Group 2
1
What is SDC? Where is SDC used ?
2
Introduce basic commands in SDC ?
3
What is internal/interface timing?
4
What is input/output external delay ?
5
What is CU/OCV? What are the operating conditions?
6
What is lib/db, TLU+ file,
briefly explain the lib and TLU+ file structure?
1. What is SDC? Where is SDC used ?
Present STA : Group 2
What is SDC?
Full form of SDC: Synopsys Design Constraints.
What is SDC: SDC is a format used to specify the design intent, including the timing,
power and area constraints for a design. SDC is TCL based.
Tool used this format: DC (Design compiler, ICC (IC compiler), Prime Time (PT).
Format is .SDC
Information In the SDC:
1. The SDC version (optional)
2. The SDC units (optional)
3. The Design Constraints
4. Comments (Optional)
Present STA : Group 2
Where is SDC used ?
SDC is a widely used format that allows designers to utilize the same sets of
constraints to drive synthesis, timing analysis, and place-and-route
How to generate The SDC file Automatically ?
Using Synopsys Tool like DC, ICC or PrimeTime you can generate the SDC.
(There may be slight variation between the generated SDC across the different tool)
Command for generation: - write_sdc
Validation of manually generated SDC files:Command file: read_sdc -syntax_only
Present STA : Group 2
6. What is lib/db file ?
Briefly explain the lib file structure?
Present STA : Group 2
What is lib/db file ?
ASCII format
Provided by semiconductor vendor
(TSMC/SAMSUNG/FUJITSU...)
Timing information
of standard cel,
soft macros, hard
macros.
Timing information
like cell
delay setup,
hold, recovery, rem
oval.
Power information
Design rules like
max tran, max cap,
max fanout,
min cap
Cell delay is a function of input
transition and output load and is
calculated based on lookup tables.
Present STA : Group 2
PVT corners
(every PVT corer
there is a.lib
file present)
Example
sky130_fd_sc_hs_tt_025C_1v80.lib
• sky130: is the name of the library used
• fd: stands for "foundry", meaning this library is provided by the chip manufacturer.
• sc: stands for "standard cells", meaning a library containing standard cells.
• hs: stands for "High Speed", for a set of libraries that contain cells optimized for
faster performance.
• tt_025C: is the design ambient temperature calculated in Celsius (C), this is the
normal temperature during the design process.
• 1v80: operating voltage of the circuit (1.8V).
Present STA : Group 2
What is the difference between a.lib and a.db file ?
a.lib
a.db
ASCII format
Binary format
We can trace information
easily by *.lib format
EDA tool using *.db will process
the job faster than *.lib
Contain same information as
the .lib files but encrypted
Present STA : Group 2
Briefly explain the lib file structure?
File Header
Cell Header
The .lib file
structure
Pin Header
Timing Table
Present STA : Group 2
What is lib/db file ?
File Header
Cell Header
Pin Header
Timing Table
Present STA : Group 2
LEF
TLU+
RC
RC
Present STA : Group 2
Cell LEF file
RC
R
C
What is lib/db file ?
SPEF
TLU+
( R, C => Net )
Delay
cell, net
File .lib
File lef
Present STA : Group 2
Briefly explain the lib file structure?
TLU+ Files are extracted or generated from ITF files( contains Interconnect details).TLUPlus models are a set of
models containing advanced process effects that can be used by the parasitic extractors in Synopsys place-and-route
tools for modeling.
R,C
parasitics of
metal per unit
length
Present STA : Group 2
R,C
parasitics are
used for
calculating
Net Delays
If TLU+ files
are not given
then these
are extracted
from .ITF file.
For Loading
TLU+ files we
have to load
three files
Those are
Max Tlu+,Min
TLU+,MAP
file.
MAP file
maps the
.ITF file and
.tf file of the
layer and via
names.