Maximizing clock frequency
using Quartus
Explore the optimization options
Optimize for speed/area/balanced
Writing and using a “sdc” file
• sdc = “synopsys design constraint file”
• Open “Timequest timing analyzer” GUI
from task menu
Writing a “sdc” file
Writing a “sdc” file
• wep_encrypt.out (sdc) file is created using
the GUI
• Inside the file, look for the line:
– create_clock -name {clk} -period 1.000 waveform { 0.000 0.500 } [get_ports {clk}]
– The target clock period is set to 1 ns using the
“–period” option
– Change that to the target period you want to
run your design
Adding “sdc” file to project
Adding “sdc” file to project
• “sdc” files will appear under “script files”
• Play around with target clock periods
• Being too aggressive may not lead to the
fastest design
• Use this as a last optimization step after
exploring all other optimization options