A HIGH P E R F O R M A N C E
LINE
REGULATOR
G. I. Cardwell and D. J. Packard
Hughes Aircraft CompanyEl Segundo, California
ABSTRACT
A. high performance 10 k H z switching line
regulator featuring isolated drive with full
dynamic range is described. Also described are
a wide-band isolated output sense circuit and
suitable compensation extended transient
response beyond the resonant frequency of the
output filter. This switching regulator w a s
designed and developed as part of a p r o g r a m
sponsored by N A S A Lewis Research Center,
Contract N o . N A S 3-17223, under the direction
of Jim Sovey.
INTRODUCTION
This paper describes the design of a
10 k H z 500 W switching buck type regulator used
as a line regulator in a power conditioner for an
ion thruster. The design specifications w e r e to
regulate a 200 to 400 volt solar panel input to a
180 volt output with 1 percent regulation for line
and load variation. Additional constraints w e r e
that the regulator be able to respond rapidly to
large load transients requiring a full dynamic
range of operation and a wide bandwidth. A wide
bandwidth w a s necessary because the regulator
is used to provide an input to an inverter whose
output is supplying magnetic amplifier loads
(Figure 1). Since each magnetic amplifier load
has a c o m m a n d a b l e reference with its o w n closed
loop negative feedback control, it reflects a neg­
ative impedance to the output of the switching
regulator at low frequencies. Often a negative
impedance load causes a negative resistance type
oscillation w h e n attached to a resonant L C filter
source such as an L C filtered switching regulator.
T o stabilize this network, a resistor m a y be
added in series with the output filter capacitor.
H o w e v e r , the large resistor can cause an unac­
ceptable voltage ripple on the output of the regu­
lator. In the case discussed in this paper, the
bandwidth of the magnetic amplifier could not be
significantly reduced. Therefore, it w a s neces­
sary to raise the frequency response of the
switching regulator to a frequency beyond the
resonant frequency of the output L C filter to pro­
duce a positive total network impedance and pre­
vent the negative resistance oscillation discussed
above. A n analytical treatment of this problem
is included in this paper.
1 0 6 - P E S C 74
R E C O R D
A further design constraint w a s that the
control electronics be isolated to greater than
2000 volts from the power switch, requiring both
an isolated power transistor drive circuit and an
isolated feedback sense circuit. Finally, the
goal w a s for an efficiency of greater than 93 per­
cent full load with a weight of less than
2. 0 pounds. The following is a description of the
approach taken to m e e t these requirements on
drive and sense circuitry and wide band
compensation.
Since good quality high power, high
voltage N P N transistors are far m o r e available
than P N P transistors, it is desirable to use a
power N P N transistor in a high voltage switching
regulator. The problem in this case is to provide
the base drive for that N P N transistor. A c o m ­
m o n technique used in the present state of the art
is a P N P driver connected in a Darlington config­
uration to drive the power N P N transistor. With
this technique, an N P N transistor is used to drive
the P N P - N P N Darlington pair (see Figure 2). In
a high voltage application, this configuration has
a serious deficit in that all three transistors m u s t
be capable of supporting the m a x i m u m line volt­
age. Such a configuration does not offer the
ground isolation required in this application.
Typically, where ground isolation is required,
the magnetically coupled switching driver is nor­
mally limited by the magnetic reset time of the
coupling transformer. It is a simple matter to
INVFRTER
1
^
PUWtK
SWITCH
SOLAR
PANEL
MAGNETIC
AMPLIFIERS
DC
FEEDBACK
CONTROL
CIRCUIT
AC
FEED­
BACK
ISOLATED
"RETURN
FIGURE 1 . FUNCTIONAL BLOCK DIAGRAM
INPUT
LOAD
10 k H z
FUNDAMENTAL
SUBHARMONIC
CARRIER
TYPE 1
MODULATION
INPUT
TYPE 2
MODULATION
INPUT
j—ι
ι—I
I
"L
XT
J~L
_ΓΊ_
n_TL
η
OUTPUT
COMMON
F I G U R E 2.
BASIC S W I T C H I N G R E G U L A T O R
turn off (i. e. , 0 percent duty cycle) the magneti­
cally coupled switching regulator, it is usually
impossible to turn on the magnetically coupled
switching regulator all the time (i.e. , 100 per­
cent duty cycle).
In the series switching regulator, it is
highly desirable to have as wide a dynamic range
of control as possible. The capability to turn on
the regulator completely is important if the regu­
lator is to be subjected to transient loads or if the
input voltage to the regulator is allowed to fall to
a value very near the output regulated value. B y
utilizing s o m e type of modulated ac carrier, a
100 percent dynamic range of drive can be m a g ­
netically coupled to the power transistor in a
switching regulator. For example, a carrier m a y
be applied to a transformer with a full w a v e recti­
fier, current limiting resistor, and power trans­
istor connected to the secondary (see Figure 3).
If this carrier is applied continually the power
transistor is driven continually. If the carrier
w e r e turned on and off by a duty cycle modulator,
the drive to the power transistor would be m o d u ­
lated. The technique shown would utilize a high
frequency carrier, which might not be readily
available or simply generated.
y
MODULATOR
CARRIER
^
OUTPUT
H-
F I G U R E 4. S U B H A R M O N I C
MODULATION
utilizing type 1 modulation, volt second balance
is maintained on the center tap drive transformer
by applying modulation on alternate half cycles of
the subharmonic carrier. Type 1 modulation
shown in Figure 4 is expanded about the center of
the subharmonic carrier and at all times, the
modulated input is applied in the s a m e half cycle
of the subharmonic carrier. The advantage to
this type of modulation is that the output of the
rectifiers that provide drive to the power transis­
tor is constant and contains no switching transients
due to the subharmonic carrier except for that
special condition w h e n the modulator is requesting
100 percent duty cycle.
The type 2 modulator also maintains volt
second balance on the drive transformer. In this
case, balance is maintained by splitting the
modulated time in half and applying half of the
modulated w a v e f o r m to either side of the trans­
former during the subharmonic switching interval.
In this case, a small switching transient occurs in
the output of the rectifiers in the middle of the
modulated period. Initially type 1 modulation w a s
considered for this switching regulator. H o w e v e r ,
an investigation into the isolated sensing technique
to be used in the regulator disclosed the fact that
the subharmonic carrier could also be used as a
carrier for the remote sensing if type 2 modula­
tion w e r e utilized. This discussion will be
expanded as a part of the sense circuitry descrip­
tion included later.
MODULATED OUTPUT
F I G U R E 3. H I G H F R E Q U E N C Y C A R R I E R
MODULATION
For the problem at hand, a better solution
seemed to be one of using a first subharmonic of
the 10 k H z operating frequency to perform the
driving function. The 5 k H z subharmonic carrier
is easily generated by using a toggle flip-flop
clocked by the 10 k H z fundamental frequency.
Modulation utilizing subharmonic carrier m a y be
accomplished in two ways (see Figure 4). W h e n
The primary concern of utilizing type 2
modulation is that of the switching transient dur^
ing the toggling interval of the subharmonic gen­
erator. B y using high frequency pulse
transformer techniques and high speed diodes, it
w a s possible to reduce the transient to something
under 200 ns. The storage times of power tran­
sistors considered for this application w e r e in
excess of 1 μβ and, as a result, change in col­
lector voltage or current w a v e f o r m s could not be
observed during the transient caused by the
switching of the subharmonic carrier.
PESC 74 R E C O R D - 1 0 7
FIGURE 5. SIMPLIFIED DRIVE SCHEMATIC
U s e of a subharmonic drive circuit
provides a solution to the problems mentioned in
that a magnetically isolated switching regulator
with a 100 percent dynamic range can be
implemented. This method works equally well
with a power N P N or P N P transistor and allows
that transistor to be fully saturated. Moreover,
the power transistor is the only transistor sub­
jected to a high voltage stress.
DRIVE CIRCUIT
Figure 5 is a simplified schematic of the
drive circuit.
A square w a v e clock signal is applied to
R l and to the toggle input of the flip-flop. Resis­
tor R l and capacitor C l form an integrator that
integrates the square w a v e signal into a small
voltage r a m p which is applied to one of the inputs
of level detector A l . The other input to the level
detector is a feedback signal. If this signal is
allowed to vary slowly through the range of the
r a m p , the level detector forms a pulse width
modulated output. This action is shown in wave­
forms 3 and 4 of the master timing diagram,
Figure 6. The falling edge of the square w a v e
clock is used to toggle the flip-flop m a d e up of
transistors Q 5 , Q 6 , and toggle gating circuitry.
Transformer T2 is the m a i n base drive
transformer for power transistor Q 7 . The
1 0 8 - P E S C 74 R E C O R D
CLOCK
SUBHARMONIC
DRIVE TO DRIVE
AND SENSE
TRANSFORMERS
RAMP
LEVEL
DETECTOR
OUTPUT
POWER SWITCH
OUTPUT FILTER
RIPPLE
SENSE INPUT
RIPPLE
SENSE OUTPUT
RIPPLE
A1 OUTPUT TO
LEVEL DETECTOR
FIGURE 6. MASTER TIMING DIAGRAM
primary side of transformer T 2 is connected
through diodes to the collectors of Q 5 and Q 6 .
Q 5 and Q 6 form a discrete toggle binary which
is clocked at 10 kHz.
The center tap of the primary of T2 is
connected to transistors Q 3 and Q 4 . These two
transistors are a complementary pair which drive
the center tap of transformer T 2 as dictated by
the output of the level detector (modulator). The
output of transformer T 2 is connected through
diodes C R 2 and C R 3 and the current limiting
resistor R 7 to the base emitter of the power
transistor Q 7 .
For any interval of time, with the excep­
tion of the toggling interval, either Q 5 or Q 6 is on.
Therefore, during any interval, the center tap of
T2 primary m a y be raised to provide base drive
to Q 7 .
Transistor Q 2 and resistor R 6 drive the
complementary pair Q 3 and Q 4 . The transistor
Q 2 is driven from the basic duty cycle modulator,
Al.
T o turn off Q 7 quickly, TI is used as a
magnetically timed blocking oscillator that is
triggered by the rising edge of the output of A l .
Diode C R 1 and resistor R 4 form a turn-on,
turn-off network for the blocking oscillator. The
output of level detector A l is at a voltage below
ground w h e n power transistor Q 7 is on. At that
time, diode C R 1 is forward biased and is conduc­
ting current through resistors R 4 and R 5 and into
the output of level detector A l . At the time that
level detector A l c o m m a n d s power transistor Q 7
off, its output rises very rapidly. This rapid
rise in output of A 1 forces clearing current to
flow through diode C R 1 . Diode C R 1 is a low
speed rectifier and therefore passes clearing
current for a significant time. This clearing
current flows into the base of transistor Q l ,
initiating the time interval of the positive feed­
back blocking oscillator.
Transformer TI is connected in such a
polarity that w h e n the blocking oscillator is on,
i. e. , Q l conducting, a negative voltage is applied
at output transformer TI. This negative voltage
causes a current to flow out of the base of transis­
tor Q 7 , and the negative current (on the order of
IA) causes transistor Q7 to turn off very rapidly.
Transistor Q l is turned on at approximately the
s a m e time that the center tap of transformer T 2
is actively forced to ground. Because of the
action of these twc transformers, the base drive
to power transistor Q 7 changes from the positive
drive of approximately 250 m A to a negative drive
of approximately 1 A in approximately 100 ns.
The magnetic time constant of the blocking c
oscillator is nominally longer than 15 μβ, thereby
ensuring that negative current can be removed
from the base of Q 7 for a period in excess of its
storage time.
If the switching regulator is operating at
nominal or low duty cycles, the magnetically
timed blocking oscillator will time out and switch
off. If, however, the input voltage to the switch­
ing regulator is low and the switching regulator
is required to operate at long duty cycles, level
detector A l m a y switch negative before the block­
ing oscillator has timed out. In this case, transis­
tor Q l will rapidly turn off because of the forward
currents through diode C R 1 and resistor R 4 . The
blocking oscillator m a y therefore be turned off
at any time prior to its normal time out interval.
Because of this and the subharmonic carrier
nature of the on drive to transistor Q 7 , the
switching regulator has an extremely broad dyna­
mic range. It m a y indeed be operated over a
0 percent to 100 percent duty cycle.
ISOLATED SENSE CIRCUIT
Figure 7 illustrates a m e a n s of
transmitting a dc voltage across a winding in an
isolated sense circuit. The two transistors are
driven by two square waves of the s a m e frequency
180° out of phase. This impresses the input volt­
age across first one half and then the other of the
center tapped primary of the transformer T. The
ac secondary voltage that results from this action
is rectified by the diode bridge and filtered by the
R C network. This circuitry is suitable for the
passage of dc information, but if the input has an
ac component, the R C network limits the band­
width of the signal that m a y be actively transmitted
through this circuit. If there is no filtering, a
switching transient will always be evident in the
output w h e n the transistors switch. This transient
normally presents a problem in maintaining the
fidelity of the high frequency information. In
this application, the output voltage of the line
regulator contains the desired ac information.
Also a subharmonic carrier w a s available to
transmit this information. B y modifying the cir­
cuit shown in Figure 7 to that shown in Figure 8,
the desired information is transmitted across
transformer T3. Notice that the primary of
transformer T 3 is n o w current driven, and it is
the center tap of the primary T3 that contains the
desired output information. In essence, the sig­
nal flow is reversed through the sensing
transformer.
The switching transient problem w a s
solved by taking advantage of the fact that the
occurrence of the switching transient in the time
domain is controlled by the excitation frequency
of the driving transistors, and it is possible to
synchronize the sense excitation to that of the
pulse width modulator clock. If phased as shown
in the master timing diagram of Figure 6, this
INPUT V O L T A G E
R
F I G U R E 7. V O L T A G E C H O P P E R I S O L A T E D S E N S E C I R C U I T
PESC 74 R E C O R D - 1 0 9
will cause the switching transient to occur between
pulse width sampling intervals. Using this method,
ac information of a bandwidth beyond the excita­
tion frequency can be transmitted. A description
of the circuit techniques utilized follows (refer to
Figure 8).
w o r k for the line regulator. Its loads include a
square w a v e inverter that drives several magnetic
amplifiers. These constant power loads appear
incrementally to be negative impedances.
One type of compensation c o m m o n l y used
in regulators is achieved with the placement of a
dominant pole s o m e w h e r e in the feedback loop,
such that unity loop gain is below the resonant
frequency of the output filter. If this method is
used, then the closed loop output impedance of the
regulator is roughly equal to the open loop output
impedance for frequencies above unity gain. It
should be noted that the following analysis assumes
the output of the switching element m a y be timeaveraged and linearized. With this assumption,
Laplace transform methods are used and perfor­
m a n c e inferred from the frequency domain. The
output impedance of a circuit with voltage feed­
back is indicated in Equation 1
Ζ oc =
Zoo
1+T
(1)
where Zoe is the closed loop output impedance,
Zoo is the open loop output impedance, and Τ is
the loop gain. T o see the effect of a negative
resistance load with this type of compensation,
consider the following argument.
F I G U R E 8.
I S O L A T E D SENSE CIRCUIT
The collector of transistor Q 9 is connected
to the base of transistor Q 8 and as a result, the
emitter of Q9 and the collector of Q 8 form a very
low impedance voltage shunting source. The volt­
age on the collector of Q 8 is approximately the
voltage at the junction of the voltage divider R 8
and R 9 . The diode bridge is forced to maintain
the voltage defined by the junction of the voltage
divider R 8 and R 9 , and therefore, the center tap
of the primary of transformer T 3 is held at a
voltage which is proportional to the voltage at the
junction of the resistor divider R 8 and R9 and is
therefore proportional to the bus voltage. Capa­
citor C 2 provides high frequency lead compensa­
tion. Although from a stability standpoint it
m a k e s no difference w h e r e the loop compensation
is placed, the effect of the switching transient
caused by the switchover of T3 is reduced by plac­
ing this compensation in front of the sense
transformer.
A dc isolated wide bandwidth voltage is
thus produced at signal level that is proportional
to the switching regulator output voltage. Since
the subharmonic carrier is generated for the
power transistor drive, this s a m e carrier is used
to excite the sense transformer.
C O M M E N T S O N STABILITY
Referring to Figure 9, if this circuit is
to oscillate, then a right half plane pole m u s t be
present in the driving point impedance seen at
the terminals labeled A B. This impedance ( Z ^ g )
is shown in Equation 2
J
A B
Zoe//
R
-Zoe · R
Zoe - R
T o deduce whether a right half plane pole is
present, divide top and bottom by Zoe to get
Equation 3.
1 +
(-Zo-c>
1 + T
110-PESC 74 RECORD
(3)
f
A s shown T is a pseudo loop gain which allows
the use of the Nyquist criterion to determine
whether the loaded filter will be unstable. If it
is assumed that dominant pole compensation is
used and that the unity gain frequency of the
regulator is well below the resonant frequency of
the filter, it m a y be assumed that the output
impedance of the regulator is that of the L C
filter. Then the closed loop output impedance
(Zoe) m a y be simplified as shown in Equation 4
for frequencies where Τ « 1.
1
Ç *V
-R
" ^ o c
During the power subsystem developmental
phase for the ion engine, it b e c a m e evident that
standard compensation techniques w e r e not to
(2)
M— Ć
AB
Β
F I G U R E 9. N E G A T I V E R E S I S T A N C E L O A D E D L C F I L T E R
„
sL + R ,
„
Zoo
„
L
Zoc = —
- Zoo = —
s LC + s C R
+ 1
L
(4)
R
L
s LC
2
(sL/R
+
s
C
+ 1)
L
+
R
L
1
With this assumption T , the pseudo loop
gain, m a y be
1
The approach here w a s to r e m o v e the
resonant peaking of Zoe by extending the band­
width of the regulator beyond the resonant fre­
quency of the filter. This solves the oscillation
problem by reducing the magnitude of Zoe, and
significantly improves the transient response to
line and load changes. This type of compensation
also tends to m a k e the regulator insensitive to
the Q of the output filter. At frequencies where
the loop gain is m u c h greater than 1, Zoe is
approximately given bv Equation 6.
Zoe =
-R (s L C
T
R
=
+ sCR
(sL/R
T
L
+
T
L
+ 1)
( f 0 P T « l )
1)
Zoo
1+T
Zoo
Τ
(if Τ » 1 )
(6)
(5)
The poles of Τ include the poles of Z o o
since output voltage is fed back. Thus considering
an unloaded output filter of the type shown in
Figure 9. Τ will contain the transfer function f r o m
the source Η · V (which represents the linearized
power switch) to the output A B . Zoe m a y be c o m ­
puted for frequencies w h e r e Τ » 1 as shown in
Equation 7.
L
approximated by Equation 5. Figure 10 is a
Nyquist plot of this pseudo loop gain.
s L + R,
Zoe
Zoo
1+T
Zoo
M
~
s LC
+ sCR
L
+ 1
j
ô
H(s) . \-r
s L C + sCR. + 1
L
sL + R
l
R_
( S ^ L C+ S C R
(SL/R
L
L
+
+
1)
1)
Z
FIGURE
10.
NYQUIST
PLOT
O F L O A D E D
FILTER
LOOP
GAIN
Ô
It is clear that if the Q of the output filter
is sufficiently high, the filter with a negative resis­
tance load will oscillate. Note that the method
used here to deduce instability is well suited to
experimental verification. That is if the true
magnitude and phase of the load can be measured,
then this information coupled with design data on
Zoc should allow determination of potential
instability by plotting a Nyquist plot of Zload/Zoc
and checking for clockwise encirclements of the
-1 point.
With dominant pole compensation in the
circuit, the output filter had sufficient Q such
that the load induced oscillation near the reso­
nant frequency of the output filter.
Considering Equation 2 for Ζ ^ β , it is noted
that if the magnitude of the closed loop impedance
can be m a d e m u c h less than the magnitude of the
load impedance, then Ζ ^ β is approximately Zoc
regardless of the load characteristic and the
regulator is stable. Another approach to
stabilizing the loaded filter would be to directly
lower its Q by adding a small series resistor to
the output capacitor. This approach can work,
but only with increased output ripple and lower
efficienc y.
o
c
=
H f i T
f
°
r
T
> y
1
(8)
Equations 7 and 8 show that sufficient
feedback beyond the resonant frequency can
effectively r e m o v e the resonance f r o m the closed
loop output impedance. Using this approach and a
simple describing function technique, a suitable
feedback function H (s) w a s developed.
COMPENSATION
CIRCUIT
The switching part of the feedback loop w a s
linearized in the following m a n n e r . Referring to
Figure 5, note that as the feedback input to the
level detector m o v e s over the full range of the
triangle input, the duty cycle varies f r o m 0 per­
cent to 100 percent causing the average output of
the regulator to vary from 0 to V s volts. The
gain of the modulator w a s then characterized as
G M = V s / V p p where V s is the input voltage to the
line regulator and V p p is the peak to peak voltage
on the triangle input. Since for simplicity, the
size of the triangle w a s fixed and V s varies f r o m
200 to 400 volts, G m then varies by a factor of
two.
This variance in gain with line voltage
m e a n s that the magnitude plot of loop gain could
be translated 6 d B for line variations.
A s mentioned earlier, stability considera­
tions required that the loop gain cross over 0 d B
above the resonant frequency of the output filter.
P E S C 74 R E C O R D - 1 1 1
30
F R E Q U E N C Y , HZ
F I G U R E 11. L I N E R E G U L A T O R B O D E
T o m a k e the describing function approach valid
and to keep noise from triggering the level detec­
tor, it w a s decided to have the loop gain cross
zero no higher than a factor of 3 below the switch­
ing frequency. Referring to the loop gain plot of
Figure 11, stability w a s achieved by placing a
zero at 1 k H z to overcome part of the phase shift
that the two 400 H z poles of the resonant filter con
tribute. T w o additional poles w e r e placed at
20 k H z to attenuate switching noise and provide
additional phase shift after crossover to balance
the subharmonic drive circuit after the level
detector. Referring to Figure 12, the midfrequency gain w a s set by resistors R a and R b on
operational amplifier A 2. This w a s chosen to
m a k e unity gain crossover occur between 1 k H z
and 2 k H z for line variations. Finally, to obtain
o p t i m u m dc regulation, the operational amplifier's
full open loop gain w a s used at low frequencies by
making it an integrator with capacitors C a and Cb.
The resistor divider and capacitor C 2
shown in Figure 8 provide the 1 k H z zero and one
of the 20 k H z poles. The other 20 k H z pole is
derived from R b and C a connected to operational
amplifier A 2 . The combination of high frequency
poles and zeros provided nearly a constant 60° of
phase margin over the range of possible crossover
frequencies as shown in Figure 11. These data
w e r e taken with a w a v e analyzer.
112-PESC 74 RECORD
DIAGRAM
REFERENCE
FEEDBACK
o—AAAr-
F I G U R E 12. C O M P E N S A T I O N C I R C U I T R Y
The net result of this compensation w a s
the transient response shown in Figure 13 and a
dc output virtually independent of line voltage or
load variation.
A n additional wrinkle that w a s added to the
actual system w a s to ac couple the high speed
feedback from the subharmonic sense circuit and
combine this signal with the 15 volt system power
which is derived from the regulator through a con­
verter. Thus, the +15 volt supply w a s directly
regulated while the wideband sense provided high
frequency stability.
30 c m L I N E R E G U L A T O R S T E P L O A D R E S P O N S E
authors feel that these solutions m a y be useful in
far m o r e general applications. For example, the
subharmonic carrier technique m a y be useful in
any switching regulator application and in parti­
cular, useful where high voltage isolation is
required. E v e n if the control circuitry need not
be high voltage isolated, it is convenient to have
only one switching transistor subjected to high
voltage stresses and the subharmonic carrier
drive would s e e m to be an excellent general solu­
tion to this problem. It should be noted that the
subharmonic carrier drive technique, w h e n
actually implemented, allowed the construction of
a lightweight (approximately 1.5 pounds) 500 watt
switching regulator which operated at an efficiency
of approximately 96 percent at full load and
300 volt input. Further, the isolated sensing cir­
cuitry provided a m e a n s of high frequency output
signal feedback that w a s necessary to meet the
system stability criteria. Equally important,
this paper presents a linearized technique that
can be used to obtain a stability criterion for
resonant circuits loaded by a negative impedance.
CONCLUSIONS
Certain simplifying assumptions w e r e
m a d e in the analysis to illustrate an example of
the technique. The only necessary assumption
is that a describing function can adequately char­
acterize the modulator and switch. The tech­
nique is sufficiently general to apply to a n u m b e r
of regulated dc-dc type converters with resonant
input or output filters which are loaded with
negative impedances.
In conclusion, this paper describes the
techniques used to solve s o m e rather special
design problems. Even though these techniques
w e r e developed to satisfy a specific need the
Hopefully, this paper will be both speci­
fically useful to those attempting to design high
voltage converters, and generally useful to those
w h o m u s t face the stability problems encountered
by operating with negative impedance loads.
UPPER T R A C E
LOWER TRACE
180 V O U T P U T , 1 V / C M
L O A D C U R R E N T S T E P , 0.2 A / C M
F I G U R E 13. R E G U L A T O R T R A N S I E N T R E S P O N S E ,
10 T O 100 W L O A D
P E S C 74 R E C O R D - 1 1 3