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FPGA implementation of configurable three-Phase SPWM module
Conference Paper · August 2012
DOI: 10.1109/CCCA.2012.6417879
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FPGA implementation of configurable threePhase SPWM module
Ahmed Belkheiri1,2, Mohammed Belkheiri2 , Said Aoughellanet1 and A. Rabhi3
1- Department of electronics, University of Elhadj Lakhdar, Batna, Algeria
2- Laboratoire de Télécommunications, Signaux et Systèmes, Université Amar Telidji- Laghouat Algeria
3- Laboratoire de Modélisation, Information et systèmes (MIS), Université de Picardie Amiens, France
Abstract — The work presented in this note concerns
designing and implementation of a three phase SPWM
reconfigurable module for power inverters to drive
induction machines. In this paper we emphasise on
reconfigurabilty of the SPWM characteristics such as
modulation index, carrier frequency, modulating signal
frequency and dead-time. The resulting vhdl code is
simulated first using Quartus II software of Altera.
Simulation and experimental results on DE2 cyclone FPGA
are presented to verify the performance of this module.
Keywords — FPGA, SPWM, VHDL, index
modulation, carrier frequency, logic elements (LEs).
I. INTRODUCTION
Advances in digital systems such as microprocessors,
microcontrollers, Digital Signal Processors (DSP), Very
Large Scale Integration VLSI circuits and Programmable
logic devices enable the design of efficient digital control
techniques for power inverter control. Power inverters
controller design may be implemented either on a
microprocessor, DSP, or a microcontroller. And the
designer must change the software when new algorithms
are designed. Sometimes the algorithm become complex
and could not fit in the digital system and the designer
must find a new hardware set-up to fulfill these needs.
Digital control algorithms implementation using FPGA
becomes today more than necessary for inverter control
thanks to their reconfigurability, design reuse, flexibility
and parallel processing [1,2].
Pulse Width Modulation PWM strategy is proven to be
the most adapted technique for inverter control because it
provides large range of output voltage and frequency, and
low total harmonic distortion (THD) [3-6]. Almost all
research on AC machines control implementation is
realized on DSP and only few research papers have
implemented their control algorithms on FPGAs but they
do not present details about the PWM technique
implementation issues. Among problems arising in using
FPGA devices is limited space resources [7-9] and at the
same time, we have to design full adjustable SPWM
module. The user has the choice to set some input
parameters such as modulating and carrier frequency with
high resolution. Another issue of the designed module is
that it uses less number of logic cells (LCs).
978-1-4673-4695-5/12/$31.00 ©2012 IEEE
The FPGA implementation of SPWM technique that
was introduced in [9-11] uses 841 of logic cells, with
fixed carrier frequency and 1 Hz step to adjust the
modulating frequency, whereas in our design all the
characteristics of SPWM can be adjusted by 0.5 HZ step
for modulating signal frequency and by exactly 0.78%
step for amplitude.
The objective of this paper is to present a
reconfigurable module to generate SPWM for three phase
inverter control. This module will be integrated within an
embedded system using a System on programmable chip
SOPC to implement efficient control algorithms for
induction machine control and other power drives
applications. This paper is organized as follows: the next
section is devoted to review of SPWM technique. Then in
section III the whole Design architecture will be detailed.
Section VI is devoted on Simulations and Experimental
results. Finally some concluding remarks are presented.
II. SINUSOIDAL PULSE-WIDTH MODULATION REVIEW
Sinusoidal pulse width modulation SPWM is a
traditional method to control the amount of power sent to
a load [3,11] of a power source. It is based on the
modulation of its duty cycle , where sinusoidal control
voltages are compared with a triangular carrier signal M,
with a frequency fc and of amplitude U/2 to generate the
switching pattern to turn-on and turn-off the two
complementary switches (K1 and K’1) for one singlephase half-bridge with a desired reference signal with a
frequency fr as illustrated in Fig. 1. The resulting output
voltage (Va–Vo) either equals to +U/2 or –U/2 according
to the switch logic. If the reference varies sinusoiddally
which is the case for Sine PWM, the average value of
(Va–Vo) varies in the same way. The aim of this paper is
to achieve an approximate sinusoidal output voltage by
sinusoidally varying the average value by turning on and
off the inverter switches.
Fig. 1 the main idea of SPWM technique
III. THE PROPOSED SPWM ARCHITECTURE
The block diagram of the proposed architecture is
shown in Fig. 2. The system inputs are three 8-bit data
word, the first (frequency_ref) refer to the modulating
wave frequency the second(Amplitude_ref) refer to the
modulation index ma, and the last corresponding to the
frequency carrier, so that it can be easily interfaced to a
FPGA development board DE2 I/O port pins. The
designed system is implemented to fit in a low cost DE2
Altera board [11]. It is composed of three identical
modules to generate the reference modulating shifted by
120°. Each signal is implemented as a 7bit pointer that
reads a ROM containing 256 values of a sampled sine
wave.
The frequency of the generated waveform can be
controlled by the clock of the pointer counter. Hence a
configurable sub-module is designed to generate adequate
clock frequency. It can be configured to generate a sine
wave of (0.5 to 60 Hz) frequency as specified by the
parameter Frequenc_ref. (Fig.3).
The value of frequency_ref is determined by the
following formula:
Frequency ref
Fig. 2 The Architecture Of FPGA SPWM Module
FFPGA
2
2 N Fw
Where:
Fw is desired sine wave frequency
FFPGA is the FPGA board clock frequency (27 MHZ
in this work).
N: is the data width of counter (8 bit in our case)
Fig. 3 Generation sine wave with adjusted frequency
Using the previous formula we have calculated and
stored all Frequency_ref values in a memory to enable us
to generate the frequency range (0.5~60 Hz).
Another specification should be achieved is to scale
the generated sine wave amplitude related to
amplitude_ref (0 to 1 by requested step), to perform this
operation we have used the fixed point arithmetic, since
not a high accuracy is requested here. Two operations are
used the multiplication and the division which is carried
easily by shift operation. In this approach, each 8 bit data
sine wave sample is read from the memory then is
multiplied by a preselected amplitude_ref, the result is 16
bit data signed which again shifted by 7 (division by
127), finally the result is converted to 8 bit signed data.
This approach allows us to scale the sine wave between 0
and 0.992 by 0.00780 step.
The carrier waveform is a triangle wave that was
implemented in FPGA like an up-down counter, with
same way described in previous paragraph we can
generate the carrier waveform with desired frequency
related to Carrier_frequency_ref input.
The deadbeat time which is necessary for power
switch turn-on and off synchronization to prohibit the
short circuit in the inverter. Its insertion was embedded
after the outputs of the comparators. Every comparator
output with its complement are subject to an adjustable
delay when they switch from logic '0' to logic '1'. The
deadbeat time can be adjusted by controlling the clock
which is used to trigger deadbeat time delay registers.
With these approaches any desired specification can be
easily achieved.
The designed SPWM top module has been developed
and implemented on the Altera DE2 development and
education board [11], which includes a Cyclone II 2C35
family FPGA devise in a 672-pin package, and EPCS16
serial configuration device. The HDL code was
synthesised using Quartus II 7.2 software provided by
Altera. Fig. 4 shows the top level entity of SPWM which
is developed by using schematic and vhdl description
langage.
Figure 5 displays the compiler flow summary section,
which indicates that only 2% (607) logic element, 4% of
memory bits, 13% of pins, 0% of PLLs unit are needed to
implement this circuit on the selected FPGA chip.
Fig. 4 Schematic of top-level entity of SPWM generator
Fig. 8 Simulation Results - Frequency_ref=40Hz,
Amplitude_ref=0.629. Carrier frequency =750 hz
Fig. 5 compiler flow summary of SPWM module
V. EXPERIMENTAL VALIDATION
IV.
SIMULATION RESULTS
Figures (6,7, and 8) show functional simulation
results of the designed system for different entered
specifications using 27-MHz as the main clock input
system in all simulations. It is evident that the proposed
FPGA three phase SPWM generator architecture works
properly .
After achieved satisfactory simulation results as
illustrated above we will switch to system experimental
validation. Figure 9 shows the block diagram of the
experimental set-up, which consists of:
• ALTERA DE2 board to generate the SPWM
pulses.
• Opto-coupler (HP2200) to isolate electrically the
control circuit and the power circuits from each other,
and gate drivers (IR 2113) to drive the gates of the
inverter switches, by creating a floating supply.
• A current sensor circuit, based on LEM 25 a.
• Tektronix oscilloscope with Signal Express
software, for measurement acquisition and analysis.
• The three-phase voltage inverter, based on six
(three arms) IRG4BC20KD insulated gat bipolar
transistor with ultrafast soft recovery diode.
Fig. 6 Simulation Results- Frequency_ref=60Hz,
Amplitude_ref=0.984, carrier frequency 1.35kHz
Fig. 9. Block diagram of the experimental set-up.
Fig. 7 Simulation Results-Frequency_ref=60Hz,
Amplitude_ref=0.629, carrier frequency 1.35kHz
In order to analyze, the implemented SPWM
generator, First, an LC output low-pass filter
(L=12.5mH, C=1 μF) is used, and an LR circuit as a
load (L=1.3mH, R= 20 Ω). The bus voltage is chosen to
be 20V.
Figure 10 shows the experimental results of the
inverter output, line to line, voltage Vab. The carrier
frequency is set to 5.3kHz, the modulation index is set
to 90% and the modulating frequency is set to 60Hz.
(a)
7
Figure 11 shows the filter output, line to line,
voltages Vab and Vbc, with deferent modulating
frequencies. We can see here, that the inverter output
voltages are easily filtered, and the implemented
SPWM module can generate any desired output voltage
frequency.
VI. CONCLUSION
(b)
Fig. 10 Experimental results inverter
output line to line voltages Vab,(a) 1.3
KHZ carrier frequency, (b) 5.3 KHZ
This paper presented the design and implementation of
adjustable and configurable three-Phase SPWM generator
based on FPGA which can be used for power inverter
driving to control adjustable output voltage in both
frequency and amplitude. A novel approach was
introduced to designing such module in order to reduce
the number of used logic elements (LEs) 607 in our case.
ACKNOWLEDGEMENT
The authors would like to acknowledge the contributions of the head
of Laboratoire d'études et développement des matériaux Semiconducteurs et diélectriques LeDMaScD of Laghouat University for
providing the necessary hardware and development tools.
REFERENCES
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(a)
(b)
(c)
Fig.11 (a) :Experimental results of filter
output line to line voltages Vab,Vbc,
(b):filter output Vab with modulating
frequency is set to 60Hz, (c): filter output
Vab with modulating frequency is set to
20Hz
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