Microprocessors and
Microcontrollers
Module – 1
Introduction
1
Internal organization of computing device
Microprocessor – Block Diagram
CPU
 Fetch, decode and executes the instruction stored in memory
 CPU must equipped with necessary resource
 Important resources of CPU:
 Registers – to store the information temporarily
 ALU – to carryout Arithmetic and Logical operation
 Program Counter – to point the next instruction to be
executed
 Instruction decoder – to interpret the instruction fetched into
the CPU
MEMORY











One of the important feature
Binary digits : 0’s and 1’s
Bit: 0 or 1
Nibble: 4-Bits or half a byte – ex:
0101
Byte: 8-Bit or Byte – ex:
1010 0101
Word : 16-bits – ex:
1111 0000 1010 0101
Kilo Byte: 210 = 1024 bytes, Mega : 220, Giga : 230, Tera : 240
Ex: 16 Megabyte = 16 x 220 = 24 x 220 =224 Bytes
Memory Types: RAM & ROM
RAM or Volatile Memory : Temporary storage
ROM or Non-volatile Memory : Permanent storage
Input and outputs
 I/O devices used to provide a communication with CPU via
keyboard, video monitor etc.,
Buses
 CPU is connected through stripes of wires called Buses
 Address bus: To identify the device connected to CPU. Total
number of memory location addressable by a CPU is 2x, where x
is the number of bits.
 Data Bus: To carry info. in and out of CPU, 8-bit to 64-bit
 Control bus: To provide the read or write signal to CPU
Steps to execute an instruction
1. Fetch Instruction from Memory
2. Decode Instruction and Fetch Operands
3. Perform ALU Operations
4. Store ALU result to register file
5. Memory Access (for load/store)
6. Update Program counter
 Microprocessor is a CPU on a single chip.
 Microprocessor has several support devices like ROM, Read
write memory, timer, serial interface, I/O ports, etc.
 All these support devices are
microprocessor through a system bus.
interfaced
to
the
 So finally we can conclude that all support devices in a
microprocessor are connected externally.
Microprocessor applications
•
•
•
•
•
•
•
•
•
Calculators
Accounting system
Games machine
Complex Industrial Controllers
Traffic light Control
Data acquisition systems
Multi user, multi-function environments
Military applications
Communication systems
Microprocessor Based Temperature Monitoring System
What was the first microprocessor?
History behind first microprocessor?
1969: The assignment
 Nippon Calculating Machine Corporation approached Intel to design 12 custom
chips for its new Busicom 141-PF* printing calculator.
The Intel solution
 lntel designed a set of four chips known as the MCS-4. It included CPU(4004), Shift registers(4003)
RAM(4002), ROM(4001)
1971: Era of integrated electronics
 Intel purchased the rights from Nippon Calculating Machine Corporation and launched the Intel®
4004 processor and its chipset with an advertisement in the November 15, 1971
History behind first microprocessor?
15
First Microprocessor 4004 - Inventors
Federico Faggin
Marcian "Ted" Hoff
Stanley Mazor
Masatoshi Shima
Evolution of Intel processors
Evolution of Intel processors (2)
18
Introduction
• Apple's A11 Bionic system-on-chip, also used in
the iPhone 8 and 8 Plus, which is a six-core
processor with two cores optimized for
performance
• Qualcomm Snapdragon. The Snapdragon was
used in the Tegra 2 of last year, as it was the first
to market with 1 GHz speeds.
• The Snapdragon was based on the ARM CortexA8
• Tegra processors used in smartphone and tablet
markets
18
Introduction
• Broadcom BCM2835 SoC used in the first
generation Raspberry Pi includes a 700
MHz ARM11 76JZF-S processor, VideoCore
IV graphics processing unit (GPU), and RAM
• Arduino Uno is a microcontroller board based
on the ATmega328P
• Intel Core i5 used in laptops
19
2
UNIT - I :
ECE3003 – Microcontroller and its
2
UNIT - I :
ECE3003 – Microcontroller and its
2
Microprocessors and
Microcontrollers
Module – 2
Introduction
26
Features of 8086
• It is an 16-bit microprocessor i.e. 8086 μp can read or
write or perform any arithmetic & logical operation
on 16-bit data at a time
• It is a 40 pin IC
• It can perform arithmetic operation on 8-bit or 16-bit
data including multiplication & division
• It can operate in single mode (Minimum mode) & in
multiprocessor mode (Maximum mode)
27
• It requires external clock generator
• It works on maximum clock frequency of 10
MHz & Minimum clock frequency of 5 MHz
• It has 16-bit data bus
• It provides 20 address line so 8086 μp can
access (220) = 1Mbytes of memory
• It requires single +5V power supply
• It contains 16-bit flag register
• It support multiprocessing
28
8086 Architecture
29
30
Internal Features
• It has ALU, flags, registers, instruction byte
queue and segment registers
• 8086 is divided into two independent
functional parts namely
– The Bus Interface Unit (BIU)
– Execution Unit (EU)
• Dividing work between two units speeds up the processing
32
Flag Register of 8086
8086 has 9 flags and they are divided into two
categories
 Condition code or status Flags
 Machine Control Flags
Carry Flag(CF):indicates an overflow condition for
unsigned integer arithmetic
Auxiliary Flag(AF):is set when carry/barrow from
the lower nibble. It is internally used by processor
during binary to BCD conversion
41
Memory Segmentation
• Physical address of 8086 is 20 bit wide to
access 1Mbyte memory.
• But the register and data line width are only
16 bit.
• Hence 1 MB memory can be divided into 16
segments.
• Each segment maximum size is 64 Kbytes.
• With in this segment 16 bit address are
accessed.
44
45
Generation of 20 bit Physical Address
• Content of the segment register is multiplied
by 16 (i.e.)Left shift the 4 bits by inserting
zeros.
For eg:Segment address->348AH-0011 0100 1000 1010
4 bit Left shifted ->0011 0100 1000 1010 0000
=348A0H
• Content of the Pointer register is summed
with shifted segment register
47
48
RQ/GT0 , RQ/GT1 –Bus Request/Bus Grant
• These pins are used by the other local bus master in
Max mode
• Force the processor to release the local bus
• It is similar to HOLD/HLDA of minimum mode
• Processor communicate that the request is granted
by grant signal
51
Physical Memory Organisation
• 1 Mbyte memory is physically organised as
odd bank and even bank each of 512 Kbytes
• Addressed in parallel
• Byte(word) data with even address is
transferred to D7-D0
• Byte data with odd address is transferred to
D15-D8
• BHE & A0 used to choose the banks
52
Addressing modes of 8086
• Indicates a way of locating data or operands
Types of addressing modes
1. Immediate addressing modes
2. Register addressing modes
3. Memory addressing modes
4. Control transfer addressing modes
53
Addressing modes
1. Immediate Addressing Mode
Data is part of instruction
Eg: MOV AX,0005H
2. Register Addressing mode
Data is available in the registers, data is moved from one
register to another except IP.
Eg: MOV AX,BX
54
Memory addressing Modes
3. Direct Addressing mode
• A 16 bit address/offset is directly specified in
instruction.
• Default segment is DS
• Effective address is calculated from the displacement
Eg: MOV AX,[5000H]
EA=10H*DS +5000H
55
Addressing modes
4. Register Indirect
• The address of the memory location is determined
in a indirect way using offset registers
• Offset data is in either BX or SI or DI registers
• Default segment is DS or ES
Eg: MOV AX,[BX]
EA=10H*DS +[BX]
56
Addressing modes
5.Indexed Addressing mode
• Offset is stored in one of the index registers
• DS is default for index register SI and DI
• In case of string instruction ES and DS are default
segments
Eg: MOV AX,[SI]
EA =10H*DS +[SI]
57
Addressing modes
6.Register Relative(Based with displacement)
• EA is formed by adding 8 or 16 bit displacement with
base register BX,BP,SI and DI
• Default segment is DS or ES
Eg: MOV AX,50H[BX]
EA=10H*DS + 50H+[BX]
58
Addressing modes
7.Based Indexed addressing mode
• EA is formed by adding the base register (BX or BP) to
the content of the index register (SI or DI)
• DS is the default segment
Eg: MOV AX,[BX][SI]
EA=10H*DS+[BX]+[SI]
59
Addressing modes
8.Relative Based Indexed addressing mode
• A 8 or 16 bit displacement is added with base
register(BX or BP) to the content of index register (SI
or DI)
Eg: MOV AX,50H[BX][SI]
EA= 10H*DS+[BX]+[SI]+50H
60
Control transfer addressing mode
9. Intra-segment Direct Mode
• Address to which the control to be transferred lies in
the same segment in which the control transfer
instruction lies.
• The address appears directly as an immediate
displacement value.
Eg: JMP 1010
61
Addressing modes
10. Intra-segment Indirect Mode
• Address to which the control to be transferred lies in
the same segment in which the control transfer
instruction lies.
• The address is passed indirectly
Eg: JMP [BX]
62
Addressing modes
11. Inter-segment Direct Mode
• Address to which the control to be transferred lies in
another code segment.
• CS and IP of destination address is specified directly
Ex. JMP 5000H:2000H
CS 5000H and IP 2000H
63
Addressing modes
12. Inter-segment Indirect Mode
• Address to which the control to be transferred lies in
another code segment.
• The address is passed indirectly
Ex. JMP [2000H]
2000H IP(LSB)
2001H IP(MSB)
2002H CS(LSB)
20003H CS(MSB)
64
Instruction Set of 8086
8086 instruction categorized as following types
1. Data Transfer
2. Arithmetic and Logic
3. Branch
4. Loop
5. Machine control
6. Flag Manipulation
7. Shift & Rotate
8. String
65
Data Transfer Instructions
• MOV – transfer data from one register/memory to
another register/memory
• PUSH –Pushes content of specified
register/memory into stack
-SP in decremented by 2
-PUSH AX ,PUSH [5000H]
• POP-content of top of stack is loaded in to AX
-SP is incremented by 2
-POP AX ,POP [5000H]
66
Instruction set
• XCHG :Exchange
- exchanges the content of specified source and
destination operands
- exchange of two memory locations not permitted
- XCHG BX,AX
• IN: Input the Port
-Reads the specified input port
-DX is only register allowed to carry port address
- IN AL,03H
- IN AX,DX
67
Instruction set
• OUT : Output the port
-Writes the data to specified port
- DX is the only register allowed to carry port
address
OUT 03H,AL
OUT DX,AX
68
LEA:Load Effective address
• Loads effective address formed by destination
operand into the specified source register
Eg:
LEA BX,ADR ;where ADR is label.offset of ADR
;will be transferred to BX
• LAHF :Load AH from Lower byte of flag
• SAHF :store AH to lower byte of flag register
• PUSHF:push flag to stack
• POPF:Pop flag from stack
69
Arithmetic & logical instruction
•
•
•
•
•
•
•
•
•
ADD
ADC
SUB
SBB
MUL
DIV
INC
DEC
CMP
if (destination – source) ==0 then set ZF=1
if (source>destination) then set CF=1 else CF=0
70
Arithmetic instructions
71
Increment - Decrement
• INC / DEC
– INC register
DEC register
– INC memory DEC memory
• EX.
– INC AX
– DEC BL
– How can we increment a byte of memory?
• INC ??? [100]
72
Add
•
•
•
•
•
ADD reg, imm
ADD reg, mem
ADD reg, reg
ADD mem, imm
ADD mem, reg
ADC reg, imm
ADC reg, mem
ADC reg, reg
ADC mem, imm
ADC mem, reg
73
EX. ADD
•
•
•
•
•
•
•
•
MOV
ADD
MOV
MOV
ADD
MOV
ADD
ADC
AL, 10h
AL, 20h
;AL =
BX, 200h
;BX =
WORD PTR [BX], 10h
WORD PTR [BX], 70h
AH, 89h
;AX =
AX, 9876h
;AX =
BX, 01h
;BX =
30h
0200h
8930h
21A6h
0202h ?
74
Subtract
•
•
•
•
•
SUB reg, imm
SUB reg, mem
SUB reg, reg
SUB mem, imm
SUB mem, reg
SBB reg, imm
SBB reg, mem
SBB reg, reg
SBB mem, imm
SBB mem, reg
75
Ex. SUB
•
•
•
•
•
•
•
•
MOV
ADD
MOV
MOV
SUB
MOV
SBB
SBB
AL, 10h
AL, 20h
;AL =
BX, 200h
;BX =
WORD PTR [BX], 10h
WORD PTR [BX], 70h
AH, 89h
;AX =
AX, 0001h
;AX =
AX, 0001h
;AX =
30h
0200h
8930h
892Eh ?
892Dh
76
Compare
•
•
•
•
CMP reg, imm
CMP reg, mem
CMP reg, reg
CMP mem, reg
• There is no “CMP mem, imm”
77
Ex. CMP
•
•
•
•
•
•
MOV
CMP
MOV
CMP
MOV
CMP
CX,
CX,
BX,
BX,
AX,
AX,
10h
20h
40h
40h
30h
20h
;Z=0,S=1,C=1,O=0
;Z=1,S=0,C=0,O=0
;Z=0,S=0,C=0,O=0
78
Negation
• Compute 2’complement.
• Carry flag always set.
• Usage
– NEG reg
– NEG mem
79
Ex. NEG
•
•
•
•
•
•
MOV
NEG
MOV
NEG
MOV
NEG
CX, 10h
CX
; CX = 0FFF0h
AX,0FFFFH
AX
; AX = 1
BX,1H
BX
; BX = 0FFFFh
80
Multiplication
• IMUL (Integer multiplication) unsigned
multiplication
• MUL (Multiplication) signed multiplication.
– MUL reg
– MUL mem
IMUL reg
IMUL mem
• Always perform with accumulator.
• Effected flag are only over and carry flag.
81
8 bit multiplication
• AL is multiplicand
• AX keep the result
• MOV AL,10h
• MOV CL,13h
• IMUL CL
; AL = 10h
; CL = 13h
; AX = 0130h
82
16 bit multiplication
• AX is multiplicand
• DX:AX keep the result
• MOV AX,0100h
; AX = 0100h
• MOV BX,1234h
; BX = 1234h
• IMUL BX
; DX = 0012h
; AX = 3400h
83
Division
• IDIV (Integer division) unsigned division.
• DIV (Division) signed division.
– DIV reg
– DIV mem
IDIV reg
IDIV mem
• Always perform with accumulator.
84
8 bit division
• AL is dividend
• AL keep the result
• AH keep the remainder
• MOV AX, 0017h
• MOV BX, 0010h
• DIV BL
; AX = 0701
85
16 bit Division
• DX:AX dividend.
• AX keep the result, DX keep the remainder.
•
•
•
•
MOV AX,4022h
MOV DX,0000h
MOV CX,1000h
DIV CX
;
;
;
;AX = 0004
;DX = 0022
86
Conversion
• Byte to Word : CBW
– Signed convert AL -> AX
• Word to Double word : CWD
– Signed convert AX -> DX:AX
87
Ex. Conversion
•
•
•
•
•
•
MOV AL,22h
CBW
; AX=0022h
MOV AL,F0h
CBW
; AX=FFF0h
MOV AX, 3422h
CWD
; DX=0000h
; AX=3422h
88
89
Instruction set
• AAA –ASCII Adjust After Addition
- instructions support BCD arithmetic
-corrects the results in AH,AL after addition when
working with BCD
Algorithm:
if low nibble of AL>9 or AF=1 then
AL=AL+6
AH=AH+1
CF=1 & AF=1
Else
AF=0 & CF=0
In both the cases clear the high nibble of AL
90
Instruction set
Eg:
ADD AL,BL ; where AL=BL=35H(ASCII equivalent 5)
AAA ;
AH=00 AL=6A
AL 0110 1010
+6
0110
0111 0000
AL=70
Higher nibble AL is set to 0
Add 1 to AH
Answer: AX=0100 (packed Decimal 10)
91
Instruction set
• AAS - ASCII Adjust after Subtraction
- Corrects AH,AL after the subtraction when
working with BCD
Algorithm
If the low nibble of AL >9 or AF=1 then
AL=AL-6
AH=AH-1
AF=1 & CF=1
Else
AF=0 & CF=0
In both the cases clear the higher nibble of AL
92
Instruction set
Eg :
• ASCII (9-5)
;AL=0011 1001,BL=0011 0101
SUB AL,BL ;RESULT AL=0000 0100 =BCD(04)
AAS
;RESULT AL=0000 0100
• ASCII(5-9)
SUB AL,BL ;RESULT 11111100 (-4) IN 2’S Compliment & CF=1
AAS
;RESULT 0000 0100 =BCD (04) & CF=1
93
Instruction set
• AAM –Adjust After Multiplication
– Adjust the AH,AL after multiplication when working
with BCD
– It works after multiplication
Example:
;AL=0000 0101 =BCD 5
;BH=0000 1001=BCD 9
MUL BH;result in AX=0000 0000 0010 1101 =002DH
AAM ;AX=0000 0100 0000 0101=0405
94
Instruction set
• AAD –ASCII Adjust Before Division
- Converts two unpacked BCD digits in AH & AL to
equivalent binary number in AL.
- Done before dividing the unpacked BCD in AX by an
unpacked BCD byte.
- After divisional contains unpacked BCD quotient .AH
contain remainder
Example:
;AX=0607 Unpacked BCD for 67 decimal
;CH=09 H, Now adjust to binary
AAD ;Result:AX=0043=43H=67 in decimal
DIV CH;Q:-AL=07 R:-Ah=04 unpacked BCD
95
Instruction set
• DAA –Decimal Adjust after Addition
– Corrects the result of addition of two packed BCD
Values
– Result addition must be in AL
Algorithm:
if low nibble of AL > 9 or AF = 1 then:
AL = AL + 6
AF = 1
if AL > 9F H or CF = 1 then:
AL = AL + 60 H
CF = 1
96
Eg:
Instruction set
;AL=0101 1001=59 BCD
;BL=0011 0101=35 BCD
ADD AL,BL ;AL=1000 1110=8EH
DAA
;AL =1001 0100=94 BCD
;AL=1000 1000=88 BCD
;BL=0100 1001=49 BCD
ADD AL,BL ;AL=1101 0001 AF=1
DAA
;AL=0011 0111=37 BCD ,CF=1
97
Instruction set
• DAS: Decimal Adjust after Subtraction
-Corrects the result of subtraction of two packed BCD
values
Algorithm:
if low nibble of AL > 9 or AF = 1 then:
AL = AL - 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL - 60h
CF = 1
98
Instruction set
• NEG: Negate instrution find the 2’s
complement of specified destination operands
Eg:
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh
NEG AL ; AL = 05h
99
Logical Instructions:
• AND – bit by bit AND operation with source
and destination operands
- Source operand may be immediate or register
or memory
- Destination operand may be register or
memory
Eg:
AND AX,0008H consider AX=3F0F
100
Instruction set
• OR -bit by bit OR operation with source and destination
operands
- Source operand may be immediate or register or
memory
- Destination operand may be register or memory
Eg: OR AX,008F consider AX=3F0F
• NOT- Complements the content of memory or register
Eg: NOT AX
101
Instruction set
• XOR - bit by bit XOR operation with source
and destination operands
Eg: XOR AX,0098H Consider AX=3F0F
• TEST -Logical AND between all bits of two
operands for flags only
-Result is not stored anywhere
-These flags are effected: ZF, SF, PF
Eg:
MOV AL, 00000101b
TEST AL, 1 ;
ZF = 0.
TEST AL, 10b ; ZF = 1.
102
SHIFT & Rotate Instruction
• SHL/SAL –Shift Logical Left/Arithmetic left
-Bit by bit left shift inserting zero at right most
position
-Operands cannot be a immediate data
-Flag get affected depending on the results
Eg:
MOV AL, 11100000b
SHL AL, 1 ;
AL = 11000000b, CF=1.
103
Instruction set
SHR:Shift Logical Right
-Bit wise right shift on the operand
-Zero is inserted to the Left most position
Eg:
MOV AL, 00000111b
SHR AL, 1 ;
AL = 00000011b, CF=1.
104
Instruction set
• SAR : Shift Arithmetic Right
-performs right shift
-it inserts MSB bit to the new position
Eg:
MOV AL, 0E0h ;
SAR AL, 1 ;
AL = 11100000b
AL = 11110000b, CF=0.
MOV BL, 4Ch ;
BL = 01001100b
SAR BL, 1 ;
BL = 00100110b, CF=0.
105
Instruction set
• RCL -Rotate Left through carry
106
Instruction set
• ROL -Rotate Left
107
Instruction set
• RCR –Rotate Right through carry
108
Instruction set
• ROR-Rotate Right
109
Control Flow Instructions
• Loop instruction
• Unconditional Jump
• Conditional Jump
• LOOP:-executes a part of pgm from label or address
Eg: loop label
• JMP :- unconditionally jumps to the label
Eg: JMP start or JMP 1024
110
Loop
• Base on CX (Counter register) to count the
loop.
• Instructions :
– LOOP
; Dec CX … 0
– LOOPZ
;CX<>0 and Z=1
– LOOPNZ
;CX<>0 and Z=0
– JCXZ
; Jump if CX=0, used with
LOOP to determine the CX before loop.
111
Instruction set
112
Instruction set
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
113
String Manipulation Instructions
• Series of data bytes or word stored in memory at
consecutive locations
• Each character may be represented by its ASCII
equivalent
• For referring to a string two parameters are required
– Start or End address of the string
– Length of the string (generally stored in CX)
• Increment and decrement of the pointer depends on
the Direction Flag(DF)
• If string is of type “byte” the pointer is updated by one
• if string is of type “Word” the pointer is updated by two
114
• REP: repeat instruction prefix
– Repeats execution until CX becomes zero
• REPE/REPZ ,REPNE/REPNZ ---these options
are used for CMPS,SCAS instructions only as
prefix
115
• CMPSB/CMPSW
It compares the string bytes or words
length of string must be stored in CX
if both strings are equal ZF is set
116
CMPS
Seg1 SEGMENT
String1 db “abcd”
Seg1 ENDS
Seg2 SEGMENT
String2 db “abcd”
Seg2 ENDS
Code SEGMENT
ASSUME CS:Code,DS:Seg1,ES:Seg2
START:
Mov AX,Seg1
Mov DS,AX
Mov AX,Seg2
Mov ES,AX
Mov SI,OFFSET String1
Mov DI,OFFSET String2
Mov CX,04h
CLD
REPE CMPS
Code ENDS
END START
117
• MOVSB/MOVSW
– It causes moving of byte or word from one string
to another
– In this instruction, the source string is in Data
Segment and destination string is in Extra
Segment
– SI and DI store the offset values for source and
destination index
118
Data segment
Stirng1 db “hello$”
Data ends
Extra segment
String2 db 20 dup(?)
Extra ends
Code segment
Assume CS:Code,DS:Data,ES:Extra
START:
Mov AX,Data
Mov DS,AX
LEA SI,String1
Mov AX,Extra
Mov ES,AX
LEA DI,String2
Mov cx,6
CLD
REP MOVSB
Code ENDS
END START
119
SCAS
• Scans a string of bytes or words for an
operand byte or word specified in AL or AX
register
• String is pointed to by ES:DI
• Whenever a match is found in the string ZF is
set
• If no match found ,ZF is reset
120
Mov AX,SEG
Mov ES,AX
Mov DI,OFFSET
Mov CX,010H
Mov AX,word
CLD
REPNE SCASW
121
• LODSB/LODSW :Load String Byte or String
Word Loads AL/AX register by the content of a
string pointed to by DS:SI
• STOSB/STOSW :Store String Byte or Word
Stores the AL/AX register contents to a
location in the string pointed by ES:DI
122
CALL :unconditional call
• Used to call a subroutine from main program
• Near CALL -displacement in the same segment
• Far CALL –displacement in the another segment
•
•
•
•
RET – Return from the procedure
INT N – Interrupt Type N
INTO – Interrupt on overflow
IRET – Return from ISR
123
Machine control Instructions
•
•
•
•
•
WAIT – wait for TEST input pin to go low
HLT – Halt the processor
NOP – No operation
ESC - Escape to external device like NDP
LOCK – Bus lock instruction prefix
124
Pin Configuration of 8086
125
Signal Description –Common for
MAX/MIN mode
AD15-AD0
• Time multiplexed I/O address and data lines
• Address available during T1 state
• Data available during T2,T3,Tw,T4 state
• Where T1,T2,T3,Tw&T4 are clock state of machine
cycle
A19/S6,A18/S5,A17/S4,A16/S3
• Time multiplexed address and status lines
• Address available during T1
• Status information available at T2,T3,Tw,T4
126
• S4 & S3 indicates segment registers currently used for
memory access
• S6 is always low
• S5 indicates interrupt enable flag bit
BHE/S7 –Bus High Enable
• Indicates the data transfer over D15-D8 higher order
• Used to select odd address memory banks
• Status information is available at T2,T3,T4
• S7 is not currently used
127
RD-Read
• When it is low indicates the peripherals that processor is performing
memory or I/O read operation
READY
• It indicates acknowledgement from the slow devices or memory that they
have completed data transfer
128
129
INTR-Interrupt request
• Level Triggered input
• When, it is 1 CPU prepares to service the interrupt
• If any Interrupt request is pending,CPU enters Interrupt ack cycle
TEST
• This is examined by the WAIT instruction
• If low, execution will continue
• Else processor remains idle
NMI-Non Mask able Interrupt
• This is edge triggered input
• NMI is not maskable internally by software
130
RESET -clears all the CS,DS,ES,SS and starts new execution
CLK -Clock input provided basic timing for processor and bus
control activity
VCC -+5V power supply
GND-ground
MN/MX- Decides whether the processor is to operate in either
Minimum mode (Single processor) Or Maximum Mode
(Multiprocessor)
131
Following pin function of Minimum
Mode operation
M/ I/0 –Memory / I/O
• When it is low indicates CPU is having I/O operation
• When it is high indicates CPU is having memory operation
INTA –Interrupt Acknowledgement
• When it goes low indicates processor has accepted the
interrupt
ALE –Address Latch Enable
• Indicates availability of valid address on address/data lines
132
DT/R – Data Transmit /Receive
• Decides the direction of flow through buffer
• If high, Processor sends data out
• Else ,Processor receives data
DEN –Data Enable
• Indicates availability of valid data address/data lines
• Used to enable transceivers to separate data from the
multiplexed address and data segment
133
HOLD/HLDA - Hold/Hold Ack
• When it is high ,indicates that another master is requesting
bus access
• On receiving HOLD request processor issues hold
acknowledgement HLDA
134
Following pin function are applicable for
Maximum Mode
S2,S1,S0 -Status Lines
• Indicates type of operation carried by the processor
135
LOCK
• While low,it indicates that the other system will be
prevented by accessing the system bus
QS1,QS0 -Queue Status
• Gives information about the status of code prefetch
queue(Instruction queue)
136
Minimum Mode
• Turns MN/MX pin to logic 1
• Control signals are given by microprocessor chip itself
• Single processor with latches ,transceivers, clock generators
,memory & I/O
• Latches are used to separate valid address from address/data
signals controlled by ALE
• Transceivers are bidirectional buffers controlled by DEN &
DT/R
137
Minimum mode
138
Minimum mode
• Working of Minimum mode can be described
in terms of timing diagrams
• There are two parts in timing diagram
1) read cycle
2)Write cycle
139
140
141
142
Maximum Mode
• Turns MN/MX pin to logic 0
• Control signals are given by external bus
controller
• There may be more than one microprocessor
• The bus controller(8288) has input lines
S0,S1,S2 and derives output lines
ALE,DEN,DT/R,MRDC,MWTC,AMWC,IORC,
IOWC and AIOWC
143
144
145
146
•
•
•
•
•
•
•
•
AEN-Address Enable
CEN-Control Enable
IOB-I/O bus mode
AIOWC-Advanced I/O write
IORC-I/O read command
IOWC-I/O write command
AMWT-Advanced Memory write
MWTC-Memory Write
147
8086 Interrupts
• Two types
– Internal
• initiated by the state of the CPU (e.g. divide by zero
error) or by an instruction.
– External Hardware interrupts
• occurs when a peripheral device asserts an INTR or NMI
• Maskable Interrupts and Non-Maskable Interrupts
148
Interrupt sequence on the 8086
1. External interface sends an interrupt signal, to the Interrupt
Request (INTR) pin, or an internal interrupt occurs
2. The CPU finishes the present instruction (for a hardware
interrupt) and sends Interrupt Acknowledge (INTA) to
hardware interface
3. The interrupt type N is sent to the Central Processor Unit
(CPU)
4. The contents of the flag registers are pushed onto the stack.
149
5.Both the interrupt (IF) and (TF) flags are cleared
6.The contents of the code segment register (CS) are pushed
onto the Stack.
7. The contents of the instruction pointer (IP) are pushed
onto the Stack.
8.The interrupt vector contents are fetched
9. While returning from the interrupt-service routine by the
Interrupt Return (IRET) instruction, the IP, CS and Flag
registers are popped from the Stack
150
IVT
151
152
153
154
INT 21h / AH=25h - set interrupt vector;
input: AL = interrupt number. DS:DX -> new interrupt handler.
INT 21h / AH= 40h - write to file.
entry:
BX = file handle.
CX = number of bytes to write.
DS:DX -> data to write.
return:
CF clear if successful; AX = number of bytes actually written.
CF set on error; AX = error code.
note: if CX is zero, no data is written, and the file is truncated or
extended to the current position data is written beginning at the current file position,
and the file position is updated after a successful write the
usual cause for AX < CX on return is a full disk.
155
INT 21h / AH= 3Ch - create or truncate file.
entry:
CX = file attributes:
mov cx, 0 ; normal - no attributes.
mov cx, 1 ; read-only.
mov cx, 2 ; hidden.
mov cx, 4 ; system
mov cx, 7 ;hidden, system and read-only!
mov cx, 16 ; archive
DS:DX -> ASCIZ filename.
returns:
CF clear if successful, AX = file handle.
CF set on error AX = error code.
156
data segment
msg db "procedure executed$"
data ends
code segment
assume cs:code,ds:data
start:
mov ax,data
mov ds,ax
call foo
Hlt
foo proc
lea dx,msg
mov ah,09
int 21h
ret
foo endp
code ends
end start
157
8086 ASSEMBLER DIRECTIVES
• SEGMENT
– The SEGMENT directive is used to indicate the
start of a logical segmen
• ENDS (END SEGMENT)
– indicate the end of that logical segment
• END
– tell the assembler that this is the end of the
program module
158
• ASSUME
– Tells the assembler the name of the logical
segment it should use for a specified segment
• DB (DEFINE BYTE)
– used to declare a byte type variable
– PRICES DB 49H, 98H, 29H
– NAMES DB “THOMAS”
– TEMP DB 100 DUP (?)
159
•
•
•
•
DD (DEFINE DOUBLE WORD)
DQ (DEFINE QUADWORD)
DT (DEFINE TEN BYTES)
DW (DEFINE WORD)
• EQU (EQUATE)
– used to give a name to some value or symbol
– CONTROL EQU 11000110 B
160
• LENGTH
– an operator, which tells the assembler to
determine the number of elements in some
named data item, such as a string or an array
– MOV CX, LENGTH STRING1
161
• OFFSET
– tells the assembler to determine the offset or
displacement of a named data item (variable), a
procedure from the start of the segment, which
contains it.
– MOV BX, OFFSET PRICES
162
• PTR (POINTER)
– used to assign a specific type to a variable or a
label
– It is necessary to do this in any instruction where
the type of the operand is not clear
– INC [BX] either to increment by byte or word
– INC BYTE PTR [BX] increment by byte
– INC WORD PTR [BX]
163
• EVEN (ALIGN ON EVEN MEMORY ADDRESS)
– tells the assembler to increment the location
counter to the next even address, if it is not
already at an even address
164
• PROC (PROCEDURE)
• ENDP (END PROCEDURE)
• ORG (ORIGIN)
165
• EXTRN
– used to tell the assembler that the name or labels
following the directive are in some other assembly
module
• PUBLIC
– any variable name or label referred to in other
modules must be declared PUBLIC in the module
in which it is defined
166
Passing parameters to procedures
1.
2.
3.
4.
5.
Using global declared variable
Using registers of CPU
Using memory locations
Using stack
Using PUBLIC & EXTRN
167
MACRO
• Can be defined any where in program using
directive MACRO and ENDM
DISPLAY MACRO
MOV AX,SEG MSG
MOV DS,AX
MOV DX,OFFSET MSG
MOV AH,09H
INT 21H
ENDM
168
Passing parameters to MACRO
MyMacro MACRO p1, p2, p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM
Code SEGMENT
MyMacro 1, 2, 3 ;Calling & passing parameter
MyMacro 4, 5, DX ;Calling & passing parameter
Code ENDS
169
Parallel port -Serial port
170
Programmable Peripheral interface -8255
Features:
• Designed by Intel to interface with 8,16 bit & higher
capability microprocessor with I/O peripherals
• It has 24 i/o lines which may be programmed in to two
groups of 12 lines or three groups of 8 lines
• The two group i/o pins named as GROUP A and GROUP B
• Each group contains a two sub group of 8 bit i/o lines & 4
bit i/o lines
• Group A contains an 8 bit port A along with a 4 bit port C
called Cupper
• Group B contains an 8 bit port B along with a bit port C
called
Clower
171
8255 Pin diagram
•
•
•
•
•
•
•
•
•
PA7-PA0 buffered/latched i/o 8 bit PORT A
PB7-PB0 buffered/latched i/o 8 bit PORT B
PC7-PC4 Upper nibble of PORT C
PC3-PC0 Lower nibble of PORT C
RD –Read
WR-Write
CS-Chip Select
A0-A1 Address Lines
D0-D7 Data Lines carries DATA or Control
Word to/from processor
• RESET Clears control word registers
172
8255 internal Architecture
173
• Data Bus Buffer
• This bi-directional 8-bit buffer is used to interface the 8255
to the system data bus.
• Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU.
• Control words information is transferred through the data
bus buffer.
• Read/Write and Control Logic
• This block is to manage all of the internal and external
transfers of both Data and Control words
• It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control
Groups
174
• (CS) Chip Select
A "low" on this input pin enables the
communication between the 8255 and the CPU
• (RD) Read
A "low" on this input pin enables 8255 to send
the data or status information to the CPU on the
data bus
• (WR) Write
A "low" on this input pin enables the CPU to write
data or control words into the 8255
175
• (A0 and A1) Port Select 0 and Port Select 1
• These input signals, in conjunction with the
RD and WR inputs, control the selection of
one of the three ports or the control word
register
176
Control Word Register
177
There are 2 basic modes of operations
– I/O Mode (Mode 0,Mode1 & Mode2)
– Bit Set – Reset mode (BSR)
178
BSR Mode
• In this mode any of the 8 bit of port C can be set or reset
depending on D0 of the control word
• The bit to be set or reset is selected by D1,D2 & D3 of the
control word register
179
• Eg: If the 5th bit (PC5) of port C has to be "SET", then what is
the control word?
1. Since it is BSR mode, D7 = '0'.
2. Since D4, D5, D6 are not used, assume them to be '0'.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
4. PC5 has to be set, hence, D0 = '1'.
• Applying the above values to the format for BSR
mode, we get the control word as "0B (hex)".
180
Mode 0(Basic I/O mode)
• Features of this mode
• Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and
lower ) are available. The two 4-bit ports can be combinedly used as a
third 8-bit port.
• Any port can be used as an input or output port
• Output ports are latched. Input ports are not latched
• A maximum of four ports are available so that overall 16 I/O configuration
are possible.
• All these modes can be selected by programming the Control word
register. CWR has two formats one for BSR mode and I/O modes
181
182
183
184
185
186
Mode 1 (Strobed I/O mode)
• In this mode hand shaking signals controls the i/o operation
• Port C lines PC0,PC1 & PC2 provides the handshake signals
for port B
• Port C lines P3,PC6 & PC7 provides the handshake signals
for port A
• PC4 & PC5 can be used as independent I/O lines
Input Control Signal Definitions
• STB(Strobe input) : when it is low, data from the data lines
are loaded into the latches
• IBF (Input buffer full):if it rises high, indicates data loaded
into latches ( Acknowledgement )
187
Mode 2(Strobed bi directional I/O)
• Only 8 bit in group A is available
• The 8 bit port A is bidirectional & have 5 bit
port control lines(PC3-PC7)
• 3 I/O lines are available at port C (PC2-PC0)
188
Addressing 8255
189