Review Article
Terminal voltage analysis for the
transformerless PV inverter topologies in a
single-phase system
ISSN 1752-1416
Received on 25th January 2019
Revised 22nd June 2019
Accepted on 13th August 2019
E-First on 23rd October 2019
doi: 10.1049/iet-rpg.2019.0106
www.ietdl.org
Venu Sonti1, Sachin Jain2 , Vivek Agarwal3, Subhashish Bhattacharya4
1Department
of Electrical and Electronics Engineering, VR Siddhartha College of Engineering, Vijayawada, India
of Electrical Engineering, NIT Raipur, Raipur, India
3Department of Electrical Engineering, IIT Bombay, Mumbai, India
4Department of Electrical and Computer Science Engineering, NC State University, Raleigh, USA
E-mail: sjain.ee@nitrr.ac.in
2Department
Abstract: This study presents an analysis of the terminal voltage of the basic photovoltaic (PV) inverter topologies available in
the literature. The presented analysis utilises the switching function concept. Use of switching function in the analysis enables
the inclusion of the effect of the pulse-width modulation technique or the switching strategy on the terminal voltage of the
reviewed configuration. It gives insight into the switching action effects on the terminal voltage and provides every detail of the
high-frequency transitions in the terminal voltage for the given switching strategy. Using the terminal voltage expression derived
in terms of switching function, the analytical waveforms are obtained for various configurations. These waveforms are compared
with the simulation and experimental results waveforms to justify the analysis given. This study also presents a bar chart view of
the switching and conduction losses of the switches in the reviewed PV inverter topologies. The magnitude of high-frequency
components in the terminal voltage and the leakage current is also presented in this study. The PV inverter topologies are also
compared in terms of other aspects such as a number of devices used, asymmetry in operation, filter requirement etc.
1 Introduction
An inverter [1–7] is the heart of a photovoltaic (PV) system in all
its applications, which require an AC output. These inverters are
desired to have key features such as low cost, higher efficiency,
low leakage current, three or higher levels in the output voltage for
the better power utility, reduced size, low weight etc. Therefore, a
careful study is required for selecting the most appropriate PV
inverter topology for the given application. The PV inverter
topologies are broadly classified into two categories based on the
presence or absence of the galvanic isolation transformer in the
system. The presence of transformer [8–11] in the PV system adds
to the cost, a number of stages (i.e. more than two stages) and
losses. Thus, the inclusion of a transformer is typically not
preferred in terms of efficiency, size, weight and cost of the system.
Owing to these reasons, transformerless topologies [11–20] are
becoming increasingly popular.
The transformerless PV inverters have all the advantages
related to the size, cost, weight and efficiency. However, the
elimination of transformer results in the loss of galvanic isolation
between the input PV array and the output of the system. Thus,
there is a direct path for the leakage current [21, 22] to flow
through the PV array into the system via inherent parasitic
capacitances in the system. The flow of leakage current leads to
issues such as the safety of the person in contact with the PV array,
electromagnetic interference, increased losses etc. In an attempt to
regulate or control the leakage current in a system, standards such
as the VDE0126–1–1 [23–25] have been developed, which restricts
the magnitude of the leakage current in a PV system. The standard
stipulates that the magnitude of the leakage current cannot exceed
300 mA. In the literature, many solutions are available for leakage
current minimisation in the transformerless PV inverters [26–30].
One approach for minimisation of leakage current is by isolating
the PV array and the grid/standalone load during the zero state.
This action results in reducing the high-frequency transitions in the
terminal voltage [31]. Reduction in the high-frequency transitions
in the terminal voltage results in minimisation of the leakage
current through the parasitic capacitance. Another approach for
minimisation of leakage current is by using the passive filters to
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attenuate the high-frequency components in the circuit [31]. On the
basis of these two approaches, many PV inverter topologies are
proposed and reviewed in the literatures [32–35].
Khan et al. [31] have proposed another interesting review on
PV inverter topologies. The authors have discussed in detail the
two approaches for minimisation of leakage current in PV
inverters. The first approach is based on the topology and pulsewidth modulation (PWM) modification for minimisation of leakage
current. The second approach is based on usage of passive filters.
An effective comparison based on the operation of the PV inverter
topologies is discussed in this paper. However, still the
mathematical analysis giving the detailed expression for the
terminal voltage, which indirectly represents cause, effect and
remedy for the leakage current for various PV inverter topologies,
is missing. Another elegant review giving the classification of PV
inverters is done by Li et al. [36]. The authors have briefly
categorised the various existing PV inverter topologies in the
literature based on symmetric or asymmetric structure, coupling
circuit used etc. However, the concepts such as effect of the PWM
strategy on the terminal voltage or leakage current, comparison of
the topologies for detailed analysis of the leakage current etc. are
missing.
Jana et al. [37] have given a review of the recent PV inverter
topologies. In this review paper, the authors have given a brief
discussion on the classification of the PV inverter topologies based
on centralised, string, multi-string and AC module arrangements of
the PV array. The authors have further classified the PV inverters
based on the number of power conditioning stages, the position of
the DC electrolytic capacitor and usage of line-frequency and highfrequency transformers. In the category of the transformerless PV
inverters, the authors have discussed various important topologies
such as highly efficient reliable inverter configuration (HERIC),
H5 and various three-level inverter topologies. The authors have
also discussed various multi-level inverter topologies such as halfbridge diode-clamped, full-bridge diode-clamped and cascaded
inverter topology to be used for PV inverter application. Finally,
the authors have compared all the topologies in various vital
aspects such as power rating, the number of switches and diodes
used, power decoupling, expected lifetime and expected cost. Thus,
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conventional H-bridge inverter, is quite useful and can be extended
to other PV inverter topologies as well as for the study of the
leakage current.
This paper extends the analysis [46], which shows the effect of
switching states on the PV terminal voltage and leakage current for
other inverter topologies. Using the presented analysis, the PWM
technique can be studied to analyse the effect of the high-frequency
switching transitions on the terminal voltage. Furthermore, a
detailed analyses of the various high-frequency components in the
terminal voltage and the leakage current for the basic PV inverter
configurations are also given. The comparison between various PV
inverter topologies along with the loss calculations is also
presented in this paper. The paper is divided into four sections.
Section 2 presents the analysis of the terminal voltage for various
PV inverter topologies along with the analytical results. The
simulation and the experimental results for the considered PV
inverter topologies are shown in Section 3. The comparison details
of the various PV inverter topologies are discussed in Section 3.
The main conclusion of the work is summarised in Section 4.
2 Analysis of terminal voltage for various PV
inverter topologies
The analysis of the leakage current flowing through the parasitic
capacitance of the PV array for various PV inverter topologies can
be done using the terminal voltage expressions. In this paper, the
expressions for the terminal voltage are derived for various
configurations of grid-tied PV inverter systems. The inverter output
voltage vpq is connected to grid vg via an LCL filter. The terms Lis
and Lgs refer to the PV inverter side and grid-side filter inductors,
respectively, as shown in Fig. 1a. The terms Rd and Cd refer to the
damping resistor and the filter capacitor, respectively. The currents
ipq, id and ig refer to the inverter output current, the current flowing
through the damping branch and the current flowing into the grid,
respectively. The resistance Rg refers to the resistance between the
grid and node g. The capacitor CPV is the buffer capacitor between
the PV array and the inverter. The voltage across the capacitor CPV
is represented as VPV. The connection of parasitic elements in the
PV array is shown with dotted lines. The parasitic elements are
connected to the positive terminal (node a) of the PV array. The
negative terminal of the PV array is represented as node b. The
terms Rp and Cp refer to the equivalent parasitic resistor and
capacitor of the PV array, respectively. The equivalent parasitic
resistor and capacitor is the simplified representation of the series
connection of the parasitic resistor and capacitor at positive and
negative terminals of the PV array [31]. The term ileak represents
the leakage current flowing in the parasitic branch of the PV array.
The parasitic capacitor in the PV array forms a resonant circuit
with the low-pass filter at the inverter output [22]. At the resonant
frequency, the circuit offers minimum impedance, which results in
the flow of high magnitude leakage current at the resonant
frequency [22].
The terminal voltage expressions for different PV inverter
topologies are expressed in terms of switching functions of the
individual switches of the inverter, grid voltage vg and the PV array
voltage VPV. The switches in the inverter topologies are
represented by Swx, where x = 1, 2, 3, …. The switching states of
the individual switch Swx are denoted by Sx, where x = 1, 2, 3, ….
The pulses for the individual switches are generated using the
conventional sinusoidal PWM (SPWM) technique, where the
modulating sinusoidal reference wave is compared with the
triangular carrier wave. Using the switching function variables,
grid voltage vg and the PV array voltage VPV, the expressions for
the terminal voltage have been derived. Once the terminal voltage
expressions are obtained, then the analytical waveforms of the
terminal voltages vag and vbg are plotted in MATLAB/Simulink. In
the present case, the terminal voltage waveforms are obtained by
considering the parameters vg = 230 V (root mean square), the
frequency of grid voltage fg = 50 Hz, PV array voltage VPV = 400 V
and switching frequency of the inverter fsw = 500 Hz. This is done
to depict the switching transitions in the terminal voltage.
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good information was given for the PV inverter topologies.
However, the review paper having the comparison concerning
leakage current, expression of the terminal voltage in terms of
PWM strategy and circuit configuration, ratings of the different
components etc. for different PV inverter topologies are still
missing.
Another good review has been carried out by Meneses et al.
[38] for the transformerless step-up PV inverter topologies for AC
modules or micro-inverters. The authors have classified the PV
inverter topologies into three categories such as two-stage
topologies, pseudo-DC-link topologies and single-stage topologies.
An elegant comparison of the different PV inverter topologies is
made based on the design and rating of various components such as
the inductor, DC electrolytic capacitors etc. along with the
grounding options of the PV array. The authors have also compared
the efficiency of the various inverter topologies given in this paper.
Another useful review has been carried out by Islam et al. [39] on
the transformerless PV inverter topologies. Useful information on
various grid standards such as IEEE 1547.1–2005, IEC61727, EN
50106 and VDE0126-1-1 is explained in this paper. The
transformerless inverter topologies have been classified into the
categories such as zero state decouple topologies, zero-state
midpoint clamp topologies and solidity clamp topologies. Various
PV inverter topologies, which fall into these categories, have been
explained evidently. The given inverter topologies are then
compared in terms of the number of switches and diodes required,
the number of capacitors on the input side, efficiency and leakage
current. Thus, a good review is given on the PV inverters for three
and higher levels of operation. However, a study or review is still
needed that relates the PWM or switching strategy of the basic PV
inverters with the analysis of leakage current. It is important since
the PWM or the switching strategy has a significant effect on the
leakage current performance of a PV system [40].
A good review paper on leakage current for the basic PV
inverter configurations has been written by Lopez et al. [41]. The
authors have simulated and analysed the leakage current for PV
full-bridge inverter using unipolar and bipolar PWM techniques.
The characteristics of the leakage current are discussed by
analysing the magnitude of different high-frequency components in
the terminal voltage. However, the authors have not given any
analytical expression for the terminal voltage. Also, the leakage
current fast Fourier transform (FFT) spectrum analysis for other
basic PV inverter topologies such as H5, HERIC and H6 are
missing. Another good review paper based on the basic equivalent
circuit analysis for the derivation of common and differential mode
voltage (CDMV) for various PV inverter configurations is given by
Gubía et al. [42]. In this paper, the authors have explained the
leakage or ground current flow using the concept of CDMV. The
authors have given complex analysis, which requires an equivalent
circuit for each switching state. On the basis of the same equivalent
circuit analysis, another interesting paper for cascaded multi-level
inverter configurations is authored by Zhou and Li [43]. The
authors have given an analysis that takes into account the commonmode inductor and capacitor in the equivalent circuit during each
switching state. The given analysis is further simplified using pole
voltages. However, the authors have not considered the effect of
the PWM technique or switching state on the PV terminals.
Another important analysis of the leakage current is given by Xiao
and Xie [44]. The analytical expression for the leakage current is
obtained in terms of equivalent circuit impedances. However, the
given expression looks very complicated since it contains complex
impedance terms and the required PWM strategy for the
minimisation of the leakage current is difficult to study. Dong et al.
[45] have proposed one good solution for leakage current
elimination in the PV inverter. The expression for leakage current
is represented in terms of the Fourier series. Using the given
expression, the magnitude of leakage current at various frequencies
can be obtained. However, the authors have not considered the
effect of the PWM strategy or modulation scheme on the leakage
current. Hedayati and John [46] have proposed one such analysis,
which explains or takes into account the switching states for the
analysis of the terminal and common-mode voltages. The analysis,
given to the unipolar and bipolar PWM techniques for a
vbg = vag − V PV
(1)
The pole voltages vpg and vqg are expressed in terms of the terminal
voltages vag and vbg as
vpg = S1vag + (1 − S1)vbg
(2)
vqg = S3vag + (1 − S3)vbg
(3)
The voltages vpg and vqg are also expressed in terms of the grid
voltage vg and voltage drops in filter inductors (Lis and Lgs) as [46]
vpg =
Lis dipq Lgs dig
+
+ vg − Rgileak
2 dt
2 dt
(4)
Lis di′pq Lgs di′g
+
− Rgileak
2 dt
2 dt
(5)
vqg =
Fig. 1 Analysis of terminal voltage for various PV inverter topologies
(a) Schematic representation of the PV full-bridge inverter connected to a grid via an
LCL filter, (b) Modes of operation of full-bridge inverter for the levels VPV, 0 and
−VPV, (c) Generation of pulses for the switches Sw1, Sw2, Sw3 and Sw4 from the
reference wave and carrier wave, the output voltage of the inverter vpq, analytical
waveforms of the terminal voltages vag and vbg from the expressions
2.1 Full-bridge inverter with unipolar PWM technique
Fig. 1a shows the complete schematic representation of the PV
full-bridge inverter connected to the grid via an LCL filter, as
described in previous sections. The output voltage of the inverter
consists of three levels (i.e. VPV, 0 and −VPV) in the case of
unipolar PWM technique [47]. The full-bridge inverter uses four
switches Sw1, Sw2, Sw3 and Sw4 for the generation of three levels
at the output terminals. The pairs of switches (Sw1, Sw2) and (Sw3,
Sw4) are operated in a complementary manner. The various modes
of operation of the full-bridge inverter with the unipolar PWM
technique are shown in Fig. 1b. Whenever the switches Sw1 and
Sw4 are turned ON, the inverter output voltage becomes VPV.
Similarly, the inverter output voltage attains −VPV, if the switches
Sw2 and Sw3 are turned ON. For the 0 voltage level, either of the
top switches pair (Sw1 and Sw3) or bottom switches pair (Sw2 and
Sw4) is turned ON. Hence, the inverter output current freewheels
through the top or the bottom pair of switches.
Fig. 1c shows the waveforms of the generated gate pulses for
the switches, output and the terminal voltages for the full-bridge
inverter using the unipolar PWM technique. The unipolar PWM
technique uses two modulating/reference waves (i.e. reference
wave-1 and reference wave-2), which are in-phase opposition as
shown in Fig. 1c. The two generated reference waves are now
compared with a single carrier wave at low-frequency operation
(ten times the modulating frequency is chosen to show clearly the
switching transitions within the cycle). This generates the PWM
pulses for top switches of each leg of the inverter. Thus, in the case
of unipolar PWM technique, each leg of the inverter is controlled
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Adding (4) and (5) by assuming the currents ipq = −ipq′ and ig = −ig′
(Fig. 1) and neglecting the drop in Rg gives
vpg + vqg = vg
(6)
Adding (2) and (3) and substituting in (6) gives
vg = S1 + S3 vag + 1 − S1 + 1 − S3 vbg
(7)
Substituting (1) into (7) and simplifying gives
vag = 0.5vg + 0.5 1 − S1 + 1 − S3 V PV
(8)
During the active states of the inverter output voltage (i.e. VPV or
−VPV), either the switch pair (Sw1, Sw4) or (Sw2, Sw3) is turned
ON. Substituting the switching states (or switching function value)
of the switches for the active states of the inverter output voltage in
(8) results in
vag = 0.5vg + 0.5V PV
(9)
Similarly, during the zero state, for the switch pair combination
(Sw1, Sw3), the magnitude of the terminal voltage vag is equal to
vag = 0.5vg
(10)
Now, the value of terminal voltage during zero state using the
bottom switch pair (Sw2, Sw4) is given by
vag = 0.5vg + V PV
(11)
Similarly, the waveform of the other terminal voltage vbg can be
obtained from (1) by substituting the value of vag. Thus, in the
unipolar PWM technique, the terminal voltage switches between
three values are derived in (9)–(11). This can be easily verified in
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independently. Reference wave-1 controls the first leg of the
inverter and reference wave-2 controls the second leg. If the
magnitude of reference wave-1 is greater than the carrier wave,
then the switch Sw1 is turned ON else turned OFF. Similarly, if the
magnitude of reference wave-2 is greater than the carrier wave, the
switch Sw3 is turned ON, else turned OFF. With the unipolar PWM
technique, the inverter output voltage switches between the levels
VPV and 0 during the positive half cycle of the grid voltage. During
the negative half cycle of the grid voltage, the inverter output
switches between the levels 0 and −VPV which can be easily
observed from the waveform of the output voltage in Fig. 1c.
Owing to the switching action of the individual switches, the
inverter along with the output voltage generates the terminal
voltages vag and vbg at the nodes a and b concerning the ground.
From Fig. 1a, the terminal voltages vag and vbg are related as
2.2 Full-bridge inverter with bipolar PWM technique
Fig. 2 Full-bridge inverter with bipolar PWM technique
(a) Modes of operation of full-bridge inverter for the levels VPV and −VPV, (b)
Generation of pulses for the switches Sw1, Sw2, Sw3 and Sw4 from the reference wave
and carrier wave, the output voltage of the inverter vpq, analytical waveforms of the
terminal voltages vag and vbg from the expressions
The circuit schematic representation for full-bridge inverter
remains the same as shown in Fig. 1a. Unlike the unipolar PWM
technique, the output voltage of the inverter has two levels (i.e.
VPV and −VPV) in the case of the bipolar PWM technique [47]. The
two modes of operation of the full-bridge inverter using the bipolar
PWM technique are shown in Fig. 2a. Whenever the switches Sw1
and Sw4 are turned ON, the inverter output voltage becomes VPV.
Similarly, the inverter output voltage attains −VPV, if the switches
Sw2 and Sw4 are turned ON.
The waveforms of the gate pulses for the switches, output
voltage and the terminal voltage of the full-bridge inverter with
bipolar PWM technique are shown in Fig. 2b. The bipolar PWM
technique uses only one reference wave and a carrier wave. The
switch pair (Sw1 and Sw4) is turned ON whenever the magnitude of
the reference wave is greater than the carrier wave. Otherwise, the
other switch pair (Sw2 and Sw3) is turned ON. The inverter output
voltage oscillates within the levels VPV and −VPV during the
complete cycle of the grid voltage. This can also be observed from
the waveform of the output voltage in Fig. 2b. In the bipolar PWM
technique, the pairs of switches (Sw1 and Sw3) or (Sw2 and Sw4) are
not turned ON simultaneously due to the absence of 0 state. So, for
the complete cycle of the output voltage, either switch Sw1 or Sw3
is turned ON. Substituting the values of switching states of the
switches in (8), the terminal voltage vag for the bipolar PWM
technique is expressed as
vag = 0.5vg + 0.5V PV
(12)
The magnitude of the terminal voltage vag is equal to the average of
the instantaneous magnitude of grid voltage vg and the PV array
output voltage VPV. From (12), it can be observed that the terminal
voltage in the case of bipolar PWM technique is free from the
effect of switching states. Thus, the terminal voltage is a lowfrequency (grid frequency) sine wave with a DC offset equal to 0.5
times the PV array voltage VPV. This avoids the high-frequency
switching transitions in the terminal voltages. The waveforms of
the terminal voltages vag and vbg, shown in Fig. 2b, are obtained
using (1) and (12). From the waveforms, it can be depicted that the
terminal voltages in the case of bipolar PWM technique are free
from high-frequency switching transitions.
2.3 H5 inverter topology
Fig. 3 H5 inverter topology
(a) Schematic representation of the H5 inverter connected to a grid via an LCL filter,
(b) Modes of operation of H5 for the levels VPV, −VPV and 0, (c) Generation of
pulses for the switches Sw1, Sw2, Sw3, Sw4 and Sw5 from the reference wave and
carrier wave, the output voltage of the inverter vpq, analytical waveforms of the
terminal voltages vag and vbg from the expressions
4
Fig. 3a gives the circuit schematic representation diagram for H5
inverter [48] topology for grid-tied PV inverter. It consists of an Hbridge inverter with an additional switch Sw5. The switch Sw5 is
used to isolate the grid and PV array during the 0 state or
freewheeling state. The pairs of switches (Sw1, Sw2) and (Sw3, Sw4)
operate in a complementary mode. The H5 inverter also generates
three levels in the output voltage. Fig. 3b shows the modes of
operation of the H5 inverter for the three voltage levels VPV, 0 and
−VPV. The voltage level VPV is obtained whenever the switches
Sw1, Sw4 and Sw5 are turned ON. Similarly, the voltage level −VPV
is obtained if the switches Sw2, Sw3 and Sw5 are turned ON. During
the 0 voltage level, the switch Sw5 is turned OFF and the top
switches Sw1 and Sw3 are kept in turned ON state so that the
inverter output current freewheels through the two switches. This
provides isolation between the two sources, i.e. grid and PV array.
Fig. 3c shows the generation of pulses for the switches, output
voltage and the terminal voltage of the H5 inverter. The H5
inverter requires two triangular carrier waves (upper wave and
lower wave) which are level shifted by 1 V and one reference wave
as shown in Fig. 3c. Whenever, the magnitude of the reference
wave is greater than the upper carrier wave, the switches Sw1, Sw4
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the waveforms of the terminal voltages given in Fig. 1c. The given
terminal voltage waveform in Fig. 1c is drawn using the
expressions of vag and vbg derived above.
(17)
Equation (17) is the same as what was obtained for unipolar and
bipolar PWM during the active state. Now, during the 0 voltage
level, the switch Sw5 is turned OFF and the other switches Sw1 and
Sw3 are turned ON. Hence, the magnitude of the terminal voltage
vag becomes
vag = ∞
(18)
Fig. 3c shows the waveforms of the terminal voltages vag and vbg
obtained from (16) and (1). It can be observed that the terminal
voltages are free from the high-frequency switching transitions
such as in the case of bipolar PWM technique.
2.4 HERIC inverter topology
vpg = S5S1vag + (1 − S1)vbg
(13)
The schematic representation of HERIC topology [49], connected
to the grid via an LCL filter, is shown in Fig. 4a. The term HERIC
refers to highly efficient and reliable inverter configuration. The
HERIC topology consists of an H-bridge inverter and the bidirectional switches Sw5 and Sw6. The switches Sw5 and Sw6
provide a freewheeling path for the inductor current at the 0
voltage level. The HERIC topology also generates three levels of
the output voltage.
The modes of operation of HERIC inverter for the voltage
levels VPV, 0 and −VPV are shown in Fig. 4b. The voltage level VPV
is obtained whenever the switches Sw1 are Sw4 are turned ON.
Similarly, the voltage level −VPV is obtained if the switches Sw2
and Sw3 are turned ON. For 0 voltage level, grid current is
freewheeled through AC-by-pass switches Sw5 and Sw6. The
switches Sw5 and Sw6 are kept turned ON during the negative and
positive half cycles of the grid voltage, respectively. During 0
voltage level, the grid inductor current ipq (in Fig. 4a) freewheels
through the AC-by-pass switches Sw5 and Sw6. All the switches in
H-bridge are turned OFF at the 0 voltage level. The turn-OFF
switches in H-bridge during 0 voltage level result in isolation of
grid and PV array [47].
The generation of pulses for the switches, output voltage and
terminal voltage waveforms for HERIC inverter are shown in
Fig. 4c. The HERIC inverter requires one reference wave and twolevel-shifted carrier waves. Whenever the magnitude of the
reference wave is greater than the upper carrier wave, the switches
Sw1 and Sw4 are turned ON. Similarly, whenever the magnitude of
the reference wave is less than the bottom carrier wave, the
switches Sw2 and Sw3 are turned ON. From the waveform of output
voltage shown in Fig. 4c, it can be observed that during the
positive half cycle of the grid voltage, the HERIC output voltage
varies between VPV and 0. Similarly, in the negative half cycle of
the grid voltage, the inverter output varies within the levels 0 and
−VPV. The derivation for the terminal voltage vag for the HERIC is
given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
vqg = S5S3vag + (1 − S3)vbg
(14)
vpg = S1vag + S2vbg
(19)
vqg = S3vag + S4vbg
(20)
Fig. 4 HERIC inverter topology
(a) Schematic representation of the HERIC inverter connected to a grid via an LCL
filter, (b) Modes of operation of HERIC for the levels VPV, −VPV and 0, (c)
Generation of pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5 and Sw6 from the
reference wave and carrier wave, the output voltage of the inverter vpq, analytical
waveforms of the terminal voltages vag and vbg from the expressions
and Sw5 are turned ON. Similarly, whenever the magnitude of the
reference wave is less than the bottom carrier wave, the switches
Sw2, Sw3 and Sw5 are turned ON. The 0 voltage level occurs
whenever the magnitude of the reference wave is less than upper
carrier wave and greater than the bottom carrier wave.
The H5 inverter output voltage oscillates within the levels VPV
and 0 during a positive half cycle of the grid voltage. During the
negative half cycle of the grid voltage, the inverter output varies
within the levels 0 and −VPV, which can also be observed from the
waveform of the output voltage in Fig. 3c. The derivation for the
terminal voltage vag is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
Adding (13) and (14) and substituting into (6) gives
vg = S5 S1 + S3 vag + 1 − S1 + 1 − S3 vbg
(15)
Substituting (1) into (15) and simplifying gives
vag =
vg + 1 − S1 + 1 − S3 V PV
S5 S1 + S3 + 1 − S1 + 1 − S3
vg = S1 + S3 vag + S2 + S4 vbg
(16)
The switch pair (Sw1, Sw4) or (Sw2, Sw3) are turned ON along with
the switch Sw5 during the active states (i.e. VPV or −VPV).
Substituting the switching states of these switches in (16) for the
active states, results in terminal voltage vag given by
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Adding (19) and (20) assuming the currents iab = −iab and ig = −ig
and neglecting the drop in Rg and substituting in (6) gives
(21)
Substituting (1) into (21) and then simplifying gives
vag =
vg + V PV S2 + S4
S1 + S2 + S3 + S4
(22)
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vag = 0.5vg + 0.5V PV
vpg = S1S5vag + S2vbg
(25)
vqg = S6vag + S4vbg
(26)
Adding (25) and (26) assuming the currents iab = −iab and ig = −ig
and neglecting the drop in Rg and substituting (6) gives
vg = S6 + S1S5 vag + S2 + S4 vbg
Fig. 5 H6 inverter topology
(a) Schematic representation of the H6 inverter connected to a grid via an LCL filter,
(b) Modes of operation of H6 for the levels VPV, −VPV and 0, (c) Generation of
pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5 and Sw6 from the reference wave
and carrier wave, the output voltage of the inverter vpq, analytical waveforms of the
terminal voltages vag and vbg from the expressions
The switch pair (Sw1, Sw4) or (Sw2, Sw3) is turned ON along with
the switch Sw6 or Sw5 in the active states (i.e. VPV or −VPV).
Substituting the switching states of these switches in (22) during
the active states gives
vag = 0.5vg + 0.5V PV
(23)
During the 0 voltage level, the switches Sw1, Sw2, Sw3 and Sw4 are
turned OFF and the other switches Sw5 and Sw6 are turned ON.
From (23), the value of the terminal voltage vag is equal to
vag = ∞
(24)
Fig. 4c shows the waveforms of the terminal voltages vag and vbg
obtained from (22) and (1). It can be observed that the terminal
voltages are free from the high-frequency switching transitions
resembling the case of bipolar PWM technique and H5 inverter.
2.5 H6 inverter topology
The schematic representation of H6 inverter topology [50]
connected to the grid via an LCL filter is shown in Fig. 5a. The H6
inverter topology consists of an H-bridge inverter with an
additional two switches Sw5 and Sw6. There is only one
complementary switch pair (i.e. Sw1 and Sw3). The H6 inverter also
gives three levels of the output voltage. The modes of operation of
the H6 inverter for the voltage levels VPV, 0 and −VPV are shown in
Fig. 5b. The voltage level VPV is obtained whenever the switches
6
(27)
Substituting (1) into (27) and then simplifying gives
vag =
vg + V PV S2 + S4
S1S5 + S2 + S4 + S6
(28)
The switch pair (Sw1, Sw4 and Sw5) or (Sw2, Sw6) are turned ON in
the active states (i.e. VPV or −VPV). Substituting the switching
states of these switches in (28) for the results of the active state in
vag = 0.5vg + 0.5V PV
(29)
During the 0 voltage level, all the switches are turned OFF, except
the switches Sw1 and Sw3. From (28), the magnitude of the
terminal voltage vag becomes
vag = ∞
(30)
Fig. 5c shows the waveforms of the terminal voltages vag and vbg
obtained from (18) and (1). It can be observed that the terminal
voltages are free from the high-frequency switching transitions as
in the previous cases, except for the unipolar PWM technique.
2.6 Neutral point clamped (NPC) full-bridge topologies for
transformerless PV grid-tied inverter proposed by Zhang et
al. [51]
The schematic representation of inverter topology [51] connected
to the grid via an LCL filter is shown in Fig. 6a. The inverter
topology consists of eight switches Sw1–Sw8. The input PV voltage
to the inverter is split into two halves with the help of two equal
value capacitors, as shown in Fig. 6a. The inverter topology [51]
also generates three levels in the output voltage. The modes of
operation of the inverter for the voltage levels VPV, 0 and −VPV is
shown in Fig. 6b. The voltage level VPV is obtained whenever the
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Sw1, Sw4 and Sw5 are turned ON. Similarly, the voltage level −VPV
is obtained, if the switches Sw2 and Sw6 are turned ON. During the
0 voltage level, the inverter output current freewheels among the
switches Sw1 and Sw3. This results in the isolations of the grid and
PV array.
The generation of pulses for the switches, output and terminal
voltage waveforms in the case of the H6 inverter is shown in
Fig. 5c. The H6 inverter requires two-level-shifted carrier waves
and one reference wave. Whenever the magnitude of the reference
wave is greater than the upper carrier wave, the switches Sw4 and
Sw5 are turned ON. Similarly, whenever the magnitude of the
reference wave is less than the bottom carrier wave, the switches
Sw2 and Sw6 are turned ON. The 0 voltage level occurs whenever
the magnitude of the reference wave lies in between both the
carrier waves. The switch Sw1 is kept in turned ON state during the
positive half cycle of the grid voltage. Similarly, the switch Sw3 is
kept in turned ON state during the negative half cycle of the grid
voltage. The H6 inverter output voltage oscillates within the levels
VPV and 0 during a positive half cycle of the grid voltage. During
the negative half cycle of the grid voltage, the inverter output
varies within the levels 0 and −VPV, which can also be observed
from the waveform of the output voltage in Fig. 5c. The derivation
of the terminal voltage is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
V PV
2
(31)
vqg = S4vag + S5S6vbg + S8 vag −
V PV
2
(32)
Adding (31) and (32) and substituting (26) gives
vg = S1S2 + S4 vag + S3 + S5S6 vbg
+ S7 + S8 vag −
V PV
2
(33)
Substituting (1) into (33) and then simplifying gives
V PV
S S + S5S8
2 2 7
S1S2 + S3 + S4 + S5S6 + S7 + S8
vg + V PV S3 + S5S6 +
vag =
(34)
The switch pair (Sw1, Sw2, Sw5, Sw6) or (Sw3, Sw4) are turned ON
in the active states (i.e. VPV or −VPV). Substituting the switching
states of these switches in (34) results in
vag = 0.5vg + 0.5V PV
(35)
During the 0 voltage level, all the switches other than Sw2, Sw5,
Sw7 and Sw8 are turned OFF. From (34), the magnitude of the
terminal voltage vag becomes
vag = 0.5vg + 0.5V PV
(36)
Fig. 6c shows the waveforms of the terminal voltages vag and vbg
obtained from (34) and (1). It can be observed that there is no
undefined state in the terminal voltages. Thus, the terminal voltage
is matching with that obtained from bipolar PWM.
Fig. 6 NPC full-bridge topologies
(a) Schematic representation of the PV inverter topology proposed by Zhang et al.
connected to a grid via an LCL filter, (b) Modes of operation of H6 for the levels VPV,
2.7 H6-type transformerless single-phase inverter for gridtied PV system by Islam and Mekhilef [52]
−VPV and 0, (c) Generation of pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5, Sw6,
Sw7 and Sw8 from the reference wave and carrier wave, the output voltage of the
The schematic representation of inverter topology [52], connected
to the grid via an LCL filter, is shown in Fig. 7a. The given
inverter topology consists of six switches Sw1–Sw6. The given
inverter topology also generates three levels in the output voltage.
The modes of operation of the given inverter for the voltage levels
VPV, 0 and −VPV are shown in Fig. 7b. The voltage level ‘VPV’ is
obtained whenever the switches Sw1, Sw4 and Sw6 are turned ON.
Similarly, the voltage level −VPV is obtained if the switches Sw2,
Sw3 and Sw5 are turned ON. For 0 voltage level, grid current is
freewheeled through the switches Sw5 and Sw6. The switches Sw5
and Sw6 are kept turned ON during one-half cycle of the grid
voltage and operate at a high switching frequency in the other half
cycle, respectively. During 0 voltage level, the grid inductor
current ipq freewheels through the switches Sw5 and Sw6. The
remaining switches Sw1–Sw4 are turned OFF at the 0 voltage level.
The turn-OFF switches Sw1–Sw4 during 0 voltage level results in
the isolation of grid and PV array. Therefore, the given inverter
topology uses the AC decoupling methodology for the
minimisation of leakage current in the PV systems.
The generation of pulses for the switches, output voltage and
terminal voltage waveforms for given inverter are shown in
Fig. 7c. The given inverter requires one reference wave and two
carrier waves, which are level shifted by 1 V. Whenever the
magnitude of the reference wave is greater than the upper carrier
wave, the switches Sw1, Sw4 and Sw6 are turned ON. Similarly,
whenever the magnitude of the reference wave is less than the
bottom carrier wave, the switches Sw2, Sw3 and Sw5 are turned ON.
From the waveform of output voltage shown in Fig. 7c, it can be
observed that during the positive half cycle of the grid voltage, the
inverter output voltage varies between VPV and 0. Similarly, in the
negative half cycle of the grid voltage, the inverter output varies
inverter vpq, analytical waveforms of the terminal voltages vag and vbg from the
expressions
switches Sw1, Sw2, Sw5 and Sw6 are turned ON. Similarly, the
voltage level −VPV is obtained, if the switches Sw3 and Sw4 are
turned ON. During the 0 voltage level, the inverter output current
freewheels among the switches Sw2, Sw5, Sw7 and Sw8. This helps
in clamping the terminal voltage during zero state. Therefore, the
given inverter topology uses NPC methodology for the
minimisation of leakage current in the PV systems.
The generation of pulses for the switches, output and terminal
voltage waveforms of the given inverter is shown in Fig. 6c. The
inverter requires two carrier waves which are level shifted by 1 V.
Whenever the magnitude of the reference wave is greater than the
upper carrier wave, the switches Sw1, Sw2, Sw5 and Sw6 are turned
ON. Similarly, whenever the magnitude of the reference wave is
less than the bottom carrier wave, the switches Sw3 and Sw4 are
turned ON. The 0 voltage level occurs whenever the magnitude of
reference wave lies in between both the carrier waves. The
switches Sw2 and Sw5 are kept in turned ON state during the
positive half cycle of the grid voltage. Similarly, the switches Sw7
and Sw8 are kept in turned ON state during the negative half cycle
of the grid voltage. The given inverter output voltage oscillates
within the levels VPV and 0 during a positive half cycle of the grid
voltage. During the negative half cycle of the grid voltage, the
inverter output varies within the levels of 0 and −VPV. The
derivation of the terminal voltage is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
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vpg = S1S2vag + S3vbg + S7 vag −
Fig. 7c shows the waveforms of the terminal voltages vag and vbg
obtained from (40) and (1). It can be observed that the terminal
voltages are free from the high-frequency switching transitions,
due to the presence of undefined state as in H5 or HERIC
configuration. Also, the terminal voltage is matching with that
obtained from H5 or HERIC configuration.
2.8 Quasi-unipolar SPWM full-bridge transformerless PV
grid-connected inverter with constant common-mode voltage
by Xiao et al. [53]
Fig. 7 H6-type transformerless single-phase inverter
(a) Schematic representation of the PV inverter topology proposed by Islam et al.
connected to a grid via an LCL filter, (b) Modes of operation of H6 for the levels VPV,
−VPV and 0, (c) Generation of pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5 and
Sw6 from the reference wave and carrier wave, the output voltage of the inverter vpq,
analytical waveforms of the terminal voltages vag and vbg from the expressions
within the levels of 0 and −VPV. The derivation for the terminal
voltage vag for the inverter topology [52] is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
vpg = S1vag + S2S5vbg
(37)
vqg = S3vag + S6S4vbg
(38)
The schematic representation of inverter topology [53] connected
to the grid via an LCL filter is shown in Fig. 8a. The given inverter
topology consists of an H-bridge inverter formed by switches Sw1–
Sw4, the AC-by-pass switches Sw5 and Sw6 and four diodes D1 and
D4. The input PV voltage to the inverter is split into two halves
with the help of two equal value capacitors as shown in Fig. 8a.
The inverter topology [53] also generates three levels in the output
voltage. The modes of operation of the inverter for the voltage
levels VPV, 0 and −VPV is shown in Fig. 8b. The voltage level VPV
is obtained whenever the switches Sw1 and Sw4 are turned ON.
Similarly, the voltage level −VPV is obtained, if the switches Sw2
and Sw3 are turned ON. During 0 voltage level, the grid inductor
current ipq freewheels through the AC-by-pass switches Sw5 and
Sw6. All the switches in H-bridge are turned OFF at the 0 voltage
level. The turn-OFF switches in H-bridge during 0 voltage level
result in the isolation of grid and PV array. Therefore, the given
inverter topology uses NPC methodology for the minimisation of
leakage current in the PV systems.
The generation of pulses for the switches, output and terminal
voltage waveforms of the given inverter is shown in Fig. 8c. The
inverter requires two carrier waves which are level shifted by 1 V.
Whenever the magnitude of the reference wave is greater than the
upper carrier wave, the switches Sw1 and Sw4 are turned ON.
Similarly, whenever the magnitude of the reference wave is less
than the bottom carrier wave, the switches Sw2 and Sw3 are turned
ON. The 0 voltage level occurs whenever the magnitude of
reference wave lies in between both the carrier waves. The
switches Sw1 and Sw4 operate at higher switching frequency during
the positive half cycle of the grid voltage. Similarly, the switches
Sw2 and Sw3 operate at higher switching frequency during the
negative half cycle of the grid voltage. The given inverter output
voltage oscillates within the levels VPV and 0 during a positive half
cycle of the grid voltage. During the negative half cycle of the grid
voltage, the inverter output varies within the levels 0 and −VPV.
The derivation of the terminal voltage is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
Adding (37) and (38) and substituting into (6) gives
vg = S1 + S3 vag + S2S5 + S4S6 vbg
vg + V PV S5S2 + S4S6
S1 + S3 + S5S2 + S4S6
(40)
vqg = S3vag + S4vbg + S6 1 − S3 vag −
V PV
2
(44)
Adding (43) and (44) and substituting (6) gives
+ S5 + S6 1 − S1 vag −
V PV
2
(45)
Substituting (1) into (45) and then simplifying gives
(41)
During the 0 voltage level, the switches Sw1, Sw2, Sw3 and Sw4 are
turned OFF and the other switches Sw5 and Sw6 are turned ON.
From (40), the value of the terminal voltage vag is equal to
8
(43)
vg = S1 + S3 vag + S2 + S4 vbg
The switch pair (Sw1, Sw4, Sw6) or (Sw2, Sw3, Sw5) are turned ON
in the active states (i.e. VPV or −VPV). Substituting the switching
states of these switches in (40) results in.
vag = 0.5vg + 0.5V PV
V PV
2
(39)
Substituting (1) into (39) and then simplifying gives
vag =
vpg = S1vag + S2vbg + S5 1 − S1 vag −
V PV
S 1 − S1 + S6 1 − S3
2 5
S1 + S2 + S3 + S4 + S5 1 − S1 + S6 1 − S3
vg + V PV S2 + S4 +
vag =
(46)
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(42)
vag = ∞
(a) Schematic representation of the PV inverter topology proposed by Xiao et al.
connected to a grid via an LCL filter, (b) Modes of operation of H6 for the levels VPV,
−VPV and 0, (c) Generation of pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5 and
Sw6 from the reference wave and carrier wave, the output voltage of the inverter vpq,
analytical waveforms of the terminal voltages vag and vbg from the expressions
The switch pair (Sw1, Sw4) or (Sw2, Sw3) are turned ON in the
active states (i.e. VPV or −VPV). Substituting the switching states of
these switches in (46) results in
vag = 0.5vg + 0.5V PV
(47)
During the 0 voltage level, all the switches other than Sw5 and Sw6
are turned OFF. From (46), the magnitude of the terminal voltage
vag becomes
vag = 0.5eg + 0.5V PV
(48)
Fig. 8c shows the waveforms of the terminal voltages vag and vbg
obtained from (1) and (46). It can be observed that there is no
undefined state in the terminal voltages such as the case of inverter
topology proposed by Zhang et al.
2.9 High-efficiency single-phase transformerless PV H6
inverter with a hybrid modulation method by Ji et al. [54]
The schematic representation of inverter topology [54], connected
to the grid via an LCL filter, is shown in Fig. 9a. The given
inverter topology consists of six switches Sw1–Sw6 and two diodes
D1 and D2. The given inverter topology also generates three levels
in the output voltage. The modes of operation of the given inverter
for the voltage levels VPV, 0 and −VPV are shown in Fig. 9b. The
voltage level VPV is obtained whenever the switches Sw1, Sw4 and
Sw5 are turned ON. Similarly, the voltage level −VPV is obtained if
the switches Sw2, Sw3 and Sw6 are turned ON. For 0 voltage level,
grid current is freewheeled through the switches Sw5 and Sw6. The
switches Sw5 and Sw6 are kept turned ON during the positive and
negative half cycles of the grid voltage, respectively. During 0
voltage level, the grid inductor current ipq freewheels through the
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Fig. 9 High-efficiency single-phase transformerless PV H6 inverter
(a) Schematic representation of the PV inverter topology proposed by Ji et al.
connected to a grid via an LCL filter, (b) Modes of operation of H6 for the levels VPV,
−VPV and 0, (c) Generation of pulses for the switches Sw1, Sw2, Sw3, Sw4, Sw5 and
Sw6 from the reference wave and carrier wave, the output voltage of the inverter vpq,
analytical waveforms of the terminal voltages vag and vbg from the expressions
switches Sw5 and Sw6. The remaining switches Sw1–Sw4 are turned
OFF at the 0 voltage level. The turn-OFF switches Sw1–Sw4 during
0 voltage level results in the isolation of grid and PV array.
Therefore, the given inverter topology uses AC decoupling
methodology for the minimisation of leakage current in the PV
systems.
The generation of pulses for the switches, output voltage and
terminal voltage waveforms for given inverter are shown in
Fig. 9c. The given inverter requires one reference wave and two
carrier waves, which are level shifted by 1 V. Whenever the
magnitude of the reference wave is greater than the upper carrier
wave, the switches Sw1, Sw4 and Sw5 are turned ON. Similarly,
whenever the magnitude of the reference wave is less than the
bottom carrier wave, the switches Sw2, Sw3 and Sw6 are turned ON.
From the waveform of output voltage shown in Fig. 9c, it can be
observed that during the positive half cycle of the grid voltage, the
inverter output voltage varies between VPV and 0. Similarly, in the
negative half cycle of the grid voltage, the inverter output varies
within the levels 0 and −VPV. The derivation for the terminal
voltage vag for the given inverter topology is given below.
The pole voltages vpg and vqg are expressed in terms of the
terminal voltages vag and vbg as
vpg = S1vag + S2S5vbg
(49)
vqg = S3vag + S6S4vbg
(50)
9
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Fig. 8 Quasi-unipolar SPWM full-bridge transformerless PV gridconnected inverter
vg = S1 + S3 vag + S2S5 + S4S6 vbg
(51)
Substituting (1) into (51) and then simplifying gives
vag =
vg + V PV S3 + S4
S1S5 + S2S6 + S3 + S4
(52)
The switch pair (Sw1, Sw4, Sw5) or (Sw2, Sw3, Sw6) are turned ON
in the active states (i.e. VPV or −VPV). Substituting the switching
states of these switches in (52) results in
vag = 0.5vg + 0.5V PV
Table 1 Parameters considered for the simulation
Parameter
Value
Parameter
Value
p
2.7 kW
Rg
0.1 Ω
VDC
400 V
Li
4 mH
fsw
10 kHz
Cf
0.1 µF
vac
230 V
Rd
50 mΩ
fac
50 Hz
Cp
200 nF
Lac
4 mH
Rp
1Ω
Rac
0.01 Ω
—
—
(53)
During the 0 voltage level, the switches Sw1, Sw2, Sw3 and Sw4 are
turned OFF and the other switches Sw5 and Sw6 are turned ON.
From (52), the value of the terminal voltage vag is equal to
vag = ∞
(54)
Fig. 9c shows the waveforms of the terminal voltages vag and vbg
obtained from (1) and (52). It can be observed that the terminal
voltages are free from the high-frequency switching transitions.
Moreover, the terminal voltage waveform is similar to that
obtained from Islam and Mekhilef [52].
3 Results and discussion
3.1 Simulation of various PV inverter topologies discussed
To justify the given analysis, the PV inverter topologies explained
in the previous section are simulated in the MATLAB software
using POWERSIM block sets. The parameters used in the
simulation are listed in Table 1. The magnitude of the output
voltage of inverter vpq and the phase δ [47] to deliver an active
power P remains the same in all the considered configurations.
Using the parameters given in Table 1, the value of the resonance
frequency (fr) obtained from (55) is around 5 kHz. Owing to this
reason, the parasitic capacitance offers low impedance to the
leakage current at a resonant frequency of 5 kHz
fr =
1
1
2π
L + Lac C p
4 i
(55)
Fig. 10 shows the simulated waveforms for (i) full-bridge
inverter with bipolar PWM technique and (ii) full-bridge inverter
with unipolar PWM technique. The subplots (a) and (b) of Fig. 10
show the gating pulses for the switches in full-bridge inverter using
bipolar and unipolar PWM techniques. The switches in the Hbridge operate at a higher frequency during the complete cycle of
the output voltage for both unipolar and bipolar PWM techniques.
This can be observed in subplots (a) and (b) of Fig. 10. The
generated PWM pulses are given to their respective switches for
the generation of the required inverter output voltage and grid
current. The subplots (c) and (d) of Fig. 10 show the waveforms of
inverter output voltage and grid current for the bipolar and unipolar
PWM techniques. The comparatively high magnitude of ripple
current content and total harmonic distortion (THD) can be
observed from the subplots of the current waveforms in the case of
two-level operation (bipolar PWM technique). The subplots (e) and
(f) show the waveforms of the terminal voltage vag and leakage
current along with their FFT spectrum. The presence of highfrequency switching transitions in the terminal voltage results in
the flow of the significant amount of leakage current through the
parasitic capacitor. This can be verified by the plot of leakage
current waveform for unipolar PWM. It clearly shows that the
magnitude of leakage current is quite high in the case of unipolar
PWM in comparison with the bipolar PWM. Another interesting
thing to be noted from the FFT plot is that the magnitude of
leakage at the resonant frequency (5 kHz) is quite high for unipolar
10
Fig. 10 Simulation waveforms for
(a) Full-bridge inverter with bipolar PWM technique, (b) Full-bridge inverter with
unipolar PWM technique
PWM technique. The low-value leakage current in bipolar PWM
can be supported with the low-frequency terminal voltage
waveform.
The simulation waveforms for (i) H5, (ii) HERIC and (iii) H6
PV inverter topologies are shown in Fig. 11. Furthermore, it can be
observed in the previous section that the terminal voltage
waveform for the other derived configurations is matching with
one of the five configurations discussed above. Thus, it would be
justified to perform the analysis of the considered five
configurations in simulation and experiments. The gating pulses for
the switches in (i) H5, (ii) HERIC and (iii) H6 PV inverter
topologies are shown in subplots (a)–(c), respectively, of Fig. 11.
The subplots (d) and (e) of Fig. 11 shows the waveforms of the
output voltage and the grid current for the PV inverter topologies.
The PV inverter topologies considered have three levels of the
output voltage, as can be observed in subplot (d) of Fig. 11. Also,
the THD of grid current for the three topologies is almost nearly
the same. The waveforms of the terminal voltage vag and leakage
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Adding (49) and (50) and substituting into (6) gives
(a) H5 inverter topology, (b) HERIC inverter topology, (c) H6 inverter topology
current along with their FFT are shown in subplots (f) and (g) of
Fig. 11. It can be observed that the leakage current is almost the
same in all three PV inverter topologies. Also, the magnitude of the
terminal voltage and leakage current components at the resonant
frequency are small in all the three topologies.
3.2 Discussion on high-frequency components in terminal
voltage and leakage current for the PV inverters
The magnitudes of various high-frequency components
(frequencies which are multiples of switching frequencies [22] and
the resonant frequency [22] formed by parasitic capacitance) in the
terminal voltage and leakage current obtained from the simulation
results are summarised in Table 2. Since the parasitic capacitance
offers a high impedance for the low-frequency components, the
magnitudes of low-frequency components are not considered in
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Table 2. It can be observed that the magnitude of high-frequency
components in the terminal voltage and leakage current is very
small or nearly zero in the case of bipolar PWM technique when
compared with other topologies shown in Table 2. This can be
attributed to the continuous low-frequency (50 Hz) terminal
voltages waveform. The parasitic capacitance offers very high
impedance to the low-frequency terminal voltage resulting in a
very low leakage current flowing through it. Thus, bipolar PWM
technique results in negligible leakage current compared with the
other reviewed topologies.
Furthermore, the leakage current in the cases of H5, H6 and
HERIC configurations are also less, which can be justified with the
discontinuous low-frequency terminal voltage waveform.
Discontinuity in the waveform occurs during the freewheeling
period and thus results in a low-value leakage current [40, 55].
11
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Fig. 11 Simulation waveforms for
topology, kHz
5
10
20
30
40
50
60
70
80
90
100
bipolar
1.01 × 10–7 1.37 × 10–4 9.47 × 10–6 1.71 × 10–6 8.69 × 10–7 4.51 × 10–7 2.39 × 10–7 1.84 × 10–7 1.10 × 10–7 8.90 × 10–8 8.86 × 10–9
unipolar
0.788639 270.9256 0.091015 2.717886 0.010904 0.459475 0.006903 0.183505 0.005801 0.053875 0.001872
H5
0.012459 0.512846 0.117687 0.038902 0.032978 0.028978 0.016542 0.013218 0.011312 0.010179 0.007843
HERIC
0.010697 0.50918 0.200985 0.088434 0.041919 0.032559 0.018969 0.016423 0.011342 0.010311 0.007837
H6
0.010548 0.51375 0.201013 0.088889 0.042530 0.033601 0.019201 0.015991 0.011012 0.010308 0.008005
Magnitude of high-frequency components in leakage current, A
topology, kHz
5
10
20
30
40
50
60
70
80
90
100
–9
–6
–7
–8
–8
–8
–8
–8
–9
–9
bipolar
7.46 × 10 1.73 × 10 2.56 × 10 6.03 × 10 3.91 × 10 2.41 × 10 1.44 × 10 1.23 × 10 7.73 × 10 6.73 × 10 2.52 × 10–9
unipolar
H5
HERIC
H6
0.01649 3.379078
9.57 × 10–5 0.006459
9.31e-05 0.006413
9.25e-05 0.006464
0.001117
0.004967
0.096124
0.003139
0.000603
0.001915
0.019893
0.001747
0.000435
0.001157
0.012271
0.001096
0.000418
0.000807
0.007199
0.000768
0.000247
0.000619
0.004694
0.004456
0.0031
0.00305
0.001881
0.001658
0.00173
0.00172
0.001144
0.001140
0.001088
0.001452
0.000809
0.001002
0.000778
0.000745
0.000619
0.000595
Furthermore, during the freewheeling period inverter switches
being all tuned-OFF completely isolate the PV source and the grid
in the cases of H5, H6 and HERIC configurations. Finally, in the
case of unipolar PWM technique, the presence of high-frequency
transitions in the terminal voltage can be easily verified with
analytical expressions and also can be observed in the simulation
waveforms of the terminal voltage. Thus, the magnitude of highfrequency components in terminal voltage and leakage current is
quite high in case of the unipolar PWM technique compared with
the other compared topologies. Another interesting observation can
be derived from Table 2. The magnitude of the terminal voltage at
the frequency nearly ten times (50 kHz) the resonant frequency is
less than its resonant frequency (i.e. 5 kHz) in the full-bridge
inverter with unipolar PWM technique. In the case of other PV
inverter topologies, the magnitude of the terminal voltage at the 50
kHz frequency is greater than its resonant frequency component.
Also, it can be observed that the magnitude of leakage current at
resonant frequencies is negligible in H5, HERIC and H6. This is
due to the discontinuity in the resonant circuit during zero state.
3.3 Discussion on conduction and switching losses in various
PV inverter topologies
From the subplots (a), (b) of Fig. 10 and the subplots (a)–(c) of
Fig. 11 giving the switching strategy, the switching and conduction
losses for the various PV inverter topologies can be calculated [54,
56]. The parameters shown in Table 1 were used for the calculation
of switching and conduction losses. Fig. 12 shows the bar graph of
(i) conduction and (ii) switching losses of the switches in various
PV inverter topologies discussed in this paper. The switching and
conduction losses of the switches in the unipolar and bipolar PWM
technique are almost the same. However, the overall efficiency of
the bipolar scheme is quite low. This can be attributed to the power
fed back during the turn-OFF period of the switching cycle and
increased core losses in the filter inductor [57] due to two-level
operation.
In the case of H5 inverter topology, due to the high-frequency
operation of the switch Sw5 in both the half cycles of the grid
voltage, the switching loss of switch Sw5 is quite high. Also, the
top switches of both the legs of the inverter are kept in a turn-ON
state during the freewheeling period for both the cycles of the
output voltage. This results in higher conduction losses as can be
observed in Fig. 12a. In the case of HERIC configuration, inverter
isolates the PV array and the grid/load during the freewheeling
period. This is achieved by turning OFF the inverter switches
during the turn-OFF or freewheeling period of the switching cycle.
The output current freewheels through the AC-by-pass switches
Sw5 and Sw6. These switches are operated during the freewheeling
period of both half cycles of the grid voltage. However, the output
current flows through the switches Sw5 and Sw6 only during zero
state. As a result, the conduction loss of these switches is almost
same as the Sw1 and Sw4 in the H-bridge. The switches Sw1 and
Sw4 in the H-bridge operated at a higher switching frequency in
12
one of the positive half cycles and turned OFF during the negative
half cycle. The other pair of switches Sw2 and Sw3 operated at a
higher switching frequency in the negative half cycle and turned
OFF during the positive half cycle. Owing to this, the switching
and conduction losses of the switches Sw1–Sw4 are almost the same
in the case of HERIC inverter topologies. In the case of H6 inverter
topology, the switch Sw1 operates at low frequency (grid
frequency). As a result, the conduction loss of the switch Sw1 is
high as seen in Fig. 12a. The other switch Sw3 also operates at low
frequency. The output current flows through Sw3 only at the zerovoltage level, and in the voltage –VPV the switch remains in a turnON state, and no current flows through the switch. Hence, the
conduction loss of the switch Sw3 is less than the switch Sw1. The
switches Sw4 and Sw5 are operated at high frequency during the
positive half cycle and remain turned OFF during the negative half
cycle. The other switches Sw2 and Sw6 are operated at highfrequency during the negative half cycle and remain turned OFF in
the positive half cycle. So the switches Sw2, Sw4, Sw5 and Sw6 have
almost similar switching and conduction losses.
In the case of PV inverter topology proposed by Zhang et al.,
the switches Sw1 and Sw6 operate at higher switching frequency in
the positive half cycle and remains turned OFF during the negative
half cycle. The other pair of switches Sw3 and Sw4 operate at
higher switching frequency in the negative half cycle and remains
turned OFF during the positive half cycle. Owing to which, the
switching and conduction losses of switches Sw1, Sw3, Sw4 and
Sw6 are same. The switches Sw2 and Sw5 remain turned ON in the
positive half cycle. As a result, the conduction losses of these two
switches are high. The remaining switches Sw7 and Sw8 are turned
ON only in negative half cycle. However, the output current flows
through these two switches only during zero state. As a result, the
conduction losses of these two switches Sw7 and Sw8 are same as
the switches Sw1, Sw3, Sw4 and Sw6. In the PV inverter topology
proposed by Islam et al., the switch pair Sw1 and Sw6 operate at a
high switching frequency in the positive half cycle and remains
turned OFF in negative half cycle.
Similarly, the other switch pair Sw1 and Sw6 operate at a high
switching frequency in negative half cycle and remains turned OFF
in the positive half cycle. This results in equal switching and
conduction losses in these four switches. The switch Sw5 is kept
turned ON completely during the positive half cycle and operate at
a high switching frequency in the negative half cycle. Similarly, the
switch Sw6 is kept turned ON completely during the negative half
cycle and operate at a high switching frequency in the positive half
cycle. As a result, the conduction losses of the switches Sw5 and
Sw6 are high. In addition to conduction loss, the switches Sw5 and
Sw6 have same switching losses as the switches Sw1, Sw2, Sw3 and
Sw4.
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Table 2 Magnitude of high-frequency components in terminal voltage and leakage current
Magnitude of high-frequency components in terminal voltage vag, V
Table 3 Parameters considered for the experiment
Parameter
Value
Parameter
Value
VDC
100 V
Rp
10 Ω
fsw
10 kHz
C
50 µF
4 mH
Rload
100 Ω
200 nF
—
—
L
Cp
By using the PV inverter topology proposed by Xiao et al., the
switch pair (Sw1, Sw4) or (Sw2, Sw3) operate in higher switching
frequency in one-half cycle and remains turned OFF in the other
half cycle. Thus, the switching and conduction losses of the
switches Sw1, Sw2, Sw3 and Sw4 are same. The remaining two
switches Sw5 and Sw6 operate at a high switching frequency in both
half cycles. Therefore, the switching and conduction losses of the
switches Sw5 and Sw6 are high compared with the remaining
switches in the PV inverter topology. In the PV inverter topology
proposed by Ji et al., the switch pair Sw1 and Sw4 operate at a high
switching frequency in the positive half cycle and remains turned
OFF in negative half cycle. Similarly, the other switch pair Sw2 and
Sw3 operate at a high switching frequency in negative half cycle
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and remains turned OFF in the positive half cycle. As a result, the
switching and conduction losses of the switches Sw1, Sw2, Sw 3 and
Sw4 are same. The other switches Sw5 and Sw6 operate at the
fundamental frequency. Hence, the conduction losses of the
switches Sw5 and Sw6 are high.
3.4 Experimental results
To validate the simulation results, a hardware prototype for the
various inverter topologies were fabricated. The developed inverter
topologies were fed from the programmable DC power supply
giving voltage ‘VDC’ (Table 3) which is connected at the input DC
bus of the inverter. The output of the inverter is connected to
13
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Fig. 12 Bar graphs showing
(a) Conduction loss, (b) Switching loss for the switches in various inverter topologies discussed
The subplot (a) of Fig. 13 shows the waveforms of the output
voltage vpg of the considered inverter topologies with their
respective FFT plots. The subplots (b) and (c) of Fig. 13 give the
waveforms for terminal voltages vag, vbg and leakage current ileak,
respectively. It can be easily observed that the terminal voltage for
the unipolar PWM has maximum high-frequency voltage
transitions. The terminal voltage waveform has both the lowfrequency and significant high-frequency components, as seen in
simulation results. This results in the high leakage current in case
of unipolar PWM technique. The full-bridge inverter with bipolar
PWM technique has less leakage current among all the inverter
topologies.
Furthermore, the small transition near the middle of peak-topeak terminal voltage for H5 inverter can also be seen in the
captured experimental waveforms. Thus, the captured experimental
plots exactly match with the simulation results. The same is true
for other captured plots also.
Fig. 13 Experimental waveforms
(a) Full-bridge inverter with bipolar PWM technique, (b) Full-bridge inverter with unipolar PWM technique, (c) H5 inverter topology, (d) HERIC inverter topology, (e) H6 inverter
topology
14
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resistive load Rload through an LC filter. Furthermore, the switching
power metal-oxide-semiconductor with part number IRF 640 were
used as switches in the hardware prototype developed. The
developed inverter topologies were fed from the programmable DC
power supply giving voltage ‘VDC’ (Table 3) which is connected at
the input DC bus of the used in the developed prototype. The PWM
pulses required for switching power MOSFETs were generated
using SPATRAN 6 field-programmable gate array board. The
generated PWM pulses are given to the power MOSFETs in the
inverter circuit via a driver integrated circuit HCPL 3120. The
other important details of the parameters used in the experimental
setup are given in Table 3. Also, the series combination of parasitic
resistance Rp and capacitance Cp (with details as given in Table 3)
is connected to the output terminal of DC supply [40, 55]. Various
terminal voltage and leakage current waveforms were captured
using the developed experimental setup, as shown in Fig. 13.
E F G
H, W
I J K L
M, W
N
O
P
bipolar
unipolar
H5
HERIC
H6
Zhang et.al
Islam et al.
Xiao et al.
Ji et al.
2
2
3
2
3
4
3
2
3
17.672
17.672
19.614
13.2
14.189
19.578
19.578
17.636
15.178
4
4
3
2
2
2
3
4
2
17.16
17.16
12.87
8.58
8.58
9.66
12.87
17.16
8.58
no
no
yes
yes
yes
no
yes
no
yes
2
3
3
3
3
3
3
3
3
equal
equal
unequal
equal
unequal
unequal
unequal
unequal
unequal
4
4
5
6
6
8
6
6
6
3.31
1.99
1.92
1.92
1.92
1.92
1.92
1.92
1.92
1e-2
5.75
0.2
0.2
0.2
0.2
0.2
0.2
0.2
no
no
no
no
yes
yes
no
no
no
2
2
3
2
2
2
3
2
3
—
2
2
2
2
4
2
2
2
4
4
3
2
2
2
3
4
2
0
0
1
1
1
2
1
0
1
0
0
1
1
1
2
1
0
1
A – Number of switches used in topology.
B – THD of the grid current in percentage.
C – Peak value of leakage current, A.
D – Asymmetry in the inverter operation during positive and negative half cycles of the grid voltage.
E – Number of switches and diodes conducting during the positive half cycle of the grid voltage.
F – Number of switches and diodes conducting during the negative half cycle of the grid voltage.
G – Number of switches and diodes conducting in the zero-voltage level.
H – Total conduction loss for the inverter topology.
I – Number of switches operating at a higher frequency during the positive half cycle of the grid voltage.
J – Number of switches operating at a higher frequency during the negative half cycle of the grid voltage.
K – Number of switches operating at the fundamental frequency of the grid voltage during the positive half cycle.
L – Number of switches operating at the fundamental frequency during the negative half cycle of the grid voltage.
M – Total switching loss for the inverter topology.
N – Undefined states in the terminal voltage.
O – Number of levels of the output voltage.
P – Distribution of the losses in the four H-bridge inverter switches.
The PV inverter topologies such as H5, HERIC and H6 and
configurations having similar terminal voltage waveforms have
almost nearly the same magnitudes of leakage current. The fullbridge inverter with bipolar PWM technique has two levels in the
inverter output voltage. However, all the other configurations
discussed have three levels in output voltage. As a result, the THD
of output current will be high in full-bridge inverter with bipolar
technique compared with all the other PV inverter topologies. The
experimental results presented justify the simulation results, which
further justify the correctness of the analysis carried out.
3.5 Comparison of various PV inverter topologies
On the basis of the information obtained from the simulation
section and loss calculation, a comparison of the various PV
inverter topologies discussed is given in Table 4. The comparison
is made based on a number of switches used in topology, THD of
the grid current, filter requirement, asymmetry in the inverter
operation etc. From the economic point of view in terms of the
number of switches, bipolar and unipolar schemes are economical
compared with the other topologies shown in Table 4. However,
the size of the required filter in the case of bipolar switching is
large because of two levels of the output voltage. This increases the
cost of the system in case of the bipolar full-bridge inverter. In
terms of the switching and conduction losses, HERIC inverter
topology has low losses compared with the other inverter
topologies. The THD of grid current is high in the case of the
bipolar full-bridge inverter topology compared with the other PV
inverters discussed. Furthermore, there is asymmetry in the
operation of the inverter during the positive and negative half
cycles for the inverter topology proposed by Zhang et al. and H6
inverter topology. This may result in the DC offset in the inverter
output voltage/current. In terms of the leakage current, the bipolar
full-bridge inverter accompanied with configuration proposed by
Zhang et al. and Xiao et al have a very low magnitude of leakage
current compared with all other topologies. The full-bridge inverter
with bipolar and unipolar PWM techniques have equal losses in the
switches used in H-bridge and are having maximum losses. Equal
losses in the switches further help in simplifying the heat
dissipation and its design in the system. The H5 inverter suffers
from unequal distribution of the losses with high losses in top
switches compared with the bottom switches. The HERIC inverter
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topology seems to have equal and minimum losses in the switches
used in H-bridge. The other discussed configuration such as H6
inverter topology, inverter topology proposed by Zhang et al.,
Islam et al., Xiao et al., Ji et al. also suffers from non-uniform loss
distribution in the switches used in H-bridge.
3.6 Reactive power capability
Today, apart from feeding active power, PV inverters are also
expected to have reactive power control capability [30]. With the
flow of reactive power in the inverter, there exists both positive and
negative powers in the output of the inverter. This can be attributed
to the non-alignment or non-zero phase difference between voltage
and current waveform. Therefore, the PWM strategy designed with
unity power factor operation of the inverter needs to be modified.
Typically, it has to take care of providing the freewheeling path for
the inductor current at turn-OFF or zero periods during the
negative power output. Owing to this negative power in the
inverter, modification in the PWM strategy is required during zero
state to avoid the distortion in the grid current [30, 50]. Thus, the
problem is averted by changing the modulation technique.
In case of H5 inverter, the switch Sw1 is operated in a
complementary manner to the switch Sw2. Similarly, in switch Sw3
is operated in complementary to switch Sw4. As a result, during
zero state both the top switches are turned ON, thus providing the
path for freewheeling of inductor current [30]. In the case of
HERIC inverter, the switch Sw6 is operated in complementary to
the switches Sw2 and Sw3. The switch Sw5 is operated in
complementary to the switches Sw1 and Sw4. These changes in the
switching pattern of switches Sw5 and Sw6 results in providing the
reactive power capability for HERIC [30]. For H6 inverter
topology, the reactive power capability can be taken care by
changing the switching pattern of switches Sw1 and Sw3 [50]. The
switch Sw1 is to be operated in complementary to the switches Sw2
and Sw6. Similarly, the switch Sw3 is to be operated in
complementary to the switches Sw4 and Sw5.
4 Conclusion
This paper has presented an overview and comparison of the basic
transformerless PV inverter topologies. The details of the operation
15
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Table 4 Comparison of various PV inverter topologies
Inverter topology
A
B
C, A
D
[13]
i.
[18]
ii.
iii.
iv.
v.
vi.
vii
.
vii
i.
ix.
x.
xi.
The full-bridge inverter with bipolar PWM technique and
inverter topology proposed by Zhang et al. and Xiao et al. have
the lowest magnitude of leakage current.
The full-bridge inverter with unipolar PWM technique has the
highest magnitude of leakage current.
In full-bridge inverter bipolar and unipolar PWM techniques,
the PV source and the grid are always connected.
In the H5, HERIC, H6 and PV inverter topology proposed by
Islam et al. and Ji et al., discontinuity is enforced between the
PV array and the grid during the zero state.
The H5, H6 and inverter topology proposed by Islam et al. and
Ji et al. use a switch in the DC bus (DC decoupling) to isolate
the PV array and the grid.
The H5 inverter topology has high switching and conduction
losses compared with the H6 inverter.
The HERIC uses AC-by-pass and inverter switches (AC
decoupling) to isolate the grid and the PV array during the zero
state.
The HERIC inverter topology has a high efficiency compared
with other topologies discussed.
The H6 inverter topology and topology proposed by Zhang et
al. have asymmetry in the output voltage due to its operation.
The full-bridge inverter with bipolar PWM has a high THD in
the grid current compared with other topologies.
Using the topologies H5, HERIC, H6 and inverter topology
proposed by Islam et al. and Ji et al. the magnitude of the
leakage current components at the resonant frequency is
negligible.
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