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Index
Introduction
3
Background Information
3
Transistors in computer chips
3
Moore’s law
3
Lithography
4
Production process
4
Deposition
5
Photoresist coating
5
Lithography(machine)
5
Etching
5
Ionization
6
6
Formula
K1 factor
7
Wavelength ()
7
Numerical aperture
7
Current technology explained
8
What is EUV?
8
ASML EUV Machines
8
Shortcomings
9
Multiple Patterning
9
Double Patterning
10
LELE
10
SADP
11
LFLE
11
Triple Patterning
12
Quadruple Patterning
12
Emerging technology EUV
EUV with small NA and double patterning
13
13
2
Shortcomings
Emerging technology DUV
14
14
DUV with multiple patterning
15
Shortcomings
15
Bibliography
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Introduction
Computer Chips are found more and more often in our daily life. They can be found in phones, watches,
computers, refrigerators and so on. But what these chips are exactly made of and how they are
manufactured people often don’t know. Therefore in this report the production process and the newest
technologies are going to be explained.
Background Information
Transistors in computer chips
The machines ASML manufactures produce computer chips. Chips consist of transistors,
transistors are small semiconductors that are used to amplify or switch electrical signals and
power. For an easy imagination, a transistor can be seen as a small ‘light switch’, if you press
on, the light goes on. These days chips consist of around 2,5 billion transistors. That is in line
with Moore’s law (see subsection). A chip computational strength is determined by these
transistors, the more transistors in a chip the more complicated processes it can achieve. For
example if you press the light switch ‘on’ one lamp goes on and the other off.
Multiple materials are used in chips. These materials can be conductors, semiconductors or
insulators, depending on the type of pattern and circuit one wants on the chip. Conductors are
materials that allow current to flow, isolators on the other hand block current. Semiconductors
allow current to flow under certain conditions. Silicon is such a semiconductor which is widely
used in the chip industry. A semiconductor can be used as a light-switch, also called a transistor.
These transistors can either block current or let it flow and therefore can determine the circuit
on a chip. Because these transistors can allow current to flow, but also block current, a lot of
combinations can be made on a chip. The more transistors, the more complicated the circuits
on a chip can be made.
Moore’s law
“The number of transistors and resistors on a chip doubles every 24 months” (Moore, 1975)
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Gordon Moore was one of the founders of Intel (a big chip-company). During his time working
for Intel he observed that every two years the number of transistors and resistors would
double. This makes it possible to make faster and more powerful chips. This phenomenon is
also known as Moore’s law. His ‘law’ is a product of observation rather than a real ‘law of
physics’. His law is after 50 years still widely used in the industry.
Lithography
Photolithography or just lithography is a process that is used to fabricate very small patterns in
thin films. It was first exploited in 1796 by painters by putting some oil on some smooth
surfaces. Now it is more complex and it is used to print very small patterns, for example on
chips. For photolithography different types of light can be used; ultraviolet, extreme ultraviolet
and x-rays. ASML utilizes Extreme Ultraviolet Light and Deep Ultraviolet light, or EUV and DUV
in short, respectively.
In order to understand the
technology there are a few
fundamental terms that need
to be explained. We will start
with the physical explanation
of light
Not all the light can be seen
with our eyes, light is classified
in different wavelengths and
can easily be put in a scheme,
the so-called ‘light spectrum’
Figure 1 : the light spectrum with the wave length
(see figure 1). The light visible to our eye has a wavelength between 700-400 nm, where every
color has its own wavelength. For the production of microchips, ultraviolet light is used. This is
light with a lower wavelength compared to the visible light (400-100 nm).
4
To print patterns on a material, for example chips, this UV
light is printed on a light-sensitive material. Where light
reaches this material it interacts with the material. To make
certain patterns, light is strategically blocked in some places
where it shouldn’t interact with the material.
Figure 2: the exposure of a waver with a laser
Production process
The production of a chip is very long and complicated, but all
technologies to make microchips that will be discussed are
based on the same principle, photolithography. Here we will
discuss this in more depth.
Deposition
The whole process begins with the material silicon. Silicon wafers are the basics of a chip.
Wafers are cut of pure silicon. After that thin films of materials (conductors, semiconductors or
insulators) are put on the silicon wafer. This step is called deposition.
Photoresist coating
Then the wafer is coated with a light-sensitive layer, called photo-resist (often referred to as
resist). There is a positive and negative resist. They both react differently when exposed to
light. When light hits positive resist it is made more soluble, while negative resist polymerizes
when exposed to UV light. Positive resist is most commonly used in the chipmaking industry
When coated the wafer is ready to be put inside the lithography machine.
Lithography(machine)
In the lithography machine the wafer is exposed to some sort of radiation, UV light in the case
of ASML. The light first goes through the reticle which contains the blueprint of the pattern that
is going to be printed on the chip. This will cause light to be blocked in some places and create a
pattern. After light goes through the reticle it is projected on the photo-resist. The places where
light hits the photoresist will interact and in that way the pattern from the reticle will be
created on the wafer.
Before the exposure of the wafer a lot of things happen. As can be seen in figure 2. The light
travels a long way before actually hitting the wafer. The light reflects on a lot of different
mirrors. Every mirror has a different function, nevertheless the main function is to reflect the
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light into another mirror. This makes
a nice path for the light to hit the
wafer with the desired properties.
Figure 3: schematic view of the
exposure process of a waver
Etching
After the photolithography the
wafer is baked to make the changes
permanent. The photo-resist that is left behind on the wafer that didn’t interact with light is
removed. This is done by a process called etching. When the leftover photo-resist is removed
the 3D pattern that is created becomes visible. Etching must be done very precisely as a chip
6
has a lot of layers and while etching one layer, another must not be damaged. The more layers
the more difficult this step becomes.
There are two types of etching: wet and dry. Dry etching uses gasses and wet etching chemical
liquids to expose the pattern on the wafer.
Ionization
When the etching is done the silicon wafer is bombarded with positive and negative ions
(charged atoms). This is to tune the electrical conducting properties of part of the pattern. Raw
silicon isn’t a perfect insulator or conductor but a semiconductor. Directing ions through the
silicon, the electricity flow can be controlled and the transistors (switches) are made.
7
Formula
In the creation of these chips and improving the accuracy there is a key factor involved, namely
the critical dimension or CD in short (see formula below). Also called the Rayleigh criterion.
𝜆
𝐶𝐷 = 𝑘1 ⋅ 𝑁𝐴
CD says something about the precision and the minimum size possible for the making of the
transistors. You want the line width for the printing of the pattern to be as small as possible.
The CD itself is reliant on the 𝑘1 factor, the wavelength (𝜆) of the incoming light and the
numerical aperture or NA in short. We will explain this further in the upcoming subsections.
K1 factor
The k1 factor is a coefficient that depends on many factors related to the chip manufacturing
process like how the mirrors are chapped. The physical limit with lithography is 𝑘1 = 0.25.
However in the development of newer technologies we aim to have a lower 𝑘1 .
Wavelength (𝜆)
The wavelength of the laser can be altered by using different methods of creating these beams.
The smaller the wavelength the better the accuracy. Different technologies use different
wavelengths, which will be explained further on in this report.
Numerical aperture
The numerical aperture is a factor that gives a numerical representation of the amount of light
that is able to enter any optical system. Every optical system can receive or send out light over
a certain amount of angles. This is shown in the formula for
the numerical aperture: 𝑁𝐴 = 𝑛 ⋅ 𝑠𝑖𝑛(𝜃)
As can be seen in the picture 𝜃 is the maximum half angle
in which the beam of light enters or exits the optical
system. It is the half angle, because the angle is measured
from the perspective of a reference line.
The n in the formula is the refraction index. This is a
constant that tells us how fast light can travel through a
specific material and this constant is dependent on the
type of material.
Figure 4: NA Image, F being the focal point, f being the distance between the focal point and the lens and
D the height of the lens.
8
Current technology explained
What is EUV?
The current state of the art technology is EUV lithography with high numerical aperture. In
“Production process - ASML '' there was made mention of light and ultraviolet light. EUV goes a
step further in that ultraviolet direction. Extreme ultraviolet light or EUV for short is the term
for light with a wavelength between 124 - 10 nm. ASML makes use of EUV light with a
wavelength of 13.5nm.
ASML EUV Machines
EUV (Extreme Ultra Violet) machines are able to provide the radiation exposure needed for
lithography. To generate this radiation a CO2 laser emits a CO2 laser light, this light then travels
through the Beam Transport System, in which the light is reflected by a number of mirrors.
After that the light reaches the heart of the system. This consists of a tin droplet generator,
which generates little droplets of tin at a consistent rate of about 50.000 times per second. The
droplet of tin is dropped through the beam’s path. The light beam then hits the tin droplet and
they form a hot plasma (one of the four fundamental states of matter, just like liquid, solid and
gas) together, due to this reaction the plasma emits a photon, a tiny package of light. This is the
EUV light. The photon bounces off the collector and is focused on the connection point with the
scanner and onto the wafer stage with high NA. Which allows very precise patterns and thus
very advanced chips. A high NA gives a small CD. This whole process takes place in a vacuum
chamber, since EUV light will be absorbed by everything, even air.
Figure 5: A schematic representation of the main components of an EUV lithography system.
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Shortcomings
Current EUV machines use a wavelength of 13.5 nm and a NA of 0.33 and they are able to
produce 7 and 5 nm chips. This technique requires thin photoresist layers, since patterns that
are formed from thicker layers have a higher chance of collapsing. This can be challenging since
thinner layers absorb less photons. In general EUV is absorbed by almost any material making it
a difficult kind of radiation to work with. Also this radiation is quite difficult to generate,
requiring very expensive lasers and huge mirrors. An upcoming challenge is that if in the future
Moore’s law still holds and chips become more advanced and beyond the 3 nm node, the
current EUV machines will not be able to produce those chips. Because the wavelength will be
too big and the NA will be too low to print the patterns needed voor 3 nm chips and beyond.
Therefore new technologies are being developed and will be explained in the next chapters.
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Multiple Patterning
Multiple patterning is a group of technologies designed for photolithography to increase
feature density in integrated circuits (ICs). An integrated circuit is the circuit on the chip. This
method circumvents the lithographic constraints of chip-manufacturing. One single 193 nm
exposure has a physical resolution limit at 40 nm. Chipmakers can design 20 nm and smaller
integrated circuits utilizing multiple patterning techniques. The reason for explaining the
different multiple patterning techniques is for the reason that these techniques play a vast role
in the emerging technologies which we will be talking about in the following chapters.
Pitch splitting and spacer are the two most important types of multiple patterning. Pitch
splitting techniques include double patterning as well as triple patterning. Meanwhile, the
spacer uses self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP)
(SAQP). Both SADP and SAQP can be extended to include octuplet patterning (Corp, M. G., n.d.).
Double Patterning
Double patterning can further reduce pitch size without changing NA or λ. The most frequent
form used for double patterning is litho-etch-litho-etch (LELE). A different technology for
double patterning besides LELE or SADP is Litho-Freeze-Litho-Etch (LFLE).
LELE
The first step in the process of LELE is exposing and developing the first pattern into the resist
which is on top of a hard mask (Litho 1). Then, the first pattern is etched into the hard mask
(Etch 1). Subsequently the second pattern is exposed and developed into the resist (Litho 2) and
finally, the patterns are etched into the silicon. This all can be seen in the figure below.
Figure 6: The steps of litho-etch-litho-etch. Starting at top-left is litho 1. Then bottom left is etch 1. Top
right is litho 2 and bottom right is etch 2.
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SADP
In dense regions, the number of masks can be minimized or even removed using SADP. The first
step in SADP is to create a dummy pattern onto the silicon (litho 1). After that ‘sidewalls’ are
placed. Next, the film (basically a coating layer) is removed and then the dummy pattern is
stripped. Finally the pattern is etched into the silicon.
The method is shown in the figure below.
Figure 7: The steps of self-aligned double patterning. The first step is depicted top left, following bottom
left, then top right etc.
LFLE
LFLE is pretty similar to LELE but instead of etching twice you freeze and etch once. The first
step is exposing and developing the first pattern into the resist (litho 1). After that the freezing
starts. The remaining resist is cured and baked (freeze). Subsequently the second pattern is
exposed and developed onto the resist. Finally, both patterns are etched into the silicon. The
figure below depicts this process.
Figure 8: litho-freeze-litho-etch process. The order is again the same as the other figures. Startin at top
left (litho 1) then bottom left (freezing) then top right(litho 2) and finally bottom right (etching).
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Triple Patterning
An example of a triple patterning technique that is often used is litho-etch-litho-etch-litho-etch
(LELELE). LELE and LELELE are much the same, except for the fact that you repeat the litho-etch
process one more time. It requires three lithography and etching steps to define a single layer
during manufacture. We will not be going into detail of other triple patterning techniques as it
goes beyond the scope of this report (and it is fairly similar to double patterning techniques).
Quadruple Patterning
SAQP (self-aligned quadruple patterning) is the most common technique when it comes to
quadruple patterning. SAQP is exactly the same as repeating the SADP process twice. The CD in
SADP is always defined by the first spacing, there is only one spacing. In this case there are two
spacings. Therefore the CD can be defined by the first or the second spacer in the case of SAQP.
13
Emerging technology EUV
EUV with small NA and double patterning
EUV (Extreme Ultraviolet Lithography) is a process that is specially used to make small micro
conductors and chips. One of the new technologies is to use EUV with a small NA and double
patterning.
EUV with a small Numerical Aperture (NA of 0.33) with only one exposure will have a lower
resolution in comparison with ASML’s current technology. Therefore, multiple exposures are
needed to enhance the feature density. One way to create additional exposures is double
patterning. Double patterning also cancels out the effects of diffraction in lithography. These
effects make it difficult to manufacture integrated circuits.
Double patterning EUV involves separating the layouts that cannot be printed with a single
exposure, forming two less defined masks. Then two separate exposures are given and the
patterns are combined and superimposed which enables a single image on the wafer.
Techniques described earlier such as LELE and SADP can be used in this case for multiple
exposures with EUV. The upside of using a technology such as LELE is that it allows for more
feature density and therefore overrides the physical limits of resolution which are encountered
in other technologies for instance.
Triple patterning requires taking the original layout apart into three masks. The shapes of the
masks are combined into one final shape during manufacturing. Triple patterning may sound
easy but potential chaos waits within. It is strenuous to develop a software which automates
taking apart the layout into three masks.
So, the idea behind multiple patterning is to relax the pitches (less intense lasers) of the
features and use a higher dose. This reduces the number of defects. The clearest case for when
multiple patterning is needed (as already stated above), is when the feature pitch is at a
resolution that is too low. If the pitch is below 0.5𝜆 ÷ 𝑁𝐴 . (in the case of this technology
around 20.5 nm), it cannot be resolved in a single wafer exposure and therefore multiple
patterning is required.
Thus, another necessity for double patterning is sub-resolution pitches. There are more
situations requiring multiple patterning than there are situations where a single pattern is
sufficient. One of these is two-dimensional pattern rounding. Two-dimensional patterns are
formed from the interference of beams along the same direction. This results in rounding,
especially around the corners. This contributes to hot spots which lower the resolution. This is
avoided with additional exposures.
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Moreover, double patterning can counter diffraction.
Diffraction happens when the light passes by an object
and splits the light in different wavelengths. The
wavelength correlates with the color of the lights.
Diffraction can happen in a normal optical lithography,
which happens because of the minimum distances. The
diffraction effects make it difficult to produce accurate
wafers.
Figure 9: Diffraction pattern of light
Combining multiple patterning techniques like double patterning or triple patterning are pretty
intricate, but the imaging of EUV with small NA and double patterning are far more accurate
than ASML’s current EUV technology.
Shortcomings
Even though EUV with double patterning has been expressed as the “next generation of EUV”.
It could still be far away.
Several issues of specifically EUV still hold. These can be found in the shortcoming section of
the current technology. Though the used multi patterning technique is not without shortfallings
(LELE). One of the main issues is the fact that there are twice as many steps necessary
compared to a single exposure as can be deduced from the section about multi patterning. Also
very difficult and complicated etch steps have to be done which are time consuming.
Double patterning works best on designs where the critical layers can be separated into
different aligned patterns. This means that a design with a lot of straight lines is acceptable to
produce with double patterning. A design with a lot of diagonal lines is difficult to produce with
the technique. Creating a significant constraint on the design. If the alignment of the lasers is
sufficiently accurate, the two patterns join each other on the wafer and make the wafer much
denser. This makes the wafer stronger compared to wafers with one mask. At the same time
one huge difficulty is the alignment. The alignment is the proper placement of the wafers
relative to each other. If the alignment is not precise enough, the resolution decreases
drastically. Achieving a good alignment takes a lot of time.
15
Emerging technology DUV
DUV with multiple patterning
To make chips faster, more powerful and energy efficient ASML keeps on developing new
technologies for chips, one of them being DUV (deep ultraviolet), which has a wavelength range
in the far ultraviolet. This wavelength is far larger than the one from EUV.
To print patterns on chips, light is projected through a blueprint of the needed pattern, this is
known as reticle mask and focused on a photosensitive silicon wafer, the transistor. This action
is repeated to produce the desired pattern. It follows that with more transistors, there will be
higher performing chips. To achieve a resolution on the level of EUV, multiple patterning can be
utilized. In particular self-aligned patterning (SAQP&SADP) is used (see multiple patterning).
With this technique a much lower resolution is created than normally possible with DUV
radiation.
Also, EUV radiation is really hard to generate as opposed to DUV radiation. Only excited
electrons in the inner shell of a multiply ionized atom can emit EUV. Excited electrons are
electrons that have more energy than the ground state. Besides EUV radiation is absorbed by
air and other gasses. DUV doesn’t have this problem and is easier to generate and it uses less
material. DUV of 193 nm is generated with an argon fluoride laser, and with the bigger NA the
same resolutions can be reached.
In the figure below can be seen what resolution goes with each method.
Figure 10 : graph with resolution against wavelength
16
Shortcomings
DUV with multi patterning (SADP&SAQP) also has its flaws. Having a high wavelength makes it
more difficult to create features with a high resolution. Increasing the number of errors even
more because typically more than 2 exposures are done. More exposures also mean more
material used. Every extra exposure needs another extra mask, essentially the amount of
material used increases proportionally with the amount of exposures.
Figure 11: Multi patterning (left) and single patterning (right) visually illustrated by Samsung.
As you can see layers are "placed" on top of each other to enhance resolution.
DUV with multi patterning is able to achieve the same transistor density as EUV with double
patterning, but extreme process control is required which makes it fairly difficult. Also, with
multiple patterning many restrictions arise which prevent making all kinds of patterns.
Especially when increasing the amount of exposures to more than 2, the restrictions on the
design amount to be quite substantial. This happens because when creating the designs,
adjacent materials may not be created by the same exposure as reaching the low resolution is
not possible in that way. Due to this complicated programs need to be run to calculate if a
design is legal (possible). Some designs would lead to having programs run indefinitely and as
such the designs have to be restricted. In actuality the design is even more restricted using
these multi patterning techniques, this is because every feature on the design will have the
same linewidth.
17
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