Summer Semester Special 2021-22
CSE1003 - Digital Logic and Design
Lab Digital Assignment-2
Decoder
Slot: L29+L30+L35+L36
Date: 26 July, 2022
Faculty: Prof. Sumathi G
Name: Havila Reddy
Reg No: 19BCT0211
Decoder simulation in LTSpice:
1. Aim:
To simulate decoder circuit using logic gates
2. Software used:
LTSpice is the software used
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Procedure:
Create a new schematic in LTSpice
Select four AND gates, two NOR gates, and three voltage sources
Connect all of them as shown in picture below
Ground the voltage sources, and label the outputs from the AND gates as y0,
y1, y2 and y3 respectively
Give the Pulse input to the Voltage sources
Edit the simulation by giving the right amount of transient time (80 in this case)
Run the schematic, add 7 plot planes
Select V3 on the first plot plane, V2 on second plot plane, V1 on the third plot
plane and the outputs on the rest of the plot planes
This is the simulation of Decoder in LTSpice
Circuit Diagram:
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8. Results:
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1. In the 2 - 4 line decoder, there is a total of three inputs, i.e., V1, and V2 and V3
and four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when
the enable 'E' is set to 1, one of these four outputs will be 1.
2. The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
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3.
9. Conclusion:
• The combinational circuit that change the binary information into 2N output
lines is known as Decoders.
• The binary information is passed in the form of N input lines. The output lines
define the 2N-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder.
• At a time, only one input line is activated for simplicity. The produced 2N-bit
output code is equivalent to the binary information.
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