IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 12, DECEMBER 2006
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Automatic Scaling Procedures for
Analog Design Reuse
Alessandro Savio, Luigi Colalongo, Member, IEEE, Michele Quarantelli, Member, IEEE, and
Zsolt M. Kovács-Vajna, Senior Member, IEEE
Abstract—In this paper, a methodology for analog design reuse is
proposed. The basic idea is to keep the circuit topology unchanged
while automatically modifying the MOSFETs aspect ratio in order
and output conto control the transistor transconductances
ductances DS . If
’s and DS ’s of each transistor are kept unchanged through the scaling procedure, we show that the overall
frequency behavior of the scaled circuit remains very similar to
the original one. The approach is very simple and it is suitable
for the scaling of analog circuits. No input and output terminals
have to be defined and it can be straightforwardly implemented
in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25- m, 2.5-V voltage supply to
a 0.15- m, 1.2-V voltage supply in standard CMOS technologies.
Index Terms—Analog integrated circuits, design automation,
MOSFET, technology CAD.
I. INTRODUCTION
I
N recent years, due to the rising circuit complexity, we notice an increasing interest in the automatic circuit scaling and
design porting. The trend to include analog and digital blocks on
the same chip leads to growing difficulties for system-on-chip
(SoC) designers. Today, the synthesis of digital circuits is a
highly automated process whereas the analog design is still a
hand base procedure and the analog block of an SoC is often
the bottleneck of the whole project. The time to market pressure and the advent of deep submicron processes have enlarged
this gap. Typically, dealing with digital projects, the only degree of freedom is the transistor width and the designer’s goal
is an acceptable tradeoff between speed and power consumption. The technology scaling, by modifying several transistor
parameters such as carriers mobility, gate oxide capacitance and
voltage supply, improves the overall performances of digital circuits reducing the power delay product. On the other hand, it
does not lead to the same benefits when applied to analog circuits. In analog circuit design, in fact, additional design variables, such as transistor lengths, bias currents, or specific requirements, such as voltage gain, unit gain frequency (UGF),
Manuscript received July 27, 2005; revised May 4, 2006. This work was supported in part by PDF Solutions. This paper was recommended by Associate
Editor T. B. Tarim.
A. Savio, L. Colalongo, and Z. M. Kovács-Vajna are with the Department of
Electronics, University of Brescia, 25123 Brescia, Italy.
M. Quarantelli is with PDF Solutions Italia, 25015 Desenzano del Garda
(BS), Italy.
Digital Object Identifier 10.1109/TCSI.2006.883849
signal-to-noise ratio (SNR) and so on, turn the automatic circuit scaling to a challenging issue. While scaling analog circuits,
their overall behavior is often modified and their performances
altered. This is mainly due to several reasons intrinsically related to the fact that analog circuits operate directly with electrical quantities rather than logic thresholds or quantized levels.
Hence, the automatic migration of analog circuits design is not
a straightforward task as the digital counterpart and often involves the complete circuit redesign. Recently, in order to face
this problem, several solutions were proposed both at research
[1]–[3] and at commercial level [4]; the approaches [3] and [4]
are based on optimization loops and massive SPICE simulations, solutions [1] and [2] are fully analytical approaches. In
[5], the analytical approach of [1] and [2] defined for MOSFETs
in the saturation region was generalized to account for transistors biased in the triode region. Moreover, to compensate possible inaccurate analytical solutions, a tuning procedure based
on an optimization loop is described as well. It is worth noting
that the analytical scaling of MOSFETs in the triode region is a
challenging issue that often leads to analytical solutions, that although mathematically consistent, turn out to be inaccurate for
practical applications.
A MOSFET in the triode region, indeed, behaves as a controlled resistor and its drain current depends not linearly on the
drain-to-source voltage
. Therefore, a small inaccuracy in
scaling may lead to large bias point variations. Similar
the
considerations hold for the transconductance
and for con. On the other hand, a saturated MOS transistor beductance
haves as a current source whose current slightly depends on the
through the channel length modudrain-to-source voltage
lation. In this case, if
is not accurately controlled, the drain
current does not change significantly and the bias point remains
substantially unchanged.
In this paper, an approach leading to a possible solution of
the above issues is presented. The inaccuracies of the analytical
solution are overcome by adopting a numerical procedure. The
basic idea of the procedure is to modify the aspect ratio
of the circuit transistors in order to obtain a scaled circuit where
the MOSFET conductance parameters (
and
) are kept
as close as possible to the original ones. For a wide class of
analog circuits, this assures that the overall frequency behavior
of the original and that of the scaled circuits remain very similar.
This approach has shown to be very effective despite its simplicity and in many practical applications it preserves the whole
dc and dynamic behaviors of the original circuits. Furthermore,
when it fails, in order to strictly preserve the dynamic response
of the original circuit, another algorithm is presented as well.
1057-7122/$20.00 © 2006 IEEE
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Fig. 2. Small-signal equivalent circuit and Bode diagram (gain modulus) of the
common-source amplifier of Fig. 1.
Fig. 1. Common-source amplifier.
Although some loss of simplicity and generality occurs due to
the introduction of input and output terminals, this method allows to extend the reuse procedure to many nonlinear circuits.
The paper is organized as follows. In Section II, the scaling
procedure is presented, in Section III, the numerical approach
for small-signal analysis is explained whereas the extension to
large-signal analysis is reported in Section IV along with some
practical examples. Finally, in Section V conclusions are drawn.
II. MATHEMATICAL BASIS OF SCALING PROCEDURE
The aim of this section is to derive the mathematical relations describing the migration method that we propose. We will
show that keeping the circuit topology unchanged and properly
and
of the transisscaling the conductance parameters
, the scaled circuit pretors by changing their aspect ratio
serves its main small-signal features (voltage gain, transconductance, etc.).
Typically, we can distinguish between linear and nonlinear
electronic circuits. In linear applications, as for instance amplifiers, the circuits work around a steady state bias point and input
signals are kept small enough to avoid nonlinearities. Therefore,
to introduce the scaling procedure for linear circuits, we take
into account their small-signal equivalent circuits. On the other
hand, dealing with nonlinear circuits, as for instance comparators, only the large-signal behavior is relevant and the approach
is more cumbersome.
In order to inductively derive the mathematical approach, we
exploit on a very simple example. Then it will be shown that our
conclusions hold, in general, for more complex analog circuits
as well.
Let us consider the common-source amplifier of Fig. 1 where
the output is loaded with a dominant output capacitance . If
we neglect the MOSFET parasitic capacitances, we can draw
the small-signal equivalent circuit and the Bode diagram of the
transfer function modulus (1) of Fig. 2. Basing on this model,
(voltage gain) is easily calculated as
the transfer function
(1)
where is the Laplace complex frequency. From the low-frequency voltage gain
and the pole at the frequency
the
gain bandwidth product (GBWP) turns out to be
(2)
If we now change the technology parameters migrating to a
new process, this generally modifies many of the circuit specifications such as the supply voltages, the geometrical and physical
MOSFET parameters, the bias currents and so on.
The circuit of Fig. 1 is a simple amplifier. In order to preserve
its original behavior after the scaling procedure, the low-freand the gain bandwidth product GBWP
quency voltage gain
should remain unchanged. Furthermore, for the sake of generality we assume that the output (load) capacitance should be
scaled by a factor
. It follows (2) that, in order
to preserve the original GBWP, the new MOSFET transcon. Likeductance scaling factor should be
,
wise, to keep unchanged the amplifier’s gain
the output conductance should be scaled with the same factor
. If the output capacitance is kept unchanged
,
and
should remain the same at the end of
the scaling procedure.
These considerations derived for an ideal common-source
amplifier hold for a wide class of amplifiers and linear circuits
where the small-signal behavior is a rational function of
and
. When the small-signal behavior (voltage, current,
impedance or transimpedance gain) should be preserved,
and
of all the transistors in the circuit should remain
unchanged or equally scaled through the scaling procedure.
It may be roughly explained observing that the overall
MOSFET electrical characteristics are embodied in its conductance and transconductance. This property may exploited in
automatic tools that, changing the aspect ratio of the transistors,
and
of each MOSFET preserving the original
try to fit
topology. Moreover,
and
may be easily computed
by a simple SPICE bias point (.OP) simulation. Hence, the
scaling procedure results very easy and do not require a deep
knowledge of the circuit.
This simple approach may fail when a dominant capacitance
is missing or the MOSFET parasitics strongly influence the circuit behavior; in this case it may be difficult to find the exact
and the GBWP may not be maintained. This
scaling factor
problem could be partially overcome creating a fitting loop and
introducing, as further optimization parameters, the transistor
and
. When this apparasitic capacitances along with
proach fails as well, a numerical approach that tries to fit GBWP
or the circuit frequency response (amplitude) is required. It is
worth noting that, in this case, ac simulations are required and
the input and output terminals of the circuit should be localized,
partially relaxing the generality of the above method.
SAVIO et al.: AUTOMATIC SCALING PROCEDURES FOR ANALOG DESIGN REUSE
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The analysis carried out till now could be generalized to large
signals. Basing on the circuit of Fig. 1 we define the classical
slew rate (SR) for an amplifier as the maximum output voltage
change over time
or, equivalently, the output voltage rate as response to an ideal
output transition the
voltage step. For a low to high
and from (2) we can
SR of the circuit of Fig. 1 is
write
(3)
This equation shows the link between small-signal and largesignal parameters. It is valid when two fundamental conditions
are satisfied: the existence of dominant capacitance , typically
the compensation capacitance, and a vanishing output resistance
of the amplifier, in other words, an ideal current source. In a real
circuit, these hypotheses are often not satisfied, the expression
(3) becomes approximated and we can only assume that when
the GBWP rises, the SR increases and vice versa. Moreover, in
a linear time invariant system the step response carries the same
information of the transfer function in the -domain, this is not
true for realistic circuits due to the nonlinearities.
Basing on the above remarks, circuits with identical step responses entail similar small-signal behaviors while the contrary
and
, that
is not true. Hence, the scaling based on the
keeps the dc gain and GBWP for amplifiers, is not enough to
ensure that two circuits have similar transient responses. When
this feature is important a fitting procedure that modifies the
transistor’s aspect ratio trying to match the step response is required. This procedure, as in the case of ac small-signal fitting,
requires the definition of input and output terminals.
III. NUMERICAL APPROACH:
,
As introduced in the previous section, this approach to the
circuit scaling is very useful when the small-signal behavior of
the circuit should be preserved.
The basic idea is to find a procedure that tries to match
and
of each transistor in the original and scaled circuits, reand
, the procedure should
spectively. In order to match
modify the transistor aspect ratios, changing at each step the
and
of the
channel widths (W) and lengths (L) until
scaled circuit are as closer to the original as possible.
The flowchart of the numerical procedure is shown in Fig. 3.
It starts from the unscaled circuit designed in the original
technology. The starting point of the procedure (transistor
aspect ratios) is based on the analytical solution provided by
the scaling approach, described in the following Section III-A.
SPICE simulations are performed on the scaled circuit in order
’s and
’s which are then compared to the
to extract
corresponding values of the original circuit scaled up by the
. If they do not match, the tuning procedure, that
factor
modifies the transistor aspect ratios, is started. It is based on
the Levenberg–Marquardt algorithm, briefly summarized in
Appendix I, that has been proved to be a fast and effective way
to solve large nonlinear optimization problems of this type.
Fig. 3. Flowchart of the g
and g
scaling procedure.
At each step, the Levenberg–Marquardt algorithm requires
the evaluation of the jacobian matrix of the system which is
computed by a finite difference approach based on SPICE
simulations. The tuning loop stops when the weighted least
and
compared to the original ones is
square error of all
and
are evaluated
lower than a desired threshold. Since
from SPICE bias point simulations, the overall procedure turns
out to be very fast.
Furthermore, this approach does not require the definition of
input and output terminals: the circuit characteristics are summarized by the differential parameters of each transistor. Hence,
it is suitable for integration in automated scaling tools.
When the circuit complexity is large, and the nonlinear optimization procedure becomes a hard task, it may be useful,
and/or
even if theoretically not necessary, to remove the
parameters less relevant (typically zero) on the overall circuit
behavior.
has no influence.
•
•
has no influence.
In order to clarify this concept Fig. 4(a) shows a MOS transistor with gate and source terminals connected to constant
voltage generators. The transistor represents the triode load
of the common-source amplifier of Fig. 5. Considering the
small-signal equivalent circuit shown in the right side of
hence the controlled current source
Fig. 4(a),
is turned off, and
is negligible. Same considerations hold
when
is constant, as in Fig. 4(b). The drain voltage of
, hence the small-signal drain
M1 is forced by an opamp to
terminal is connected to the virtual ground and the conductance
may be ignored.
A. Initial Guess
The target of this step is to find a suitable initial condition for
the optimization loop. The input of the optimization procedure
is the aspect ratio of the transistors of the original circuit while
the output is the aspect ratio of the transistors of the scaled technology. A good starting point can help the numerical loop to find
a faster solution but, of course, each point in the input variable
space is suitable. The transistor aspect ratios of the original (unscaled) circuit, for instance, may be a reasonable initial guess.
In order to initialize the numerical loop as close to the final
solution as possible, we have adopted the channel length scaling
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 12, DECEMBER 2006
TABLE I
COMMON-SOURCE SCALING RESULTS
Fig. 6. Output dc transfer characteristics of the common-source amplifier.
Fig. 4. Discarding (a) g
behavior.
and (b) g
which do not influence the circuit
Fig. 7. Frequency responses (voltage gain) of the common-source amplifier.
Fig. 5. Common-source amplifier with MOS triode load.
method, defined in Appendix II. With respect to the constant
inversion level scaling, this approach allows for the reduction
of the power consumption, which could be advantageous for
analog circuits.
The entire process is summarized as follows.
• The original inversion levels and are computed by (7).
The electrical quantities,
,
,
and
are provided by the .OP Spice simulation of the unscaled circuit
for each MOSFET.
is non negative (negative), the
• If the value of
MOSFET
with the highest (lowest)
is chosen. is the
corresponding to .
• MOSFET
is scaled according to (10) and (11).
is calculated
• The newest channel length scaling factor
by means of (12).
the scaled aspect ratios
• For each MOSFET not equal to
and
are calculated.
B. Simulations
In order to validate the scaling procedure based on the fitand
, several practical examples were considered.
ting of
The circuits originally designed for a 2.5-V, 0.25- m standard
CMOS technology are scaled to a 1.2-V, 0.15- m process.
As a first example, we apply the procedure to the scaling of
the common-source amplifier with load transistor in the triode
region of Fig. 5. The output capacitance scales from 1 pF to
. As reported in Table I, the power con1.5 pF, hence
sumption and the gate area increase because of the larger output
capacitance. In order to preserve the low-frequency voltage gain
and
are scaled up by
leading to
and the UGF,
larger devices. Each iteration, the number is reported in the
table, accounts for the SPICE simulations required to compute
numerical derivatives and the linear matrix computations of the
Levenberg–Marquardt algorithm. Total CPU time is referred to
a 2.8-GHz Pentium IV processor. In Fig. 6, the dc output transfer
characteristics are reported, Fig. 7 shows that the scaled circuit
perfectly matches the original frequency response.
As a second example we scale the single-stage differential
amplifier of Fig. 8. In this case, the output capacitance does
. The
not change through the scaling procedure, hence
scaling results are reported in Table II: the gate area of the scaled
circuit is doubled while its power consumption is more than
five times smaller. It is worth adding that analog circuits scaling
is more and more critical as the supply voltage is reduced [6],
[7]. The counterintuitive area increase of the scaled circuit may
roughly be explained by the analytical scaling rules [1], [2]. The
product)
MOSFET gate area (
(4)
SAVIO et al.: AUTOMATIC SCALING PROCEDURES FOR ANALOG DESIGN REUSE
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Fig. 8. Differential amplifier with current-source load.
Fig. 10. Miller operational amplifier.
TABLE II
DIFFERENTIAL PAIR SCALING RESULTS
TABLE III
MILLER OPAMP SCALING RESULTS
Fig. 9. Frequency responses (voltage gain) of the differential amplifier.
depends on technology parameters only. Generally,
therefore the gate area increases through the scaling.
Similar remarks hold for the static power consumption. For
example (constant inversion level scaling) the bias currents inand the power dissipation reads
crease by a factor
Fig. 11. Output dc transfer characteristics of the Miller operational amplifier.
(5)
In Fig. 9, a good agreement between the ac frequency behaviors is shown, the small deviation at higher frequencies is mainly
due to the transistor parasitic capacitances.
The third circuit was the Miller operational amplifier of
Fig. 10. Here, the compensation capacitance scales down from
but, due to transistor’s parasitics,
500 to 350 fF
has been settled to 0.75 to preserve the high-frequency
response. The major scaling results are summarized in Table III.
Fig. 11 depicts the dc transfer characteristics and Fig. 12 compares the original and the scaled voltage gains.
C. AC Frequency Response Fitting
The scaling procedure based on
and
fitting does not
account for parasitic effects (e.g., parasitic capacitances) therefore, especially in recent technologies where these effects are
remarkable, the frequency behavior of the circuit may be inacand
are perfectly matched. In general, if
curate, even if
the dominant pole of the circuit is not far enough from higher
Fig. 12. Frequency responses (voltage gain) of the Miller operational amplifier.
frequency poles or the parasitic effects are relevant, the value
of
is not accurate and the small-signal behavior is not well
controlled.
In those cases, we may adopt a numerical loop that improves
the accuracy. The corresponding flowchart is shown in Fig. 13.
,
fitting
The initial condition is the scaled circuit of the
loop. At each step, the ac frequency response of the circuit
under scaling is compared to the original circuit (target), a
Levenberg–Marquardt optimization procedure is applied until
the distance between the two curves becomes lower than a
threshold (the transistor aspect ratios are modified at each step).
In order to apply this algorithm, the original (goal) and scaled
circuit frequency responses (gain curves) should be suitably
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 12, DECEMBER 2006
Fig. 13. Flowchart of the ac frequency response fitting.
Fig. 15. Frequency responses of the Miller operational amplifier after ac fitting.
Fig. 14. Frequency responses (voltage gain) of the Miller operational amplifier
before ac fitting.
TABLE IV
MILLER OPAMP SCALING RESULTS
Fig. 16. Flowchart of the transient response fitting.
IV. NUMERICAL APPROACH: TRANSIENT RESPONSE
As described in Section II the scaling method based on the
transconductance fitting may not ensure that the transient responses are correct. By the way of example, in the circuit of
Fig. 1 the SR scaling factor
sampled (we used 10 points per decade). The numerical loop is
stopped when the desired accuracy is achieved.
Generally, when the gain curve is accurately matched, the
phase response turns out to be correct as well, the dominant
poles, in fact, are placed with precision by gain curve fitting.
Therefore, the phase margin shows a good agreement and the
procedure also leads to an accurate compensation network.
On the other hand, the method requires input and output terminals to be defined, and the extreme generality of the transconductance fitting approach is reduced. Furthermore, the scaled
circuit accurately fits the frequency response of the original circuit only through the input and the output terminals (the internal
nodes do not appear in the optimization function).
D. AC Fitting: Simulation Results
As an example, we scale the Miller opamp of Fig. 10 with
. The fitting of
and
leads to
scaling factor
an inaccurate matching of voltage gains at high frequencies
because of the parasitic capacitances as shown in Fig. 14. Furthermore, the phase margin is reduced at about 15 , Table IV
resumes the migration results. Fig. 15 shows that the scaling
method allows to perfectly compensate inaccuracies with a
small change of the gate area and power consumption.
is a cumbersome function that depends on technology and bias
. When the transient response
parameters and rarely
becomes an important issue, another scaling procedure should
be adopted. The transient response is an important task for
many analog circuits, especially for nonlinear circuits, such as
amplifiers, comparators and so on. As for the ac fitting, input
and output terminals must be defined. The procedure is exactly
the same as that of the ac fitting, but now, the fitting curve at
the Levenberg–Marquardt optimization loop is the transient
response. In the following we will adopt as input signal a
voltage step, but same considerations hold for each type of
input signals (ramps, sinusoidal signals and so on).
The flowchart is reported in Fig. 16. The fitting starts from the
original design as initial guess and the transient response is assumed as the goal function of the optimization. Afterwards, the
optimization loop is started and, at each step, a transient Spice
simulation is run. If the transient response of the scaled circuit
does not mach the goal function, the Levenberg–Marquardt procedure modifies the transistor aspect ratios in order to minimize
the total square error. Transient responses have to be sampled
in order to apply this procedure, a large number of samples is
preferable for highly accurate solutions but, of course, it increases the optimization time.
SAVIO et al.: AUTOMATIC SCALING PROCEDURES FOR ANALOG DESIGN REUSE
TABLE V
MILLER OPAMP SCALING RESULTS
Fig. 17. Frequency responses of the Miller opamp scaled with ac and transient
fitting.
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V. CONCLUSION
In this paper, a procedure for analog circuit design reuse is
proposed. The goal is to obtain a scaled circuit with a frequency
behavior similar to the original one. Starting from an analytical
migration approach (channel length scaling or constant inversion level scaling), the method modifies the transistor aspect ratios in order to properly scale the transistor’s transconductances
and the output conductances. For linear circuits this ensures that
the original and the scaled small-signal equivalent circuits are
the same. The approach is very general, it does not require the
definition of input and output terminals and it is suitable for implementation in automatic scaling tools.
When transistor’s parasitics reduce the frequency performances, a numerical loop tries to compensate for the
inaccuracies.
Furthermore, when the dynamic behavior becomes an important issue a transient fitting procedure may be adopted. The approach loses its generality but allows for the scaling of nonlinear
circuits as well.
The scaling procedures were tested on different topologies
designed in a 0.25- m, 2.5-V voltage supply standard CMOS
technology and they were scaled to a 0.15- m, 1.2-V standard
CMOS technology.
APPENDIX I
LEVENBERG–MARQUARDT METHOD
Fig. 18. Normalized transient responses of the Miller opamp scaled with ac
and transient fitting.
Fig. 19. Normalized transient responses of the Miller opamp connected as
voltage follower.
In order to demonstrate the effectiveness of this method we
have scaled the Miller opamp of Fig. 10 using ac and transient
response fitting simultaneously.
The results are reported in Table V while Fig. 17 and 18 show
the amplifier voltage gains and the normalized output signals,
respectively. Finally, the original and the scaled amplifiers have
been simulated in a closed loop configuration. Fig. 19 shows the
normalized responses to squared input signals when the Miller
opamps are connected as voltage followers (buffers). The mean
value of the input signals, in order to avoid output saturation, is
while the peak to peak amplitude is 20% of
.
This Appendix briefly introduces the Levenberg–Marquardt
optimization algorithm [8] for nonlinear least squares optimization problems.
is a function that depends nonlinearly on a set of M un: in our approach
is
known parameters ,
or width
. The model to be
a transistor channel length
fitted and the goal function to be minimized as a weighted sum
of squares errors are
where
is the model evaluated at , is the sampled
are weights associated
target function, and ,
are as follows.
with each sample. In our problem
• Transistor transconductances in
,
fitting.
• Samples of the ac frequency response evaluated at frequency in ac fitting.
in
• Samples of the transient response evaluated at time
transient fitting.
and
are provided by Spice simulations for original
and target technologies, respectively. The goal is to minimize
and scaled circuit
the differences between the original
behaviors. By defining
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 12, DECEMBER 2006
where
is a factor used by the algorithm, and combining
the above equations, the following system of linear equations
results:
(6)
Given an initial guess for the problem parameters , the algorithm works as follows.
.
• Compute
).
• Choose a small value for (
and evaluate
.
• ( ) Solve the linear (6) for
• If
, increase by a factor of 10 and
go back to ( ).
, decrease by a factor of 10, update
• If
, and go back to ( ).
the solution
The algorithm is stopped when one of the following conditions are met.
is lower than a fixed value.
• Final error
decreases by a negligible amount even
• Quadratic error
absolute or relative.
value.
• The factor exceeds a
• The maximum number of iterations is reached.
APPENDIX II
ANALYTICAL SCALING EQUATIONS
Analytical scaling equations are based on the application
of the Advanced Compact Model (ACM) MOSFET model
described in [9]. In [9], very accurate expressions for largeand small-signal characteristics are derived. These expressions
are valid for a MOSFET working in the triode and saturation
regions as well as in weak, moderate and strong inversion.
From the ACM equations the MOSFET forward and reverse
normalized currents or inversion levels can be computed as
If we consider the transistor’s intrinsic cutoff frequency
[11], we can find its expression for a
,
MOS transistor in the triode region (
and
), and in the saturation region (
,
and
). Using ACM model
equations we are able to write a relation between the intrinsic
cutoff frequency and the inversion levels
(9)
Following the approach proposed in [1] and [2], two different strategies may be derived, namely constant inversion level
scaling and channel length scaling.
A. Constant Inversion Level Scaling
This is a fully analytical approach which tries to preserve the
inversion levels of the original transistors in the scaled circuit
and
. From (9), if has to remain the same, the
ratio
cannot change during the scaling procedure, hence
the channel length should scale as
where
is the mobility scaling factor
from Section II results that
scales up by
difference
and assuming an invariant slope factor
turns out to be
width
where
(7)
. Finally,
. Writing the
, the new transistor
is the scaling factor for the gate oxide capacitance
.
B. Channel-Length Scaling
where
This is a fully analytical approach to scale down the MOSFET
channel length
(10)
is the drain current,
the thermal voltage and the three
transconductances are defined as
and from
sults
the new channel width re-
(11)
In ACM model all voltages are referred to the local substrate
,
and
can be linked to the MOSFET
(bulk) so
transconductances
,
and
by [10]
(8)
where
is the channel length scaling factor, i.e., the ratio
. If the
between minimum channel lengths,
slope factor is invariant during the scaling,
and
scale
as shown in Section II. Since
and
up by
[9], also
and
scales up by the same
SAVIO et al.: AUTOMATIC SCALING PROCEDURES FOR ANALOG DESIGN REUSE
factor
results
. The drain current scaling factor
Now,
must be the same for each MOSFET, so the channel
should be recomputed. In order to
length scaling factor
avoid that some transistors have channel lengths smaller than
, is chosen as
if
otherwise
where
results
. For each MOS transistor
(12)
Summarizing, in order to apply the scaling to a MOSFET
circuit, the channel length of the transistor corresponding to
is fully scaled by means of (10) and (11). Then
is computed
and scaled according to
for the other devices using (12),
(10) and (11) and finally
for
are replaced.
These scaling equations are useful to initialize a numerical
loop. In many applications as, for instance, voltage amplifiers,
the low-frequency voltage gain depends linearly on the Early
[2] and analytical calculations may
voltage scaling factor
be inaccurate. As an example, considering a saturated MOSFET
operating in weak inversion, the dc scaling factor is
[2]. If the ratio is lower than one, the scaled circuit has a smaller
voltage gain. Furthermore, the procedure does not account for
parasitic effects and the scaling factors are not accurately accounted for.
ACKNOWLEDGMENT
The authors would like to thank PDF Solutions Italia for the
help and encouragement provided.
REFERENCES
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Alessandro Savio was born in Brescia, Italy, in 1977.
He received the Laurea degree (summa cum laude) in
electronics engineering and the Ph.D. degree in information engineering from the University of Brescia,
Brescia, Italy, in 2001 and 2005, respectively.
He is currently a Research Associate in the Department of Electronics for Automation, University
of Brescia. His main research interests are in the field
of analog circuit technology migration, in design of
integrated step-up converters and in modeling of organic thin film transistors.
Luigi Colalongo (M’04) was born in Bologna, Italy,
in 1965. He received the Laurea degree in electronics engineering from the University of Bologna,
Bologna, Italy, and the Ph.D. degree in electronics
engineering and material science from the University
of Trento, Trento, Italy.
From 1991 to 1999, he was with the Department
of Electronics (DEIS), University of Bologna. He is
currently an Associate Professor at the University of
Brescia, Brescia, Italy, where he is involved in the
numerical simulation of semiconductor devices and
in integrated circuit design.
Michele Quarantelli (M’94) was born in Parma,
Italy, in 1965. He received the Laurea degree in
electronics engineering at the University of Bologna,
Bologna, Italy, in 1990 and the M.S. and Ph.D.
degrees in electrical and computer engineering (in
the field of mismatch modeling and characterization)
from Carnegie Mellon University, Pittsburgh, PA, in
1997 and 2003 respectively.
From 1996 to 1999, he was an Assistant Professor
at the University of Brescia, Brescia, Italy. He is now
with PDF Solutions, Desenzano del Garda, Italy. His
main research interests are in the fields of process characterization, test structures design, and in the design of integrated circuits for applications such as
wireless systems, analog signal processing, and basic analog building blocks.
Zsolt M. Kovács-Vajna (M’90–SM’00) received the
D.Eng. degree with honors and the Ph.D. degree in
electronics engineering and computer sciences from
the University of Bologna, Bologna, Italy, in 1988
and 1994, respectively.
From 1989 to 1998, he was with the Department
of Electronics Engineering (DEIS), University of
Bologna, where he was an Assistant Professor and
Research Associate in Electronics. In 1998, he joined
the Department of Electronics Engineering (DEA)
of the University of Brescia, Brescia, Italy. He is currently Full Professor of Electronics. He was an ST-Microelectronics consultant
for several years. His research activities covered circuit simulation techniques,
electromagnetic interference analysis in integrated circuits, several aspects of
pattern recognition and integrated voltage converters based on capacitors or on
inductors. Currently he is involved in integrated circuit design for innovative
applications and technologies, as for example, integrated UWB radars for civil
applications. He has authored more than 100 publications, including two books,
articles in journals, in conference proceedings and 16 patents.