1. Create a new ISE Project 2. Create KURM library (as explained in Lab 0 Directions) 3. The following steps are for creating your own source files (skip this for lab0): a. To create a new VHDL file, click the New Source Icon b. Choose VHDL Module and enter the name for the new file (it will automatically name an entity with the same name) c. You can choose to enter all of the ports, and specify their direction (for this class don’t use inout) and their size if applicable. If you leave bus unchecked, it will assume it’s 1 bit. If you check bus, you can enter the size. For a 4-bit signal, put the msb as 3, and the lsb as 0, etc. d. Click through to finish, and it will open a skeleton file with the specifications you just entered. 4. Create 2 VHDL files for each problem—one for the problems’ entity and architecture, one for the testbench entity and architecture. 5. Then create one additional file that will include all synthesis instantiations (we will show you how to do this).