Synopsys IC Compiler Tutorial for a logic block using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version 3.0 From the command line invoke this command with the script below updated with your design name and informaGon. The remainder of the script is commented out and should be executed one line at a Gme and the results should be verified. The script loads the libraries and design. Two windows will appear. The main window with command input and log output. The layout window with all cells placed on top of one another Helpful hints with layout. “f” fits the design in the screen. + and – are good for zoom Can pan with arrows This command will allocate space for the chip and place the pins evenly on the border. The purple boxes on the right are the unplaced cells. The core_uGlizaGon will determine how dense the design will be at the expense of routability later. This command simply describes the vdd and ground used by the standard cells. It may be necessary to run at the end of the process as well. This command creates power rings around the edge. Blue is metal 1, yellow metal 2 and Red is metal 3. Note also that via1 squares connect metal 1 to 2 and via2 Squares conect metal 2 to 3. This command creates addiGonal power network robustness but at the expense of routability later. The blue metal 1 is the power and ground ring on the top of the chip. The red metal 3 is the power strap that will help Ge each of the circuit rows to ground and vdd with less resistance. The command “place_opt” places all cells. The opGons “-­‐effort high” and “-­‐congesGon” may help. The congesGon opGon spreads cells apart that may be in areas of high rouGng to provide extra tracks and increase the odds of a successful route later. Change visibility of the pins to see the connectable metals used by the standard cells. The underlying cells are not visible to the logic designer / implementer. Later we will merge these shapes in with Custom Designer and the wells, polys and acGve areas will be visible. This command connects the rows to the rings/straps. This command inserts the clock tree. See the metal 2 and 3 lines below which are the clock tree. The “report_clock_tree” command. From this, the tree is 4 levels deep and has a max skew of 73 pS. Less than 200pS is a good rule of thumb. Timing shows the worst case path with “report_Gming”. Plenty of posiGve slack here. NegaGve slack means you have a problem. “route_opt –effort high” routes the rest of the design. This takes the longest of all steps and can be where the most problems occur if you design is too dense. Check the “route_opt” log for violaGons and good Gming To avoid violaGons, make your design less dense, use less straps for power, or use a technology with more metal layers. These may not be an opGon normally. This command will fix many problems: Route_search_repair \ -­‐rerun_drc \ -­‐loop “100”
\ Aaer everything else is finalized, we need to “fill” the empty space between cells to ensure conGnuity across the circuit rows. No more cells can be added aaer this step so we are almost done. Below, purple cells are standard cells and blue are fill. The rouGng visibility has been turned off to clearly see that it is filled. LVS is Layout Versus SchemaGcs. Basically this is a test for all of your connecGons. There are problems reported below. Under the verificaGon menu. If two shorts exist between ground and vdd with the net NULL. Rerun the derive_pg_connecGons command from the earlier in the stop and re-­‐run LVS. DRCs are Design Rules Checks and basically are tests that your spacings and widths are goods. As well as standard cell library placement on rows. Under the verificaGon menu. Write out the file to the Milkyway database. Also, you can write out a GDS file that is the standard format accepted by foundries. First use the set_write_stream_opGons -­‐output_pin {text geometry} -­‐keep_data_type write_stream -­‐lib_name uproc_LIB -­‐format gds "uproc.gds"