Answer all the three questions.
Q1. Consider the Self-Aligned Gate-Last Surface Channel MOSFET shown
below. The channel is made of undoped InGaAs. The source and drain are
the green regions and are made of n++ InGaAs. The metal contacts to the
source and drain are made of Ti/Pd/Au. Starting with the semi-insulating InP
wafer, discuss the fabrication steps by drawing appropriate cross-section
figures. In each figure, identity the process carried out giving possible process
parameters. You need to draw the figures neatly.
[10 marks]
Q2. In a silicon wafer, a trench with the shape as shown below needs to be
fabricated. The red color region in the figure is photoresist. Provide the
fabrication steps and identify the corresponding processes by drawing neat
figures for each step.
[8 Marks]
Q3. On a silicon wafer of (100) orientation, a trench of 500 nm depth is made
using an oxide mask of 200 nm thickness. If oxidation is carried out on this
wafer, silicon dioxide will grow in the trench and on the silicon dioxide.
However, the oxidation growth rate will be lower in the region where the
silicon dioxide is present as compared to the oxidation growth rate in the
trench region. Assume that wet oxidation is carried out. Choose an oxidation
temperature of your choice. Find the total time at which the oxide thicknesses
in the trench and outside the trench will catch up making the silicon wafer
surface planar.
[7 Marks]