DATASHEET SpyGlass CDC Comprehensive, lownoise clock domain crossing verification Overview Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues. Introduction CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Clock Domain (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass® provides a high-powered, comprehensive solution. SpyGlass RTL Signoff Lint Clock domain crossing verification Reset domain crossing verification Power estimation and exploration Design for test Figure 1: SpyGlass RTL signoff solution synopsys.com Features and Benefits • Protocol Independent Analysis, recognition of widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations • Architecture for scalable CDC and RDC verification • Simple setup by automatically extracting the clock, reset and clock domains information; It can also extract the same information from existing SDC constraints providing a jump start to the users • Comprehensive structural and functional analysis using formal based and simulation based solutions to deliver signoff quality • Highest performance and CDC/RDC centric debug capabilities • Hierarchical SoC flow to support IP based design methodologies to deliver quickest turnaround time for very large size SoCs • Integrated with other SpyGlass solutions for RTL signoff for lint, constraints, DFT and power • Low learning curve and ease of adoption Check if signal A is held long enough to be captured by slower clock clk_B F1 D clk_B EN D clk_A D F1 A F2 B F3 C A F4 clk_B clk_A F1 F2 F3 Improper data enable sequence X 01 clk_A Data changing while EN is active clk_B Data loss in fast to slow transfer D1 10 rst_n D1 D2 clk_B rst_n clk_B clk_B D2 F6 F7 F8 Y F2 X Y F3 o_rst_n o_rst_n Synchronous de-assert 01 01 11 10 10 10 clk_A EN F3 clk_A B clk_B F2 clk_B clk_B Re-convergence of synced signals Reset synchronization Figure 2: Typical CDC bugs CDC Bugs The success of static CDC verification tools is determined by two critical measures—the time taken to sign off the RTL and the completeness of CDC verification. Conventional CDC analysis tools fall short in both areas. They generate large amounts of noise (false violations), extending the verification cycle, and provide poor coverage on various types of CDC issues. Figure 2 describes the class of bugs/scenarios, which, if not verified correctly, can cause design respins. These bugs can be structural as well as functional in nature. 2 Market Leader Hierarchical Intuitive debug Low noise Performance Signoff QoR Simple setup SpyGlass CDC Methodology Figure 3: Scalable CDC verification SpyGlass CDC Verification Synopsys’ SpyGlass CDC architecture is based on six pillars of scalable CDC verification (see Figure 3). Ease of Use and Functionality • Simple setup assisted by automatically extracting the clock, reset and clock domains information. The tool can also extract the same information from existing SDC constraints, providing a jump-start to the users • Comprehensive structural and functional CDC analysis using formal-based and simulation-based solutions to deliver signoffquality CDC verification • Protocol-independent analysis, recognition of the widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations • Fast performance • CDC-centric debug capabilities • Hierarchical SoC flow to support IP-based design methodologies to deliver quickest turnaround time for very large SoCs • Integrated with the SpyGlass solution which targets other RTL analysis, like Lint, DFT, constraints and power Solving Problems at the RTL and Netlist Level SpyGlass CDC provides an easy-to-use and comprehensive guide for solving CDC problems at the RTL and gate-level netlist to avoid costly respins. • Methodology documentation and rule-sets delivered as part of the product • User-guided CDC methodology results in fewer, more meaningful violations, saving time for the RTL designer • Walks users through a series of recommended steps to analyze CDC problems at block-level as well as chip-level; the steps include design setup, setup checks, design-unit integration, chip-level CDC verification, report review and CDC verification signoff 3 Separating True from False Violations To isolate real clock domain crossing issues, it is necessary to detect various synchronization schemes, not just basic two-flop or multi-flop synchronizers, and perform comprehensive protocol-independent analysis. As part of the protocol-independent analysis, SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent. It also detects the list of potential quasi-static signals. Users review the auto generated list of quasi-static signals and use them as part of the setup. This helps to produce CDC analysis with the lowest possible noise. SpyGlass CDC has integrated structural and functional CDC analysis. Users make use of formal based functional CDC analysis to verify CDC protocols. Users also have the flexibility to generate SystemVerilog Assertions (SVA) to verify CDC protocols and assumptions made for structural analysis. SpyGlass CDC also provides a signoff-quality hierarchical SoC flow to perform CDC analysis for very large SoCs. This helps users to use a divide-and-conquer approach to achieve the highest productivity and quickest turnaround time. The SpyGlass Predictive Analyzer® technology significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex SoCs fueling today’s consumer electronics revolution. ©2017 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners. 12/05/17.CS11926_SpyGlassCDC_DS.
