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Sinusoidal Pulse-width Modulated Three-phase Multilevel Inverter Topology
a
Charles Ikechukwu Odeh
a
Department of Electrical Engineering, University of Nigeria, Nsukka, Nigeria
Published online: 20 Nov 2014.
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To cite this article: Charles Ikechukwu Odeh (2015) Sinusoidal Pulse-width Modulated Three-phase Multi-level Inverter
Topology, Electric Power Components and Systems, 43:1, 1-9, DOI: 10.1080/15325008.2014.963260
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Electric Power Components and Systems, 43:1–9, 2015
C Taylor & Francis Group, LLC
Copyright ISSN: 1532-5008 print / 1532-5016 online
DOI: 10.1080/15325008.2014.963260
Sinusoidal Pulse-width Modulated Three-phase
Multi-level Inverter Topology
Charles Ikechukwu Odeh
Department of Electrical Engineering, University of Nigeria, Nsukka, Nigeria
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CONTENTS
1. Introduction
2. Proposed Three-Phase Multi-Level Inverter
3. Simulation and Experimental Results
4. Conclusions
References
Abstract—This article presents a sinusoidal pulse-width modulated
three-phase multi-level inverter topology. In this configuration, the
basic two-level, three-phase inverter is modified to synthesize higher
voltage levels by the insertion of two auxiliary switches per phase leg.
The multi-level inverter configuration generates output voltage levels
similar to the corresponding well-known conventional diode-clamped
flying capacitors and cascaded H-bridge inverters but with fewer
power circuit components and more simplicity. For output voltage
and frequency variations demanded by such applications as variablespeed drives, active power filters, photovoltaic power conversions,
etc., the sinusoidal pulse-width modulation technique is employed
in the generation of the gating signals for the proposed three-phase
multi-level inverter. A balanced three-phase R-L load is applied at
the inverter output terminals, and the inverter performance is compared with that of other sinusoidal pulse-width modulated conventional multi-level inverter configurations. The validity of the proposed
multi-level inverter topology and the modulation scheme are verified
through simulations and experiments.
1.
Keywords: Inverter, multi-level, cascaded, pulse-width modulation,
H-bridge, total harmonic distortion
Received 4 February 2013; accepted 19 July 2014
Address correspondence to Charles Ikechukwu Odeh, Department of
Electrical Engineering, University of Nigeria, Nsukka 410, Nigeria. E-mail:
charles.odeh@unn.edu.ng
Color versions of one or more of the figures in the article can be found online
at www.tandfonline.com/uemp.
INTRODUCTION
Multi-level converters (MLCs) are currently popular for
medium-voltage high-power applications due to their reduced
rating of power semiconductor devices; improved quality of
output voltage; near sinusoidal input currents; lower commonstress; smaller input and output filters;
mode voltages; less dv
dt
and increased efficiency due to the possibility of low switching
operation, reduced output torque ripple, reduced electromagnetic interference (EMI) problems, and possible fault-tolerant
operation [1–6].
The different topologies mainly reported in the literature
for multi-level inverters (Figure 1) include diode-clamped or
neutral-point converters (NPCs) [7], flying-capacitor converters (FCs) [8], and cascaded H-bridge converters (CHBs) [9]. In
addition, generalized multi-level inverter topology with selfvoltage balancing [10], mixed-level hybrid multi-level cells
[11], asymmetric hybrid multi-level cells [12], soft-switched
multi-level inverters [13–15], and modular multi-level cascade
converters (MMCCs), [16–21] have been proposed. The topology of the NPC inverter is limited to three-level operation
1
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Electric Power Components and Systems, Vol. 43 (2015), No. 1
due to capacitor voltage balancing issues as well as excessive clamping diodes required for high-level inverters [4]. The
topology of capacitor-clamped inverters is limited to three or
four levels due to such limitations as capacitor voltage balance
requirement, pre-charge of the capacitors at the start, and need
of larger number of capacitors. In addition, this topology is
not suitable for low and medium switching frequencies due
to the high cost of flying capacitors [22]. For higher-level operation, cascaded inverters are preferred as they require the
least number of components compared to other topologies as
well their modularized circuit layout, packaging is possible
because each level has a similar structure [22]. Although the
modular structure solves the voltage imbalance problem, this
approach requires many isolated DC sources and link voltage
controllers.
The concept of enhancing the quality of the waveforms of
the classical inverter by inserting an auxiliary circuit between
the source and the power switches of the basic full-bridge inverter was reported for a single-phase inverter only in [23–28].
In [23], the auxiliary circuit was formed from two switching
elements and two diodes, while in [24, 25] the auxiliary circuit
contained one switching element and a full bridge of diodes. In
[26], a switched capacitor circuit was used, which was formed
from two diodes, two capacitors, and a switching element. As
a result, a five-level voltage waveform was obtained at the
inverter output. An extension of this principle was seen in
[27], where two auxiliary circuits were inserted to synthesize
a seven-level voltage waveform. In [28], the concept of cascading similar inverter modules was explored, where four of
the basic five-level inverter cells proposed in [24] were cascaded. The result is the synthesis of a 17-level output voltage
waveform for single-phase applications. In all, the resultant
effect is a significant suppression of the load harmonic currents when compared with the classical three-level full-bridge
inverter [29–33].
In line with the aforementioned principle and for threephase system, an inverter configuration was presented in [34]
wherein the output line voltage of five levels is synthesized.
In this referred work, pre-computed switching angles resulted
in fixed output voltage. But to be used on such applications as
the variable-speed drive, active power filter, photovoltaic power
conversion, etc., on-line variation of the inverter output voltage amplitude and frequency is imperative. This article proposes a sinusoidal pulse-width modulated (PWM) three-phase
multi-level inverter topology consisting of two bi-directional
switches inserted between the DC source and each phase leg
of the classical full-bridge three-phase inverter. As a result, a
seven-level output line voltage waveform is synthesized per cycle. The multi-carrier sinusoidal pulse-width modulation technique is employed in the generation of the gating signals for
the proposed three-phase multi-level inverter for on-line variation of inverter output voltage and frequency. The increased
level in the PWM output voltage waveform drastically reduced
the harmonic components inherent in the classical three-level,
three-phase full-bridge inverter and also in the inverter configuration proposed in [34]. Greater advantage of the proposed
three-phase inverter topology is seen in the reduction of the
active power semiconductor switches when compared with
other classical three-phase, PWM multi-level inverters. Additionally, with this low-power circuit component count, the
proposed three-phase inverter achieves a total harmonic distortion (THD) value of the output voltage that is on par with
those of the diode-clamped and flying capacitor multi-level
inverter configurations of the same level.
2.
PROPOSED THREE-PHASE MULTI-LEVEL
INVERTER
The proposed inverter configuration, operational principles,
and modulation scheme are given in this section. Simulation and experimental results are adequately presented to verify the validity of the proposed three-phase PWM inverter
configuration.
2.1.
Principle and Operation of the Proposed
Three-phase Multi-level Inverter
The proposed three-phase inverter topology, shown in Figure 2,
is a modification of the basic three-phase, three-level inverter
configuration, where two (upper and lower) auxiliary circuits
are inserted per phase leg. Each auxiliary circuit constitutes
one switching element and full-bridge diodes. The DC source
is split into three equal parts by capacitor banks. One terminal
of each of the upper and lower auxiliary circuits is connected
to two-thirds and one-third of the split DC source, respectively,
while the other terminals of the upper and lower are hooked to
the center of the respective phase leg. In all, only four active
switches are utilized per phase leg.
Proper switching of the inverter can produce four PWM
output voltage levels per phase—0, Vs /3, 2Vs /3, and Vs —and
seven PWM line-line output voltage levels—Vs /3, 2Vs /3, Vs ,
0, –Vs /3, –2Vs /3, and –Vs —for every cycle.
For phase A, the synthesized voltage levels and the corresponding switching states of the proposed three-phase inverter
are summarized in Table 1.
2.2.
PWM Modulation Scheme
The carrier-based modulation scheme for multi-level inverters is adopted in the generation of the gating pulses for the
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Odeh: Sinusoidal Pulse-width Modulated Three-phase Multi-level Inverter Topology
3
FIGURE 2. Configuration of proposed three-phase, PWM
multi-level voltage source inverter.
proposed inverter topology. Precisely, the in-phase disposition
(IPD) modulation technique of the level-shifted multi-carrier
modulation scheme is used, since it provides the best harmonic
profile of all the multi-carrier modulation schemes [35]. In this
modulation scheme, a multi-level inverter with m voltage levels requires (m – 1) triangular carriers, all having the same
frequency, phase, and amplitude. The (m – 1) triangular carriers are vertically disposed such that the bands they occupy
are contiguous. The modulating signal is usually a three-phase
sinusoidal wave with adjustable amplitude and frequency. The
gate signals are generated by comparing the modulating wave
with the carrier waves. The frequency modulation index is
Switching states
Inverter phase voltage, Van
g1
ga2
ga1
g4
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
VS
3
2VS
3
VS
FIGURE 1. Per phase circuit configuration of the conventional multilevel inverters: (a) 4-level diode-clamped multilevel inverter. (b) 4-level flying capacitor multilevel inverter.
(c) 4-level CHB multilevel inverter.
TABLE 1. Switching states and output voltages of proposed threephase multi-level inverter
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Electric Power Components and Systems, Vol. 43 (2015), No. 1
FIGURE 4. Simulated inverter output line voltages, ma = 0.9.
signals. As depicted in Figure 3, line voltage VAB is simply the
difference of the two phase voltages VAn and VBn .
The logical expressions from which the gating pulses of
phase A (g1 , ga2 , ga1 , and g4 ) are derived are given in Eqs.
FIGURE 3. Phase A switching patterns and output voltages of
the proposed three-phase, PWM multi-level inverter.
given by
mf =
fc
,
fm
(1)
where f c and f m are the frequency of the carriers and the
modulating signals, respectively; the amplitude modulation
index is defined as
ma =
Vm
,
Vc (m − 1)
(2)
where Vm and Vc are the peak amplitude of the modulating
wave and peak amplitude of each carrier wave.
Figure 3 shows the comparison of the modulating wave
(vma ) and carrier signals (T 1 , T 2 , and T 3 ) that generated the
four gating pulses (g1 , ga2 , ga1 , and g4 ) for phase A power
switches; synthesized phase voltage Van is also shown. Gating
pulses and phase voltages for phases B and C are obtained by
similar comparison of vmb and vmc with the triangular carrier
FIGURE 5. Simulated inverter output line currents, ma = 0.9.
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Odeh: Sinusoidal Pulse-width Modulated Three-phase Multi-level Inverter Topology
5
FIGURE 8. FFT analysis of synthesized output line voltage
of four-level diode-clamped inverter.
FIGURE 6. Simulated inverter output line voltages, ma = 0.7.
g4 = vma < T3 .
(6)
(3)–(6):
g1 = vma > T1 ,
(3)
ga2 = (vma < T1 ) AND (vma > T2 ) AND vma > 0, (4)
ga1 = [(vma > T3 ) AND (vma < 0)] OR
[(vma < T2 ) AND (vma > 0)] ,
(5)
FIGURE 7. FFT analysis of synthesized output line voltage
of proposed inverter.
It is worth mentioning that VAB is composed of three, five,
and seven voltage levels for 0 ≤ ma ≤ 0.33, 0.33 ≤ ma ≤ 0.74,
and 0.74 ≤ ma ≤ 1.0, respectively.
FIGURE 9. FFT analysis of synthesized output line voltage
of four-level flying capacitor inverter.
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Electric Power Components and Systems, Vol. 43 (2015), No. 1
Inverter type
Main
switching
device
Main diodes
DC bus
Balancing
capacitor
Proposed
inverter
Diodeclamped
Flying
capacitors
Cascaded
H-bridge
4
6
6
12
8
1
0
6
1
0
0
1
6
0
3
0
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TABLE 2. Comparison of proposed PWM inverter with well-known
three-phase inverters of the same voltage level on the basis of number
of power circuit components per phase
3.
3.1.
SIMULATION AND EXPERIMENTAL RESULTS
Simulation Results
To assess the validity of the proposed multi-level inverter
topology, simulations are normally carried out in advance.
MATLAB SIMULINK (The MathWorks, Natick, Massachusetts, USA) simulated the proposed three-phase inverter
topology in accordance to the PWM switching scheme presented in Figure 4 and Table 1. A balanced three-phase starconnected RL load with 40-Ω resistance and 50-mH inductance per phase was used.
Figure 4 show the simulated inverter output line voltage
waveforms for an amplitude modulation index value of 0.9 and
a carrier frequency of 2 kHz. The line-to-line voltage waveS
S
, −2V
, and − VS ,
forms show seven levels: V3S , 2V3 S , VS , 0, −V
3
3
as earlier predicted. For the indicated loading condition, the
simulated output line current waveforms are shown in Figure 5.
To typify the voltage variation capability of the proposed
PWM three-phase inverter configuration, modulation index ma
is reduced to a value of 0.7, and the corresponding synthesized
line voltages are given in Figure 6.
Spectral analysis of the inverter line voltage waveform in
Figure 4 is conducted. The spectral results are displayed in
Figure 7, wherein a THD value of 23.0% is achieved in the line
voltage waveform. Under the same simulation conditions and
voltage level, the diode-clamped and flying capacitor threephase multi-level inverters, the phase configurations of which
are shown in Figures 1(b) and 1(c), are simulated. The spectral
FIGURE 10. Experimental gate signals for phase A: g1 , ga2 ,
ga1 , and g4 .
analyses results of the individual synthesized line voltages are
shown in Figures 8 and 9, respectively, which is in accordance
with the results in [35]. In these simulated results, the line
voltage waveforms have THD values of 24.67% and 24.63%
for the four-level diode-clamped and flying-capacitor multilevel inverters, respectively.
With respect to obtaining a quasi-sinusoidal voltage waveform at the output terminal, the proposed inverter topology
performance is on par with those of the aforementioned two
conventional multi-level inverter configurations.
Further comparison of the proposed three-phase inverter
configuration with the major topologies in the literature in
terms of power circuit component count is given in Table 2.
Power switches: IGBT EUPEC BSM 75 GB 120 DLC (EUPEC
Power Electronics, Union, NJ, USA)
Fast switching diodes in the auxiliary circuits: STTH12012TVL
R = 30 Ω, L = 50 mH
C 1 , C 2 , C 3 = 5000 µF, 400 V
TABLE 3. Prototype specification
FIGURE 11. Experimental inverter line vab , vbc , and vca output
voltages, ma = 0.9.
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Odeh: Sinusoidal Pulse-width Modulated Three-phase Multi-level Inverter Topology
FIGURE 14. Experimental inverter line vab , vbc , and vca output
voltages, ma = 0.7.
FIGURE 12. Experimental inverter line iab , ibc , and ica currents.
3.2.
Experimental Results
Based on the simulation results, a laboratory prototype of the
three-phase multi-level inverter was set up and tested to verify
its validity. Basic complementary metal-oxide semiconductor
(CMOS) logic gates and TL 084 IC (Texas Instruments, Dallas,
TX, USA) were deployed in the generation of the inverter 12
gating pulses, four of which were specified in Figure 3 for phase
A. Figure 10 shows experimentally obtained gating signals for
the switches of one of the inverter legs g1 , ga2 , ga1 , and g4 .
The prototype specification is given in Table 3.
Shown in Figure 11 are the experimental waveforms of
output line voltages vab , vbc , and vca . For the loading condition
FIGURE 13. Experimental inverter line vab , vbc output voltages and corresponding iab , ibc line currents.
7
specified in Table 3, the corresponding output line currents are
shown in Figure 12.
The experimental waveforms for the line a and b voltages
are shown in Figure 13, wherein the corresponding line currents are incorporated. For a cycle, these voltage waveforms
exhibit seven levels as earlier proposed for line voltages.
Experimentally validating the voltage variation capability
of the proposed PWM three-phase inverter configuration, modulation index ma is reduced to a value of 0.7 in the built prototype circuit, and the corresponding line voltages are shown in
Figure 14.
4.
CONCLUSIONS
This article has presented a sinusoidal PWM three-phase
multi-level inverter topology, where additional auxiliary circuits consisting of six bi-directional switches have been inserted between the DC voltage source and the full-bridge power
switches of the classical three-phase inverter configuration. For
output voltage and frequency variations, as demanded by some
applications, the sinusoidal pulse-width modulation technique
has been used in the generation of the gating signals for the
power switches. The operational principles and switching functions have been discussed in detail. The proposed PWM multilevel inverter exhibited similar behaviors of the conventional
diode-clamped and flying capacitors inverters earlier reported,
but with reduced power circuit components and ease of implementation. The spectral analyses of the synthesized output line
voltages were given. The proposed three-phase inverter topology has been compared with classical three-phase multi-level
inverter configurations of the same voltage level, with respect
to the power circuit component count and spectral analysis re-
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Electric Power Components and Systems, Vol. 43 (2015), No. 1
sults at the same modulation conditions. It has been shown that
the harmonic spectrum performance of the proposed inverter
is quite on par with those of the diode-clamped and flying capacitor seven-level inverters. However, the proposed inverter
topology presents a power circuit of reduced component count.
Simulation and experimental results obtained validated the
proposed three-phase, PWM, multi-level inverter topology.
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BIOGRAPHY
Charles Ikechukwu Odeh received his B.Eng., M.Eng.,
and Ph.D. in electrical engineering from the Department of
Electrical Engineering, University of Nigeria, Nsukka, in
2002, 2006, and 2010, respectively. He is a senior lecturer at
the Department of Electrical Engineering, University of Nigeria, Nsukka. From January through September 2011, he was
an exchange scholar sponsored by the U.S. Navy at Tennessee
Technological University, Cookeville, TN. Currently, he is an
Alexandra Von Humboldt (AvH) fellow at E.ON Energy Research Center, RWTH University, Germany. His research interests are power electronics multi-level converter topologies
and applications.