DIGITAL LOGIC DESIGN
Lab Instructor: Engr. Sumair Aziz
Department of Electronics Engineering
University of Engineering & Technology, Taxila.
1
TABLE OF CONTENTS
Safety Rules:
1. In dealing with digital logic component IC’s, always properly note the position of VCC
and Ground pins as the wrong connection of these pins may lead to the IC damage.
2. IC’s should always be inserted in the specific place on the bread board otherwise all the
pins of an IC may get short.
3. Carefully note the input and output pins of IC’s. If you accidentally exchange their
connections, the internal circuit of IC may destroy.
4. Thoroughly check the circuit connection before power on. In case of any wrong
connection, specifically short circuiting of VCC and Ground may damage the Lab Trainer.
2
List of Experiments
1. Verification of Truth Table of all Gates using ICs.
2. Verification of DeMorgan’s Law using Universal Gates.
3. Gate Level Modeling in Verilog.
4. Implementation of Half Adder and Full Adder.
5. Design and Simulation of Half Adder, Full Adder and Four-Bit Adder in Verilog.
6. Implementation of Decoder and Multiplexer.
7. Design and Simulation of Decoder and Multiplexer using Data Flow Modeling and
implementation of Multiplexer and Decoder in Verilog.
8. Implementation of Latches and Flip Flips using Gates
9. Design and Simulation of various Flip Flops in Verilog HDL
10. Implementation of Counter and Universal Shift Registers
11. Design and Simulation of Flip Flop and Counter in Verilog HDL
12. Design and Implementation of a Traffic Light Controller using FSM
3
EXPERIMENT No. 01
VERIFICATION OF TRUTH TABLE OF ALL GATES USING IC’S
PRE LAB TASK
Objectives
• To learn how to build IC based circuits on bread board.
• To get familiar with logic gates.
• To verify truth tables of all Logic Gates.
• To learn how to build complex circuits using basic gates.
Introduction
Gates, more specifically Logic Gates, are the type of digital circuit that process signals which are
represented as 1 or 0. Usually the positive supply voltage +5V is represented as 1 and 0V (Ground)
is represented as 0. These ‘1’ and ‘0’ are known as Logic States. Other terms that are used for 1
and 0 states are shown in the table below.
Logic States
1
0
+5V
0V
True
False
High
Low
On
Off
Theory
There are three main types of logic gates which are further subdivided. These categories are based
on their function. Logic gates are usually expressed in capital letter in order to make it clear that
the term refers to a logic gate. The main types and their subdivision are listed as:
I.
Basic Gates:
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a) AND Gate
b) OR Gate
c) NOT Gate
II.
Universal Gates:
a) NAND Gate
b) NOR Gate
III.
Combinational Gates:
a) XOR Gate
b) XNOR Gate
The function of these gates is as under:
AND Gate
It is the type of logic circuit that gives a logic state ‘1’ as output only if all inputs are at logic state
‘1’. This function is denoted by dot (.). So the Boolean expression for AND Gate is given as:
𝐺 = 𝐴. 𝐵 = 𝐴𝐵
AND Gate is represented with following symbol:
OR Gate
The OR gate is an electronic circuit that gives ‘1’ as output if one or more of its inputs are at logic
state 1. A plus sign (+) is used to show the OR operation. It’s expression is given as:
𝐺 =𝐴+𝐵
Symbolically it is represented as:
5
NOT Gate
The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It
is also known as an inverter. This gate is unique in this sense that it has only one input. If the input,
let us say A, is ‘1’, the output is ‘0’ and if the input is ‘0’ the output is ‘1’. This inverted output is
known as NOT A. It is expressed as:
𝐺 = 𝐴̅ = 𝐴΄
Its symbol is:
NAND Gate
It is a NOT-AND gate which is equal to an AND gate tailed by a NOT gate. The output of this
logic gate is ‘1’ whenever any of its inputs are ‘0’. Its Boolean expression is:
𝐽 = ̅̅̅̅
𝐴𝐵
Its symbol is:
NOR Gate
It is a NOT-OR gate which is equivalent to an OR gate tailed by a NOT gate. The output of NOR
gate is ‘0’ whenever any of the inputs are ‘1’. Its expression is:
̅̅̅̅̅̅̅̅
𝐽=𝐴
+𝐵
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Its symbol is:
XOR Gate
The 'Exclusive-OR' gate is a logic circuit that will give a ‘1’ as output if either, but not both, of
its two inputs are ‘1’. An encircled plus sign (⊕) is used to show the X-OR operation. The
expression and symbol of this gate are as under:
𝑅 =𝐴⊕𝐵
XNOR Gate
The 'Exclusive-NOR' gate reverse to the X-OR gate. It will give a ‘0’ output if either, but not both,
of its two inputs are ‘1’. The expression and symbol of this gate are:
𝑅 = ̅̅̅̅̅̅̅̅
𝐴⊕𝐵
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7404 IC
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➢ 7408 IC
➢ 7432 IC
➢ 7400 IC
➢ 7402 IC
➢ 7486 IC
➢ 74266 IC
Experimental Procedure
• Place NOT gate IC on the bread board of the AT-700.
• Connect pin # 7 to Gnd and pin # 14 to +5V VCC available on DC Power Panel over the
Laboratory trainer.
• Use Logic Switch available on the Laboratory board as input switch.
• Use Led Panel to display output.
• Turn the AT-700 power on.
• Now apply logic input ‘0’ and ‘1’, one-by-one and note the output shown by Led. If the
Led glows it is considered as logic ‘1’ and if it remains off it is assumed as logic ‘0’.
• Replace NOT Gate IC with other ICs and note their result in the table.
Observations
NOT GATE:
Input
E
0
1
Output
G
AND GATE:
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Inputs
E
0
0
1
1
F
0
1
0
1
Output
G
OR GATE:
Inputs
E
0
0
1
1
F
0
1
0
1
Output
G
NAND GATE:
Inputs
H
0
0
1
1
I
0
1
0
1
Output
J
NOR GATE:
Inputs
H
0
0
1
1
I
0
1
0
1
Output
J
XOR GATE:
Inputs
P
0
Q
0
Output
R
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0
1
1
1
0
1
XNOR GATE:
Inputs
P
0
0
1
1
Q
0
1
0
1
Output
R
Questions:
1. What is the detailed expression of XOR Gate?
2.
3.
4.
5.
_______________________________________________________________________
Which M-ary type of circuit are these gates?
_______________________________________________________________________
Give the types of logic technologies upon which these gates are designed?
_______________________________________________________________________
_______________________________________________________________________
Mention the voltage range for logic ‘0’ and ‘1’ for CMOS technology.
_______________________________________________________________________
_______________________________________________________________________
Mention the voltage range for logic ‘0’ and ‘1’ for TTL technology.
_______________________________________________________________________
_______________________________________________________________________
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LAB REPORT
Discussion of Results:
1. Can the output of one logic gate be used as input for other gates? Give reason.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
2. Draw the symbolic diagram and complete the truth table for the following expression.
𝑫 = 𝑷𝑸 + 𝑷′ 𝑸 + 𝑷𝑸′ + 𝑷′𝑸′
How many gates are required to implement the above expression? __________________
P
Q
0
0
0
1
1
0
1
1
D
3. Draw the detailed diagrams of all ICs used in lab.
Conclusion/Summary:
11
EXPERIMENT No. 02
VERIFICATION OF DEMORGAN’S LAW USING UNIVERSAL GATES
PRE LAB TASK
Objectives
• To verify De Morgan’s law statements through the use of IC.
• To understand how to build all basic Gates using NAND and NOR Gates.
• To verify all equivalent Gate operations.
Introduction
There are two theorems that were proposed by De Morgan. These theorems are used commonly
in Boolean algebra. The first theorem states:
Two individually complemented variables when ORed is equivalent to the whole complement of
AND of two variables.
̅̅̅̅̅
𝐴̅ + 𝐵̅ = 𝐴.
𝐵
The second theorem is stated as:
Two individually complemented variables when ANDed is equivalent to the whole complement
of OR of two variables.
̅̅̅̅̅̅̅̅
𝐴̅ . 𝐵̅ = 𝐴
+𝐵
Theory
A universal gate is one which implements any Boolean expression without using any other gate
type. The gates, NAND and NOR, are universal because these are inexpensive and easy to fabricate
and they act as the basic building block for the fabrication of all IC digital logic families.
NAND Gate is a Universal Gate:
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To prove that any Boolean function can be executed using only NAND gates, we will demonstrate
that the AND, OR, and NOT operations being performed using only NAND gates.
Implementation of NOT Gate using NAND Gate
There are two ways in which a NAND gate can be used as NOT gate (also called inverter). The
figure below shows two ways in which a NAND gate can be used as an inverter (NOT gate).
1. All input pins of NAND gate connected to the input signal A gives an output A΄.
2. One input pin of NAND gate is connected to the input signal A while all other input pins
are connected to logic 1. The output will be A΄.
Implementation of AND Gate using NAND Gates
A NAND gate followed by a NAND inverter is equivalent to AND gate as shown in the figure
below:
Implementation of OR Gate using NAND Gates
An OR gate can be replaced by NAND gates as shown in the figure below:
Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.
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NOR Gate is a Universal Gate:
We will demonstrate basic NOT, AND and OR gate operations using NOR gates in order to prove
that any Boolean function can be implemented using NOR gates only.
Implementation of NOT Gate using NOR Gate
NOR gate can be used as NOT in following two manners:
1. All input pins of NOR gate connected to the input signal A gives an output A΄.
2. One input pin of NOR gate is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A΄.
Implementation of OR Gate using NOR Gates
A NOR gate followed by a NOR inverter is equivalent to OR gate as shown in the figure below:
Implementation of AND Gate using NOR Gates
An AND gate can be replaced by NOR gates as shown in the figure below:
Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.
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Equivalent Gates:
De Morgan theorem statements are the basis of equivalent gates.
1. From first statement it is obvious that a NAND Gate is equivalent to inverted input OR
Gate:
2. From second statement it is clear that a NOR Gate is equivalent to inverted input AND
Gate:
3. An AND Gate is equivalent to an inverted input NOR Gate:
4. An OR Gate is equivalent to an inverted input NAND Gate:
5. Two NOT Gates in series are equivalent to a Buffer because the two inverters cancel each
other as A’’ = A.
LAB SESSION
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Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7400 IC
➢ 7402 IC
Experimental Procedure
• Place NAND Gate IC on the bread board of the AT-700 and layout the circuit of NOT Gate
using NAND Gate.
• Connect pin # 7 to Gnd and pin # 14 to +5V VCC available on DC Power Panel over the
Laboratory trainer.
• Use Logic Switch available on the Laboratory board as input switch.
• Use Led Panel to display output.
• Turn the AT-700 power on.
• Apply all logic input combinations to verify the equivalence.
• Now draw all equivalent circuits and verify their result.
Observations
BUFFER GATE:
Input
A
0
1
Output
Y
Draw Following
AND GATE EQUIVALENT TO NOR GATE:
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OR GATE EQUIVALENT TO NAND GATE:
NAND GATE EQUIVALENT TO INVERTED-OR GATE:
NOR GATE EQUIVALENT TO INVERTED-AND GATE:
NAND GATE EQUIVALENT TO OR GATE:
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NOR GATE EQUIVALENT TO AND GATE:
Questions:
1. How many NAND Gates are required to implement OR Gate?
2.
3.
4.
5.
_______________________________________________________________________
How many NOR Gate ICs are required to implement AND Gate?
_______________________________________________________________________
How many NOR Gates are available in a single NOR Gate IC?
_______________________________________________________________________
How many NOT Gates are available in a single IC of NOT Gate?
_______________________________________________________________________
How many equivalent gates can be designed using De Morgan’s Theorem?
_______________________________________________________________________
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LAB REPORT
Discussion of Results
1. Draw the circuit for the expression of XNOR Gate using basic gates.
Conclusion / Summary:
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EXPERIMENT No. 03
GATE LEVEL MODELING IN VERILOG
Objectives
• To learn the basics of Verilog.
• To get started with coding in ModelSim.
• To understand gate level modeling and write codes for all gates.
• To understand how to write test bench.
Introduction
From now on we will work with a hardware description language (HDL). A hardware description
language is a type of language that defines hardware of a digital system, in a written form. It can
be used to signify logical diagrams, Boolean expressions and other complex digital circuits. The
language subjects can be stored and retrieved easily and can be treated by computer software in an
effective manner. Two major applications of this language are:
1. Simulation of Logic
2. Synthesis
Logical Simulation
It is the picture of the structure and behavior of a digital logical system through the use of a
computer. The code that tests the working of the design is called “Stimulus” or “Test Bench”.
Synthesis
Logical synthesis is the development of a list of components and their interconnections (called a
Netlist) from the module of a digital system in HDL.
Design Methodologies
There are basically two types of design methodologies:
✓ top-down design methodology
✓ bottom-up design methodology
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In a top down methodology, we describe the top level block and detect the sub blocks required to
build the top level block. We further divide the sub blocks until we reach to leaf cells, which cannot
be further subdivided. The following figure shows the top-down design:
Top Level Block
Sub-Block 1
Leaf Cell
Sub-Block 2
Leaf Cell
Sub-Block 3
Leaf Cell
Leaf Cell
Figure 1: Top down design methodology
In a bottom up design methodology, we first find the basic building blocks that are available to
us. Then we build bigger cells using these basic blocks. These cells are then used for building
higher-level blocks until we reach the top level block in the design. Following figure shows the
bottom-up design process:
Top Level Block
macro cell 1
Leaf Cell
macro cell 1
Leaf Cell
macro cell 1
Leaf Cell
Leaf Cell
Figure 2: Bottom-up design methodology
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Theory
Levels of Abstraction in Verilog
The level of abstraction to define a module can be changed without any change in the environment.
There are five levels of abstraction:
✓ Gate Level
✓ Switch Level
✓ Data Flow Level
✓ Functional Level
✓ Register Transfer Level
Gate (Structural) Level
A slightly higher level of abstraction is the gate level, which refers to the circuit description as a
netlist of basic logic gates and functions. These gates have one scalar output and multiple scalar
inputs.
Switch Level
The lowest level of abstraction would be the switch level, which refers to the description of the
circuit as a netlist of transistor switches. This is a more detailed modeling scheme that can catch
some additional electrical problems when transistors are used in this way. Now-a-days, little-used
because circuits generally aren’t built this way.
Data Flow Level
For small circuits, the gate level modeling works very well because the number of gates are limited
and designer can instantiate and connect each and every gate individually. However, in complex
design the number of gates is very large. Thus applying the function at a level higher than gate
level is nice choice. Dataflow modeling has become a popular design approach as logic synthesis
tools have become very sophisticated. This approach allows the designer to optimize the circuit in
terms of data flow.
Behavioral Modeling (Functional and Algorithmic Level)
Verilog provides the designer freedom to define the design functionality in an algorithmic manner.
In other words, the designer explains the behavior of the circuit. The concept in this modeling is
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as simple as writing the logic in C language. Verilog behavioral models contain procedural
statements that control the simulation and manipulate variables of the data types. The activity starts
at the control constructs initial and always. Each initial statement and each always statement starts
a separate activity flow. All of the activity flows are concurrent, allowing the user to model the
inherent concurrence of hardware.
Register Transfer Level
Verilog permits the designer to mix and match all four levels of abstraction in a design. In the
digital design community, the term Register Transfer Level (RTL) is frequently used for a Verilog
description that uses a combination of behavioral and data flow constructs and is acceptable to a
logical synthesis tool. RTL is a combination of Behavioral and Data flow modeling which should
be synthesizable. RTL description is more complex and less technology dependent than behavior
hardware description.
Module
A module is the basic building block in Verilog. A module can be a collection of lower level
design blocks. In Verilog, a module is declared by keyword module a corresponding end module
must appear at the end of the module definition.
Lexical Conventions in Verilog
•
White Spaces:
Blank space (\b), tabs (\t), and new lines (\n) comprise the white spaces. White space is ignored
by the Verilog except when it separates tokens. White space is not ignored in strings.
•
Comments:
Comments can be inserted into the code for readability and documentation. There are two
ways to write comments. A 1-line comment starts with “//”. Verilog skips from that position
to the end of the line. A multiple comment starts with “/*” and ends with “*/”.
a = b && c; //This is a 1-line comment
/* This is a multiple line
Comment*/
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/* This is /* an illegal */ comment */
/* This is // a legal comment */
Gate Level Modeling
Within the logic level the characteristics of a system are described by logical links and their timing
properties. All signals are digital signals. They can only have definite logical values (`0', `1', `X',
`Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc. gates).
Gate Primitives:
Gate Type
Description
Instantiation Syntax
And
N-input AND gate
and a1(out, in1, in2);
Nand
N-input NAND gate
nand a2(out, in1, in2);
Or
N-input OR gate
or a3(out, in1, in2);
Nor
N-input NOR gate
nor a4(out, in1, in2);
Xor
N-input XOR gate
xor x1(out, in1, in2);
Xnor
N-input XNOR gate
xnor x2(out, in1, in2);
Not
1-input NOT gate
not g1 (out, in);
Buf
1-input & N-output BUF gate
buf b1_2 (out1, out2, in);
bufif1
1-input,1-output,1-control BUF gate
bufif1 b0(out, in, control);
bufif0
1-input,1-output,1-control BUF gate
bufif0 b1(out, in, control);
notif1
1-input,1-output,1-control NOT gate
notif1 b2(out, in, control);
notif0
1-input,1-output,1-control NOT gate
notif0 b3(out, in, control);
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LAB SESSION
Equipment and Materials:
➢ Simulation tool: ModelSim
Circuit Diagram
input A
Output
input B
Experimental Procedure
• Open ModelSim.
• Create a New Project by selecting Top-Down Modeling, language: Verilog.
• Create New File, select its name and save it in Work Directory.
• Now write following code:
module lab_and_gate (G,alpha,beta);
input alpha, beta;
output G;
and N1(G, alpha, beta);
endmodule
module lab_and_gate_stim;
reg Alpha, Beta;
wire G;
lab_and_gate g1(G, Alpha, Beta);
initial
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begin
Alpha=0; Beta=0;
#10
begin Alpha=0; Beta=1; end
#10
begin Alpha=1; Beta=0; end
#10
begin Alpha=1; Beta=1; end
#10
begin Alpha=1; Beta=1; end
end
endmodule
Timing Diagram Verification for the written code:
Some important things that can be observed from the above code are:
✓ The module always starts with keyword ‘module’.
✓ Inside module (), we define its argument inputs and outputs but their sequence is not
important.
✓ In case of gate level modeling, it is very important that output must be written before the
inputs e.g. and (Output, Input1, Input2 ……………...Input n)
✓ We can also state additional wires i.e. Links other than input or output.
✓ Some keywords for gate level description are:
❖ and A1(output(s), input1, input2, input3………………..input n)
❖ or B1(output(s), input1, input2, input3………………..input n)
❖ not C1(output(s), input1, input2, input3………………..input n)
❖ nand D1(output(s), input1, input2, input3………………..input n)
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❖ nor E1(output(s), input1, input2, input3………………..input n)
❖ xor F1(output(s), input1, input2, input3………………..input n)
❖ xnor G1(output(s), input1, input2, input3………………..input n)
❖ buf H1(output(s), input1, input2, input3………………..input n)
✓ Stimulus module is used to verify the results, that the code is working in a right manner or
not.
✓ At the end draw the truth table for the AND gate and verify your code according the output
in the timing diagram and in the truth table.
Questions:
1. In Verilog how many levels of abstraction are available? _________________________
2. Which is the lowest level of abstraction? ______________________________________
3. Which is the highest level of abstraction? ______________________________________
4. Gate level modeling is also called ____________________________________________.
5. ______________________________________ modeling is not used now.
LAB REPORT
Discussion of Results
1. Write Verilog code for the following circuit and also attach the timing diagrams and the
truth table.
A
B
OUT
27
2. Write Verilog code for the following circuit and also attach the timing diagrams and the
truth table.
A
B
X
Y
Z
L
M
N
O
P
Conclusion / Summary
28
EXPERIMENT No. 04
IMPLEMENTATION OF HALF ADDER AND FULL ADDER
Objectives
• To build Half Adder circuit using gates.
• To obtain simplified expression of Full Adder.
• To build Full Adder circuit the simplified expression.
Introduction
All digital computers execute a variety of information-processing jobs. Among these basic tasks
are the various arithmetic operations. The most basic arithmetic operation is the addition of two
binary digits. The circuit that implements this binary addition is called Half Adder. The next stage
to this addition is the addition of three binary numbers. The circuitry for this addition is called Full
Adder.
Theory
Half Adder
Half Adder is a type of combinational logic circuit that produces the sum of two binary digits
(each of 1-bit length). This circuit has two inputs, say x and y, and two outputs i.e. sum and carry
abbreviated as SHA & CHA respectively. First, we will construct Truth Table of Half Adder as:
Inputs
Outputs
X
Y
SHA = x΄y+xy΄
CHA = xy
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Boolean function for the above mentioned Truth Table is:
𝑆𝐻𝐴 = 𝑥 ′ 𝑦 + 𝑥𝑦 ′ = 𝑥 ⊕ 𝑦
29
𝐶𝐻𝐴 = 𝑥𝑦
Above mentioned Boolean expressions are implemented by logic gates as:
x
y
SHA= x + y
(To LED)
CHA=x y
(To LED)
Full Adder
Full Adder is combination logic circuit that carry out the sum of three binary numbers, each of 1bit length. Two of the binary input variables are x and y represent the two significant bits to be
added the third input z, represents the carry from previous lower significant position. Outputs of
Full Adder are Sum and Carry represented as SFA and CFA respectively. Now we will draw the
Truth Table of Full Adder.
Inputs
Outputs
x
Y
z
SFA
CFA
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
First, we write Boolean expression for Sum of Full Adder.
𝑆𝐹𝐴 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
The above expression can be simplified using Boolean Postulates & theorems/k-map, so we get
𝑆𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧
30
𝑆𝐹𝐴 = (𝑥 ⊕ 𝑦) ⊕ 𝑧
Now we write Boolean expression for Carry of Full Adder.
𝐶𝐹𝐴 = 𝑥 ′ 𝑦𝑧 + 𝑥𝑦 ′ 𝑧 + 𝑥𝑦𝑧 ′ + 𝑥𝑦𝑧
Above expression is simplified as:
𝐶𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + 𝑥𝑦
𝐶𝐹𝐴 = (𝑥 ⊕ 𝑦). 𝑧 + 𝑥𝑦
We implement simplified Boolean expressions of SFA & CFA as:
x
y
z
HA2
HA1
SFA = (x + y) + z
To LED
CFA = (x + y) z + xy
To LED
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7408 IC
➢ 7432 IC
➢ 7486 IC
Experimental Procedure
•
Layout the circuit of Half Adder on the bread board.
•
Apply VCC = +5V and Gnd to all ICs.
31
•
Power on the trainer.
•
Apply input through the logic switches available on the trainer and verify the truth table.
•
Now layout the circuit of Full Adder on the bread board and verify the truth table.
Questions:
1. Can we implement the expressions of SFA and CFA using Basic Gates only?
_______________________________________________________________________
2. From the expression of SHA and CHA count the number of gates required to execute these
expressions
using
basic
gates
only.
_______________________________________________________________________
_______________________________________________________________________
3. From the expression of SFA and CFA count the number of gates required to execute these
expressions
using
basic
gates
only.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
4. From the result of Question 3, give the no. of ICs required.
# of OR Gate ICs : _________________
# of AND Gate ICs : _________________
# of NOT Gate ICs : _________________
LAB REPORT
Discussion of Results
1. List the applications in which Full Adder is used.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
2. Draw the circuit of Full Adder using Basic Gates only.
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Conclusion / Summary
33
EXPERIMENT No. 05
DESIGN AND SIMULATION OF HALF ADDER, FULL ADDER AND
FOUR BIT ADDER IN VERILOG
Objectives
• To write Verilog codes for Half adder and Full Adder using gate level modeling.
• To implement Full Adder through the instantiation of two Half Adders.
• To write a Verilog code and its test bench for 4-bit adder using four Full Adders.
• To verify the results through simulations.
Introduction
A Half Adder is a binary circuit that add two number which are 1-bit long. Similarly, a Full
Adder adds three 1-bit long binary numbers. A 1-bit Full Adder adds three one-bit numbers, often
written as A, B and Cin such that A and B are the operands and Cin is a bit carried in from the last
stage. The Full Adder is typically a combination of cascade of Half Adders. The circuit generates
a two-bit output usually represented by Cout and S.
The truth table is given as:
A
B
Cin
Cout
S
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
34
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Sum and Cout are expressed as:
𝑆 = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = (𝐴. 𝐵) + (𝐴 ⊕ 𝐵). 𝐶𝑖𝑛
Theory
Full Adder can be implemented in 2 different ways:
a) by direct modelling using basic logic gates.
b) by using 2 Half Adders.
LAB SESSION
Equipment and Materials
➢ Simulation tool: ModelSim
Experimental Procedure:
• Write the following codes in ModelSim. Simulate them and attach their timing diagrams.
CODE OF HALF ADDER
35
module haff_adder (cha, sha, Ina, Inb)
input Ina, Inb;
output cha, sha;
xor (sha, Ina, Inb);
and (cha, Ina, Inb);
endmodule
module stim_haff_adder;
reg a, b;
wire cha,sha;
haff_adder A1(cha, sha, a, b);
Initial
begin
a=1′b0; b=1′b0;
#10
a=1′b0; b=1′b1;
#10
a=1′b1; b=1′b0;
#10
a=1′b1; b=1′b1;
end
endmodule
CODE OF FULL ADDER
module fll_adder (cfa, sfa, a, b, cin)
input a, b, cin;
output cfa, sfa;
wire w1, w2, w2;
haff_adder H1 (w1, w2, a, b);
haff_adder H2 (w3, sfa, cin, w1);
or (cfa, w3, w2);
endmodule
module test_fll_adder;
reg a;
reg b;
36
reg c;
wire sum;
wire car;
fll_adder f1 (car, sum, a, b, c);
Initial
begin
a=0; b=0; c=0;
#10
a=0; b=0; c=1;
#10
a=0; b=1; c=0;
#10
a=0; b=1; c=1;
#10
a=1; b=0; c=0;
#10
a=1; b=0; c=1;
#10
a=1; b=1; c=0;
#10
a=1; b=1; c=1;
end
endmodule
Questions:
1. How many gates are required to implement half adder?
________________________________________________________________________
2. How many Half Adders are required to implement one Full Adder?
________________________________________________________________________
3. Can a Full Adder be implemented in ModelSim using gates?
________________________________________________________________________
4. How many Full Adders are required to implement 4-bit Adder?
________________________________________________________________________
37
LAB REPORT
Discussion of Results
1. Write Verilog code for Full Adder using gates. Simulate it and attach its timing diagram.
2. Write Verilog code for following 4-bit Adder. Simulate it and attach its timing diagram.
38
Conclusion / Summary
39
EXPERIMENT No. 06
IMPLEMENTATION OF DECODER AND MULTIPLEXER
Objectives
• To understand the difference between decoder and multiplexer.
• To implement 3-to-8-Line Decoder.
• To implement Quad 4-to-1-Line Multiplexer.
Introduction
Decoder is a type of combinational logic circuit that convert binary information from N input
lines to maximum of 2N output lines. It is actually the reverse of logic encoder. For example, if we
have 2 inputs i.e. x and y then after passing through the decoder we will get 4 outputs and hence
the size of Decoder will be 2x4 or it can also be called 2-to-4-line Decoder.
A multiplexer or ‘mux’ is a type of digital switch that has 2N digital data input lines, N select or
control input lines, and a single output line. It directs data from one of 2N data lines to its single
output line. So this is called 2N-to-1-line multiplexer. The select input lines control which data
input is linked to the output. Thus, a multiplexer behaves as a programmable digital switch.
Theory
Generally, a decoder is designated as N-to-2N-line logic circuit. Here:
N: # of input lines
2N: # of output lines
We will start our discussion with 2x4 Decoder. From its name it is obvious that there are 2 input
x
y
2X4
DECODER
d0
d1
d2
d3
output lines
data input lines
lines and 4 output lines. Its block diagram can be drawn as:
E
40
In this block diagram an additional E (enable) signal is also mentioned. This is used only for
selection of whole unit. We can write the truth table as:
Inputs
Enable
Outputs
x
y
E
d3
d2
d1
d0
1
1
0
X
X
X
X
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
The Boolean expressions of these outputs are:
𝑑0 = 𝐸𝑥′𝑦′
𝑑1 = 𝐸𝑥′𝑦
𝑑2 = 𝐸𝑥𝑦′
𝑑3 = 𝐸𝑥𝑦
Multiplexer
Multiplexer, or Mux, is simply a data selector switch which is capable of selecting one of many
input lines (2N) and display its state on the only output line available.
A Mux has:
1.
Data input lines
2.
Select lines
3.
Output line
Block diagram of 2x1 Mux is:
I0
2X1 MUX
data i/p lines
Y
output
I1
S
select line
41
Here I0, I1 are inputs of Mux, S is select line and Y is output.The Boolean expression for 2x1
Mux is:
𝑌 = 𝐼1 𝑆 + 𝐼0 𝑆′
This expression can be implemented using basic gates as:
I1
I0
s
I1 s
I1 s + I0 s' = Y
To LED
s'
I0 s'
Block diagram of 4x1 Mux can be drawn as:
I0
data i/p lines
I1
I2
I3
4X1 MUX
Y
output
S1
S0
select lines
Here I0, I1, I2 and I3 are 4 inputs, S1 and S0 are select lines and Y is output. Truth table is given
below:
Inputs Select Lines Outputs
I
S1
S0
Y
I0
0
0
I0
I1
0
1
I1
I2
1
0
I2
I3
1
1
I3
The Boolean expression for 4x1 Mux is:
𝑌 = 𝐼0 𝑆1 ′ 𝑆0 ′ + 𝐼1 𝑆1 ′𝑆0 + 𝐼2 𝑆1 𝑆0 ′ + 𝐼3 𝑆1 𝑆0
Logic Diagram of 4x1 Mux is:
42
S1
S0
I0
I0
I1
I1
I2
I2
I3
I3
Y
To LED
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7404 IC
➢ 7408 IC
➢ 7432 IC
➢ 7454 IC
Circuit Diagram
Figure 1: Block Diagram of 3-to-8-Line Decoder
43
Figure 2: Quad 4-to-1-Line Multiplexer
Experimental Procedure
•
From figure 1, draw the truth table for 3x8 Decoder. Derive the output expressions.
•
From these equation, draw the circuit for 3x8 decoder using basic gate ICs.
•
Layout the circuit on the bread board and verify the truth table by applying input from data
switches.
•
For Multiplexer, layout the circuit of figure 2 on bread board and verify.
Observations
3x8 Decoder:
44
Truth Table:
Inputs
Enable
Outputs
Output Expressions:
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
Circuit Diagram:
45
Questions:
1.
2.
3.
4.
Give the generic representation of Decoder. ________________________________
Decoder is a ________________________ circuit.
Decoders, that are implemented in lab, are made of ______________ gates.
Give
the
IC
numbers
of
2x4
and
3x8
Decoders.
________________________________________________________________________
______________________________________________________________________
5. These ICs are made of _______________________ gates.
6. Give the IC number of:
i. 2x1 Mux: ____________________
ii. 4x1 Mux: ____________________
iii. 8x1 Mux: ____________________
46
iv. 16x1 Mux: ____________________
7. Enable input of Mux is also called ___________________.
8. Mux is also known as ________________________.
9. Suppose a logic circuit is labelled as ‘8x3’, would it be a Mux? ___________
10.How many select lines are required to implement 1024x1 Mux? __________
11.Give the no. of data lines, select lines and outputs for 28-to-1-line Multiplexer.
_____________________________________________________________
_____________________________________________________________
_____________________________________________________________
LAB REPORT
Discussion of Results
1. List the applications of Decoders.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
2. Draw the circuit of 4x16 Decoder using 2x4 Decoders.
47
3. Discuss
the
purpose
of
‘Strobe’
input
in
Mux
ICs.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
Conclusion/ Summary
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
48
EXPERIMENT No. 07
DESIGN AND SIMULATION OF DECODER AND MULTIPLEXER
USING DATA FLOW MODELING IN VERILOG
Objectives
• To understand data flow modeling.
• To write Verilog codes for 2-to-4-line decoder and verify.
• To write Verilog code for 4x1 Mux and verify the code using simulation.
• To define full adder and 4-bit adder using dataflow modeling and verify through
simulation.
Introduction
For smaller circuits, the concept of gate level modeling works well as there are few number of
gates. But when we have to design a large circuit with huge number of gates, it becomes quite
difficult to code each and every gate, also it is too much time consuming. Thus executing that
function at a higher level is a good choice. Dataflow modeling is a popular design method as logic
synthesis tools have become sophisticated. This approach permits the designer to focus on
enhancing the circuit in terms of data flow.
Theory
Dataflow modeling is based on the assignment procedures. There are two types of assignment
statements:
a) Continuous Assignment
b) Implicit Continuous Assignment
Continuous Assignment
It is the basic statement type in dataflow modeling as it is used to drive a value onto a net. It
substitutes gates description of the circuit and defines the circuit at a higher level of abstraction. A
continuous assignment statement always starts with the keyword assign. The general syntax is:
assign net = expression;
49
For example: input b,c;
output a;
assign a=b&c;
In Continuous assignment, the variables are first declared separately and then they are used in
assignment statement. These variables can be scalar as well vector quantities.
Implicit Continuous Assignment
Instead of first defining a net and then writing a continuous assignment on that net, Verilog offers
a shortcut by which a continuous assignment can be employed on a net when it is declared. There
can only be one implicit assignment declaration per net because a net can be defined only once.
For example: wire out = X & Y; here variable out is defined wire and assigned value in a single
statement.
AND Gate defined by Dataflow Modeling:
module data_flow_and (h, k, j);
input k, j;
output h;
assign h=k & j;
endmodule
module try_data_flow_and;
reg J, K;
wire H;
data_flow_and a1(H, J, K);
initial
begin
J = 1; K = 1;
#15
J = 0;
K = 1;
#15
J = 1;
K = 0;
#15
J = 0;
K = 0;
end
50
endmodule
In Data Flow modeling, symbols of gates are very important which are given below:
Gate
Symbol
AND
&
NOT
~
OR
|
XOR
^
Timing Diagram for the written code
LAB SESSION
Equipment and Materials
➢ Simulation Tool: ModelSim
Experimental Procedure
•
Open ModelSim.
•
Create new project and then new file.
•
Write following code.
•
Simulate it and attach timing diagram.
Verilog Code for 2-to-4-line Decoder:
module flow_data_2_x_4_dcod (u0, u1, u2, u3, b, h0, h1);
input b, h0, h1;
output u0, u1, u2, u3;
assign u3 = (b & h1 & h0);
assign u0 = (b & ~h1 & ~h0);
51
assign u2 = (b & h1 & ~h0);
assign u1 = (b & ~h1 & h0);
endmodule
Verilog Code for 4x1 Mux
module data_mux_4_to_1(Z, M, N);
input [1:0] M;
input [3:0] N;
output Z;
assign Z = (~ M[1] & ~ M[0] & N[0])| (~ M[1] & M[0] & N[1]) | (M[1] & ~ M[0] & N[2]) | (M[1]
& M[0] & N[3]);
endmodule
Questions:
1. It is necessary for a Mux to have inputs that are 1-bit long only? ____________________
2. How many select lines are required for 4x1 Mux? ________________________________
3. How many input lines are required for 4x1 Mux? _________________________________
4. How many output variables are required for 3-to-8-line Decoder? ____________________
LAB REPORT
Discussion of Results
1. Write a Verilog code for Full Adder using Data Flow Modeling. Also write its test bench
and simulate. Attach its timing diagram.
2. Using above designed Full Adder, write a Verilog code for 4-bit adder using Data Flow
modeling. Simulate the code to show results.
Conclusion / Summary
52
EXPERIMENT No. 08
IMPLEMENTATION OF MAGNITUDE COMPARATOR
Objectives
• To get familiarization to the magnitude comparator.
• To write truth table for different magnitude comparators.
• To verify truth tables using circuit build out of ICs.
Introduction
Magnitude comparators are combinational logic circuits that process digital/ binary data. These
are made up of standard gates and they compare the data present at their input terminals and
generate output of the comparison as equal, less and greater. These comparators always compare
two inputs but length of inputs may vary. Depending upon the length of input (# of bits) we define
types of comparators as 1-bit magnitude comparator, 2-bit magnitude comparator and so on.
Theory
1-bit Magnitude Comparator
One Bit Magnitude Comparator is logic circuit which is used to compare two input binary numbers
(each of 1-bit length) to check weather two inputs are equal or less than or greater then. From this
statement we write its truth table as:
Inputs
Outputs
x
y
Ex=y
Gx>y
Lx<y
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
53
Boolean expressions for the outputs are:
̅̅̅̅̅̅̅̅̅̅
𝐸 = 𝑥𝑦 + 𝑥 ′ 𝑦 ′ = (𝑥
⊕ 𝑦)
𝐺 = 𝑥𝑦′
𝐿 = 𝑥′𝑦
The circuit diagram is:
2-Bit Magnitude Comparator
In 2-bit Magnitude Comparator we compare two binary inputs (each of two-bit length) to check
weather two inputs are equal or one less than other or greater then. Now we will write Truth Table
of 2 Bit magnitude Comparator.
Inputs
A
Outputs
B
A1
A0
B1
B0
EA=B
GA>B
LA<B
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
54
0
1
0
0
0
1
0
0
1
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
1
1
0
0
To write Boolean expressions we simplify outputs by k-map technique.
k-map of “E”:
E
B1B0
A1 A0
00
01
11
10
00
1
01
11
10
1
1
1
k-map of “G”:
G
B1B0
A1A0
00
01
11
10
00
01
1
1
1
1
1
11
10
1
k-map of “L”:
55
Boolean expression for E is:
𝐸 = 𝐴1′ 𝐴′0 𝐵1′ 𝐵0′ + 𝐴1′ 𝐴0 𝐵1′ 𝐵0 + 𝐴1 𝐴′0 𝐵1 𝐵0′ + 𝐴1 𝐴0 𝐵1 𝐵0
𝐸 = 𝐴1′ 𝐵1′ (𝐴′0 𝐵0′ + 𝐴0 𝐵0 ) + 𝐴1 𝐵1 (𝐴′0 𝐵0′ + 𝐴0 𝐵0 )
𝐸 = (𝐴′0 𝐵0′ + 𝐴0 𝐵0 )(𝐴1′ 𝐵1′ + 𝐴1 𝐵1 )
𝐸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴0 ⊕ 𝐵0 ) . ̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴1 ⊕ 𝐵1 )
Boolean expression for G is:
𝐺 = 𝐴1 𝐵1′ + 𝐴1′ 𝐴0 𝐵1′ 𝐵0′ + 𝐴1 𝐴0 𝐵1 𝐵0′
𝐺 = 𝐴1 𝐵1′ + 𝐴0 𝐵0′ (𝐴1′ 𝐵1′ + 𝐴1 𝐵1 )
𝐺 = 𝐴1 𝐵1′ + 𝐴0 𝐵0′ ̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴1 + 𝐵1 )
Similarly, we can write expression of L as:
𝐿 = 𝐴1′ 𝐵1 + 𝐴′0 𝐵0 (𝐴1′ 𝐵1′ + 𝐴1 𝐵1 )
𝐿 = 𝐴1′ 𝐵1 + 𝐴′0 𝐵0 ̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴1 + 𝐵1)
56
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7404 IC
➢ 7408 IC
➢ 7432 IC
➢ 7411 IC
Experimental Procedure
• Connect the circuit of 1-bit Magnitude Comparator using basic gate ICs.
• Apply VCC and Gnd.
• Power on the AT-700 board.
• Apply the inputs through data switches and verify the truth table.
• Now draw the circuits of ‘E’, ‘G’ and ‘L’ expression derived above for 2-bit Magnitude
Comparator.
• Apply inputs and verify the truth table.
Observations
Circuit Diagram for ‘E’
57
Circuit Diagram for ‘G’
Circuit Diagram for ‘L’
Questions:
1. How many gates are required to implement the circuit of 1-bit Magnitude Comparator?
2.
3.
4.
5.
______________________________________________________________________
How many basic gates are required to implement ‘E’ expression of 2-bit Magnitude
Comparator? ___________________________________________________________
How many basic gates are required to implement ‘G’ expression of 2-bit Magnitude
Comparator? ___________________________________________________________
How many basic gates are required to implement ‘L’ expression of 2-bit Magnitude
Comparator? ___________________________________________________________
How many gates are required to implement complete circuit of 2-bit Magnitude
Comparator? ___________________________________________________________
58
LAB REPORT
Discussion of Results
1. List the practical applications of Magnitude Comparator?
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
2. For two binary numbers, say A and B, list all possible outcomes of Magnitude
Comparator.
_______________________________________________________________________
_______________________________________________________________________
_______________________________________________________________________
Conclusion / Summary
59
EXPERIMNENT No. 09
DESIGN AND SIMULATION OF MAGNITUDE COMPARATOR USING
BEHAVIORAL MODELING IN VERILOG
Objectives
• To get familiarize to Behavioral Modeling in Verilog.
• To understand the working of different Blocks in ModelSim Coding.
• To understand the difference between Blocking and Non-Blocking Statements in
Behavioral Modeling.
Introduction
Behavioral modeling is the highest level of abstraction in the Verilog. The other modeling levels
are comparatively more detailed and lengthy. All these require knowledge of how hardware circuit,
or hardware signals work. The concept in this modeling is as humble as writing the logic in C
language. This is a very powerful notion. All that designer’s needs are the procedure/algorithm of
the design, which is the basic information for any design.
Theory
All of the behavioral modeling is accomplished using two important constructs/concepts: initial
and always. All the other behavioral modeling statements appear only inside these two designed
procedure concepts.
Initial Block/Construct
The statements which come under the initial concept create the initial block. The initial block is
performed only once in the simulation, at time 0. If there are more than one initial blocks, then all
of them are executed concurrently i.e. in parallel fashion. The initial construct is used as follows:
initial
begin
rst = 0;
ck = 1;
end
60
Or
initial
clok = 1;
Since there are more than one statements in first initial block hence they are written between
‘begin’ and ‘end’. If there is only one statement in any block, then there is no need to put begin
and end.
Always Block/Construct
The statements which come under the roof of always concept form the always block. The always
block starts at time 0, and keeps on running all the simulation time. It works like an infinite loop.
It is generally used to model a task that is repeated continuously.
always
#5 cp = ~cp;
initial
cp = 0;
The above code generates a clocking signal by the name cp, which has a time period of 10 units.
The initial block initializes the cp value to 0 at time 0. Then after every 5 units of time it switched,
hence we get a time period of 10 units. This is a general procedure used to generate a clock signal
to be used in test benches.
always @ (posedge cP, negedge rST)
begin
v = y + w;
u = 1'b0;
end
In this example, the always block will be performed whenever there is a positive edge in the cP
signal, or there is negative edge in the rST signal.
always @ (n, t, d)
begin
g = (z + n) *d;
61
h = n | t;
end
In the above example, whenever there is a change in n, t or d the always block will be processed.
Here the list of variables n, t, and d is called the sensitivity list. In higher versions of Verilog, this
sensitivity list is also specified as always @ (*) as it is equivalent to include all input signals, used
in the always block. This is quite useful when always block is used for executing the combination
logic.
Procedural Assignments
Procedural assignments are used for updating data types reg, integers, time, real, realtime
and memory data types. These variables preserve their values until updated by another procedural
assignment. There is a significant difference between procedural assignments and continuous
assignments.
Continuous assignments drive nets and are valued and updated whenever there is a change in
value of an input operand. However, procedural assignments update the value of variables under
the control of the procedural flow constructs that surround them. The LHS of a procedural
assignment could be:
✓ reg, integer, real, realtime, or time data type.
✓ Bit-select of a reg, integer, or time data type, rest of the bits are untouched.
✓ Part-select of a reg, integer, or time data type, rest of the bits are untouched.
✓ Memory word.
✓ Concatenation of any of the previous four forms can be specified.
When the RHS calculates fewer bits than the LHS, then if the right-hand side is signed, it will be
sign-extended to the size of the left-hand side. There are two types of procedural assignments:
blocking and non-blocking assignments.
Blocking Assignment
Blocking assignment statements are executed in the order they are stated in a sequential block.
The implementation of next statement begins only after the completion of the present blocking
62
assignment. A blocking assignment will not block the implementation of the next statement in a
parallel block. The blocking assignments are specified by the ‘=’ operator.
initial
begin
a = 1;
b = #5 2;
c = #2 3;
end
In the above example, variable ‘a’ is assigned value 1 at time 0 and variable ‘b’ is assigned value
of 2 at time 5, and ‘c’ is assigned value of 3 at time 7.
Non-Blocking Assignment
Non-Blocking assignment permits assignment scheduling without blocking the procedural flow.
The non-blocking assignment statement can be used whenever several variable assignments within
the same time step can be made without concerning order or dependence upon each other. Nonblocking assignments are executed using the operator ‘<=’. This ‘<=’ is same for less than or equal
to operator, so whenever it appears in an expression it is considered to be comparison operator and
not as non-blocking assignment.
initial
begin
a <= 1;
b <= #5 2;
c <= #2 3;
end
In this example, variable ‘a’ is given value 1 at time 0 and variable ‘b’ is given value 2 at time 5,
and variable ‘c’ is passed value 3 at time 2 (because all the statements execution starts at time 0,
as they are non-blocking assignments).
Block Statements
Block or block statements are used to set two or more statements together, so that they act as one
statement. There are two types of blocks:
63
✓ Sequential block.
✓ Parallel block.
Sequential Block
The sequential block is well-defined using the keywords ‘begin’ and ‘end’. The procedural
statements in sequential block are implemented sequentially in the given order. In sequential block
delay values for each statement shall be preserved comparative to the simulation time of the
execution of the previous statement. The control will be thrown out of the block after the
implementation of last statement.
Parallel Block
The parallel block is specified using the keywords ‘fork’ and ‘join’. The procedural statements in
parallel block are implemented simultaneously. In parallel block delay values for each statement
are considered comparative to the simulation time of entering the block. The delay control can be
used to provide time-ordering for procedural assignments. The control will be thrown out of the
block after the execution of the last time-ordered statement. Note that blocks can be nested. The
sequential and parallel blocks can be mixed.
Block Names
All the blocks can be named, by specifying blockname after the keyword begin or fork. The
advantages of naming a block are:
✓ It allows us to define local variables, which can be retrieved by using hierarchical name
referencing.
✓ They can be disabled using the disable statement (disable blockname;).
In behavioral modeling there are two types of behaviors. First is single-pass behavior that is
implemented by initial block. Second type is cyclic behavior which is implemented under always
block. In cyclic behavior the system is designed by the statements that can repeat multiple times
specified in the code. Cyclic behavior is implemented by:
✓ If-else statements
✓ Case statements
✓ Loops
64
If-else Conditional Statement
This statement is used to make a decision whether a statement will be implemented or not. The
keywords if and else make conditional statement. The conditional statement appears in coding as:
if (condition_1)
statement_x;
if (condition_2)
statement_y;
else
statement_z;
These statements can also be written as:
if (conditionA)
statement 1;
else if (conditionB)
statement 2;
else
statement 3;
The conditional statement block may contain multiple statements. These are specified as:
if (condition1)
begin
statement1;
statement2;
end
else
begin
statement3;
65
statement4;
end
Conditional (if-else) statements specified here are similar to that of if-else statements in C
language, except that here parenthesis is replaced by begin and end.
Case Statement
The case statement is a multi-option judgement statement that checks whether an expression
matches one of the expressions and branches consequently. Keywords case and endcase constitute
a case statement. The case statement is as under:
case (expression)
case1: statementA;
case2: statementB;
case3: statementC;
...
default: this_ is_default_statement_ for_case;
endcase
If there are more than one case statements under a single case item, then they are assembled using
begin and end keywords. The default case statement is optional.
Case statement with don't cares: casez and casex
Casez works with high-impedance values (Z) as don't cares. Casex treats both high-impedance
(Z) and unknown (X) values as don't care conditions. Don't-care values (Z values intended
for casez, Z and X values defined for casex) in any bit position of either the case expression or the
case items will be thought of as don't-care conditions during the comparison and that bit position
will be ignored. The don't cares are shown by the ‘?’ mark.
Loop Statements
In Verilog, there are four types of loop statements used. These are:
66
✓
forever
✓
repeat
✓
while
✓
for
Forever Loop
Forever loop is well-defined using the keyword forever, which executes a statement continuously.
It ends when the structure assignment $finish is called. A forever loop can also be ended by calling
the disable statement. For example
initial
begin
clk = 1'b0;
forever #50 clk = ~clk;
end
In the example above, a clock signal is obtained with time period 100 units.
Repeat Loop
Repeat loop is designed or called by the keyword repeat. The repeat loop block continuously
performs the task for a given number of times. The number of times the loop implements can be
mention using a constant or an expression. The expression is assessed once before the loop starts
and not during the accomplishment of the loop. If the expression value goes out to be Z or X, then
it is treated as zero, and hence loop block is not implemented at all.
initial
begin
a = 10;
b = 5;
b <= #10 10;
67
i = 0;
repeat (a*b)
begin
$display ("repeat in progress");
#1 i = i + 1;
end
end
In the above example the loop is effected only 50 times, and not 100 times. It calculates (a*b) at
the beginning, and uses that value only.
While Loop
The while loop is defined using the keyword while. The while loop comprises an expression. The
loop lasts until the expression is true. It ends up when the expression is false. If the calculated
value of expression is Z or X, it is assumed as a false. The value of expression is calculated each
time before start up of the loop.
initial
begin
a = 20;
i = 0;
while (i < a)
begin
$display("%d",i);
i = i + 1;
a = a - 1;
end
end
68
In the above example the loop runs for 10 times.
For Loop
The for loop is defined using the keyword for. The implementation of for loop is organized by:
1. Performs an assignment, normally used to initialize a variable that controls the number of
times the for loop is executed.
2. Estimates an expression, if the result is false or Z or X the for-loop will terminate and if it
is true, the for-loop will execute its task.
3. Performs an assignment normally used to modify the value of the variable that controls the
loop and then repeats with second step.
Note that the first step is implemented only once.
initial
begin
a = 20;
for (i = 0; i < a; i = i + 1, a = a - 1)
$display ("%d", i);
end
LAB SESSION
Equipment and Materials
➢ Simulation Tool: ModelSim
Experimental Procedure
• Open ModelSim.
• Write the following codes.
• Simulate them and attach the timing diagram.
69
Code for 4x1 MUX:
module 4x1_mux (out, in0, in1, in2, in3, s0, s1);
output out; // out is declared as reg, as default is wire
reg out;
// out is declared as reg, because we will do a procedural assignment to it.
input in0, in1, in2, in3, s0, s1;
// always @ (*) is equivalent to always @ (in0, in1, in2, in3, s0, s1)
always @ (*)
begin
case ({s1, s0})
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
default: out = 1'bx;
endcase
end
endmodule
Code for Full Adder:
module full_adder (sum, c_out, in0, in1, c_in);
output sum, c_out;
reg sum, c_out;
input in0, in1, c_in;
always @ (*)
{c_out, sum} = in0 + in1 + c_in;
Endmodule
Code for 8-bit Binary Counter
module (count, reset, clk);
output [7:0] count;
70
reg [7:0] count;
input reset, clk;
// consider reset as active low signal
always @ (posedge clk, negedge reset)
begin
if(reset == 1'b0)
count <= 8'h00;
else
count <= count + 8'h01;
end
endmodule
71
LAB REPORT
Discussion of Results
1. Draw the circuit diagram of binary counter you have implemented in lab work.
Conclusion / Summary
72
EXPERIMENT No. 10
IMPLEMENTATION OF R-S FLIP FLOP AND D FLIP FLOP USING
GATE ICs
Objectives
• To learn how to build R-S Flip Flop using Gate ICs.
• To implement and verify D Flip Flop circuit through the circuit built for R-S Flip
Flop.
Introduction
In modeling different flip flops in Verilog, we used behavioral modeling. Also we have
implemented these flip flops using cyclic behavior. These flip flop can easily be checked and
verified using gate ICs as these gates are the building blocks of entire digital systems. In this lab
we will use Basic Gates only.
Theory
Flip flops are the basic memory elements in digital synchronous systems. There are four type of
flip flops that are known very commonly. These are:
✓ R-S Flip Flop
✓ D Flip Flop
✓ J-K Flip Flop
✓ T Flip Flop
All of the above mentioned flip flops are synchronous logic circuits so all have clock pulse
dependence. These can be edge-triggered or level-triggered.
R-S Flip Flop
R-S flip flop is a time or clock pulse dependent flip flop so is referred as Synchronous flip flop.
In all circuits where we have to give a notion of time, we use pulsating clock signal. This signal is
just a type of square pulse signal that changes its state from low to high and then high to low in
73
quite small duration of time. Hence this clock signal is high frequency signal. Given below is the
generic circuit of R-S Flip Flop implemented using NAND Gates.
Truth table of the above circuit can be written as:
Q
R
S
Next State of Q
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
Indeterminate or unknown
1
0
1
1
1
1
0
0
1
0
0
1
1
1
1
Indeterminate or unknown
D Flip Flop
D Flip Flop is also clock time dependent type Synchronous flip flop. Here output responds to the
edge of the clock pulse that is either a positive edge triggered or negative edge sensitive element.
The output of the D Flip Flop follows the state of input D.
Implementation of D Flip Flop Using R-S Flip Flop Circuit
74
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7400 IC
➢ 7404 IC
Experimental Procedure
• Using NAND gate, build the circuit of R-S Flip Flop on the bread board of the trainer.
• Properly check all the connections.
• Power on the trainer.
• Apply VCC and Gnd.
•
Using Data Switches on the trainer apply inputs and verify the truth table.
• Now power off the trainer.
• Make the circuit of D Flip Flop by carefully changing the circuit of R-S Flip Flop.
• Power on the trainer and apply VCC and Gnd.
• Verify the truth table.
Questions:
75
1. List the differences between D Flip Flop and R-S Flip Flop.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
2. Can the circuit of R-S Flip Flop and D Flip Flop be implemented using only one gate type?
If
yes,
then
mention
their
names
and
IC
number.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
3. Can the above mentioned Circuits be implemented using Basic Gates? ________________
LAB REPORT
Discussion of Results
1. Draw the truth table of D Flip Flop you have implemented in lab.
2. Draw the circuit of T Flip Flop.
Conclusion / Summary
76
EXPERIMENT No. 11
IMPLEMENTATION OF J-K FLIP FLOP USING D AND R-S FLIP FLOP
PRE LAB TASK
Objectives
• To learn how to build J-K Flip Flop using Gates.
• To build J-K Flip Flop using D Flip Flop.
• To verify the truth table of J-K Flip Flop using R-S Flip Flop Circuit.
Introduction
J-K Flip Flop is the most flexible of all flip flops as It combines the basic characteristics of timed
D Flip Flop and R-S Flip Flop. Like D Flip Flop its output always tracks input states of J but it has
two inputs like R-S Flip Flop.
Theory
J-K Flip Flop can appear to be same as R-S Flip Flop because both of these digital circuit elements
have two input variables. In normal conversion procedure input J is considered equivalent to S
input of R-S Flip Flop which is also called set. Similarly, K is equivalent to R input variable that
means reset. This is done by thinking of the condition R = S = 1 as toggle or flip situation. Here
the output is set by the setting of input variable J = 1 and K = 0. To reset the output vice versa
conditions are applied to input variables and hence the circuit toggles or flips. Circuit diagram of
J-K Flip Flop as a function of R-S Flip Flop is given below:
Figure 3
77
J-K Flip Flop resembles D Flip Flop in its characteristics. As we know D Flip Flop is clock pulse
dependent Synchronous element whose output follows the state of input D variable only. In similar
fashion, J-K Flip Flop is driven by the change in state of input variable J only with the clock signal
variations. Circuit Diagram of J-K Flip Flop designed by making changes to D Flip Flop Circuit
is shown below:
Figure 4
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7400 IC
➢ 7404 IC
➢ 7408 IC
Experimental Procedure
• Using gates, build the circuit shown in Figure 1 of J-K Flip Flop on the bread board of
the trainer.
• Properly check all the connections.
78
• Power on the trainer.
• Apply VCC and Gnd.
•
Using Data Switches on the trainer apply inputs and verify the truth table.
• Now power off the trainer.
• Connect the circuit shown in Figure 2.
• Power on the trainer and apply VCC and Gnd.
• Verify the truth table of J-K Flip Flop.
Questions:
1. Are these all flip flops available in individual IC Packages? _______________________
2. Give the IC number of:
J-K Flip Flop: ____________________
R-S Flip Flop: ____________________
D Flip Flop: ______________________
T Flip Flop: ______________________
LAB REPORT
Discussion of Results
1. Draw the truth table of J-K Flip Flop.
Conclusion / Summary
79
EXPERIMENT No. 12
DESIGN AND SIMULATION OF VARIOUS FLIP FLOPS ON VERILOG
Objectives
• To learn what are sequential circuits.
• To understand the difference between Synchronous and Asynchronous Circuits.
• To implement J-K flip flop, d flip flop and T flip flop in Verilog.
Introduction
Sequential logic circuits are the type of circuits whose output depend on the present as well as
past states of input variable. Also we can say that their output depends upon the ordering and
timing of inputs. In Verilog these circuits are designed and modeled using edge sensitive features
in the sensitive list of always blocks. Sequential logic circuits are designed only using always
blocks through non-blocking assignments. Variables on the left side of assign statements should
be reg type in always blocks.
Synchronous circuits are the type of sequential logic circuit whose outcome responds upon the
change in clocking pulse type input signal. Synchronous circuit designs contain memory elements
like flip flops. In comparison to synchronous, Asynchronous circuits are the sequential circuits
that do not include memory units in their designs. Their outputs are not the function of clock
pulsing signals.
Theory
In designing logic circuit for flip flops it is recommended to use reset input because after power
on, circuits attain a known value. This reset signal can be designed as synchronous or
asynchronous. If we design synchronous reset, the output of the flip flop changes on the rising
edge of pulsating clock while asynchronous reset acts immediately. For example, flip flop using
Synchronous reset is designed as:
module SYN_RST_FF (clok, rst, di, que);
input clok, rst;
80
input [3:0] di;
output [3:0] que;
reg [3:0] que;
always @ (posedge clok)
if (rst)
que <= 4’b0000;
else
que <= di;
endmodule
Similarly, flip flop designed using Asynchronous reset is given as:
module ASYN_RST_FF (RST, CK, DI, QUE);
input RST, CK;
input [3:0] DI;
output [3:0] QUE;
reg [3:0] QUE;
always @ (posedge RST or posedge CK)
if (RST)
QUE <= 4’b0000;
Else
QUE <= DI;
endmodule
The important points to be noted from these examples are
✓ Asynchronous flip flop generates its output with positive edge of either the clocking
pulse or reset pulse.
✓ Synchronous flip flop acts only upon the positive edge of pulsating clock and not the
reset pulses.
Behavioral Modeling is also used to design latching circuits like D latch. This type of latch is
also known as transparent latch because whenever clocking pulse is high, the data at the input
terminal is directly passed to output so this is transparent state. This latch can also become
81
opaque when clock pulse is low and output of latch remains unchanged. In Verilog this latch can
be modeled as:
module TRANSPARENT_LATCH (TRANS_CK, TRANS_D_IN, TRANS_D_O);
input TRANS_CK;
input [3:0] TRANS_D_IN;
output [3:0] TRANS_D_O;
reg [3:0] TRANS_D_O;
always @ (TRANS_D_IN or TRANS_CK)
if (TRANS_CK)
TRANS_D_O <= TRANS_D_IN;
endmodule
J-K Flip Flop
J-K flip flop is modeled by following symbol and its truth table is also shown herewith:
J
K
Next State of Q
0
0
Q
0
1
0
1
0
1
1
1
Q΄
82
T Flip Flop
Symbol and truth table of T flip flop are given as:
Q
T
Next State of Q
0
0
0
0
1
1
1
0
1
1
1
0
LAB SESSION
Equipment and Materials
➢ Simulation Tool: ModelSim
Experimental Procedure
• Open ModelSim.
• Write the codes of D Flip Flop for both Synchronous and Asynchronous designs.
• Simulate them and attach the results.
• Write the following codes for J-K Flip Flop and T Flip Flop.
• Simulate them and also show the results.
Code of J-K Flip Flop in terms of simple Behavioral Modeling
module J_dash_K_FiFo (jay,kay,rst,clk,que,quedash);
83
input jay, kay, rst, clk;
output que, quedash;
reg que, quedash;
always @ (posedge clk)
begin
if (!rst)
que <= 1’b0;
else
que <= (jay & ~que) | (~kay & que);
end
assign quedash= ~que;
endmodule
Implementation of J-K Flip Flop using Conditional Statements
module J_dash_K_FiFo_Condition (jay,kay,rst,clk,que,quedash);
input jay, kay, rst, clk;
output que, quedash;
reg que, quedash;
always @ (posedge clk)
begin
if (!rst)
que <= 1’b0;
else if (jay == 0 && kay == 0)
que <= que;
else if (jay == 0 && kay == 1)
que <= 0;
else if (jay == 1 && kay ==0)
que <= 1;
else
que <= quedash;
end
assign quedash = ~que;
84
endmodule
Implementation of J-K Flip Flop using Case Statements
module J_dash_K_FiFo_Cse (jay,kay,rst,clk,que,quedash);
input jay, kay, rst, clk;
output que, quedash;
reg que, quedash;
always @ (posedge clk)
begin
if (!rst)
que <= 1’b0;
else
begin
case({jay,kay})
2΄b00: que <= que;
2΄b01: que <= 0;
2΄b10: que <= 1;
2΄b11: que <= quedash;
endcase
end
end
assign quedash= ~que;
endmodule
Code of T Flip Flop in terms of simple Behavioral Modeling
module _FiFo_Tea (tea, rst, clk, que, quecomp);
input tea, rst, clk;
output que, quecomp;
reg que, quecomp;
always @ (posedge clk or negedge rst)
begin
if (rst)
85
que <= 1;
else
que <= (tea & ~que) | (~tea & q) ;
end
assign quecomp = ~que;
endmodule
Implementation of T Flip Flop using Conditional Statements
module _FiFo_Tea_Condition (tea, rst, clk, que, quecomp);
input tea, rst, clk;
output que, quecomp;
reg que, quecomp;
always @ (posedge clk or negedge rst)
begin
if (rst)
que <= 1;
else if (tea == 0)
que <= que;
else if (tea == 1)
que <= ~que;
end
assign quecomp = ~que;
endmodule
Implementation of J-K Flip Flop using Case Statements
module _FiFo_Tea_Condition (tea, rst, clk, que, quecomp);
input tea, rst, clk;
output que, quecomp;
reg que, quecomp;
always @ (posedge clk or negedge rst)
begin
if (rst)
86
que <= 1;
else
begin
case (tea)
1’b0: que <= que;
1’b1: que <= ~que;
endcase
end
end
assign quecomp = ~que;
endmodule
Questions:
1. What are the differences between synchronous and asynchronous circuits? List three
differences.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
2. What
is
the
difference
between
flip
flop
and
latch?
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
3. List
the
names
of
all
flip
flops.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
87
LAB REPORT
Discussion of Results
1. Draw the truth table and Symbolic Diagram of D flip flop.
Conclusion / Summary
88
EXPERIMENT No. 13
IMPLEMENTATION OF DECADE, BINARY RIPPLE AND UP/DOWN
COUNTERS
Objectives
•
To implement various counters using flip flops.
Introduction
Counters are the type of digital devices that stores and counts the number of times an event or
process occurs [1]. Counters are usually constructed through flip flops but they are also available
in the form of integrated circuits (ICs). In certain situation, counters are also used for the
measurement of time, frequency and increment memory addresses [2]. These are particularly
designed synchronous sequential circuits in which the state of output pins shows the count of the
event happened.
Theory
There are different types of counters. Some of them are:
i.
Decade counter
ii.
Binary Ripple counter
iii.
Up/Down counter
iv.
Ring counter
Decade Counter
This counter is also called BCD counter. Decade counter counts in decimal digits, rather than
binary numbers. We can also say that the output count of this counter is truncated to ten. We the
counter counts the value of ten, all flip flops are cleared. Counters with different number of counter
are also available, these are called mod-counters. For example, a mod-counter of 64 can count
from 0 to 63. Circuit of decade counter implemented through J-K Flip Flop is given below:
89
Figure 1: Decade Counter
Binary Ripple Counter
Binary ripple counter is the one that usually count binary values (0 and 1). In ripple counter, only
the first flip flop is triggered through external clock while next flip flop’s clock is connected to the
output of previous flip flop. This clock connection is given the name as ripple. If we have
connected ‘n’ flip flops, then there will be 2n outputs. This is defined as the mod of ripple counter.
For example, if we have to count 8 numbers, we will connect 3 flip flops and the circuit will be
called 3-bit binary ripple counter. Since it is binary counter so its count starts from 000(0) and ends
at 111(2n-1 = 7).
Figure 2: 3-bit Binary Ripple Counter
Timing diagram of the above counter is as follows [3]:
90
Up/Down Counter
This is the type of binary counter that can count in both directions that is either the count is
incremented or decremented on each clock pulse [4]. The direction of count can be controlled by
control input signal. Here output of all flip flops are combined to form a number. To design 3-bit
up/down counter, we require 3 flip flops. Up/down counter implemented using J-K Flip Flops is
given as:
Figure 5: 3-bit Up/Down Counter
91
Timing detail of above circuit is:
Ring Counter
Ring counter is designed on the principle of feedback network. The output of last flip flop is fed
back to the input of first flip flop, hence a closed loop is created and named as ring counter. A
ring counter that is built with 4 flip flops is shown below:
92
Figure 6: 4-bit Ring Counter
Timing diagram is:
93
LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7432 IC
➢ 7404 IC
➢ 7408 IC
➢ 7476 IC
➢ 7474 IC
Experimental Procedure
•
Connect the circuit of decade counter as shown in Figure 1 on the bread board.
•
Power on the trainer and apply VCC and GND to the ICs.
•
Connect LEDs to the output of flip flops and check their state after the application of input
signals to read the output count.
•
Repeat the above mentioned procedure for all counter circuit mentioned in theory.
Questions:
1. For a counter built with ‘n’ flip flops, what is the possible range of bit-count?
2.
3.
4.
5.
________________________________________________________________________
What
is
Johnson
Counter?
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
A decimal counter has _______________ number of states at output.
BCD counter is also known as ___________________________________.
Ripple counter is also called _____________________________________.
94
LAB REPORT
Discussion of Results
1. What is Johnson Counter. Draw its circuit diagram.
Conclusion / Summary
95
References:
[1] "https://en.wikipedia.org/wiki/Counter_(digital)," [Online].
[2] "http://www.electronicshub.org/introduction-to-counters/," [Online].
[3] "https://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter02.html," [Online].
[4] "http://www.electronics-tutorials.ws/counter/count_4.html," [Online].
96
EXPERIMENT No. 14
DESIGN AND SIMULATION OF COUNTERS IN VERILOG
Objectives
• To write code of various counters in Verilog.
• To simulate the counters in Verilog.
Introduction
Counters are used for event counting as well as timing signal generation. Basic building block
of counters is flip flops. In counters, the output count is read from the binary state of the output
pins of flip flops. Any type of flip flop, e.g. J-K Flip Flop, R-S Flip Flop, D Flip Flop and T FlipFlop, can be used to build a counter.
Theory
Counters are usually defined as n-mod count type, in which ‘n’ is the number of flip flops required
to implement the counter. Using this concept, we can design counters in Verilog as well. A decade
counter designed in Verilog is given as:
module BCDcountmod(Clock, Clear, E, BCD1, BCD0);
input Clock, Clear, E;
output [3:0] BCD1, BCD0;
reg [3:0] BCD1, BCD0;
always @(posedge Clock)
begin
if (Clear)
begin
BCD1 <= 0;
BCD0 <= 0;
end
97
else if (E)
if (BCD0 == 4′b1001)
begin
BCD0 <= 0;
if (BCD1 == 4′b1001)
BCD1 <= 0;
else
BCD1 <= BCD1 + 1;
end
else
BCD0 <= BCD0 + 1;
end
endmodule
Similarly, ring counter is given as:
module ring_count(q,clk,clr);
input clk,clr;
output [3:0]q;
reg [3:0]q;
always @(posedge clk)
if(clr==1)
q<=4′b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule
module ring_count_test();
98
reg clk_tb,clr_tb;
wire [3:0]q_tb;
ring_count dut1(q_tb,clk_tb,clr_tb);
initial
begin
$display(“time,\t clk_tb,\t clr_tb,\t q_tb”);
$monitor(“%g,\t %b,\t %b,\t %b”,$time,clk_tb,clr_tb,q_tb);
clr_tb=1′b0;
#50 clr_tb=1′b1;
#100 clr_tb=1′b0;
end
always
begin
#50 clk_tb=1′b1;
#50 clk_tb=1′b0;
end
endmodule
Up/Down counter is designed in Verilog as:
module up_down_counter
out
(
, // Output of the counter
up_down , // up_down control for counter
clk
, // clock input
data
, // Data to load
reset
// reset input);
output [7:0] out;
input [7:0] data;
input up_down, clk, reset;
reg [7:0] out;
always @(posedge clk)
if (reset) begin // active high reset
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out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule
LAB SESSION
Equipment and Materials
➢ Simulation Tool: ModelSim
Experimental Procedure
• Open ModelSim.
• Write the Verilog code for decade counter.
• Simulate the code and show results.
• Repeat the above mentioned procedure for other counters mentioned in theory.
LAB REPORT
Discussion of Results
1. Write a Verilog code for ripple counter. Simulate it and show its timing diagram.
Conclusion/Summary
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EXPERIMENT No. 15
IMPLEMENTATION OF 8-BIT SHIFT REGISTER USING FLIP FLOP IC
Objectives
•
To implement shift register using flip flops.
Introduction
Registers are the sequential circuits that are build using flip flops. As we know, flip flops are
capable of storing one-bit, so ‘n’ flip flips can store n-bit data. This ‘n’ flip flop based circuit
forms n-bit register [5]. A register that can shift its bits in one or both directions is called a shift
register. Direction of data flow means data can either be stored in or passed out. Shift register
also constitute flip flops where output of first flip flop is connected to the input of next and a
common clock pulse is applied to all flip flops.
Theory
Shift registers are able to hold and store data bits. Depending upon the data in and data out of
shift register, these are classified as:
➢ Serial-in serial-out (SISO) shift register
➢ Serial-in parallel-out (SIPO) shift register
➢ Parallel-in serial-out (PISO) shift register
➢ Parallel-in parallel-out (PIPO) shift register
➢ Universal shift register
SISO Shift Register
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In this shift register, input data is applied in serial fashion, that is, one bit at a time, to the
register module. While the output data also appears in serial fashion at output pin.
SIPO Shift Register
In this register, input data is applied through a single input pin serially but for output we have
multiple pin that can give out data in parallel manner.
PISO Shift Register
Here multiple input pins provide parallel data in connections. Output in this module is a single
pin for serial data out.
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PIPO Shift Register
In this register both the input and output pins are parallel.
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LAB SESSION
Equipment and Materials
➢ AT-700 Portable Analog and Digital Laboratory
➢ 7403 IC
➢ 7404 IC
➢
Circuit Diagram
Experimental Procedure
• Layout the above mentioned circuit on the bread board.
• Power up all ICs.
• Now apply the input through data switches and note the output.
Observations
Table for data flow through the register:
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Clock Pulse No.
QA
QB
QC
QD
QE
QF
QG
QH
1
2
3
4
5
6
7
8
Timing Diagram:
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LAB REPORT
Discussion of Results
1. What is Universal Shift Register? Give its applications.
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Conclusion/Summary
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Reference:
Logic and Computer Design Fundamentals, M. M. Mano and Charles Kime.
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