UltraScale Architecture
Packaging and Pinouts
Advance Product Specification
User Guide
UG575 (v1.0) December 10, 2013
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Revision History
The following table shows the revision history for this document.
Date
Version
12/10/2013
1.0
Revision
Initial Xilinx release.
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
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2
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Packaging Overview
Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction to UltraScale Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3: Device Diagrams
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBVA676 Package–XCKU035 and XCKU040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBVA900 (XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFVA1156 (XCKU035, XCKU040, XCKU060, and XCKU075) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
27
29
Chapter 4: Mechanical Drawings
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU060 and XCKU075) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 5: Package Marking
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Chapter 6: Packing and Shipping
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 7: Soldering Guidelines
Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 8: Recommended PCB Design Rules for BGA Packages
BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 9: Thermal Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 10: Thermal Management Strategy
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Some Thermal Management Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Heat Sink Attachments for Lidless FBVA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reasons for Thermal Interface Material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Appendix A: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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Chapter 1
Packaging Overview
Introduction to the UltraScale Architecture
The Xilinx® UltraScale™ architecture is a revolutionary approach to creating programmable
devices capable of addressing the massive I/O and memory bandwidth requirements of next
generation applications while efficiently routing and processing the data brought on chip.
UltraScale devices address a vast spectrum of high-bandwidth, high-utilization system
requirements through industry-leading technical innovations. UltraScale architecture-based
devices share many building blocks to provide optimized scalability across the product
range, as well as numerous new power reduction features for low total power consumption.
Kintex® UltraScale FPGAs provide high performance with a focus on optimized
performance per watt for applications including wireless, wired, and signal or image
processing. High DSP and block RAM-to-logic ratios, and next generation transceivers are
combined with low-cost packaging to enable an optimum blend of capability for these
applications.
Virtex® UltraScale FPGAs provide the highest system capacity, bandwidth, and
performance. Delivering unprecedented logic capacity, serial I/O bandwidth, and on-chip
memory, the Virtex UltraScale family pushes the performance envelope ever higher.
This packaging and pinout specification user guide is part of the UltraScale Architecture
documentation suite available at: www.xilinx.com/ultrascale.
Introduction to UltraScale Device Pinouts
This section describes the pinouts for the UltraScale architecture-based FPGAs in various
organic flip-chip 1.0 mm pitch BGA packages.
•
Kintex UltraScale devices are offered in low-cost, space-saving flip-chip and lidless
flip-chip packages that are optimally designed for high performance-to-price ratio.
•
Virtex UltraScale devices are offered exclusively in high performance flip-chip BGA
packages that are optimally designed for highest system capacity, bandwidth and
signal performance. Package inductance is minimized as a result of optimal placement
and even distribution as well as an increased number of power and GND pins.
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Chapter 1: Packaging Overview
IMPORTANT: All standard packages are lead-free (signified by an additional V in the package name).
All of the UltraScale devices supported in a particular package are pin compatible. Each device is split
into I/O banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture
SelectIO Resources User Guide (UG571) [Ref 1].
Differences from Previous Generations
The packaging and pinout specifications for UltraScale architecture-based FPGAs differ
from past generations, including the 7 series devices. These details are outlined in this
section.
•
All packages are constructed on organic laminate substrates.
•
All package and die components, including flip-chip solder bumps, are lead-free.
•
Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package.
•
VCCAUX_IO pins are not divided into bank groups.
•
Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
•
Groups of gigabit serial transceiver (GT) power pins are separated by column for each
column of GT Quads.
•
Standard I/O banks each have a total of 52 SelectIO™ pins, optionally configurable as
up to 24 differential pairs.
•
A limited number of banks have 26 SelectIO pins, including 12 differential pairs and 2
single-ended pins.
•
Each bank has one dedicated VREF pin.
•
Eight clock pins per bank (four per 26-pin bank) consist of a single type of global clock
(GC) input.
•
Four memory byte groups per I/O bank (two per 26-pin bank) are each separated into
an upper and a lower memory byte group.
•
All configuration pins are located in bank 0 and bank 65.
•
A POR_OVERRIDE pin is used to override the default power-on-reset delay. See
Table 1-4.
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Chapter 1: Packaging Overview
Device/Package Combinations and Maximum I/Os
Table 1-1 shows the size, BGA pitch, and the maximum number of user I/Os possible in the
UltraScale device packages.
Table 1-1:
Package Specifications
Package Specifications
Packages
FBVA676
FBVA900
FFVA1156
FFVA1517
FLVA1517
FLVB1517
FFVA1760
FLVA1760
FLVD1924
FLVF1924
Description
Size
(mm)
Maximum
HP I/O(1)
Maximum
HR I/O(1)
Lidless
flip-chip,
fine-pitch
27 x 27
208
104
31 x 31
364
104
Flip-chip,
fine-pitch
35 x 35
416
104
40 x 40
520
104
40 x 40
520
104
40 x 40
260
104
42.5 x 42.5
624
104
42.5 x 42.5
624
104
45 x 45
676
156
45 x 45
624
104
SSIT,
flip-chip,
fine-pitch
Package Type
BGA
Pitch
(mm)
1.0
Flip-chip,
fine-pitch
SSIT,
flip-chip,
fine-pitch
Notes:
1. The maximum user I/O numbers do not include pins in the configuration bank 0 or the GT serial transceivers.
Gigabit Transceiver Channels by Device/Package
Table 1-2 lists the quantity of gigabit transceiver channels for the UltraScale devices. In all
devices, a gigabit transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and
MGTTXN pins.
Table 1-2:
Serial Transceiver Channels (GTH/GTY) by Device/Package
Device
Package
GTH Channels
GTY Channels
16
0
16
0
16
0
16
0
Kintex UltraScale Devices
XCKU035
XCKU040
XCKU035
XCKU040
FBVA676
FBVA900
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Chapter 1: Packaging Overview
Table 1-2:
Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)
Device
Package
GTH Channels
GTY Channels
16
0
20
0
28
0
28
0
32
0
48
0
48
0
48
0
64
0
64
0
52
0
52
0
52
0
52
0
52
0
64
0
64
0
XCKU035
XCKU040
FFVA1156
XCKU060
XCKU075
XCKU060
FFVA1517
XCKU075
XCKU100
FLVA1517
XCKU115
XCKU100
FLVB1517
XCKU115
XCKU075
FFVA1760
XCKU100
FLVA1760
XCKU115
XCKU100
FLVD1924
XCKU115
XCKU100
FLVF1924
XCKU115
User I/O Pins by Device/Package
Table 1-3 lists the number of available 3.3V-capable high-range (HR) and 1.8V-capable
high-performance (HP) I/Os and the number of differential I/O pairs for each UltraScale
device/package combination.
Table 1-3:
Device
Available I/O Pins by Device/Package
Package
Total User I/O
Differential Pairs
HR
HP
HR
HP
104
208
48
96
104
208
48
96
104
364
48
168
104
364
48
168
Kintex UltraScale Devices
XCKU035
XCKU040
XCKU035
XCKU040
FBVA676
FBVA900
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Chapter 1: Packaging Overview
Table 1-3:
Device
Available I/O Pins by Device/Package (Cont’d)
Package
XCKU035
XCKU040
XCKU060
FFVA1156
XCKU075
XCKU060
XCKU075
XCKU100
XCKU115
XCKU100
XCKU115
XCKU075
XCKU100
XCKU115
XCKU100
XCKU115
XCKU100
XCKU115
FFVA1517
FLVA1517
FLVB1517
FFVA1760
FLVA1760
FLVD1924
FLVF1924
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Total User I/O
Differential Pairs
HR
HP
HR
HP
104
416
48
192
104
416
48
192
104
416
48
192
104
416
48
192
104
520
48
240
104
520
48
240
104
520
48
240
104
520
48
240
104
260
48
120
104
260
48
120
104
624
48
288
104
624
48
288
104
624
48
288
156
676
72
312
156
676
72
312
104
624
48
288
104
624
48
288
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Chapter 1: Packaging Overview
Pin Definitions
Table 1-4 lists the pin definitions used in UltraScale device packages.
Table 1-4:
Pin Definitions
Pin Name
Type
Direction
Description
User I/O Pins
IO_L[1 to 24][P or N]_T[0 to 3] [U or L]_N[0 to 12]_ [multi-function]_[bank number] or
IO_T[0 to 3][U or L]_N[0 to 12]_[multi-function]_[bank number]
Dedicated
Input/
Output
Most user I/O pins are capable of differential signaling
and can be implemented as pairs. Each user I/O pin name
consists of several indicator labels, where:
• IO indicates a user I/O pin.
• L[1 to 24] indicates a unique differential pair with P
(positive) and N (negative) sides. User I/O pins without
the L indicator are single-ended.
• T[0 to 3][U or L] indicates the assigned memory byte
group for the pin.
• N[0 to 12] the number of the I/O within its memory byte
group.
• [multi-function] indicates any other functions that the
pin can provide. If not used for this function, the pin can
be a user I/O.
• [bank number] indicates the assigned bank for the user
I/O pin.
There are four global clock (GC) pin pairs in each bank that
have direct access to the global clock buffers, MMCMs,
and PLLs that are in the clock management tile (CMT)
adjacent to the same I/O bank. GC inputs provide
dedicated, high-speed access to the internal global and
regional clock resources. GC inputs use dedicated routing
and must be used for clock inputs where the timing of
various clocking features is imperative.
Up-to-date information about designing with the GC pin
is available in the UltraScale Architecture Clocking
Resources User Guide (UG572) [Ref 2]
User I/O Multi-Function Pins
GC
Multifunction
Input
VRP (1)
Multifunction
N/A
DBC
QBC
Multifunction
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Input
This pin is for the DCI voltage reference resistor of P
transistor (per bank, to be pulled Low with a reference
resistor).
Byte lane clock (DBC and QBC) input pin pairs are clock
inputs directly driving source synchronous clocks to the
bit slices in the I/O banks. In memory applications, these
are also known as DQS. For more information, consult the
UltraScale Architecture SelectIO Resources User Guide
(UG571) [Ref 1].
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Chapter 1: Packaging Overview
Table 1-4:
Pin Definitions (Cont’d)
Pin Name
PERSTN[0 to 1]
Type
Direction
Multifunction
Input
Description
PERSTn is the persistence feature for use with the
integrated block for PCI Express.
User I/O Multi-Function Configuration Pins
For further descriptions, including configuration modes and recommended external pull-up/pull-down resistors,
see the UltraScale Architecture Configuration User Guide (UG570)[Ref 3]
EMCCLK
Multifunction
Input
DOUT_CSO_B
Multifunction
Output
D[04 to 15]
Multifunction
Bidirectional
Configuration data pins.
A[00 to 28]
Multifunction
Output
Address address output.
CSI_ADV_B
Multifunction
Input or
Output
Active-Low chip-select input or address valid.
FOE_B
Multifunction
Output
Active-Low flash output enable.
FWE_FCS2_B
Multifunction
Output
RS[0 to 1]
Multifunction
Output
External master configuration clock.
Active-Low data output or chip-select output.
Active-Low flash write-enable or flash chip select.
RS0 and RS1 revision select output.
Dedicated (Bank 0) Configuration Pins(2)
For more information see the UltraScale Architecture Configuration User Guide (UG570)[Ref 3]
M[0 to 2]_0
Dedicated
Input
INIT_B_0
Dedicated
Bidirectional
(open-drain)
CFGBVS_0
Dedicated
Input
Configuration mode selection.
Active-Low initialization
Bank 0 and bank 65 voltage select. This pin determines the
I/O voltage operating range and voltage tolerance for the
dedicated configuration bank 0 and multi-function
bank 65. Connect CFGBVS High or Low per the bank
voltage requirements.
• VCCO_0 = 2.5V or 3.3V, tie CFGBVS High (connect to
VCCO_0).
• VCCO_0 = 1.5V or 1.8V, tie CFGBVS Low (connect to GND)
CAUTION! To avoid device damage, this pin must be
connected correctly to either V CCO_0 or GND.
PUDC_B_0
Dedicated
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Input
Active-Low input enables internal pull-ups during
configuration on all SelectIO pins:
0 = Weak preconfiguration I/O pull-up resistors enabled.
1 = Weak preconfiguration I/O pull-up resistors disabled.
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Chapter 1: Packaging Overview
Table 1-4:
Pin Definitions (Cont’d)
Pin Name
Type
Direction
Description
All configuration modes
Power-on reset delay override.
POR_OVERRIDE
Dedicated
Input
CAUTION! Do not allow this pin to float before and
during configuration. This pin must be tied to V CCINT or
GND. Do not connect to VCCO_0.
Up-to-date information about designing with the
POR_OVERRIDE pin is available in the UltraScale
Architecture Configuration User Guide (UG570) [Ref 3]
DONE_0
Dedicated
Bidirectional
Active-High, DONE indicates successful completion of
configuration.
PROGRAM_B_0
Dedicated
Input
Active Low, asynchronous reset to configuration logic.
TDO_0
Dedicated
Output
TDI_0
Dedicated
Input
JTAG test data input.
RDWR_FCS_B_0
Dedicated
Input
Active-Low read/write or flash chip-select.
Data bus direction control signal for reading or writing
configuration data.
TMS_0
Dedicated
Input
JTAG test mode data select.
TCK_0
Dedicated
Input
JTAG test clock
CCLK_0
Dedicated
Input/
Output
D00_MOSI_0
Dedicated
Bidirectional
D01_DIN_0
Dedicated
Input
Data Bit 1 or data input
D02_0
Dedicated
Input
Data Bit 2
D03_0
Dedicated
Input
Data Bit 3
Dedicated
Input
Temperature-sensing diode pins (Anode: DXP; Cathode:
DXN). The thermal diode is accessed by using the DXP and
DXN pins in bank 0. When not used, tie to GND.
To use the thermal diode an appropriate external thermal
monitoring IC must be added. Consult the external
thermal monitoring IC data sheet for usage guidelines.
Multifunction
Input
System Monitor differential auxiliary analog inputs 0–15.
VCCADC
Dedicated
N/A
System Monitor analog positive supply voltage.
GNDADC
Dedicated
N/A
System Monitor analog ground reference.
VREFP
Dedicated
N/A
Voltage reference input.
VREFN
Dedicated
N/A
Voltage reference GND.
JTAG test data output.
Configuration clock. Output in Master mode or input in
Slave mode.
Data Bit 0 or master-output, slave-input
Other Dedicated Pins
DXN
DXP
System Monitor Pins(3)
AD[0 to 15][P or N]
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Chapter 1: Packaging Overview
Table 1-4:
Pin Definitions (Cont’d)
Pin Name
Type
Direction
Description
VP
Dedicated
Input
System Monitor dedicated differential analog input
(positive side).
VN
Dedicated
Input
System Monitor dedicated differential analog input
(negative side).
I2C_SCLK
Multifunction
Bidirectional
I2C serial clock. Directly connected to the System Monitor
DRP interface for I2C operation configuration.
I2C_SDA
Multifunction
Bidirectional
I2C serial data line. Directly connected to the System
Monitor DRP interface for I2C operation configuration.
Power/Ground Pins
For more information on voltage specifications see the Kintex UltraScale Architecture Data Sheet: DC and AC
Switching Characteristics (DS892)[Ref 4]
GND
Dedicated
N/A
Ground.
VCCINT
Dedicated
N/A
Power-supply pins for the internal logic.
VCCINT_IO
Dedicated
N/A
Power-supply pins for the I/O banks.
VCCAUX
Dedicated
N/A
Power-supply pins for auxiliary circuits.
VCCAUX_IO
Dedicated
N/A
Auxiliary power-supply pins for the I/O banks.
VCCBRAM
Dedicated
N/A
Block RAM power supply pins.
VBATT
Dedicated
N/A
Decryptor key memory backup supply; this pin should be
tied to the appropriate VCC or GND when not used.
VCCO_[bank number](4)
Dedicated
N/A
Power-supply pins for the output drivers (per bank).
VREF_[bank number]
Dedicated
N/A
These are input threshold voltage pins. They become user
I/Os when an external threshold voltage is not needed
(per bank).
Multi-gigabit Serial Transceiver Pins (GTHE3 and GTYE3)
For more information on the GTH transceivers see the UltraScale Architecture GTH Transceivers User Guide
(UG576)[Ref 5]
MGTHRX[P or N][0 to 3]
_[GT quad number]
Dedicated
Input
Differential receive port GTH Quad.
MGTHTX[P or N][0 to 3]
_[GT quad number]
Dedicated
Output
Differential transmit port GTH Quad.
MGTYRX[P or N][0 to 3]
_[GT quad number]
Dedicated
Input
Differential receive port GTY Quad.
MGTYTX[P or N][0 to 3]
_[GT quad number]
Dedicated
Output
Differential transmit port GTY Quad.
MGTAVCC_[L or R]
[N or S]
Dedicated
Input
Analog power-supply pin for the receiver and transmitter
internal circuits.
MGTAVTT_[L or R]
[N or S]
Dedicated
Input
Analog power-supply pin for the transmit driver.
MGTVCCAUX_
[L or R][N or S]
Dedicated
Input
Auxiliary analog Quad PLL (QPLL) voltage supply for the
transceivers.
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Chapter 1: Packaging Overview
Table 1-4:
Pin Definitions (Cont’d)
Pin Name
Type
Direction
Description
MGTREFCLK[0 or 1]
[P or N]
Dedicated
Input
MGTAVTTRCAL_
[GT quad number]
Dedicated
N/A
Precision reference resistor pin for internal calibration
termination.
MGTRREF_
[GT quad number]
Dedicated
Input
Precision reference resistor pin for internal calibration
termination.
Differential reference clock for the transceivers.
Notes:
1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 1] for more information on the
VRP pins.
2. All dedicated configuration pins are powered by VCCO_0.
3. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 6] for the default connections required to support
on-chip monitoring.
4. VCCO pins in unbonded banks must be connected to the VCCO for that bank (for package migration). Do NOT connect
unbonded VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be
tied to a common supply (VCCO or GND).
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Chapter 1: Packaging Overview
Pin Compatibility between Packages
UltraScale devices are pin compatible only with other UltraScale devices with the same
number of package pins and the same preceding alphabetic designator. For example,
XCKU060-FFVA1517 is compatible with XCKU075-FFVA1517 and XKU115-FLVA1517, but not
with XCKU115-FLVB1517. Pins that are available in one device but are not available in
another device with a compatible package include the other device's name in the No
Connect column of the package file. These pins are labeled as No Connects in the other
device's package file. Table 1-5 shows the pin compatible devices available for each
UltraScale device package.
Table 1-5:
Pin Compatibility
Package
Pin Compatible Devices
FBVA676
XCKU035
XCKU040
FBVA900
XCKU035
XCKU040
FFVA1156
XCKU035
XCKU040
FFVA1517
or
FLVA1517
XCKU060
XCKU075
FLVB1517
XCKU100
FFVA1760
or
FLVA1760
XCKU075
FLVD1924
XCKU100
XCKU115
FLVF1924
XCKU100
XCKU115
XCKU060
XCKU075
XCKU100
XCKU115
XCKU115
XCKU100
XCKU115
Notes:
1. Pin compatible packages can have substantially different decoupling capacitor recommendations. Refer to the
UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 7].
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Chapter 1: Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
•
For each device, not all banks are bonded out in every package.
GTH/GTY Columns
•
One GT Quad = Four transceivers = Four GTHE3 or GTYE3 primitives.
•
Not all GT Quads are bonded out in every package.
I/O Banks
•
Each user I/O bank has a total of 52 I/Os where 48 can be used as differential
(24 differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
•
A limited number of banks have 26 SelectIO pins, including 12 differential pairs and
2 single-ended pins.
•
Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
•
Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
•
Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
Clocking
•
Each bank has four pairs of global clock (GC) inputs for four differential or four
single-ended clock inputs. Single-ended clock inputs should be connected to the P side
of the differential pair.
•
Clock signals are distributed through global buffers driving routing and distribution
networks to reach any clock region, I/O, or GT.
•
Global clock inputs can connect to an MMCM and two PLLs within the horizontally
adjacent CMT.
Bank Locations of Dedicated and Multi-Function Pins
•
In all UltraScale devices, bank 65 contains the multi-function configuration pins. Bank 0
contains the dedicated configuration pins.
•
All dedicated configuration I/Os (bank 0) and HR I/Os are 3.3V capable.
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Chapter 1: Packaging Overview
Figure 1-1 through Figure 1-4 visually describe a die view of each device bank numbering.
XCKU040 Banks
Figure 1-1 shows the I/O and transceiver banks for the XCKU040.
FBVA676 Package
•
HP I/O banks 47, 48, 67, and 68 are not bonded out.
•
All HR I/O banks are fully bonded out.
•
GTH Quad 228 is not bonded out.
FBVA900 Package
•
The HP I/O bank 68 is not bonded out.
•
All HR I/O banks are fully bonded out.
•
GTH Quad 228 is not bonded out.
FFVA1156 Package
•
All HP I/O banks, HR I/O banks, and the GTH Quads are fully bonded out in this
package.
X-Ref Target - Figure 1-1
Bank 48
HP I/O
Bank 47
HP I/O
Bank 46
HP I/O
Bank 45
HP I/O
Bank 44
HP I/O
PLL[08:09]
CMT
MMCM[04]
PLL[06:07]
CMT
MMCM[03]
PLL[04:05]
CMT
MMCM[02]
PLL[02:03]
CMT
MMCM[01]
PLL[00:01]
CMT
MMCM[00]
Bank 68
HP I/O
Bank 67
HP I/O
Bank 66
HP I/O
Bank 65
HR I/O
Bank 64
HR I/O
PLL[18:19]
CMT
GTH Quad 228
MMCM[09]
PLL[16:17]
CMT
GTH Quad 227
MMCM[08]
PLL[14:15]
CMT
GTH Quad 226
MMCM[07]
PLL[12:13]
CMT
GTH Quad 225
MMCM[06]
PLL[10:11]
CMT
GTH Quad 224
MMCM[05]
ug575_c1_01_102013
Figure 1-1:
UltraScale Device Packaging and Pinouts
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XCKU040 Banks
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Chapter 1: Packaging Overview
XCKU060 Banks
Figure 1-2 shows the I/O and transceiver banks for the XCKU060.
FFVA1156 Package
•
HP I/O banks 24 and 25 are not bonded out.
•
All HR I/O banks are fully bonded out.
•
GTH Quad 126 is not bonded out.
FFVA1517 Package
•
All HP I/O banks are fully bonded out.
•
All HR I/O banks are fully bonded out.
•
GTH Quads are fully bonded out in this package.
X-Ref Target - Figure 1-2
GTH Quad 128
GTH Quad 127
GTH Quad 126
Bank 25
HP I/O
Bank 24
HP I/O
PLL[02:03]
CMT
MMCM[01]
PLL[00:01]
CMT
MMCM[00]
Bank 48
HP I/O
Bank 47
HP I/O
Bank 46
HP I/O
Bank 45
HP I/O
Bank 44
HP I/O
PLL[12:13]
CMT
MMCM[06]
PLL[10:11]
CMT
MMCM[05]
PLL[08:09]
CMT
MMCM[04]
PLL[06:07]
CMT
MMCM[03]
PLL[04:05]
CMT
MMCM[02]
Bank 68
HP I/O
Bank 67
HP I/O
Bank 66
HP I/O
Bank 65
HR I/O
Bank 64
HR I/O
PLL[22:23]
CMT
GTH Quad 228
MMCM[11]
PLL[20:21]
CMT
GTH Quad 227
MMCM[10]
PLL[18:19]
CMT
GTH Quad 226
MMCM[09]
PLL[16:17]
CMT
GTH Quad 225
MMCM[08]
PLL[14:15]
CMT
GTH Quad 224
MMCM[07]
ug575_c1_02_102013
Figure 1-2:
UltraScale Device Packaging and Pinouts
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XCKU060 Banks
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Chapter 1: Packaging Overview
XCKU075 Banks
Figure 1-3 shows the I/O and transceiver banks for the XCKU075.
FFVA1156 Package
•
HP I/O banks 69, 70, 71, and 72 are not bonded out.
•
All HR I/O banks are fully bonded out
•
GTH Quads 129, 130, 229, 230, 231, and 232 are not bonded out.
FFVA1517 Package
•
HP I/O banks 48 and 72 are not bonded out.
•
All HR I/O banks are fully bonded out
•
GTH Quad 132 is not bonded out.
FFVA1760 Package
•
HP I/O bank 48 is not bonded out.
•
All HR I/O banks are fully bonded out. HR I/O bank 64 is split into 26-pin banks 84 and
94 in this package.
•
GTH Quads are fully bonded out in this package.
X-Ref Target - Figure 1-3
GTH Quad 132
GTH Quad 131
GTH Quad 130
GTH Quad 129
Bank 48
HP I/O
Bank 47
HP I/O
Bank 46
HP I/O
Bank 45
HP I/O
Bank 44
HP I/O
PLL[08:09]
CMT
MMCM[04]
PLL[06:07]
CMT
MMCM[03]
PLL[04:05]
CMT
MMCM[02]
PLL[02:03]
CMT
MMCM[01]
PLL[00:01]
CMT
MMCM[00]
Bank 72
HP I/O
Bank 71
HP I/O
Bank 70
HP I/O
Bank 69
HP I/O
Bank 68
HP I/O
Bank 67
HP I/O
Bank 66
HP I/O
Bank 65
HR I/O
Bank 64
HR I/O
PLL[26:27]
CMT
GTH Quad 232
MMCM[13]
PLL[24:25]
CMT
GTH Quad 231
MMCM[12]
PLL[22:23]
CMT
GTH Quad 230
MMCM[11]
PLL[20:21]
CMT
GTH Quad 229
MMCM[10]
PLL[18:19]
CMT
GTH Quad 228
MMCM[09]
PLL[16:17]
CMT
GTH Quad 227
MMCM[08]
PLL[14:15]
CMT
GTH Quad 226
MMCM[07]
PLL[12:13]
CMT
GTH Quad 225
MMCM[06]
PLL[10:11]
CMT
GTH Quad 224
MMCM[05]
ug575_c1_03_102013
Figure 1-3:
UltraScale Device Packaging and Pinouts
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XCKU075 Banks
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Chapter 1: Packaging Overview
XCKU115 Banks
Figure 1-4 shows the I/O and transceiver banks for the XCKU115.
FLVA1517 Package
•
HP I/O banks 29, 30, 49, 50, 51, 52, 69, 70, 71, 72, and 73 are not bonded out.
•
HR I/O banks 69 and 70 are not bonded out.
•
GTH Quads 131, 132, 133, and 233 are not bonded out.
FLVB1517 Package
•
HP I/O banks 24, 25, 29, 30, 44, 45, 46, 46, 47, 48, 49, 50, 51, 52, 53, and 68 are not
bonded out.
•
HR I/O banks 69 and 70 are not bonded out. HR I/O bank 64 is split into 26-pin banks
84 and 94 in this package.
•
GTH Quads are fully bonded out in this package.
FLVA1760 Package
•
HP I/O banks 24, 25, 26, 29, 30, 68, 71, 72, and 73 are not bonded out.
•
HR I/O banks 69 and 70 are not bonded out. HR I/O bank 64 is split into 26-pin banks
84 and 94 in this package.
•
GTH quads 126, 127, and 229 are not bonded out.
FLVD1924 Package
•
HP I/O banks 24, 25, 29, 30, 48, 49, and 68 are not bonded out.
•
HR I/O bank 69 is not bonded out. HR I/O bank 64 is split into 26-pin banks 84 and 94
in this package.
•
GTH quads 228, 229, and 230 are not bonded out in this package.
FLVF1924 Package
•
HP I/O banks 24, 25, 29, 30, 47, 48, 49, and 50 are not bonded out.
•
HR I/O banks 64 and 69 are not bonded out.
•
GTH Quads are fully bonded out in this package.
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-4
PLL[26:27]
PLL[46:47]
PLL[24:25]
PLL[44:45]
PLL[22:23]
PLL[42:43]
PLL[06:07]
PLL[20:21]
PLL[40:41]
PLL[04:05]
PLL[18:19]
PLL[38:39]
GTH Quad 133
Bank 53 CMT Bank 73 CMT GTH Quad 233
HP I/O MMCM[13] HP I/O MMCM[23]
GTH Quad 132
Bank 52 CMT Bank 72 CMT GTH Quad 232
HP I/O MMCM[12] HP I/O MMCM[22]
GTH Quad 131
Bank 51 CMT Bank 71 CMT GTH Quad 231
HP I/O MMCM[11] HP I/O MMCM[21]
Bank 30 CMT Bank 50 CMT Bank 70 CMT
GTH Quad 230
HP I/O MMCM[03] HP I/O MMCM[10] HR I/O MMCM[20]
Bank 29 CMT Bank 49 CMT Bank 69 CMT
GTH Quad 229
HP I/O MMCM[02] HP I/O MMCM[09] HR I/O MMCM[19]
Interposer
PLL[16:17]
PLL[36:37]
PLL[14:15]
PLL[34:35]
PLL[12:13]
PLL[32:33]
PLL[02:03]
PLL[10:11]
PLL[30:31]
PLL[00:01]
PLL[08:09]
PLL[28:29]
GTH Quad 128
Bank 48 CMT Bank 68 CMT GTH Quad 228
HP I/O MMCM[08] HP I/O MMCM[18]
GTH Quad 127
Bank 47 CMT Bank 67 CMT GTH Quad 227
HP I/O MMCM[07] HP I/O MMCM[17]
GTH Quad 126
Bank 46 CMT Bank 66 CMT GTH Quad 226
HP I/O MMCM[06] HP I/O MMCM[16]
Bank 25 CMT Bank 45 CMT Bank 65 CMT GTH Quad 225
HP I/O MMCM[01] HP I/O MMCM[05] HR I/O MMCM[15]
Bank 24 CMT Bank 44 CMT Bank 64 CMT GTH Quad 224
HP I/O MMCM[00] HP I/O MMCM[04] HR I/O MMCM[14]
ug575_c1_04_102013
Figure 1-4:
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
XCKU115 Banks
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Chapter 2
Package Files
About ASCII Package Files
The ASCII package files for each package include a comma-separated-values (CSV) version
and a text version optimized for a browser or text editor in fixed-width fonts. The
information in each of the files includes:
•
Device/Package name (family-device-package), with date and time of creation
•
Seven columns containing data for each pin:
°
Pin—Pin location on the package.
°
Pin Name—The name of the assigned pin.
°
°
°
•
Memory Byte Group—Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the
UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
[Ref 8].
Bank—Bank number.
I/O Type—CONFIG, HR, HP, or GT (GTH or GTY) depending on the I/O type. For more
information on the I/O type, see the UltraScale Architecture SelectIO Resources User
Guide (UG571) [Ref 1].
°
Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.
°
No-Connect—This list of devices is used for migration between devices that have
the same package size and are not connected at that specific pin.
Total number of pins in the package.
ASCII Pinout Files
Links to the ASCII pinout information by device/package are listed in Table 2-1.
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Chapter 2: Package Files
Table 2-1:
Package/Device Pinout Files
Package
Device
FBVA676
XCKU035
XCKU040
FBVA900
XCKU035
XCKU040
FFVA1156
XCKU035
XCKU040
FFVA1517
XCKU060
XCKU075
FLVA1517
XCKU100
XCKU115
FLVB1517
XCKU100
XCKU115
FFVA1760
XCKU075
FLVA1760
XCKU100
XCKU115
FLVD1924
XCKU100
XCKU115
FLVF1924
XCKU100
XCKU115
XCKU060
XCKU075
Note: All package files are ASCII files in TXT and CSV file format. Download all available UltraScale
Architecture package/device/pinout files at:
www.xilinx.com/support/packagefiles/ultrascale-pkgs.htm
Note: Only the available files listed in Table 2-1 are linked and consolidated in this ZIP file.
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Chapter 3
Device Diagrams
Summary
This chapter provides diagrams detailing the pinout of each UltraScale Architecture
device/package combination. The I/O-bank diagram shows the location of each user I/O
and GTH/GTY transceiver and the respective bank or GT quad. The configuration-power
diagram shows the location of every power pin and dedicated as well as multi-function
configuration pin in the package. These diagrams provide a top-view perspective of the
package pinout.
Table 3-1:
Package
Cross-Reference to UltraScale Architecture Device Diagrams by Package
Footprint
Compatibility
Device
XCKU035
XCKU040
FBVA676
page 25
page 25
FBVA900
page 27
page 27
FFVA1156
page 29
page 29
FFVA1517
FLVA1517
FLVA1517
FFVA1517
XCKU060
XCKU075
page 29
page 29
XCKU100
XCKU115
FLVB1517
FFVA1760
FLVA1760
FLVA1760
FFVA1760
FLVD1924
FLVF1924
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Chapter 3: Device Diagrams
FBVA676 Package–XCKU035 and XCKU040
X-Ref Target - Figure 3-1
1
2
3
4
5
6
7
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
6
6
4
2
CO
VC 46
18 16
5
4
2
17 18
15 15
5
3
1
17
13 14
3
1
3
15 15 16
8
7
7
1
1
CO
VC 46
18
CO
VC 66
227
9
3
6
B
6
C
A
227
2
2
2
2
16
8
9
CO
VC 46
B
8
3
3
CO
VC 66
3
A
3
4
5
4
5
2
2
D
7
E
227
227
1
16
17 18 14 13
CO
VC 46
1
C
10 10
227
0
1
0
1
227
S
S
CO
VC 46
D
S
23 23
14 13 12 12
227
17
0
S
11 10 10
8
13 14 12 12
11 11
S
CO
VC 45
0
CO
VC 66
E
7
S
9
12
9
8
G
H
227
1
1
226
24 24 22 11
7
8
7
22 20
CO
VC 46
3
CO
VC 66
3
20 21 21 19
10 10
F
227
CO
VC 66
G
20 20 22
CO
VC 46
3
3
CO
VC 66
F
19 15 17 17
226
0
226
2
19 19
23
S
9
9
22 24 24 15
8
14 11 11
4
J
4
K
18 13 13 12
227
21 21 23
2
23 23 18
CO
VC 45
J
CO
VC 45
2
0
CO
VC 66
H
2
226
1
1
19
1
226
CO
VC 45
K
1
20 20 16 14
226
16
S
3
6
CO
VC 45
L
0
21 22 24
5
CO
VC 45
1
3
6
2
M
CO
VC 45
L
5
1
1
2
N
1
21 21 23 20
19 21 22
1
226
M
0
0
0
226
226
N
0
S
0
24
226
P
3
3
1
225
19
23 20 16 16
P
18 15
R
225
2
2
0
0
225
19 22 22
14 13 13
S
T
225
2
24 24 14
11
S
10
U
CO
VC 44
2
CO
VC 44
U
CO
VC 44
T
17 17 18 15
225
3
CO
VC 44
R
3
10
V
8
8
W
9
9
Y
AA
225
1
1
1
1
225
10 10
S
12 12 11
224
23 23 24 24
1
10 10
8
7
9
S
8
7
11 11
9
12
8
CO
VC 65
1
CO
VC 64
W
22 22
CO
VC 44
V
12
8
7
7
225
0
0
0
21
0
225
CO
VC 64
Y
20 20
S
5
224
3
5
1
4
CO
VC 44
14 14 17
3
CO
VC 44
21 19 19
0
1
4
2
AB
CO
VC 65
0
S
6
6
2
AC
11 11
9
7
CO
VC 65
AA
S
7
S
2
1
2
5
15
15 18 18
S
13 13
225
3
3
3
224
13 13
5
17
3
1
5
4
S
3
1
3
3
4
2
2
1
6
6
S
14
23 24 24 22 AD
16 16 19 23
CO
VC 65
6
16 14
224
1
1
20 22 AE
224
0
G
6
7
8
16
4
4
CO
VC 65
0
V
0
0
6
CO
VC 65
17 15
1
CO
VC 64
1
224
CO
VC 64
2
2
1
19 21 21 20
AF
224
224
2
3
4
5
9
Quad 226
Quad 227
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SelectIO Pins
Dedicated Pins
#
IO_L#P
VREF
#
IO_L#N
V
Bank 44
Bank 45
Bank 46
Bank 64
Bank 65
Bank 66
Quad 224
Quad 225
17 15
2
224
AE
AF
9
5
224
2
CO
VC 64
AD
18 18 12 12
3
CO
VC 64
AB
AC
MGTAVTTRCAL
S
IO (single−ended)
G
MGTRREF
#
IO_L#P_GC
#
IO_L#N_GC
VRP
Transceiver Pins
#
#
#
#
#
#
MGT[H or Y]RXP#
MGT[H or Y]RXN#
MGT[H or Y]TXP#
MGT[H or Y]TXN#
MGTREFCLK#P
MGTREFCLK#N
ug575_c3_01_112413
Figure 3-1:
FBVA676 Package—XCKU035 and XCKU040 I/O Bank Diagram
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
www.xilinx.com
Send Feedback
25
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
B
B
V
C
E
C
V
D
D
E
E
E
F
V
G
E
V
H
13
F
9
G
11
V
J
H
15
J
10
K
V
L
E
12
V
M
E
P
V
E
V
T
19
L
14
N
R
K
M
16
18
5
20
24 21
P
4
17
22 23
R
N
3
E
U
8
2
7
T
0
U
6
V
V
V
W
V
Y
25
1
V
26 26 26 25
W
25 26 26
E
AA
26 26
25 31
AB
V
AC
E
37
E
AE
3
4
5
6
7
8
Power Pins
9
AC
33 30 28 29 AD
26 26 29 34
25 25 25 25
2
AB
29 35
25 26 29 29
25 25
AF
1
Y
AA
26 26 29
36 32 25 26
V
AD
26 25
35 27 26 26
29 29 AE
29 29 29 29
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Dedicated Pins
Multi−Function I/O Pins
GND
0
CCLK_0
15
PUDC_B_0
25
A[16 to 28]
VBATT
1
CFGBVS_0
16
RDWR_FCS_B_0
26
A[00 to 15]_D[16 to 31]
VCCAUX_IO
2
D00_MOSI_0
17
TCK_0
27
CSI_ADV_B
VCCAUX
3
D01_DIN_0
18
TDI_0
28
DOUT_CSO_B
VCCINT
4
D02_0
19
TDO_0
29
D[04 to 15]
VCCINT_IO
5
D03_0
20
TMS_0
30
EMCCLK
VCCO_[bank number]
6
DONE_0
21
VP
31
FOE_B
VCCBRAM
7
DXP
22
VN
32
FWE_FCS2_B
VCCADC
8
DXN
23
VREFP
33
I2C_SCLK
GNDADC
9
INIT_B_0
24
VREFN
34
I2C_SDA
n
NC
10
M0_0
35
PERSTN[0 to 1]
E
MGTAVCC_[R or L]
11
M1_0
36
RS0
V
MGTAVTT_[R or L]
12
M2_0
37
RS1
V
MGTVCCAUX_[R or L]
13
POR_OVERRIDE
14
PROGRAM_B_0
ug575_c3_02_110513
Figure 3-2:
FBVA676 Package—XCKU035 and XCKU040 Configuration/Power Diagram
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
www.xilinx.com
Send Feedback
26
Chapter 3: Device Diagrams
FBVA900 (XCKU035 and XCKU040)
X-Ref Target - Figure 3-3
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CO
VC 66
4
5
5
6
21 21 18
1
4
1
1
S
7
7
3
3
3
5
5
9
9
5
3
2
10 10
5
6
1
1
2
4
2
B
4
CO
VC 47
3
1
CO
VC 47
3
23 23 22
3
CO
VC 48
24 24
CO
VC 67
3
A
C
7
7
D
8
E
A
227
B
2
3
2
20 20 22
3
227
S
227
6
2
2
CO
VC 48
19 19
2
2
CO
VC 66
2
CO
VC 67
C
8
8
4
6
4
6
6
227
15 15 17 17
18
7
7
S
9
11 11 12
14 16 15
9
11 11
8
9
CO
VC 47
1
1
227
CO
VC 48
1
1
CO
VC 66
D
8
9
11 11
13 13 15
S
227
E
1
S
1
13 13 14 16
12 12
227
11
11 12 12
14 12 10 17
9
7
7
3
3
5
2
1
2
4
6
15 13 13 14
CO
VC 66
0
CO
VC 67
0
9
12 12
8
10
F
S
10
G
227
CO
VC 67
G
S
CO
VC 47
0
0
227
CO
VC 48
0
0
CO
VC 67
F
10 17 14 14
15 21 21 14
227
10 10
8
17
8
17 19 18
18 16 16
4
6
S
16 16 18 18
19 14 13 13
H
226
3
5
20 20 20 21
CO
VC 48
3
CO
VC 47
1
226
J
CO
VC 66
3
1
CO
VC 67
H
3
23 23 19 24
15 15
S
J
16
K
226
2
0
226
22 19 23 23
20 21 19
S
CO
VC 47
0
CO
VC 66
K
2
23 24 17 17
226
1
2
S
22
24 21 21 22
19
S
23
CO
VC 47
2
CO
VC 66
L
20 18 18 16
L
226
1
24
1
22 24 24
CO
VC 48
M
22 22 20
3
M
226
1
24 24 16 16
9
9
5
3
CO
VC 46
1
CO
VC 46
N
1
1
P
4
R
N
226
0
0
18 18 11 11
5
7
7
226
0
20 20
0
S
17
CO
VC 46
R
12 12
226
3
23
17 14 14
6
4
T
CO
VC 46
3
CO
VC 46
T
22 22
CO
VC 46
P
10
6
13 13
S
10
8
2
2
U
8
S
225
U
3
23 21 19
3
225
2
21 19 15 15
S
9
9
7
7
CO
VC 45
2
CO
VC 46
V
V
225
2
5
2
5
CO
VC 45
W
2
2
4
4
23 23 21 W
225
23
24 24 22
5
5
S
4
6
CO
VC 45
1
1
225
CO
VC 64
1
1
CO
VC 65
Y
20 24
21
Y
225
2
2
6
7
8
8
10 10
16
7
12 12
11 11
22
S
3
1
1
3
6
6
12
6
3
8
12 11 14
6
1
8
11 14 13 15
1
10 10
S
CO
VC 44
3
18 18 16
23 21 21
1
CO
VC 45
CO
VC 64
4
CO
VC 64
1
CO
VC 65
AA
20 24 22 19 AA
225
AB
0
0
0
19 19 20 20
0
225
22 19 AB
225
4
2
4
CO
VC 45
17 15
0
CO
VC 44
0
CO
VC 65
AC
AC
225
S
S
1
2
5
5
16 16 18
1
8
12 12 13
3
9
CO
VC 45
3
9
13 15 17 AD
224
9
3
13 13
S
10
CO
VC 65
AE
17 15 14 14
CO
VC 44
1
1
224
CO
VC 64
3
3
CO
VC 64
AD
S
10 17 13
S
16 16
17 AE
S
224
AF
2
2
0
0
224
11
19 19 18 18 AF
11 12 12
5
8
8
S
19
1
3
3
2
6
19 21 21
1
2
4
4
6
8
9
17 13 14 14
18
3
8
S
11 11 14
14 13 17 17
CO
VC 44
7
5
CO
VC 65
2
CO
VC 65
2
7
CO
VC 65
AG
9
224
21
S
AG
224
1
1
15 15 20 20
CO
VC 44
1
1
CO
VC 64
AH
18 24 24 21
AH
224
224
0
22 22
7
7
CO
VC 44
0
9
CO
VC 64
AJ
S
10 10
9
15 15 18
22 22 23 AJ
224
G
5
6
23 23 24 24
CO
VC 44
0
0
V
AK
16 16 20 20
23 AK
224
1
3
4
7
Bank 67
Quad 224
Quad 225
Quad 226
Quad 227
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SelectIO Pins
Dedicated Pins
#
IO_L#P
VREF
#
IO_L#N
V
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
2
MGTAVTTRCAL
S
IO (single−ended)
G
MGTRREF
#
IO_L#P_GC
#
IO_L#N_GC
VRP
Transceiver Pins
#
#
#
#
#
#
MGT[H or Y]RXP#
MGT[H or Y]RXN#
MGT[H or Y]TXP#
MGT[H or Y]TXN#
MGTREFCLK#P
MGTREFCLK#N
ug575_c3_03_112413
Figure 3-3:
FBVA900 Package—XCKU035 and XCKU040 I/O Bank Diagram
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
www.xilinx.com
Send Feedback
27
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-4
1
2
3
4
5
A
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
A
E
C
B
B
V
C
V
D
E
E
F
V
G
E
V
H
15
D
9
E
10
F
11
G
12
H
6
K
E
J
K
V
L
14
V
M
N
J
1
L
19
M
18
N
V
P
P
V
R
20
24 21
V
T
0
U
V
V
E
AA
V
E
V
AD
U
7
V
W
5
33
4
34 29 29
3
AB
AC
T
8
13
V
Y
22 23
17
V
W
28 30 29
29 26
26
E
26
AD
26 26 27 26
AE
25 25
E
37
2
3
4
5
6
35 26
AF
7
8
9
AG
25 25 25
36 25 25 31
AK
1
AC
25 26 26 26
V
AJ
AB
29 29 26
26 25 26
AF
AH
AA
29 29 29 29
2
E
V
Y
29 35
16 29 26 26 26
AE
AG
R
AH
25
AJ
32 25 25 25
AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi−Function I/O Pins
GND
0
CCLK_0
15
PUDC_B_0
25
A[16 to 28]
VBATT
1
CFGBVS_0
16
RDWR_FCS_B_0
26
A[00 to 15]_D[16 to 31]
VCCAUX_IO
2
D00_MOSI_0
17
TCK_0
27
CSI_ADV_B
VCCAUX
3
D01_DIN_0
18
TDI_0
28
DOUT_CSO_B
VCCINT
4
D02_0
19
TDO_0
29
D[04 to 15]
VCCINT_IO
5
D03_0
20
TMS_0
30
EMCCLK
VCCO_[bank number]
6
DONE_0
21
VP
31
FOE_B
VCCBRAM
7
DXP
22
VN
32
FWE_FCS2_B
VCCADC
8
DXN
23
VREFP
33
I2C_SCLK
GNDADC
9
INIT_B_0
24
VREFN
34
I2C_SDA
n
NC
10
M0_0
35
PERSTN[0 to 1]
E
MGTAVCC_[R or L]
11
M1_0
36
RS0
V
MGTAVTT_[R or L]
12
M2_0
37
RS1
V
MGTVCCAUX_[R or L]
13
POR_OVERRIDE
14
PROGRAM_B_0
ug575_c3_04_110513
Figure 3-4:
FBVA900 Package—XCKU035 and XCKU040 Configuration/Power Diagram
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
www.xilinx.com
Send Feedback
28
Chapter 3: Device Diagrams
FFVA1156 (XCKU035, XCKU040, XCKU060, and
XCKU075)
X-Ref Target - Figure 3-5
1
2
3
4
5
6
7
8
4
4
1
3
1
3
5
2
2
17
4
17 15 15
S
S
10
8
6
10
8
9
2
6
4
V
23 23
CO
VC 67
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
2
CO
VC 67
9
2
CO
VC 68
3
CO
VC 66
3
A
G
A
3
C
228
B
2
3
2
3
21 20
5
4
3
228
228
3
2
5
21 20 24
7
S
6
6
4
CO
VC 67
2
CO
VC 66
C
B
3
132
16 16 13 12
9
2
3
5
228
6
19
6
19
24
7
8
11
22
8
11 12 12
10 10 18 18
13 12 11
7
CO
VC 67
0
5
7
1
3
3
S
20 20 14 14
11
2
11 12
S
22
9
9
14 14 16 22
CO
VC 67
1
0
CO
VC 66
0
23 21 21 19
11 12 13 14
15 15 13 13
CO
VC 68
3
16 22 24 23
19
2
2
1
1
227
8
13 14 18
S
17 17 18 18
24
S
S
6
CO
VC 65
8
9
5
CO
VC 65
9
6
4
4
5
1
0
18 19 19 23
22 22
1
7
10 15 17 16
21 23 20 20
CO
VC 68
0
0
CO
VC 66
1
227
24 24
S
10
9
3
3
3
S
17 16
21
S
24 24 22
10
8
CO
VC 65
7
1
7
12 11 11
7
8
9
CO
VC 65
22 23 19
0
23 19
S
12
13
1
S
1
N
0
R
21 21 18
3
17 17 15
23
U
21 23
V
0
131
CO
VC 47
1
1
226
17 17 16 16
0
15
131
0
226
T
0
131
15 15
2
20 20 22 22
CO
VC 47
2
P
1
131
0
226
2
1
131
CO
VC 65
18 14 14 13
CO
VC 65
3
20 20
227
2
U
1
1
131
0
0
R
M
2
131
CO
VC 65
0
226
L
2
131
2
227
227
T
2
0
132
1
1
3
3
K
3
0
227
N
J
3
131
131
CO
VC 68
1
0
0
227
P
1
228
L
M
3
132
1
H
0
132
10 15
227
K
G
F
132
228
2
CO
VC 66
2
CO
VC 68
1
1
227
0
0
1
132
2
2
E
1
132
CO
VC 66
3
2
1
1
228
J
D
2
132
227
G
H
2
132
1
228
3
3
5
228
0
E
F
3
1
CO
VC 67
1
228
CO
VC 68
1
1
CO
VC 68
D
132
S
226
1
0
0
226
18 16 16
24 19 19 23
24
S
226
1
18
S
S
11
7
11 12 12
13 13 14 24
21 23 20 24
CO
VC 48
1
CO
VC 47
W
CO
VC 47
V
1
19 21 W
226
1
0
1
226
14
1
1
21
CO
VC 48
Y
0
20 22 22 19
Y
225
5
6
5
4
4
3
2
3
7
1
2
1
2
16
13
S
17 AA
CO
VC 48
9
0
CO
VC 48
0
CO
VC 47
AA
17 AB
226
0
3
0
225
9
10
7
CO
VC 47
AB
3
3
8
8
3
6
16 14 14 13
225
10
3
1
3
1
5
5
2
6
8
2
4
6
9
9
4
12 12 10
CO
VC 48
3
CO
VC 44
3
CO
VC 47
AC
12 12 18 15 AC
225
2
1
1
225
24 24
19 19
2
7
8
S
5
11 11
18 15 AD
224
9
7
9
7
20 20
22 22 23 21
5
S
9
10
4
6
9
8
6
7
7
CO
VC 48
16 10
CO
VC 48
15
2
CO
VC 45
2
S
CO
VC 64
AE
17 17 16 10
CO
VC 44
2
CO
VC 45
AD
AE
225
AF
1
1
0
0
225
23 21
14 13 12 11
18 18 15 15
17
CO
VC 46
1
CO
VC 45
1
CO
VC 64
AG
15 14 13
10 AF
224
4
5
S
8 AG
225
0
225
18 18
0
12 11
8
S
14 13 13 17
CO
VC 44
0
0
CO
VC 45
AH
1
11 11 10
1
5
17 17 16 18 AH
225
16 16 14
5
6
9
12 12 11
5
6
7
9
5
11
S
16 13
6
13 15 15
3
3
6
4
11 12
CO
VC 46
8
S
CO
VC 46
S
CO
VC 44
S
21
CO
VC 45
23 23
3
CO
VC 64
3
AJ
16 18 AJ
224
3
224
24
3
CO
VC 45
2
2
CO
VC 64
AK
16 13 14 14
S
13 14 14
S
AK
224
8
15
17 17 18 18
5
3
8
15 19 20
3
4
4
2
6
2
4
2
2
7
9
9
10
7
CO
VC 46
10 10
CO
VC 46
24 21 19
2
CO
VC 44
2
CO
VC 45
AL
8
8
19 19 24 AL
224
3
4
7
4
2
1
2
1
21
S
11 12
23
24 AM
G
V
0
5
6
CO
VC 46
3
22 20
1
1
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
22 20
0
19 20 24 21
224
0
S
CO
VC 46
19
CO
VC 64
0
1
6
22 22
24 23 23
21 23 20 22 AN
10 21
20 22 AP
224
2
3
4
Bank 67
Bank 68
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
7
9
Quad 228
SelectIO Pins
Dedicated Pins
#
IO_L#P
VREF
#
IO_L#N
V
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
S
1
224
224
AN
AP
1
CO
VC 44
1
1
CO
VC 64
AM
MGTAVTTRCAL
S
IO (single−ended)
G
MGTRREF
#
IO_L#P_GC
#
IO_L#N_GC
VRP
Transceiver Pins
#
#
#
#
#
#
MGT[H or Y]RXP#
MGT[H or Y]RXN#
MGT[H or Y]TXP#
MGT[H or Y]TXN#
MGTREFCLK#P
MGTREFCLK#N
ug575_c3_05_112413
Figure 3-5:
FBVA1156 Package—XCKU035, XCKU040, XCKU060, and XCKU075
I/O Bank Diagram
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-6
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
V
C
E
V
V
D
C
V
E
E
D
E
E
E
F
E
V
25 25
E
J
K
V
L
E
V
M
30 28 35 26
11
29
12
29 34 29
6
V
V
R
V
T
15
V
J
L
M
E
N
E
29 29 26
V
R
26
T
18
24 21
V
1
20
22 23
W
U
5
8
4
7
Y
0
AA
17
AC
V
3
AB
V
AC
E
AB
2
V
AD
P
V
9
V
Y
K
V
26 27
29 26 26 26
26 26
H
V
19
E
AA
25
26 26 26 25
29 29 29
V
16
V
W
29 29
14
E
U
26 25 25 26
G
E
26 25 25
33 29 35 26
13
P
E
25 25 25 25
10
E
N
25 36
V
V
H
F
31 32 37
V
V
G
AD
AE
E
AE
E
AG
AF
AF
V
AG
V
AH
AH
AJ
AJ
E
AK
AK
V
AL
E
AL
V
AM
AM
E
AN
AN
AP
AP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins
Multi−Function I/O Pins
GND
0
CCLK_0
15
PUDC_B_0
25
A[16 to 28]
VBATT
1
CFGBVS_0
16
RDWR_FCS_B_0
26
A[00 to 15]_D[16 to 31]
VCCAUX_IO
2
D00_MOSI_0
17
TCK_0
27
CSI_ADV_B
VCCAUX
3
D01_DIN_0
18
TDI_0
28
DOUT_CSO_B
VCCINT
4
D02_0
19
TDO_0
29
D[04 to 15]
VCCINT_IO
5
D03_0
20
TMS_0
30
EMCCLK
VCCO_[bank number]
6
DONE_0
21
VP
31
FOE_B
VCCBRAM
7
DXP
22
VN
32
FWE_FCS2_B
VCCADC
8
DXN
23
VREFP
33
I2C_SCLK
GNDADC
9
INIT_B_0
24
VREFN
34
I2C_SDA
n
NC
10
M0_0
35
PERSTN[0 to 1]
E
MGTAVCC_[R or L]
11
M1_0
36
RS0
V
MGTAVTT_[R or L]
12
M2_0
37
RS1
V
MGTVCCAUX_[R or L]
13
POR_OVERRIDE
14
PROGRAM_B_0
ug575_c3_06_110513
Figure 3-6:
FBVA1156 Package—XCKU035, XCKU040, XCKU060, and XCKU075
Configuration/Power Diagram
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Chapter 4
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the UltraScale
Architecture packages.
•
FFVA1156 Flip-Chip, Fine-Pitch BGA (XCKU035 and XCKU040)
•
FFVA1156 Flip-Chip, Fine-Pitch BGA (XCKU060 and XCKU075)
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Chapter 4: Mechanical Drawings
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040)
X-Ref Target - Figure 4-1
ug575_c4_01_112213
Figure 4-1:
Kintex UltraScale Device FFVA1156 Package (XCKU035 and XCKU040)
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Chapter 4: Mechanical Drawings
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU060 and XCKU075)
X-Ref Target - Figure 4-2
ug575_c4_02_112213
Figure 4-2:
Kintex UltraScale Device FFVA1156 Package (XCKU060 and XCKU075)
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Chapter 5
Package Marking
Introduction
The package top-markings for the Kintex UltraScale device are similar to the example
shown in Figure 5-1. The markings are explained in Table 5-1.
X-Ref Target - Figure 5-1
XILINX®
®
UltraScale TM
Device Type
Package
Speed Grade
XCKU040
TM
FFVA1156xxxYYWW
DXXXXXXXA
1C ES
Date Code
Lot Code
Engineering Sample
Operating Range
ug575_c5_01_110813
Figure 5-1:
Table 5-1:
Kintex UltraScale Device Package Marking
Xilinx Device Marking Definition—Example
Item
Definition
Xilinx Logo
Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family
Brand Logo
Device family name with trademark and trademark-registered status. This line is optional
and could appear blank.
1st Line
Device type.
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Chapter 5: Package Marking
Table 5-1:
Xilinx Device Marking Definition—Example (Cont’d)
Item
Definition
2nd Line
Package code, circuit design revision, the location code for the wafer fab, the geometry
code, and date code.
All UltraScale Architecture devices have Pb-free RoHS compliant packaging. For more
details on Xilinx Pb-Free and RoHS Compliant Products, see: www.xilinx.com/pbfree.
3rd Line
Ten alphanumeric characters for Assembly, Lot, and Step information. The last digit is
usually an A or an M if a stepping version does not exist.
4th Line
Device speed grade and temperature range. When not marked on the package, the
product is considered to operate at the commercial (C) temperature range. For more
information on the ordering codes, see the UltraScale Architecture and Product Overview
(DS890) [Ref 9].
Other variations for the 4th line:
L1I
The L1I indicates a -1LI device. The -1LI speed grade offers reduced maximum
power consumption. For more information, see the specific device’s data
sheet.
1C xxxx
The xxxx indicates the SCD for the device. An SCD is a special ordering code
that is not always marked in the device top mark.
1C ES
The addition of an ES indicates an Engineering Sample.
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Chapter 6
Packing and Shipping
Introduction
The UltraScale devices are packed in trays. Trays are used to pack most of Xilinx
surface-mount devices since they provide excellent protection from mechanical damage. In
addition, they are manufactured using antistatic material to provide limited protection
against ESD damage and can withstand a bake temperature of 125°C. The maximum
operating temperature is 140°C.
Table 6-1:
Standard Device Counts per Tray and Box
Package
Maximum Number
Maximum Number of
of Devices Per Tray Units In One Internal Box
FBVA676
40
200
FBVA900
27
135
FFVA1156
24
120
FFVA1517
FLVA1517
FLVB1517
21
105
FFVA1760
FLVA1760
12
60
FLVD1924
FLVF1924
12
36
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Chapter 7
Soldering Guidelines
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the
Pb-free solder reflow process and how each element of the process is related to the end
result must be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes
using package samples.
The primary phases of the Pb-free reflow process are:
•
Melting the particles in the solder paste
•
Wetting the surfaces to be joined
•
Solidifying the solder into a strong metallurgical bond
The peak reflow temperature of a plastic surface-mount component (PSMC) body should
not be more than 245–260°C for Pb-free packages (220°C for eutectic packages), package
size dependent. For multiple BGAs in a single board and because of surrounding
component differences, Xilinx recommends checking all BGA sites for varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading.
Components might overheat due to lack of thermal constraints. Unbalanced loading can
lead to significant temperature variation on the board. These guidelines are intended to
assist users in avoiding damage to the components; the actual profile should be
determined by those using these guidelines. For complete information on package
moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC
Standard J-STD-020C.
Pb-Free Reflow Soldering
Xilinx uses SnAgCu solder balls for BGA packages. In addition, suitable material are
qualified for the higher reflow temperatures (245°C–260°C) required by Pb-free soldering
processes.
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Chapter 7: Soldering Guidelines
Xilinx does not recommend soldering SnAgCu BGA packages with SnPb solder paste using
a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow
temperature of 220°C. At this temperature range, the SnAgCu BGA solder balls do not
properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields
can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board,
the density of the components on the board, and the mix between large components and
smaller, lighter components. Profiles should be established for all new board designs using
thermocouples at multiple locations on the component. In addition, if there is a mixture of
devices on the board, then the profile should be checked at various locations on the board.
Ensure that the minimum reflow temperature is reached to reflow the larger components
and at the same time, the temperature does not exceed the threshold temperature that
might damage the smaller, heat sensitive components.
Table 7-1 and Figure 7-1 provide guidelines for profiling Pb-free solder reflow.
In general, a gradual, linear ramp into a spike has been shown by various sources to be the
optimal reflow profile for Pb-free solders (Figure 7-1). This profile has been shown to yield
better wetting and less thermal shock than conventional ramp-soak-spike profile for the
Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235°C. When profiling,
identify the possible locations of the coldest solder joints and ensure that those solder
joints reach a minimum peak temperature of 235°C for at least 10 seconds. It might not be
necessary to ramp to peak temperatures of 260°C and above. Reflowing at high peak
temperatures of 260°C and above can damage the heat sensitive components and cause the
board to warp. Users should reference the latest IPC/JEDEC J-STD-020 standard for the
allowable peak temperature on the component body. The allowable peak temperature on
the component body is dependent on the size of the component. Refer to Table 7-1 for
peak package reflow body temperature information. In any case, use a reflow profile with
the lowest peak temperature possible.
Table 7-1:
Pb-Free Reflow Soldering Guidelines
Profile Feature
Convection, IR/Convection
Ramp-up rate
3°C/s maximum
Preheat Temperature 150°–200°C
60–120 seconds
Temperature maintained above 217°C
60–150 seconds (60–90 seconds typical)
Time within 5°C of actual peak temperature
30 seconds maximum
Peak Temperature (lead/ball)
235°C minimum, 245°C typical (depends on solder paste,
board size, component mixture)
Peak Temperature (body)
245°C–260°C, package body size dependent (see data
sheet)
Ramp-down Rate
6°C/s maximum
Time 25°C to Peak Temperature
3.5 minutes minimum, 5.0 minutes typical, 8 minutes
maximum
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Chapter 7: Soldering Guidelines
X-Ref Target - Figure 7-1
Tbody (MAX) = 245–260°C (package type dependent)
Temperature (°C)
See data sheet for maximum value by package type
Tlead (MIN) = 235–260°C (10s minimum)
217°C
Ramp down 6°C/s maximum
t 217
Wetting time = 60–150 s
150–200°C
Ramp up 3°C/s maximum
Preheating
60–120s
Time (s)
Figure 7-1:
ug575_c7_02_102213
Typical Conditions for Pb-Free Reflow Soldering
Table 7-2: Peak Package Reflow Body Temperature for Xilinx Pb-Free Packages
(Based on J-STD-020 Standard)
Package
Peak Package Reflow Body
Temperature
JEDEC Moisture Sensitivity Level
(MSL)
Note 1
4
BGA
Flip-Chip
FBVA676
FBVA900
FFVA1156
FFVA1517
FLVA1517
FLVB1517
FFVA1760
FLVA1760
FLVD1924
FLVF1924
Notes:
1. See the specific UltraScale device data sheet for more information.
For sophisticated boards with a substantial mix of large and small components, it is critical
to minimize the ΔT across the board (<10°C) to minimize board warpage and thus, attain
higher assembly yields. Minimizing the ΔT is accomplished by using a slower rate in the
warm-up and preheating stages. Xilinx recommends a heating rate of less than 1°C/s during
the preheating and soaking stages, in combination with a heating rate of not more than
3°C/s throughout the rest of the profile.
It is also important to minimize the temperature gradient on the component, between top
surface and bottom side, especially during the cooling down phase. The key is to optimize
cooling while maintaining a minimal temperature differential between the top surface of
the package and the solder joint area. The temperature differential between the top surface
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Chapter 7: Soldering Guidelines
of the component and the solder balls should be maintained at less than 7°C during the
critical region of the cooling phase of the reflow process. This critical region is in the part of
the cooling phase where the balls are not completely solidified to the board yet, usually
between the 200°C–217°C range. To efficiently cool the parts, divide the cooling section
into multiple zones, with each zone operating at different temperatures.
Sn/Pb Reflow Soldering
Figure 7-2 shows typical conditions for solder reflow processing of Sn/Pb soldering using
IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture
sensitivity of PSMCs must be verified prior to surface-mount flow.
X-Ref Target - Figure 7-2
TMAX (body) = 220°C
TMAX (leads) = 235°C
Temperature (°C)
2–4°C/s
Ramp down
2–4°C/s
T = 183°C
t183
60s < t183< 120s
applies to lead area
Preheat & drying dwell
120–180 s between
95–180°C (Note 3)
(Note 2)
Time (s)
ug575_c7_01_102213
Figure 7-2:
Typical Conditions for IR Reflow Soldering of Sn/Pb Solder
Notes for Figure 7-2:
1. Maximum temperature range = 220°C (body). Minimum temperature range before
205°C (leads/balls).
2. Preheat drying transition rate 2–4°C/s
3. Preheat dwell 95–180°C for 120–180 seconds
4. IR reflow must be performed on dry packages
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Chapter 8
Recommended PCB Design Rules for BGA
Packages
BGA Packages
Xilinx provides the diameter of a land pad on the package side. This information is required
prior to the start of the board layout so the board pads can be designed to match the
component-side land geometry. The typical values of these land pads are described in
Figure 8-1 and summarized in Table 8-1 for 1.0 mm pitch packages. For Xilinx BGA
packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a
clearance between the land metal (diameter L) and the solder mask opening (diameter M)
as shown in Figure 8-1. An example of an NSMD PCB pad solder joint is shown in Figure 8-2.
It is recommended to have the board land pad diameter with a 1:1 ratio to the package
solder mask defined (SMD) pad for improved board level reliability. The space between the
NSMD pad and the solder mask as well as the actual signal trace widths depend on the
capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces
are smaller.
X-Ref Target - Figure 8-1
M
L
Opening in
Solder Mask (M)
Solder Mask
Solder Land (L)
e
UG575_c8_01_102213
Figure 8-1:
Suggested Board Layout of Soldered Pads for BGA Packages
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Chapter 8: Recommended PCB Design Rules for BGA Packages
X-Ref Target - Figure 8-2
BGA Package
SMD
BGA Solder Ball
Land Pad
Solder Mask
L
M
PCB
UG358_aA_02_110513
Figure 8-2:
Table 8-1:
Example of an NSMD PCB Pad Solder Joint
BGA Package Design Rules
Packages
1.0 mm Pitch: FBVA, FFVA, FLVA, FLVB, FLVD, FLVF
Design Rule
Dimensions in mm (mils)
Package land pad opening (SMD)
0.53 mm (20.9 mils)
Maximum PCB solder land (L) diameter
0.53 mm (20.9 mils)
Opening in PCB solder mask (M) diameter
0.63 mm (24.8 mils)
Solder ball land pitch (e)
1.00 mm (39.4 mils)
Notes:
1. Controlling dimension in mm.
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Chapter 9
Thermal Specifications
Introduction
UltraScale devices are offered exclusively in thermally efficient flip-chip BGA packages.
These 1.0 mm flip-chip packages range in pin-count from the smaller 27 x 27 mm FBVA676
to the 50 x 50 mm FFVA2377. This suite of packages is used to address the various power
requirements of the UltraScale devices. UltraScale devices are implemented in the 20 nm
process technology.
In line with Moore's law, the transistor count in this family of devices has been increased
substantially. Though several innovative features at the silicon level have been deployed to
minimize power dissipation, including leakage at the 20 nm node, these products have
more densely packed transistors and embedded blocks with the capability to run faster than
before. Thus, a fully configured UltraScale architecture design that exploits the interconnect
logic speed and incorporates several embedded circuits and systems can present power
consumption challenges that must be managed.
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a
user application is not known to the component supplier. Therefore, it remains a challenge
for Xilinx to predict the power requirements of a given FPGA when it leaves the factory.
Accurate estimates are obtained when the board design takes shape. For this purpose,
Xilinx offers and supports a suite of integrated device power analysis tools to help users
quickly and accurately estimate their design power requirements. UltraScale devices are
supported similarly to previous FPGA products. The uncertainty of design power
requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore,
Xilinx devices do not come with preset thermal solutions. The user's operating conditions
dictate the appropriate solution.
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Chapter 9: Thermal Specifications
Thermal Resistance Data
Table 9-1 shows the thermal resistance data for UltraScale devices (grouped in the packages
offered). The data includes junction-to-ambient in still air, junction-to-case, and
junction-to-board data based on standard JEDEC four-layer measurements.
IMPORTANT: The data in Table 9-1 is for device/package comparison purposes only. Do not apply
directly to your system design. Attempts to recreate this data are only valid using the transient 2-phase
measurement techniques outlined in JESD51-14.
TIP: The thermal data query for all available devices by package is available on the Xilinx website:
www.xilinx.com/cgi-bin/thermal/thermal.pl.
Table 9-1:
Package
Thermal Resistance Data
Package
Body Size
FBVA676
27 x 27
FBVA900
31 x 31
Devices
θ JB
(°C/W)
θ JC
(°C/W)
θ JA
(°C/W)
θ JA-Effective (°C/W)(1)
@250 LFM
@500 LFM
@750 LFM
XCKU035
XCKU040
XCKU035
XCKU040
XCKU035
FBVA1156
35 x 35
XCKU040
XCKU060
XCKU075
FFVA1517
40 x 40
FLVA1517
40 x 40
FLVB1517
40 x 40
FFVA1760
42.5 x 42.5
FLVA1760
42.5 x 42.5
FLVD1924
45 x 45
XCKU060
XCKU075
XCKU100
XCKU115
XCKU100
XCKU115
XCKU075
XCKU100
XCKU115
XCKU100
XCKU115
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Chapter 9: Thermal Specifications
Table 9-1:
Package
FLVF1924
Thermal Resistance Data (Cont’d)
Package
Body Size
45 x 45
Devices
θ JB
(°C/W)
θ JC
(°C/W)
θ JA
(°C/W)
θ JA-Effective (°C/W)(1)
@250 LFM
@500 LFM
@750 LFM
XCKU100
XCKU115
Notes:
1. All θ JA-Effective values assume no heat sink and include thermal dissipation through a standard JEDEC four-layer board. The
Xilinx power estimation tools (PPE, Vivado® Power Analysis, and Xilinx Power Estimator), which require detailed board
dimensions and layer counts, are useful for deriving more precise θ JA-Effective values.
Support for Compact Thermal Models (CTM)
Table 9-1 provides the traditional thermal resistance data for UltraScale devices. These
resistances are measured using a prescribed JEDEC standard that might not necessarily
reflect the user's actual board conditions and environment. The quoted θ JA and θ JC
numbers are environmentally dependent, and JEDEC has traditionally recommended that
these be used with that awareness. For more accurate junction temperature prediction,
these might not be enough, and a system-level thermal simulation might be required.
Though Xilinx continues to support these figure of merit data, for UltraScale devices,
boundary conditions independent compact thermal models (BCI-CTM) are also available to
assist users in their thermal simulations.
Two-resistor as well as eight to ten-resistor network models are offered for all UltraScale
devices. These compact models seek to capture the thermal behavior of the packages more
accurately at predetermined critical points (junction, case, top, leads, and so on) with the
reduced set of nodes as illustrated in Figure 9-1.
Unlike a full 3D model, these are computationally efficient and work well in an integrated
system simulation environment. Delphi CTM models are available for download on the
Xilinx website (under the Device Model tab).
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Chapter 9: Thermal Specifications
X-Ref Target - Figure 9-1
DELPHI BCI-CTM Topology for
FCBGA
TI
Two Resistor Model
TO
Rjc
Junction
Junction
SIDE
Rjb
BI
BO
Figure 9-1:
UG575_c9_01_102213
Thermal Model Topologies
The CTM models are based on the DELPHI approach that JEDEC has proposed. Since the
JEDEC neutral (XML) format proposal has not been adopted yet, the DELPHI approach is
used to generate these files and the data saved in the NATIVE and proprietary file formats
of the targeted CFD tools - rather than follow a neutral file format. The CTM libraries are
available in FloTherm (PDML) format - good for V5.1 and above and Icepack format (version
4.2 and above).
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Chapter 10
Thermal Management Strategy
Introduction
As described in this section, Xilinx relies on a multi-pronged approach to consuming less
power and dissipating heat for systems using UltraScale devices.
Design and Silicon
Power consumption reduction when using 20 nm node UltraScale devices is achieved
through innovative process and circuit design. For example, transistor static leakage current
is minimized by more than 50% by deploying the multi-gate oxide transistors in the
power-efficient UltraScale architecture.
Despite these improvements and a low operating voltage, the base transistor counts are still
large; UltraScale devices pack high gate densities. Still, when comparing previous silicon
generations, a UltraScale architecture-based logic implementation has lower power
consumption.
However, the increased resources and functionality associated with higher gate density
devices and faster switching programmable logic resources implies increased computation
with less delay. Also associated with this improved functionality is the potential for better
power dissipation due to the silicon and device-based innovations.
Flip-Chip Packages
UltraScale devices are offered in flip-chip BGA packages, which present a low thermal path.
These packages incorporate a heat spreader with additional thermal interface material
(TIM), as shown in Figure 10-1.
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Chapter 10: Thermal Management Strategy
X-Ref Target - Figure 10-1
Thermal Interface Material (TIM)
Lid-Heat Spreader
Die
Substrate
UG575_c10_01_102313
Figure 10-1:
Heat Spreader with Thermal Interface Material
Materials with better thermal conductivity and consistent process applications deliver low
thermal resistance to the heat spreader. The junction-to-case thermal resistance (top of
heat spreader) of the UltraScale device packages is typically less than 0.20°C/W. These
packages deliver a low resistance platform for heat-sink applications.
A parallel effort to ensure optimized package electrical return paths produces the added
benefit of enhanced power and ground plane arrangement in the packages. A boost in
copper density on the planes improves the overall thermal conductivity through the
laminate. In addition, the extra dense and distributed via fields in the package increase the
vertical thermal conductivity. These packages offer up to 20% lower θ JB compared to
previous flip-chip packages.
Heat Sink Solutions at the System Level
Depending on the system's physical as well as mechanical constraints, the expectation is
that an overall thermal budget is maintained with custom or OEM heat sink solutions, thus
providing the third prong in the thermal management strategy. A heat-sink solution is
managed by the system-level designer to tailors the design and solution to the specific
system constraints with knowledge of the device's inherent capabilities for delivering heat
to the surface. Heat-sink solutions are available and can be effective on these low θ JB
flip-chip platforms.
The packages used by the UltraScale devices can be described as medium or
high-performance packages based on their power handling capabilities. All UltraScale
device packages can benefit by using thermal enhancements, ranging from simple airflow
calculations to schemes that include passive as well as active heat sinks. This is particularly
true for the larger flip-chip BGA packages where system designers have the option to
further enhance the packages with larger, more elaborate heat sinks to handle excesses of
25W with arrangements that consider both system and physical constraints.
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Chapter 10: Thermal Management Strategy
Some Thermal Management Options
The flip-chip thermal management chart in Figure 10-2 illustrates incremental power
management schemes that can be applied on a flip-chip BGA package.
X-Ref Target - Figure 10-2
Low End
1–6W
Bare package with
moderate air
8–12°C/W
Mid Range Passive heat sink
4–10W
plus air
5–10°C/W
Bare package
Package can be
used with moderate
airflow within a system
Package used with
various forms of
passive heat sinks
Heat spreader techniques
High End
Active heat sink
8–25W
2–3°C/W or Better
Package used with
active heat sinks
TEC and board level
heat spreader techniques
UG575_c10_02_102313
Figure 10-2:
Thermal Management Options for Flip-Chip BGA Packages
•
For moderate power dissipation (less than 6W), the use of passive heat sinks and heat
spreaders attached with thermally conductive double-sided tapes or retainers (with TIM
around 0.2°C/W) offer quick thermal solutions in flip-chip BGA packages.
•
The use of lightweight, finned, external, and passive heat sinks can be effective for
dissipating up to 10-25W in the larger packages. Since the more efficient external heat
sinks tend to be tall and heavy, additional design considerations can help protect
component joints from heat sink induced stress cracks. Whenever a bulky heat sink is
considered it is advisable to use spring-loaded pins or clips that transfer the mounting
stress to a circuit board.
•
The flip-chip BGA packages offered for UltraScale devices are thermally enhanced BGAs
with the die facing down (see Note). These packages have an exposed metal heat sink
at the top. These high-end thermal packages lend themselves to the application of
efficient external heat sinks (passive or active) for further heat removal efficiency.
Precautions must be taken to prevent component damage when a bulky heat sink is
attached. The thermal interface resistance needs to be controlled to take full advantage
of these packages.
Note: Lidless (FB) packages are not thermally enhanced. See guidelines for applying heat sinks
to lidless packages in Chapter 11, Heat Sink Guidelines for Lidless Flip-Chip Packages.
•
An active heat sink can include a simple heat sink incorporating a mini fan or even a
Peltier Thermoelectric Cooler (TEC) with a fan to carry away any dissipated heat. When
considering the use of a TEC for heat management, it is important to consult with
experts about using the device because these devices can be reversed and cause
damage to components. Also condensation can be an issue with these devices.
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Chapter 10: Thermal Management Strategy
•
The printed circuit board with a mounted device can have a significant impact on
thermal performance. As much as 60 to 80% of the heat dissipated can go through the
BGA balls directly to the board. A typical systems board is larger than the standard 4 x 4
inch JEDEC thermal board. Components mounted on these boards, with multiple
copper layers and several internal vias, show low effective junction-to-ambient thermal
resistances.
Table 10-1 shows this impact as a typical flip-chip package's effective junction to
ambient resistance is changed depending on the mounting board.
Table 10-1:
Impact of Mounted Board Characteristics on θ JA
θ JA (°C/W) for Different Board Sizes
Layer Count of
Mounted Board
4 x 4 in
10 x 10 in
20 x 20 in
4
9.1 (1)
8.3
–
8
8.0
5.5
4.9
12
7.5
4.7
4.4
16
7.2
4.5
4.2
24
–
4.3
4.0
Notes:
1. Base JEDEC mount conditions.
•
Designs can be implemented to take advantage of the board's ability to spread heat.
The effect of the board depends on its size and how it conducts heat. Board size, the
level of copper traces, and the number of buried copper planes all lower the
junction-to-ambient thermal resistance for a package mounted on the board. The cold
ring junction-to-board thermal data for UltraScale device packages is listed in
Table 9-1. Users must be aware that a direct heat path to the board from a component
also exposes the component to the effect of other heat sources on the board,
particularly if the board is not cooled effectively. An otherwise ambient component can
be heated by other heat contributing components on the board.
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Chapter 11
Heat Sink Guidelines for Lidless Flip-Chip
Packages
Heat Sink Attachments for Lidless FBVA Packages
Heat sinks can be attached to the package in multiple ways. For heat to dissipate effectively,
the advantages and disadvantages of each heat sink attachment method must be
considered. Factors influencing the selection of the heat sink attachment method include
the package type, contact area of the heat source, and the heat sink type.
Silicon and Decoupling Capacitors Height Consideration
When designing heat sink attachments for lidless flip-chip BGA packages, the height of the
die above the substrate and also the height of decoupling capacitors must be considered
(Figure 11-1). This is to prevent electrical shorting between the heat sink (metal) and the
decoupling capacitors.
X-Ref Target - Figure 11-1
Decoupling
Capacitor
Silicon
Underfill
Substrate
UG575_c11_01_102213
Figure 11-1:
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Types of Heat Sink Attachments
There are six main methods for heat sink attachment. Table 11-1 lists their advantages and
disadvantages.
•
Thermal tape
•
Thermally conductive adhesive or glue
•
Wire form Z-clips
•
Plastic clip-ons
•
Threaded stand-offs (PEMs) and compression springs
•
Push-pins and compression springs
Table 11-1:
Heat Sink Attachment Methods
Attachment
Method
Advantages
Disadvantages
Thermal tape
• Generally easy to attach and is inexpensive.
• Lowest cost approach for aluminum heat
sink attachment.
• No additional space required on the PCB.
• The surfaces of the heat sink and the chip
must be very clean to allow the tape to
bond correctly.
• Because of the small contact area, the tape
might not provide sufficient bond strength.
• Tape is a moderate to low thermal
conductor that could affect the thermal
performance.
Thermally
conductive
adhesive or glue
• Outstanding mechanical adhesion.
• Fairly inexpensive, costs a little more than
tape.
• No additional space required on the PCB.
• Adhesive application process is
challenging and it is difficult to control the
amount of adhesive to use.
• Difficult to rework.
• Because of the small contact area, the
adhesive might not provide sufficient bond
strength.
Wire form Z-clips
• It provides a strong and secure mechanical
attachment. In environments that require
shock and vibration testing, this type of
strong mechanical attachment is necessary.
• Easy to apply and remove. Does not cause
the semiconductors to be destroyed (epoxy
and occasionally tape can destroy the
device).
• It applies a preload onto the thermal
interface material (TIM). Pre-loads actually
improve thermal performance.
• Requires additional space on the PCB for
anchor locations.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Table 11-1:
Heat Sink Attachment Methods (Cont’d)
Attachment
Method
Advantages
Disadvantages
Plastic clip-ons
• Suitable for designs where space on the
PCB is limited.
• Easy to rework by allowing heat sinks to be
easily removed and reapplied without
damaging the PCB board.
• Can provide a strong enough mechanical
attachment to pass shock and vibration
test.
• Needs a keep out area around the silicon
devices to use the clip.
• Caution is required when installing or
removing clip-ons because localized stress
can damage the solder balls or chip
substrate.
Threaded
stand-offs
(PEMs) and
compression
springs
• Provides stable attachments to heat source
and transfers load to the PCB, backing
plate, or chassis.
• Suitable for high mass heat sinks.
• Allows for tight control over mounting
force and load placed on chip and solder
balls.
• Holes are required in the PCB taking
valuable space that can be used for trace
lines.
• Tends to be expensive, especially since
holes need to be drilled or predrilled onto
the PCB board to use stand-offs.
Push-pins and
compression
springs
• Provides a stable attachment to a heat
source and transfers load to the PCB.
• Allows for tight control over mounting
force and load placed on chip and solder
balls.
• Requires additional space on the PCB for
push-pin locations.
Heat Sink Attachment
Component Pick-up Tool Consideration
For pick-and-place machines to place lidless flip-chip BGAs onto PCBs, Xilinx recommends
using soft tips or suction cups for the nozzles. This prevents chipping, scratching, or even
cracking of the bare die (Figure 11-2).
X-Ref Target - Figure 11-2
Preferred
Decoupling
Capacitor
Metal
Tip
Nozzle
Incorrect Pickup Method
Silicon
Substrate
Decoupling
Capacitor
Metal
Tip
Nozzle
Silicon
Substrate
Soft Tips
Metal Pick Up Tip Nozzle with Soft Tips or
Suction Cups is Preferred
Metal Pick Up Tip Nozzle Can Damage
the Exposed Silicon
UG575_c11_02_102213
Figure 11-2:
Recommended Method For Using Pick-up Tools
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Heat Sink Attachment Process Considerations
After the component is placed onto the PCBs, when attaching a heat sink to the lidless
package, the factors in Table 11-2 must be carefully considered (see Figure 11-3).
Table 11-2:
Heat Sink Attachment Considerations
Consideration(s)
Effect(s)
Recommendation(s)
In heat sink attach process,
what factors can cause
damage to the exposed die
and passive capacitors?
• Uneven heat sink placement
• Uneven TIM thickness
• Uneven force applied when
placing heat sink placement
• Even heat sink placement
• Even TIM thickness
• Even force applied when placing heat sink
placement
Does the heat sink tilt or tip
the post attachment?
Uneven heat sink placement will
damage the silicon and can
cause field failures.
• Careful handling not to contact the heat
sink with the post attachment.
• Use a fixture to hold the heat sink in place
with post attachment until it is glued to
the silicon.
X-Ref Target - Figure 11-3
Preferred
Even Force
Incorrect Alignment
Even Force
Decoupling
Capacitor
Even Force
Decoupling
Capacitor
Silicon
Silicon
Substrate
Substrate
Preferred
Incorrect Force
Even Force
Decoupling
Capacitor
Heat Sink
Silicon
Silicon
Substrate
Substrate
Mother Board
Preferred application of heat sink
1. Heat sink is aligned parallel to silicon
2. Even bond line thickness of TIM
3. Even compressive force is applied on all sides
Improper application of heat sink can cause damage
to heat sink
1. Heat sink is not aligned parallel to silicon
2. Uneven bond line thickness of TIM
3. Uneven force is applied
UG575_c11_03_110513
Figure 11-3:
Recommended Application of Heat Sink
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Standard Heat Sink Attach Process with Thermal Conductive Adhesive
Prior to attaching the heat sink, the UltraScale device needs be surface mounted on the
motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of
silicon in a pattern using automated dispensing equipment. Automated dispensers are
often used to provide a stable process speed at a relatively low cost. The optimum
dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat
transfer.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is
normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer’s specifications.
Standard Heat Sink Attach Process with Thermal Adhesive Tape
Prior to attaching the heat sink, the UltraScale device needs be surface mounted on the
motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the
heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to
help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force
transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a
defined time.
Note: The thermal adhesive tape hold time is based on manufacturer’s specifications.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM)
Application
Prior to attaching the heat sink, the UltraScale device needs be surface mounted on the
motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
Note: The jig or fixture needs to account for the push pin depth of the heat sink.
2. PCM tape, cut to the size of the heat sink, os applied on the underside of the heat sink
at a modest angle with the use of a squeegee rubber roller. Apply pressure to help
reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking
action with the PCB holes. The compression load from springs applies the appropriate
mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the
mechanical locking action which requires manual handling. The PCB drill hole tolerances need to
be close enough to eliminate any issues concerning the heat sink attachment.
Package Loading Specifications
For lidless flip-chip BGA packages, Xilinx specifies a maximum static load of 60 psi. This
mechanical maximum load limit cannot be exceeded during heat sink assembly, shipping
conditions, or standard use conditions. Any mechanical system or component testing must
not exceed the maximum limit.
The static load of maximum 60 psi is:
•
Applied as uniform compressive loading in a direction normal to the package.
•
The maximum allowed load from the heat sink retention clip.
•
Based on limited testing for design characterization. Loading limits are for the package
only.
Note: As a precaution; a minimum point force of 75 ft-lbs can cause the die to crack.
For thermal and mechanical solutions, the package substrate must not be used as a
mechanical reference or load-bearing surface. For heat sink clip pre-load calculations, the
post-reflow package height must be used.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Reasons for Thermal Interface Material
When installing heat sinks for UltraScale devices, a suitable thermal interface material (TIM)
must be used. This thermal material significantly aids the transfer of heat from the
component to the heat sink. For optimum heat transfer, Xilinx recommends the use of
thermal interface materials.
For lidless flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded
flip-chip BGAs, the lid contacts the heat sink. The surface size of the lidless FCBGA and
lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal material
for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot
effectively cool an UltraScale device unless there is good physical contact between the base
of the heat sink and the top of the UltraScale device. The surfaces of both the heat sink and
the UltraScale device silicon are not absolutely smooth. This surface roughness is observed
when examined at a microscopic level. Because surface roughness reduces the effective
contact area, attaching a heat sink without a thermal interface material is not sufficient due
to inadequate surface contact.
A thermal interface material such as phase-change material, thermal grease, or thermal
pads fills these gaps and allows effective transference of heat between the UltraScale
device die and the heat sink.
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface
materials are:
•
Thermal pads, also called phase-change materials.
•
Thermal grease, also called thermal paste.
Phase-change materials are usually thin pads approximately 1 inch x 1 inch
(2.5 cm x 2.5 cm) in size and have protective films attached on both surfaces. The color is
vendor-specific but is usually gray or pink. Thermal grease usually comes in a syringe, a
tube, or a small plastic sachet. Thermal grease is similar in consistency to ordinary
toothpaste and is typically gray or white.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Guidelines for Thermal Interface Materials
Five factors affect the choice, use, and performance of the interface material used between
the processor and the heat sink:
•
Thermal Conductivity of the Material
•
Electrical Conductivity of the Material
•
Spreading Characteristics of the Material
•
Long-Term Stability and Reliability of the Material
•
Ease of Application
Thermal Conductivity of the Material
Thermal conductivity is the quantified ability of any material to transfer heat. The thermal
conductivity of the interface material has a significant impact on its thermal performance.
The higher the thermal conductivity, the more efficient the material is at transferring heat.
Materials that have a lower thermal conductivity are less efficient at transferring heat,
causing a higher temperature differential to exist across the interface. To overcome this less
efficient heat transfer, a better cooling solution (typically, a more costly solution) must be
used to achieve the desired heat dissipation.
Electrical Conductivity of the Material
Some metal-based TIM compounds are electrically conductive. Ceramic-based compounds
are typically not electrically conductive. Manufacturers produce metal-based compounds
with low-electrical conductivity, but some of these materials are not completely electrically
inert. Metal-based thermal compounds are not hazardous to the UltraScale device die itself,
but other elements on the UltraScale device or motherboard can be at risk if they become
contaminated by the compound. For this reason, Xilinx does not recommend the use of
electrically conductive thermal interface material.
Spreading Characteristics of the Material
The spreading characteristics of the thermal interface material determines its ability, under
the pressure of the mounted heat sink, to spread and fill in or eliminate the air gaps
between the UltraScale device and the heat sink. Because air is a very poor thermal
conductor, the more completely the interface material fills the gaps, the greater the heat
transference.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Long-Term Stability and Reliability of the Material
The long-term stability and reliability of the thermal interface material is described as the
ability to provide a sufficient thermal conductance even after an extended time or
extensive. Low-quality compounds can harden or leak out over time (the pump-out effect),
leading to overheating or premature failure of the UltraScale device. High-quality
compounds provide a stable and reliable thermal interface material throughout the lifetime
of the device. Thermal greases with higher viscosities are typically more resistant to pump
out effects on lidless devices.
Ease of Application
A spreadable thermal grease requires the surface mount supplier to carefully use the
appropriate amount of material. Too much or too little material can cause problems. The
thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Comparing the Types of Interface Materials
Thermal Grease
Thermal grease is a paste made up of thermally conductive ceramic fillers in silicone or
hydrocarbon oils. It is applied to one of the two mating surfaces. When the surfaces are
pressed together, the grease spreads to fill the void. See Table 11-3 for the thermal
resistance, and pros and cons of usage.
Table 11-3:
Thermal Grease
Thermal Resistance
0.2 to 1°C cm2/W
Pros
• Eliminates air gaps between
components and the heat sink.
• Compensates for uneven heat sink
surface and silicon.
• It is soft and is easy to compress to
the height differential of multiple
components.
• Stress-free with outstanding
mechanical shock absorption.
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Cons
• Hard to use in manufacturing
because it is difficult to dispense and
apply due to a high viscosity.
• Requires cleanup to prevent
contamination problems.
• Requires mechanical clamping to
hold the heat sink and component in
its place.
• Applications with repeated power
on/off cycles might cause occurrence
of pump-out, where the grease is
forced from between the silicon die
and the heat sink each time the die is
heated up and cooled down. This can
cause thermal performance
degradation over time and
contaminate the neighboring
components.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Thermal Gel
Thermal gels are dispensed like thermal grease. They are cured to a partially cross-linked
structure, which eliminates the pump-out issue. See Table 11-4 for the thermal resistance,
and pros and cons of usage.
Table 11-4:
Thermal Gel
Thermal Resistance
0.15 to 1°C cm2/W
Pros
• No pump out issues.
• Eliminates air gaps between
components and the heat sink.
• Compensates for uneven heat sink
surface and silicon.
• It is soft and is easy to compress to
the height differential of multiple
components.
• Stress-free with outstanding
mechanical shock absorption.
Cons
• A mechanical fastener is essential to
maintain the joint once it is
assembled.
Thermal Conductive Compound
A thermally conductive compound incorporates thermally conductive fillers. However,
unlike thermal greases, the binder is a rubber material. When first applied, the paste-like
compound flows into the interstices between the mating surfaces. Then, when subjected to
heat, it cures into a dry rubber film. Besides its thermal properties, this film also serves as
an adhesive, allowing a tight, void-free joint without the need for additional fasteners.
Thermally conductive compounds can successfully fill larger gaps in situations where
thermal greases might ooze from the joint. Although application and performance is similar
to that of thermal grease, cleanup is easier, simply involving removal of the excess cured
rubber film. See Table 11-5 for the thermal resistance, and pros and cons of usage.
Table 11-5:
Thermal Conductive Compound
Thermal Resistance
0.15 to 1°C cm2/W
Pros
• Mechanical clamping not required.
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Cons
• Cannot be reworked.
• Metal-based conductive adhesives
can cause electrical shorting with
contamination on the UltraScale
device and other devices on the
motherboard.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Thermally Conductive Elastomeric Pads
Thermally conductive elastomeric pads consist of a silicone elastomer filled with thermally
conductive ceramic particles and can incorporate woven glass fiber or dielectric film
reinforcement. Typically, the recommended thickness is from 0.1 mm to 1 mm. The
recommended hardness rating is from 5 to 85 Shore A. By providing both electrical
insulation and thermal conductivity, they are useful in applications requiring electrical
isolation. Thicker pads are used when large gaps must be filled. During application, the
pads are compressed between the mating surfaces to make them conform to surface
irregularities. See Table 11-6 for the thermal resistance, and pros and cons of usage.
Table 11-6:
Thermally Conductive Elastomeric Pads
Thermal Resistance
1 to 3°C cm2/W
Pros
• Simple assembly.
Cons
• A mechanical fastener is essential to
maintain the joint once it is
assembled.
• Mounting pressure must be adjusted
according to the hardness of the
elastomer to ensure that voids are
filled.
Thermal Tapes
A thermal tape is a double-sided pressure sensitive adhesive film filled with thermally
conductive ceramic powder. To facilitate handling, aluminum foil or a polyimide film can be
used to support the tape; the latter material also provides electrical insulation. When
applied between mating surfaces, the tape must be subjected to pressure to conform to the
surfaces. Once the joint is made, the adhesive holds it together permanently, eliminating
the need for supplemental fasteners. No bond curing is needed. See Table 11-7 for the
thermal resistance, and pros and cons of usage.
Table 11-7:
Thermal Tapes
Thermal Resistance
1 to 4°C cm2/W
Pros
• Simple assembly.
• Mechanical clamping not required.
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Cons
• Cannot fill large gaps between
mating surfaces as well as liquids,
which can affect thermal
performance.
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Chapter 11: Heat Sink Guidelines for Lidless Flip-Chip Packages
Phase Change Materials
Solid at room temperature, phase change materials are melted (i.e., undergo a phase
change) as the temperature rises to the 104°F to 158°F (40°C to 70°C) range. This makes the
material (0.13 mm thick in its dry film form) as easy to handle as a pad, while assuring that
it will, when subjected to heat during the assembly process, flow into voids between mating
surfaces as effectively as a thermal grease. Ordinarily, applying power to the electronic
component introduces the needed heat for the phase change to occur, establishing a stable
thermal joint. These materials consist of organic binders (i.e., a polymer and a
low-melt-point crystalline component, such as a wax), thermally conductive ceramic fillers,
and, if necessary, a supporting substrate, such as aluminum foil or woven glass mesh. See
Table 11-8 for the thermal resistance, and pros and cons of usage.
Table 11-8:
Phase Change Materials
Thermal Resistance
0.3 to 0.7°C cm2/W
Pros
• Simple assembly.
• Mechanical clamping not required.
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Cons
• Cannot be reworked.
• A mechanical fastener is essential to
maintain the joint once it is
assembled.
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Appendix A
Additional Resources
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
For a glossary of technical terms used in Xilinx documentation, see the Xilinx Glossary.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
References
1. UltraScale Architecture SelectIO Resources User Guide (UG571)
2. UltraScale Architecture Clocking Resources User Guide (UG572)
3. UltraScale Architecture Configuration User Guide (UG570)
4. UltraScale device data sheets:
°
Kintex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics
(DS892)
5. UltraScale Architecture GTH Transceivers User Guide (UG576)
6. UltraScale Architecture System Monitor User Guide (UG580)
7. UltraScale Architecture PCB and Pin Planning User Guide (UG583)
8. UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
9. UltraScale Architecture and Product Overview (DS890)
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Appendix A: Additional Resources
10. The following websites contain additional information on heat management and
contact information.
°
Wakefield: www.wakefield.com
°
Aavid: www.aavidthermalloy.com
°
Advanced Thermal Solutions: www.qats.com
11. Refer to the following websites for interface material sources:
°
Power Devices: www.powerdevices.com
°
Bergquist Company: www.bergquistcompany.com
°
AOS Thermal Compound: www.aosco.com
°
Chometrics: www.chomerics.com
°
Kester: www.kester.com
12. Refer to the following websites for CFD tools Xilinx supports with thermal models.
°
Flomerics, Flotherm, and FloPCB: www.flomerics.com
°
Fluent, Icepak: www.icepak.com
UltraScale Device Packaging and Pinouts
UG575 (v1.0) December 10, 2013
www.xilinx.com
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