�ASK
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---
--·-- -
--
CT5256B,·
Data Sheet
Tabla of contents
CTS2S6B
Contactless Ticket
1
2
3
4
lnlroduction
Functlonal description
4.1
4.2
Protocol
Frames
4.2.1
6
6
6
Reader to chip
Chip to reader
4.2.2
4.3
Timing
4.4
Example REQT
C.ticket®
ISO 14443 type B
''
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'
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rn
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Product overview
Chip features
4.5
46
Chip states diagram
Memory mapping
4.8
Securrty setup:
4.7
8
System bits
4.9
Power on reset
5 Electrical characteris\tcs
6
7
Memory del1very format
Personallsallon
DATA SHEET
V1.6
0ASK
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Reference documen!s:
CTS256B User Mánual
Software specrficalion -ASK GEN3XX reader- CSC Interface
Software specLJ
ification - DLL - Interface with ASKCSC.DLL
NlCE
ASKS.A.
15. trasor.,o dos BF>Jcs l.es
e""'''""'
065GO Valbo""" Sopt11aAnt;µ<>li,;
FRANC�
Tol: 0497214000
Fax·04923BS321
PARIS sales office
ASK SA.
15. rue du l.,,uv,é
75001 PARIS
,-�
Tel· 01 42336415
Fo,. 01 •2 336414
lnk>,mat,on
Support
HONG-KONG
Suilo 90&!
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89 Quee<1..,ay
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Tol •8522021 7218
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!ill-�/fw'!=••< !t
support@ask1<
The soliemalócs and ;nro,mo'"1n oontained ;n ,r,;, '""'""'""' aro not con�ocUJol and moy I» cbango wr.hollt no'"'"
Uso In füa support rlev,ce, o, syslems ma,I bo o,pmssly oulho<=<I w,lh • wnllOn appro,al ofASK $ /\
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Product Information
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1
Data Sheet
CTS256B
3
Product overview
t iishe<l product containing a contactless chip, one anlenna and a support.
CTS256B I s a ftn
CTS256B could be delivered in multi ple formats: ISO, Edmonson or module, paper or plastic maleria/.
CTS256B chip is a non-volatile memory with simple wire<l log ic and con\actless inlt!!face.
Power supply and data transfer are receive through magnetic field sent by any readerfollowing ISO 14443 type B.
Chip could be read ar\d write many, four areas could be wrile prolected by the applicalion.
Product is optimised for high volume and low cost.
There Is no extra pin connect,on excepl coil antenna.
2
�ASK
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CTS256B
Data Sheet
lntroduction
For many pubtic transport networks contactless smartcards are the best solution lor frequent travellers but what is
the solulion for occasional traveIJers7
CTS2568 and CTx512B ara a range of low cost contactless disposable \Icllets, fully compatible with ASK
contactless smart card readers. They comply wilh the lSO 14443 standard and operate on the same terminal ns
contactless smartcards. They are the best solution to occasional travellers, and necessîtate no imrastment in
another different technology such as magnet,c or barcode, which would increase cost and complexily.
The CTS256B ts a C.tlcl<et"for single trips, with !he possibility of murnmodal conneciions or for instant entranca
licl<ets to stadiums or museums. lt is available in various types of paper pacl<agir>g ranging from Edmonson to 1S0
formats.
The CTS256B is compatible wilh ISO raqui,ements end the ASK con!actless range of products
CTS256B is a membor of ASK product family with CTx512B (contacUess ticket with en1i-Oone) and others
contactless microprocessors.
Chip features
ISO 14443- 2 type B: Air interface compliant
CTS2568 chip is a 256 bits EEPROM memory with wired logic and RF interface.
1S0 14443 - 3 type B: Frame format compllanl
Chip block diagram:
13.56 MHz Operation
Baud rate: 106 l<bils/S
Data Modulalion:
ASK /rom readerto chip
BPSK !rom chip to reader
CTS256B
CHlP
256 bits READ I WRITE / ERASE EEPROM
Read, Wrilo and Erase by 16 bits. (lypical wrilt!/erase = 2 ms)
Unique serial number 64 bits write protected
4 zones of secure<l memory (read only mode) by otp system bits (One Time Programmable)
12 otp bïits as fuses for user application (oneway counter)
Data integrily guaranlied by CRC16 1S0 14443 type B
Optimised lnslruction set
Highly reliable CMOS EEPROM Technology
10 years data retention
rl
Demr,dula!e and
decade
Reclifuor
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Extemal
capa
T
ance
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laglc
machine
Voltage
rcferenca
1
Rest,!
Clock
EEPROM
256 bits
Memory
lnterlace
'"'
Modulate and
encode
se<:urlty
More lhan 1000 Erase/Write cycle en durance
Whole memory become reed only alter intens;ve UV exposure (sectm1y feature)
Distance communications from O to 20 cm depend on package, reader and antenna
Typical RF commun,calion time less than 100 ms
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OS/CTS: 1.6
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Product Information
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Pr<:lduct Information
OSJCTS: 1.6
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�ASK
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Data Sheet
CTS256B
4.1
Pro\ocors instruction is reduce to the minimum. Only five instrucUons are used to activets, read and update data then
deactivate the chip
REQT:
Request înstruction
Alter power up, the chip is walting forlhis lnstruction (READ at address O equivalent)
Beforo this, lhe chip never executes instructians
Afler this, chip answers at any read instruclion and chip executes any others instructions:
REAO (at all addresses), WRITE, ERASE and DESACTJVATE.
READ:
Read instn,ction
Allow a readmg from block O untilj bl[ock 15.
Before write or erase blocks, one raad at address 1 have to be done to refresh the system
bits.
WRITE:
Depend on system bit, wr ite is perfom,ed from block O to 15 or not.
Write instruction put at "1" or keep \he slate depend on data transmitted.
Erased state Is 0000 Hexa and full wr1�en state !s FFFF He><a.
Write instruction is perform only ifthe internal power supply reaches an. enough level lo ftnish
correctly the operation without keeping odd va lue in memory.
ERASE·
DESACTIVATE:
Depend on system bit, era se is perforrned from block O to 15 or not
Alter erase operalion. all bits in black are OOOOHexa
Erase instruction Is perform only ifthe internal power supply reaches an enough level to
finish correcUy the operation without keeping odd value in memory.
Desactivate instruction
After rece ivlng lhis instruction chip never answer at any read instruction and never execute
others instructions.
Chip stay in lhis state unUI power supply goes done and chip reset.
Chip response
Reader commands
REOT
0001 0000
CRC lsb
CRC msb
READ
0001 aaaa
CRC lsb
CRC msb
WRITE
0010 aaaa
DATA1
0ATA2
ERASE
0100 aaaa
CRC !sb
CRC msb
OESACTIVATE 1000•-··
CRC lsb
CRCmsb
Frames
4.2.1
Protocol
Chip code Fab code
DATA1
CRC lsb
DATA2
CRC lsb
CRC msb
CRC lsb
CRC msb
CRC msb
a = address bits
• "don"t care bits
-
Hii'ffl:M
Data Sheet
4.2
Functional description
4
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Reader to chip
Bit lransmission and frame format are ISO 14443-3 type B.
Start Of Frame. End Of Frame and Extra Guard Time from the reader to the chip ara ISO.
10<ElU<1 1
2<ETU<3
î""""'"
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ins\ruction
�_Jol1l213l4151611I, ,I
12<:ETU<14
• +
---,
stop
start
O<ETU<6
lasl CR.C byte
-- - ----- -'----7 Jol1j2j3j4jsl6l1
I
1
EGT
0<ETU<6
LJ0111213141,
),
1!kETU <11
EOF
/
Communlcation between reader and chip takes place vla ASK 10% amplitude modulation of the RF operating field
Bits are sent LSB first. (see ISO 14443-2 type B)
During frame rnception, chip controls all paramote� start stop bit and EGT lhen compares inlemal 16 bits CRC with
lhe CRC sent within the end of frame. !fall parameters are in specification. chip understands instruction.
LSB is sent first
Note: EGT= 0 is f<Jster and if EGT timing is an ETU multiple, coupier gem,rates less transm]ss;on error.
Al! data being received by the CTS256B Is sampled by 1he receiverm lhe middle of each bit t ime period The timjng
begins with the first falling edge detected lor the SOT and is nol resynchronized at any pointduring receipt of the
frame. Forlhis reason. all data sent to the IC must be an integer number of ETU: the fract ional bit times pemutted by
14443-3 lor the EGT and SOT will not be properly received by the CTS256B.
4.2.2
Chip t o reader
Bit transmission and frame format are in ISO 14443--3 lype B
CRC transmit is ISO 14443 type B compliant
Start Of Frame, End Of Frame and Extra Guard Time trom the chip to the reader Is wlthin ISO.
No SOF and E.OF are sent by the chip. An ISO reader shoul d support suppression of SOF and EOF.
EGT is fixed at 0.
TRO = 16 b its= 151 µs
(16 bits
TR1 = 16 bits= 151 µs
➔(16 bits :,.
··--,-
CTS256B chip is full !SO 14443-2 type B compliantand could wmk wilh ISO 14443/1-2·3 readers.
CR.C receiV<! and sent is ISO 14443 type B
Unmodulaled phase
- �
0
1startlbit0 PPPl4 l0 l6 171LJ
1112114 15 16 171
stopbit
Modulatedphase
L
Data coding ls NR.Z wilh BPSK modulation. Bits are sent LSB first.
Copyoght<s:>2000-2003 ASK S.A.
OS/CTS: 1.6
Page 5 113
Product b;formatlon
Th1s documoot may rlOt be corn.mun,c,sted lo tH•ttl pM;es w>\houl pMr wn•ton authoósotloo !rom ASK SA Com�ai
Product lnfonnatio_a________ - Cop)'!li,ht�2000.2003 ASK S.A.
öSicTs: 1.6
Page 6 / 13
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Data Sheet
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4.3
CTS256B
Timing
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4.5
Data Sheet
CTS256B
Chip states diagram
lnslruchon following one Wnte or Erase lnslruction;
Acli�e fiald
Wiile er Erase instruction
ne>ct instruclion
l
REOT
Min2 mS
Oth<>rinstruction
<,'espGri;i%'
!nstruction following a Read instruciion without answer or a Desactivale inslruction
:espons�;
lnstructio11
'""'
tAcTIVE
next lnstruction
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Reader talks first and aciives the chip by a spedfic "RËQuesl Tk:ket ".
Chip is aclive by the inslruction REQT. chip answers manuf;,clurlng code and product code.
Alt.,,- lhat, transaction could start and exe<:1.1te the applic:ation with Tnslructlon READ, ERASE and WRlTE.
At !he end cftransaelion DESACTIVATE allows ilnr'Mdlalèly a new lransaciion wilh a second ticket without disturb
the first one.
In HALT state, chip is waiting field off without executes any lnslruction.
Th<ma is no an!i-.collision sche,m, in the chip, the applicatîon assume \hare is only on chip in the field in the same time
or checks possible oollision.
Any way, with the instruction REQT and DESACTIVATE, the cr�icat time to aciivetwochips in the same time is very
short less than 1 ms.
Il a ticket enters in the field durlng a transmlssion wilh any others chips, lt doesn't disturb the apl)lica!ion.
lf two tickets CTS256B are active in the same time, the readerrould deteci it reading the serial number blocks.
In lhis case, the two answers are overJapped and CRC is wrong.
Appticalions have to manage this.
lnstruction following a successful Read lnstruction
response
next lnslrucllon
d ---Min0.1in,�­
�
4.4
REQT
+
Example REQT
g����rrommar,d
command
ere
'"
"
Action
OESACTIVATE
Min0.3mS
Read înst,uction
WRITE
ERASE
Tickets ln reader field
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"
Chip_response
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'"
,.,
"'
"
REQT
-+\iokel 1
transaction 1
licgitz
�
i; ms
t
DESACTIVATE---...
REQT
�
transaction 2
DESACTIVATE---...
COJ>)'righl©2000-W03ASKSA
Os/CTS: 1.6
Page 7 (1j
Product Information
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1· parilos l>llhoul p,;o,wn••n •Ull'H>nsaUon lcom ASK SA Comj)ar,y
Product [r,formation
Tm•
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DSÎèTS: 1.6
Page 8 / 13
"°"'"'"'"' may not 00 commL<nlcatB<I 10 thiaJ pa�"''
willlout pnorwriMo authonsa
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�ASK
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1
1
1
1
1
1
J
1
1
1
1
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Data Sheet
CTS256B
Memory mapping
4.6
1 Address
CTS256B
Data Sheet
4.8
16 bleeks ol 1 6 EEPROM bits
''
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16 bits black
Product code
Manufacturin" code 1
lnvalidat!on bits
Svstem bits
Embedder c-ode
""licali!in code
1 Ä""
Serial number LSB
1
Se rial number MSB
1
A DDlication
1
ADl'llication
1
A l'lDllcatîon
1
Area
m,O
'
'
'
ADDlication
Security setup:
Securltv
Read onlu after fabrlcat!on
Tlckct enlcr.; ifl reader field
OTP attor fabrication
f Road only afler bit systorn O written
1
Reader sends REQT
1 Read only attor bit system 1 wrltten
ADDlication
A PPlication
A ppl!callon
ADDlicatlon
A pp!lcation
Annlication
Ann!ication
1 -R!cADY TO RlcAD 1
Read on!y after bit system 2 written
Read onty after b!t system 3 written
Read is al!owed
in all memory bic,r:ks
Reader sends READ @ 1
Area J is reserved forembedder pre-personalization.
In !his area, uniquo serial number is guaranty for !he final application.
Area 4, 5 and/or 6 could be use for applicative personallzation.
READY TOREAD ANDWRITE
L---,----1
Erased value is •o•. Wrillen velue is ·1•.
4. 7
Ticket never answcr.;
IDLE
Read andwrite are a!lowed
· memory blocks
iin all
Reader sends RELEASE
System bits
HALTED
System bit. alter writing, loci< in read only mode the arna 3, 4, 5 or/and 6.
Aller power up, maximum securily is set in the chip.
Sefore any write or erase instruction, one read al Sys1em brt address have to be perform to update log1c secunty bits.
Alter updating System bits, a new read at System btt address have lo be perform to update sec:urily bits.
Aller UV exposure, all bits are read as •1•. maximum security is set, memory is read only.
Tfeket never answera
and no more execules
inslrucHoos
Before anywrite and crase, the application must read b lock 1 In order t o initialise the securily level.
0TP bits are rese,ve for user apphcat,on. Theses bits cou ld be only set and never reset.
Afler pre-personalizati on System bits values are:
'
Address
'
Ama
Securodmea
bit 15 1 bit 14 bit 1l
Svslcm bits
'
Area6
'
Area 5
'
Area4
1 :
16 bits block
bit 12
bit 11
bil 10
'
Area 3
Area 3 is road only after pre-personal ization.
0
bit9 1
0TP b!ts
0
0
No area affecied
'
:-1
1 bltO
'
0
Area 4, 5 and 6 coold be prolected by the user appl;cauon.
0thers 01P bits could be used lor application non-reversible bits.
C"l'\'fight©2000·2003ASi<'. 5A
-f'f0duct Information
DS/CTS: 1.6---Pags 9113
This O,;,;umerrt ,my nol bo oommun�e<l lo lh,rd P'l""'" w1111ou1p,<a,wFitlen aull1oosattoo ln>m ASK SI\ Company
coPyngh,@ 2aaa.200a 11SKs.11.
DSICTSC T:"6- Page 10,-1 3
TNsdocument may oo, b& commun;ca<ed to third part,o, wrthou! pnor"1ilten authon,abon fc<>m ASK SA Company
Pro-;iUêtInformation
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4.9
lïtïïf.1'111=1
Data Sheet
�ASK
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A power on reset feature with a specific hysterisis guaranties afler the first response that the chip could execute any
instruction without reset int,muptian.
Th1s feature guaranties that chlp is reset properly when enter In lhe field, no odd value is written in EEPROM and
aftar selection each instruct ion sent by the reader is well execule.
,�
T,.,,..
Mtcamo,
Tr, T,
Twsof
Îèà!ner
Tfü�<lala
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FsuJ,oa<Tior
lnlemal "'gu!ator
1(
/
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.
/
/
/,
Power on rosol
�'-\\: t ,.,_
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�d sequonco
Wrile oequonce
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Pow•to!fro,et
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TRO
TR,
Tin.str
Re
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A••
Cyde
Re<
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'°
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'°
Condition
Min
Werking temperalurn range
T-•
Hf,old
Afler !ransaction, when card is leaving field, chip is wen reseUing.
,----
--· ------
Parameter
Symbol
An inlemal power regulator guaranLies a good luncUonality in all different magnetic fields ISO compl1ant.
1
1 .,o
13,553
A
'
rn
13.56
0
os
94.4
S5
0
o.s
·c
·c
%
s
847.5
Unit
13.567
,s
,0
mS
Afm
Afm
M,,
kohm
,
EEPROM pmgramming time
By 16 Ms
Number of EEPROM programmJng cycle
Data retenlTOll in E EPROM
After maximum cycie
lntemat Regulated Voltage
Typioal 25 •c
CUrrenl consumptlon
Typical 25 •c
-------.--
s,
00
Following ISO 10373-2
• Depend on packaging
T"
0
Storage tomperalure range
Extemal R F signal frequency
Carrier modulation ;ndex
ISO 14443-2
Reader to chin at 106 KHz
10% riseand fall time
Minimum pulse widlh for SOFIEOF
Carr ier rise time
0 to 7.5AlM
T i;me from carrier start lo first data
ISO 14443-3
Guaranleed operaling fiel d strengths
ISO 14443-2
Maximum field guerantywlth no irreversible destruction
Genera.led sub carrier frequency
Fcc/16
Antenne Reversal delay
ISO 14443-3
Synchronization delay
ISO 14443-3
Time b<!!ween end of chip response and SOF read"r
Res iistiive Load
Load modulation amplitude
Chi� to reader at 847.5 KHz
.
04½.J.iij:i
Data Sheet
.. ··· ·· ·· ·- ·--···
Electrical characteristics
5
Power o n reset
' . . ..
"
so
1000
,0
eoo
mV
mS
1 Cyc l1es
Yearn
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T,
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Teamo, ...,.. Tfüs<da!o
CO]>l'nghl@ Z000.2003ASK S.A
Product lflformatlon
OS/CTS: 1.6
Page 11 / 13
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�j ,.� \__
èèpi,i;yhi©zooo-2003 A5KS.A
-Product Information
OS/CTS: 1.6
Page f;f i fa
Th"' docum,'"I maynol be oommun,caled lo tl>1fll parue, wm,outpaorwnuon a"tl\Onso\oón fromASKSA Company
�ASK
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CTS256B
Data Sheet
Memory delivery fo �!_Tlat
6
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Address
0
Area
0
0
j
l
j
1
1
1
Manufadurino code
Svstem bits 1
Embedder code
Annlical1jon
Annlication
Ann[ication
Änlllication
A on!lcation
A onlication
A 00lication
A 00lication
Ano,
r,callon
1
1
1
l
1
1
'
,,o
H
1S
"
"
He"' valuc
Product code
OTP bits
Am'lication code
Serial number LSB
Serlal number MSB
Annlication
Annlica\ion
"
1
=ro
0
l
1
000
00
1 00
00
00
0000
0000
0000
00 00
1
00 00
00 00
00 00
00 00
1
0000
0000
0000
02 correspond lo STM chip Manufaclurer.
5xH corresponds 1o CTS256B chip version
Al l ethers areas are in vlrgin state 00 hexa.
7
Personalisation
The embedder maneges the area 3 then foc� il ln reed only mode befare any sh'tpment.
Product lnfonnatlon
Co;,yrtght©200D-;lOO>As°KSA
--i.fSICTS: 1.6
Page 1 3 1 13
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