Materials Science Forum Vols. 821-823 (2015) pp 524-527
© (2015) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/MSF.821-823.524
Submitted: 2014-09-12
Revised: 2014-11-14
Accepted: 2015-01-29
Online: 2015-06-30
High-Speed Dicing of SiC Wafers by Femtosecond Pulsed Laser
Akira Nakajima1, a *, Yosuke Tateishi3, Hiroshi Murakami1,
Hidetomo Takahashi3, Michiharu Ota3, Ryoji Kosugi2, Takeshi Mitani2,
Shin-ichi Nishizawa1 and Hiromichi Ohashi1
1
2
Energy Technology Research Institute, National Institute of Advanced Industrial Science and
Technology (AIST), Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, JAPAN
Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science
and Technology (AIST), Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, JAPAN
3
Aisin Seiki Co., Ltd., 2-1 Asahi, Kariya, Aichi 448-8650, JAPAN
a
a-nakajima@aist.go.jp
Keywords: SiC wafer, dicing, femtosecond pulsed laser
Abstract. A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) is demonstrated
as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process
consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip
separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33
mm/s. Kerf loss is negligible in the developed FSPL dicing process. In addition, the residual lattice
strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical
process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser
processes.
Introduction
SiC power devices have been making big
efforts for commercialization in the last decade
and used in a number of applications, such as
power converters for consumer electronics and
social infrastructures. However, the commonly
utilized dicing process, which uses diamond
saws, is low in speed and high in cost due to the
mechanical hardness and brittleness of
wide-bandgap SiC (~9 on the Mohs scale). To
expand the possible applications of SiC devices,
novel dicing technologies for SiC wafers have
been desired to produce a large number of SiC
chips [1-3]. Recently, optical micromachining of
SiC wafers has been presented using
short-pulsed lasers [4-5]. In this paper, we
demonstrate a high-speed SiC dicing technology
that utilizes femtosecond pulsed lasers (FSPLs)
and does not exhibit kerf loss.
Experimental
Fig. 1 shows the schematics of the developed
SiC dicing process. After device fabrication on
SiC wafers, cleavage grooves were formed on
Fig. 1. Schematics of developed dicing
processes of (a) groove formation by the
FSPL, followed by (b) chip separation by
pressing a cleavage blade from the backside.
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Materials Science Forum Vols. 821-823
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the wafer surfaces by the FSPL, as
illustrated in Fig. 1(a). Then the wafers
were flipped over and separated into
individual SiC chips by pressing a
cleavage blade into the wafer backside, as
shown in Fig. 1(b). In this study, we
utilized four-inch, 360-µm-thick 4H-SiC
wafers with 600-V-rated Schottky barrier
diodes (SBDs), as illustrated in Fig. 2(a).
The anode electrodes have a 1594 ×
1594-µm square shape. The distance
between adjacent anode electrodes was
346 µm, as shown in Fig. 2(c). The wafers
were diced into SiC chips by the developed
FSPL process, and also by a conventional
Fig. 2. (a) Schematic cross-sectional structure of
mechanical dicing technique that used
4-inch SiC wafers with 600-V-rated SBDs and
50-µm-thick diamond saws. The FSPLs
(b-c) top-view optical microscopy images.
have a wavelength of 1045 nm, pulse width
of 800 fs, repetition rate of 100 kHz, and
pulse energy of 3.6 µJ. The laser scan speed on the SiC wafer surfaces was 100 mm/s using a
motorized x-y-z translation stage. The laser scanned the surface three times to form a linear groove.
Therefore effective scan speed was ~33 mm/s.
Results and Discussion
Fig. 3 shows SEM images of SiC chips diced by the FSPL process. Although debris was observed
on the as-cleaved SiC chips, as seen in Fig. 3(b), the debris can be removed by using an organic
solvent, as shown in Fig. 3(c). Fig. 4 shows the relationship between dicing yield and cutting center
distance ∆x from the anode electrodes. In this study, the cutting center positions were changed from
the street center position (∆x = 173 µm) to -7 µm in 20-µm steps. Here, the dicing yield was obtained
Fig. 3. (a) SEM images of SiC chip by
FSPL dicing and enlarged images at
the corners of (b) as-cleaved and (c)
cleaned SiC chips after FSPL dicing.
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Silicon Carbide and Related Materials 2014
Fig. 4. Schematic drawings of dicing dimensions as a result of (a) FSPL and
(b) conventional mechanical dicing processes. (c) Relationship between the
cutting center position and the dicing yield.
Fig. 5. Typical reverse leakage characteristics of the SiC-SBDs measured before and
after (a) FSPL and (b) conventional mechanical dicing processes at ∆x = 13 µm.
Fig. 6. (a) Schematic drawing of the measurement position on diced chips and (b) variations
of the frequency shift of the FTO mode along <11–20> and (c) <1–100> directions.
by comparing it to the reverse leakage current (VAC = -600 V) before and after the dicing process.
Using the FSPL dicing process, we successfully obtained a 100% yield at a narrow ∆x value of 13 µm,
with no effect on the reverse characteristics. Fig. 5 shows typical reverse leakage characteristics of the
SiC-SBDs before and after the dicing processes at ∆x = 13 µm. These results indicate that kerf loss
can be neglected in the FSPL dicing, and therefore the cutting street width can be reduced.
The residual lattice strain distribution after the dicing process was evaluated by micro-Raman
measurement. Scattered light was dispersed with a 1 m double monochromator with 1800 gr/mm
gratings, and the 514.5 nm line of an Ar+ laser was used for the excitation source. We measured the
Materials Science Forum Vols. 821-823
variation of the peak frequency of the
FTO mode when making line scans on
the (0001) surface from the cutting edges,
as illustrated in Fig. 6(a). ∆ω (=ωd-ωv)
corresponds to the difference in the peak
frequencies between the diced chips (ωd)
and a virgin epilayer (ωv). As shown in
Figs. 6(b)–(c), the shifts to low
frequencies in the diced chips were
observed around the edges, which
indicates that tensile stress remains. The
residual lattice strain in the FSPL-diced
SiC chips was comparably small to that
of the conventional mechanical process
due to the absence of the lattice heating
effect in the femtosecond-laser ablation
process.
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Fig. 7. SEM image of SiC chip diced from
100-µm-thick SiC bare wafer by the FSPL process.
Recently, SiC wafer-thinning technologies have been utilized in some commercially available SiC
devices to minimize substrate resistance [6]. Thus, we have also diced thin 4H-SiC wafers using the
developed FSPL process. Fig. 7 shows a SEM image of a SiC chip diced from a three-inch,
100-µm-thick SiC wafer. The developed dicing technology can also be utilized with such thin SiC
wafers.
Summary
We demonstrated the high-speed SiC dicing technology utilized FSPLs. Kerf loss can be neglected
in the FSPL dicing, and therefore the wafer area will be utilized more effectively. The residual lattice
strain in the FSPL-diced SiC chips was evaluated by microscopic Raman spectroscopy, and was
comparably small to that of the conventional mechanical process due to the femtosecond laser
ablation properties with no heat damage to the surrounding SiC. The effective laser scan speed on the
SiC wafer surfaces was 33 mm/s, which is one order of magnitude higher than that of conventional
mechanical dicing. In addition, unlike the mechanical dicing process, the optical dicing process has no
trade-off limitation between throughput time and cutting quality. Therefore further increments of the
laser scan speed for productivity improvement could be made possible by increasing the laser output
power in the future.
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High-Speed Dicing of SiC Wafers by Femtosecond Pulsed Laser
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