Guru Gobind Singh Foundation’s
Guru Gobind Singh College Of Engineering & Research Center,
Nashik
ELECTRICAL ENGG.
DEPARTMENT
A
PRESENTATION ON
DIGITAL CIRCUIT
PRESENTED BY:- PROF. R. V. PATEL
CONTENT
1
• Booleans algebra
2
• Karnaugh map
3
• SOP and POS form
4
• Reduction of Boolean expressions by K-map
5
• Half and Full adder
6
• Half and Full adder
7
8
COMBINATIONAL CIRCUIT
Defined as the time independent circuits which do not depends upon previous
inputs to generate any output are termed as combinational circuits.
• Features1. Output depends only upon present input.
2. Speed is fast.
3. Easy to design.
4. There is no feedback between input and output.
5. These circuits do not have any memory element.
6. Elementary building blocks: Logic gates
SEQUENTIAL CIRCUITS
Sequential circuits are those which are dependent on clock cycles and
depends on present as well as past inputs to generate any output.
• Features1. output depends upon present as well as past input.
2. Speed is slow.
3. Complex to design.
4. Elementary building blocks: Flip-flops
5. These circuits have memory element.
6. There exists a feedback path between input and output.
BOOLEAN ALGEBRA
• The algebraic method used to simplify digital circuits applies a number of
Boolean laws to successively simplify complex equations.
• Boolean algebra was invented by George Boole in 1854.
• Boolean Algebra is the algebra of logic that deals with binary variables
and logic operations.
• Boolean Variable is a symbol, usually an alphabet used to represent a
logical quantity.
• Boolean Function consists of binary variable, constants 0 & 1, logic
operation symbols, parenthesis and equal to operator.
• Boolean operator are AND, NOT and OR
RULE IN BOOLEAN ALGEBRA
• Variable used can have only two values. Binary 1 for HIGH and Binary 0
for LOW.
• Complement of a variable is represented by an overbar (-). Thus,
complement of variable B is represented as B’. Thus if B = 0 then B’ = 1
and B = 1 then B’ = 0.
• ORing of the variables is represented by a plus (+) sign between them. For
example ORing of A, B, C is represented as A + B + C.
• Logical ANDing of the two or more variable is represented by writing a
dot (.) between them such as A.B.C. Sometime the dot may be omitted like
ABC.
FUNDAMENTAL OPERATORS IN
BOOLEAN ALGEBRA
NOT
• NOT: unary operator that complements represented as A’,~A .
• AND: binary operator which performs logical multiplication
i.e. A ANDed with B would be represented as AB or A.B
• OR: binary operator which performs logical addition
i.e. A ORed with B would be represented as A+B
A
A’
0
1
1
0
A
0
0
1
1
AND
B A.B
0
0
1
0
0
0
1
1
A
0
0
1
1
OR
B A+B
0
0
1
1
0
1
1
1
BOOLEAN LAWS
OR
AND
Identity
A+0=A
A. 1 = A
Complement
A + A’ = 1
A. A’ = 0
Commutative
A+B=B+A
A. B = B. A
Associative
A + (B + C) = (A + B) + C
A. (B. C) = (A. B). C
Distributive
A. (B + C) = A. B + A. C
A + (B. C) = (A + B). (A + C)
Null Element
A+1=1
A. 0 = 0
Involution
(A’)’ = A
Indempotency
A+A=A
A. A = A
Absorption
A + (A. B) = A
A. (A + B) = A
3rd Distributive
A + A’. B = A + B
DEMORGAN'S THEOREMS
• DeMorgan's theorems provide mathematical verification of the equivalency
of the NAND and negative-OR gates and the equivalency of the NOR and
negative-AND gates.
• One of DeMorgan's theorems is stated as follows:
“The complement of a product of variables is equal to the sum of
the complements of the variables.”
• Stated another way,
“The complement of two or more ANDed variables is equivalent to
the OR of the complements of the individual variables.”
• The formula for expressing this theorem for two variables is
(A.B)’ =A’ + B’
DEMORGAN'S THEOREMS
• DeMorgan's second theorem is stated as follows:
“The complement of a sum of variables is equal to the product of
the complements of the variables.”
•
Stated another way,
“The complement of two or more ORed variables is equivalent to
the AND of the complements of the individual variables.”
• The formula for expressing this theorem for two variables is
(A+B)’=A’. B’
BOOLEAN EXPRESSION
REPRESENTATION
• Boolean expression can be represented by either
1. Sum of Product( SOP form)
Adding or Summing of two or more product terms using a Boolean addition
operation.
2. Product of Sum (POS form)
Product of two or more Adding or Summing terms using a Boolean addition
operation.
SUM OF PRODUCT( SOP FORM)
• Adding or Summing of two or more product terms using a Boolean addition
operation.
• The sum-of-products (SOP) form is a method (or form) of simplifying the
Boolean expressions of logic gates.
• The product terms are also known as min-terms.
• Here the product terms are defined by using the AND operation and the sum
term is defined by using OR operation.
Examples:- Suppose,
First product term=ABC,
Second product term=DEF
So, SOP can be represented as,
A.B.C+D.E.F
SUM OF PRODUCT( SOP FORM)
A.B.C+D.E.F
SUM OF PRODUCT( SOP FORM)
• Construct SOP from a Truth Table:
 These rules for the SOP circuits are given below:
1. A circuit for a truth table with N input columns can use AND gates with N
inputs, and each row in the truth table with a ‘1’ in the output column
requires one N-input AND gate.
2. Inputs to the AND gate are inverted if the input shows a ‘0’ on the row, and
not inverted if the input shows a ‘1’ on the row.
3. All AND terms are connected to an M-input OR gate, where M is the
number of ‘1’ output rows.
4. The output of the OR gate is the function output.
SUM OF PRODUCT( SOP FORM)
• For an Example
SUM OF PRODUCT( SOP FORM)
• Converting Truth Table into SOP Expression
Example: - Convert following truth table into SOP
expression,
A
B
C
X
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
0
1
1
1
1
SUM OF PRODUCT( SOP FORM)
• Solution: • First, identify each row that contains
a one as the output.
• Now we need to make a product for
each of these rows.
• The product that outputs a one for
the first row where A=0, B=0, and
C=1 must invert A and B in order to
have a product of 1·1·1 = 1.
A B C X
Combination
0 0 0
0
0 0 1
1
0 1 0
0
0 1 1
0
1 0 0
1
A = 1, B = 0, and C = 0
1 0 1
1
A = 1, B = 0, and C = 1
1 1 0
0
1 1 1
1
A = 0, B = 0, and C = 1
A = 1, B = 1, and C = 1
SUM OF PRODUCT( SOP FORM)
• Solution: Therefore, our first product is:
A’B’C……………1st Product
Similarly,
AB’C’……………2nd Product
AB’C…………….3rd Product
ABC…………….4th Product
OR'ing all of these products together gives us our SOP
expression.
X=A’B’C+AB’C’+AB’C+ABC
A B C X
Combination
0 0 0
0
0 0 1
1
0 1 0
0
0 1 1
0
1 0 0
1
A = 1, B = 0, and C = 0
1 0 1
1
A = 1, B = 0, and C = 1
1 1 0
0
1 1 1
1
A = 0, B = 0, and C = 1
A = 1, B = 1, and C = 1
SUM OF PRODUCT( SOP FORM)
• Converting a SOP into Truth Table,
• Example: - Convert the SOP expression into a truth table.
X = A’BC’ + AB’ + ABC
Solution:Given Equation,
X = A’BC’ + AB’ + ABC
The first step is to determine where each product equals a one.
A’BC’ = 1 when A’=1, B=1, and C’=1, which means when A=0, B=1, and C=0.
AB’ = 1 when A=1, B’=1, and C=1 or 0, which means when A=1, B=0, and C=0
or 1, i.e., two rows will have a one output due to this term.
ABC = 1 when A=1, B=1, and C=1.
SUM OF PRODUCT( SOP FORM)
Given Equation, X = A’BC’ + AB’ + ABC
The first step is to determine where each
product equals a one.
A’BC’ = 1 when A’=1, B=1, and C’=1, which
means when A=0, B=1, and C=0.
AB’ = 1 when A=1, B’=1, and C=1 or 0, which
means when A=1, B=0, and C=0 or 1, i.e., two
rows will have a one output due to this term.
ABC = 1 when A=1, B=1, and C=1.
A
B
C
X
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
0
1
1
1
1
O/P
A’BC’
AB’
ABC
PRODUCT OF SUM( POS FORM)
• All these sum terms are ANDed (multiplied) together to get the product-ofsum form. This form is exactly opposite to the SOP form. So this can also be
said as “Dual of SOP form”.
• Here the sum terms are defined by using the OR operation and the product
term is defined by using AND operation.
• Examples: First Sum term=A+B+C
Second Sum term=D+E+F
So, POS can be represented as,
(A+B+C)*(D+E+F)
PRODUCT OF SUM( POS FORM)
• Construct POS from a Truth Table:
 Unlike the SOP the POS also has certain rules which are given below.
1.A circuit for a truth table with N input columns can use OR gates with N
inputs, and each row in the truth table with a ‘0’ in the output column
requires one N-input OR gate.
2.Inputs to the OR gate are inverted if the input shows a ‘1’ on the row, and
not inverted if the input shows a ‘0’ on the row.
3.All OR terms are connected to an M-input AND gate, where M is the
number of ‘1’ output rows.
4.The output of the AND gate is the function output.
PRODUCT OF SUM( POS FORM)
K-MAP (KARNAUGH MAP)
•
•
•
•
•
Simplification of Boolean functions using Boolean laws are time consuming.
We have to re-write the simplified expressions after each step.
To overcome this difficulty, Karnaugh introduced.
It is a graphical method, which consists of 2 n cells for ‘n’ variables.
The map is a simple table containing 1s and 0s that can express a truth table
or complex Boolean expression describing the operation of a digital circuit.
K-MAP (KARNAUGH MAP)
• Constructing Karnaugh Maps
• The shape and size of the map is dependent on the number of binary inputs
in the circuit
• The map needs one cell for each possible binary word applied to the inputs.
 2-Variable K-MAP: 2 input circuits with inputs A and B require maps with 2 2 = 4 cells
Power
21
20
Decimal
2
0
A
B
Decimal No.
1
0
0
0
0
0
0
1
1
0=A’
1
0
1
1
0
2
1=A
2
1
0
1
1
3
B’
B
0
1
2
3
K-MAP (KARNAUGH MAP)
 3-Variable K-MAP: 3 input circuits with inputs A, B & C require.
 23 = 8 cells
 4-Variable K-MAP: 4 input circuits with inputs A, B, C & D require.
 24 = 16 cells
B’C’
0=A’
1=A
A’B’
A’B
AB
AB’
B’C
BC
BC’
0
1
3
2
4
5
7
6
C’D’
C’D
CD
CD’
K-MAP (KARNAUGH MAP)
 K-MAP Grouping:  It can be simplify by grouping in three ways
1. Pair Adjacent (Group of TWO)
2. Quad Adjacent (Group of FOUR)
3. Octet Adjacent (Group of EIGHT)
K-MAP (KARNAUGH MAP)
K-MAP (KARNAUGH MAP)
K-MAP (KARNAUGH MAP)
1. )
K-MAP (KARNAUGH MAP)
 Minterms
 A minterm is defined as the product term of n variables, in which each of the
n variables will appear once either in its complemented or un-complemented
form.
 The min term is denoted as “mi” where i is in the range of 0 ≤ i < 2ⁿ.
 A variable is in complemented form, if its value is assigned to 0, and the
variable is un-complimented form, if its value is assigned to 1.
K-MAP (KARNAUGH MAP)
• The procedure for placing a minterm in a K-map:
1) Identify the minterm (product term) term to be mapped.
2) Write the corresponding binary numeric value.
3) Use binary value as an address to place a 1 in the K-map
4) Repeat steps for other minterms
K-MAP (KARNAUGH MAP)
 Reduction of boolean expression using k map in SOP form: o Minterm Solution of K Map
 The following are the steps to obtain simplified minterm solution using Kmap.
Step 1: Initiate: - Express the given expression in its canonical form
Step 2: Populate the K-map: - Enter the value of ‘one’ for each productterm into the K-map cell, while filling others with zeros.
Step 3: Form Groups
Step 4: Obtain Boolean Expression for Each Group
Step 5: Obtain Boolean Expression for the Output
K-MAP (KARNAUGH MAP)
Examples: - Minimize the following Boolean expression in SOP form using
K-MAP,
Y=A’B’+A’B+AB
K-MAP (KARNAUGH MAP)
K-MAP (KARNAUGH MAP)
 Max terms
 A max term is defined as the product of n variables, within the range of 0 ≤
i < 2ⁿ.
 The max term is denoted as “Mi”.
 In max term, each variable is complimented, if its value is assigned to 1, and
each variable is un-complimented if its value is assigned to 0.
K-MAP (KARNAUGH MAP)
 The procedure for placing a maxterm in the K-map
is:
 Identify the Sum term to be mapped.
 Write corresponding binary numeric value.
 Form the complement
 Use the complement as an address to place a 0 in
the K-map
 Repeat for other maxterms
K-MAP (KARNAUGH MAP)
 Maxterm Solution of K-Map
 To find the simplified maxterm solution using K-map is the same as to find
for the minterm solution.
 There are some minor changes in the maxterm solution, which are as
follows:
1) We will populate the K-map by entering the value of 0 to each sum-term
into the K-map cell and fill the remaining cells with one's.
2) We will make the groups of 'zeros' not for 'ones'.
3) Now, we will define the boolean expressions for each group as sum-terms.
4) At last, to find the simplified boolean expression in the POS form, we will
combine the sum-terms of all individual groups.
K-MAP (KARNAUGH MAP)
Examples 1: - Minimize the following Boolean expression in SOP form
using K-MAP, Y=(A’+B’).(A’+B).(A+B)
Solution:Step 1: Initiate: - Express the given expression in its canonical form
Y=(A’+B’).(A’+B).(A+B)
Step 2: Populate the K-map:- No. of variable=2 (i.e A & B)
22=4 (Draw 4 cell K-MAP)
K-MAP (KARNAUGH MAP)
K-MAP (KARNAUGH MAP)





Terminology for Minterms
Σ (sigma) indicates sum and lower case “m” indicates minterms.
Σm indicates sum of minterms.
The following example is revisited to illustrate our point.
Instead of a Boolean equation description of unsimplified logic, we list the
minterms.
f(A,B,C,D) = Σ m(1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 13, 15) or
f(A,B,C,D) = Σ(m1,m2,m3,m4,m5,m7,m8,m9,m11,m12,m13,m15)
 This is certainly a compact means of describing a list of minterms or cells in
a K-map.
K-MAP (KARNAUGH MAP)
Example 1: Consider Y = f(A, B, C) = Σ m (2, 3, 4, 6)
Solution: - The Karnaugh map for the given logic expression is drawn as
shown below:
The simplified expression Y = A’B + AC’
K-MAP (KARNAUGH MAP)
Example 2: Simplify Y = f(A, B, C, D) = Σ m (1, 2, 3, 6, 8, 9, 10, 12, 13, 14).
Solution: -
The simplified Boolean equation is Y = A’B’D + AC’ + CD’.
K-MAP (KARNAUGH MAP)
Example 3: Simplify Y = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13)
Example 4: Minimize the following Boolean expression using K-map and
realize it using the basic gates. Y=∑m (1, 3, 5, 9, 11, 13)
Solution: The simplified equation is Y = B’D+C’D
= D(B’+C’)
K-MAP (KARNAUGH MAP)
 Don’t Care Conditions
 In some digital systems, certain inputs conditions never occur.
 The output for the invalid inputs is not defined and it is indicated by an “X”
in the truth table.
 The “X” is called a don’t care condition.
 “X” can be considered to be either 0 (for POS form) or 1 (for SOP form),
whichever produces a simpler logic circuit.
K-MAP (KARNAUGH MAP)
Example-1: Simplify Truth Table with Don’t Care Conditions
Solution:From the truth table, we have Y = Σ m(1, 3) + d(5, 7).
Consider simplification of the K-map shown :
The simplified equation is Y = C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
X
0
X
K-MAP (KARNAUGH MAP)
Example-1: Simplify Truth Table with Don’t Care Conditions
Solution:From the truth table, we have Y = Σ m(1, 3) + d(5, 7).
Consider simplification of the K-map shown :
The simplified equation is Y = C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
X
0
X
K-MAP (KARNAUGH MAP)
• Exercise Example
Example-2: Simplify the expression given below using K-map.
Y=∑m (1, 3. 7, 11, 15) + d (0, 2)
K-MAP (KARNAUGH MAP)
 Maxterms
 Product is indicated by the Greek “Π” (pi), and upper case “M” indicates
maxterms i.e “ΠM” indicates product of maxterms.
 The Boolean equation description of unsimplified logic, is replaced by a list
of maxterms.
 f(A,B,C,D) = Π M(2, 6, 8, 9, 10, 11, 14) or
 f(A,B,C,D) = Π(M2, M6, M8, M9, M10, M11, M14)
 Once again, the numbers indicate K-map cell address locations.
 For maxterms this is the location of 0’s.
 A Product-OF-Sums solution is completed in the usual manner.
K-MAP (KARNAUGH MAP)
Example: - Minimize the following Boolean expression
using K-map and realize it using the basic gates in POS.
Solution:
In compact form Y = f(A, B, C) = πM(0, 1, 2)
Consider simplification of the K-map shown :
Simplified expression as Y = A . B
Logical Diagram:
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
K-MAP (KARNAUGH MAP)
Example: - Reduce the following function using Karnaugh map
technique f(A, B, C, D) = πM(0, 2, 4, 10, 11, 14, 15)
Solution:
The simplified logic equation in POS form is
Y = (A + B + D). (A + C + D). (A’ + C’)
ADDER
 Adder
 It is a type of digital circuit that performs the operation of additions of two
number.
 It is mainly designed for the addition of binary number, but they can be
used in various other applications like binary code decimal, address
decoding, table index calculation, etc.
 There are two types of Adder. One is Half Adder, and another one is
known as Full Adder.
ADDER
 Half Adder:
 It is a combinational circuit that performs the addition of two bits, this
circuit needs two binary inputs and two binary outputs.
 Inputs are named as A and B, and the outputs are named as Sum (S) and
Carry (C).
 The Sum is X-OR of the input A and B.
 Carry is AND of the input A and B.
 With the help of half adder, one can design a circuit that is capable of
performing simple addition with the help of logic gates.
ADDER
 The truth table of the half adder is shown.
 The Half Adder Circuit is shown below.
Inputs
A B
0
0
0
1
1
0
1
1
Outputs
Sum Carry
0
0
1
0
1
0
0
1
ADDER
 Full Adder
 The full adder is a little more difficult to implement than a half adder.
 Full Adder is a combinational circuit that performs the addition of three
bits (two significant bits and previous carry).
 The two inputs are A and B, and the third input is a carry input CIN.
 The output carry is designated as COUT, and the normal output is designated
as S.
 The output S is an EX – OR between the input A and the half adder SUM
output B.
 The COUT will be true only if any of the two inputs out of the three are
HIGH or at logic 1.
ADDER
 The truth table of the Full Adder
Circuit is shown below.
A
0
0
0
0
1
1
1
1
Inputs
B
CIN
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Outputs
COUT
S
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
 The Full adder circuit diagram is
shown below.
Thank You