# Spring 2020 DIC Assignment 1

```ELE310: Design with Integrated Circuits
Assignment I
Due Date: 1rst May 2021
Carefully read the following questions and attempt answering them in a separate document using the attached
cover page at the end of this document. The submission deadline for this assignment is Saturday, 1rst May 2021.
The marking scheme of the questions is as follows,
Question No.
1
2
3
4
5(a)
5(b)
CLO
CLO 3
CLO 1
CLO 3
CLO 1
CLO 3
CLO 1
Marks
2
2
2
2
1
1
Total: 10
Question 1: Using two 74192 ICs decade counters, two 7447 ICs 7-segment decoders, two 7- segment displays
and negative-edge triggered D-flipflop. Design a box counting system that works with a conveyor belt.
The system should stop the conveyor belt when the count of boxes reaches 23 boxes. A manual push
button should reset the count and restart the working process of the conveyor belt.
Question 2: A 4-bit SAR-type ADC can convert analog samples of up to 6V to digital form. Explain the working
process behind the conversion of a 4V analog sample into its digital form using the gin SAR-type ADC
configuration.
Question 3: Design a 4-bit DAC with a maximum output of 4V. Use a reference voltage of 12V.
Question 4: Using the designed DAC in the previous question, find the output analog voltage if the digital input is
1001.
Question 5: (a) Design a single-supply amplifier with a gain of -15 that can amplify signals with frequencies
between 10kHz to 25 kHz and a supply voltage of 7V. The input impedance of the amplifier must be at
least 2 M�. (b) Further then, draw the output waveform of the output signal if the input signal is 0.25 Sin
70000t.
P.S. See next page for the cover page to be used for this assignment
ELE310: Design with Integrated Circuits
Assignment I
Due Date: 1rst May 2021
Ajman University
College of Engineering and IT
Department of Electrical and Computer Engineering
ELE310: Design with Integrated Circuits
Assignment No. 1
Name: Mustafa Dhia Ahmed Al-Ani
Question No.
1
2
3
4
5(a)
5(b)
ID: 201811107
Course Learning Outcome
Mark Obtained
CLO 3
CLO 1
CLO 3
CLO 1
CLO 3
CLO 1