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Instructor: Jan Rabaey
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Introduction to digital integrated circuit design
engineering
 Key concepts needed to be a good digital IC designer
 Design creativity

Models that allow reasoning about circuit behavior
 Allow analysis and optimization of the circuit’s performance,
power, cost, etc.
 Understanding circuit behavior is key to making sure it will
actually work

Teach you how to make sure your circuit works
 Do you want your transistor to be the one that screws up a 1
billion transistor chip?
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Understanding, designing, and optimizing
digital circuits for various quality metrics:
 Performance (speed)
 Power dissipation
 Cost
 Reliability
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CMOS devices and manufacturing technology
 CMOS gates
 Combinational and sequential circuits
 Arithmetic building blocks
 Interconnect
 Memories
 Propagation delay, noise margins, power
 Timing and clocking
 Design methodologies

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Instructor
 Prof. Jan Rabaey
563 Cory Hall, 643-3986, jan@eecs
Office hours: We 4:00pm-5:30pm
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TAs:
 Stanley (Yuan-Shih) Chen, yschen@eecs (OH: Th. 12-1pm)
 Nam-Seog Kim, namseog@eecs (OH: Th. 5-6pm)
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Reader:
 TBD
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Web page:
http://bwrc.eecs.berkeley.edu/Classes/IcDesign/ee141_s10/
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 Discussion sessions
 Th 11am-noon, Stanley (TBD) (proposed change)
 Th 4-5pm, Namseog (521 Cory)
 Same material in both sessions!
 Labs (353 Cory)
 Mo 1-4pm (Stanley)
 Tu 2-5pm (Namseog)
 We 11am-2pm (Stanley/Namseog)
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Please choose one lab session and stick with it!
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Assignment due
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 9-10
assignments
 One design project (with multiple phases)
 Labs: 5 software
 2 midterms, 1 final
 Midterm 1: Fr Febr 19 (TBD)
 Midterm 2: We April 7 (TBD)
 Final: Tu May 11, 11:39am-2:30pm (TBD)
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Please use the newsgroup for asking questions
(news://news.csua.berkeley.edu/ucb.class.ee141)
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Can work together on homework
 But you must turn in your own solution
Lab reports due 1 week after the lab session
 Project is done in pairs
 No late assignments
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 Solutions available shortly after due date/time
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Don’t even think about cheating!
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 Homeworks:
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10%
 Labs:
10%
 Projects: 20%
 Midterms: 30%
 Final: 30%
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Textbook: “Digital Integrated Circuits – A
Design Perspective”, 2nd ed, by J. Rabaey, A.
Chandrakasan, B. Nikolic
 Class notes: Web page
 Lab Reader: Web page
 Check web page for the availability of tools
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The sole source of information

http://bwrc.eecs.berkeley.edu/icdesign/eecs141_s10
(Also via department web-site)

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Class and lecture notes
Assignments and solutions
Lab and project information
Exams
Many other goodies …
Print only what you need: Save a tree!
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All lectures streamed life
 Also available in archive

 Check: http://webcast.berkeley.edu/courses.php

However: Live experience has advantages
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 Cadence
 Widely used in industry
 Online tutorials and documentation
 HSPICE
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and Spectre for simulation
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 Assignment
1: Getting SPICE to work –
see web-page
 Due next Friday, January 29, 5pm
 NO discussion sessions or labs this
week.
 First discussion sessions in Week 2
 First software lab in Week 3
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 Digital
Integrated Circuit Design: The
Past, The Present and The Future
 What made Digital IC design what it is
today
 Why is designing digital ICs different today
than it was before?
 Will it change in the future?
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The Babbage
Difference Engine
 25,000 parts
 cost: £17,470
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First transistor
Bell Labs, 1948
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Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
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Intel, 1971.
2,300 transistors (12mm2)
740 KHz operation
(10µm PMOS technology)
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Intel, 2005.
125,000,000 transistors
(112mm2)
3.8 GHz operation
(90nm CMOS technology)
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Dual Core
Intel, 2006.
291,000,000 transistors
(143mm2)
3 GHz operation
(65nm CMOS technology)
Cache
Memory
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Cache
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Doubles every 2 years
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22 nm 364 Mbyte SRAM > 2.9 Billion Transistors 3rd genera=on high-­‐k + metal gate 25
 In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
 He made a prediction that semiconductor
technology will double its effectiveness
every 18 months
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Electronics, April 19, 1965.
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Has been doubling
every 2 years,
but is now slowing down
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100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086 386
8085
8080
8008
1 4004
10
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
 Did
this really happen?
Courtesy, Intel
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Has been > doubling
every 2 years
Has to stay
~constant
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Power Density (W/cm2)
10000
Sun’s Surface
1000
100
Rocket Nozzle
Nuclear Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
S. Borkar
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high for cost-effective cooling
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*Pictures from http://www.tomshardware.com/2001/09/17/hot_spot/
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Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …

 How to design chips with more and more functions?
 Design engineering population does not double every
two years…

Hence, a need for more efficient design methods
 Exploit different levels of abstraction
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Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
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Lecture #1
∝ DSM
∝ 1/DSM
“Macroscopic Issues”
“Microscopic Problems”
• Complexity
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
?
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…and There’s a Lot of Them!
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10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
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1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
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 Introduce
basic metrics for design of
integrated circuits – how to measure
cost, delay, power, etc.
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