Project Report on
Adiabatic Technique for Power Efficient
Logic Circuit Design
Submitted by
Akash Metre
Akash N
Sameer S Durgoji
(181EC103)
(181EC203)
(181EC240)
V SEM B.Tech
Under the guidance of
Dr.Nikhil K S
Dept of ECE, NITK Surathkal
in partial fulfillment for the award of the degree
Of
Bachelor of Technology
in
Electronics and Communication
at
Department of Electronics and Communication
National Institute of Technology Karnataka, Surathkal.
December 2020
I. Abstract:
In VLSI Design Power consumption has got a lot of significance .Nowadays the demand for low
power consuming devices is increasing .As our conventional CMOS circuits consume a lot of
power and the energy is wasted unnecessarily .So if Adiabatic techniques are included along with
these conventional CMOS circuits we would be able to reduce power consumption as well as
recycle energy which used to get wasted previously.
II. Introduction:
A significant amount of power as well as energy can be saved by using adiabatic techniques. In this
technique, some of the energy stored at the load capacitance can be recycled instead of dissipating,
and also reduce the power dissipation in the circuit. Adiabatic logic provides a system to recycle the
energy stored in the capacitors, rather than the conventional manner to discharge the power toward
the lower potential & waste it.
In analysis, three adiabatic logic families, PFAL (Positive Feedback Adiabatic Logic), 2PASCL
(Two Phase Clocked Adiabatic Static CMOS Logic) and 2PADCL (Two Phase Clocked Adiabatic
Dynamic CMOS Logic) are compared with conventional CMOS logic
for inverter ,NAND and NOR circuits. But the adiabatic technique is highly dependent on parameter
variation. With the help of MAGIC and NGSPICE simulations, the energy consumption is analyzed
by variation of parameter.
III. Problem:
In the CMOS logic the switching event of circuits causes an energy transfer from the power supply
to the output node or from the output node to the ground. During the 0 to VDD transition of the
output, the capacitor draws a charge of CL*VDD and thus an energy of CL*VDD^2 . At the end of
the transition, only half of this energy is stored on the load and the other half is dissipated through
the PMOS network. During the subsequent VDD to 0 transition, this energy stored is dissipated. To
reduce this power dissipation, we can either reduce the frequency of the transition, or reduce the
load capacitance, or reduce the voltage swing. Yet in all these cases, the energy drawn from the
power supply is used only once before being dissipated.
Fig 1. Conventional CMOS switching
https://scialert.net/fulltext/?doi=itj.2007.325.331
IV. Adiabatic Logic Families:
We used three types of adiabatic logic circuits PFAL, 2PASCL and 2PADCL.
1. PFAL (Positive Feedback Adiabatic Logic):
PFAL is one of the methods of adiabatic logic that is robust against parametric changes. It's a dual
track system as well. This offers strong noise immunity because there is no degradation of the logic.
It is evident from figure 2 that there is a latch of two NMOS and two PMOS transistors that
prohibits the input points from being logically degraded.
Fig 2. PFAL Adiabatic logic
https://scialert.net/fulltext/?doi=itj.2007.325.331
Initially, input ‘in’ is high and input ‘/in’ is low. When power clock (pwr) rises from zero to VDD,
output ‘out’ remains ground level. Output ‘/out’ follows the pwr. When pwr reaches at VDD,
outputs ‘out’ and ‘/out’ hold logic value zero and VDD respectively. This output values can be used
for the next stage as an inputs. Now pwr falls from VDD to zero, ‘/out’ returns its energy to pwr
hence delivered charge is recovered. PFAL uses four phase clocking rule to efficiently recover the
charge delivered by pwr.
2. 2PASCL (Two Phase Clocked Adiabatic Static CMOS Logic):
2PASCL logic consists of two pulsed power supplies called as power clocks. In this one clock is in
phase while the other is inverted. These power clocks will replace the constant power supply. It is a
diode based adiabatic logic.
Fig 3. 2PASCL logic circuit
http://ijarece.org/wp-content/uploads/2013/06/642-645.pdf
A method for reducing energy dissipation in 2PASCL involves the design of a charging path
without diodes. In this case, during charging, current flows only through the transistor. Thus,
the 2PASCL circuit is different from other diode- based adiabatic circuits, in which current flows
through both the diode and the transistor.
3. 2PADCL(Two Phase Clocked Adiabatic Dynamic CMOS Logic)
The 2PADCL inverter is a diode based adiabatic logic. The main difference between 2PASCL AND
2PADCL is the output voltage drop which has the effect of diode-drop. The output voltage of
2PADCL is 2Vd where Vd is the forward voltage drop. On the other hand that of PASCL is Vd
only. Therefore the output noise margin of 2PASCL is improved compared to 2PADCL .
Fig 4. 2PADCL logic circuit
http://ijarece.org/wp-content/uploads/2013/06/642-645.pdf
The power dissipation of 2PASCL is also improved because the charge path is only through PMOS
tree during charge transition.
V. Simulation Results:
The Inverter, NAND gate and the NOR gate were implemented using MAGIC tool in 180nm
technology. The spice netlists were obtained from it. The output wave forms were obtained by
running these .spice files in NG Spice. The obtained simulation results are as follows:
Inverter:
CMOS :
2PASCL:
Fig 5. CMOS Inverter Layout
Fig 9. 2PASCL Inverter Layout
Fig 6. CMOS Inverter Output at 100kHz
Fig 10. 2PASCL Inverter Output at 10kHz
2PADCL:
PFAL:
Fig 7. PFAL Inverter Layout
Fig 11. 2PADCL Inveter Gate Layout
Fig 8. PFAL Inverter Output at 10kHz
Fig 12. 2PADCL Inverter Output at 1kHz
NAND Gate:
CMOS:
2PASCL:
Fig 13. CMOS NAND Gate Layout
Fig 17. 2PASCL NAND Gate Layout
Fig 14. CMOS NAND Gate Output at 10kHz
Fig 18. 2PASCL NAND Output at 10kHz
PFAL:
2PADCL:
Fig 15. PFAL NAND Gate Layout
Fig 19. 2PADCL NAND Gate Layout
Fig 16. PFAL NAND Output at 10kHz
Fig 20. 2PADCL NAND Output at 100Hz
NOR Gate:
CMOS:
2PASCL:
Fig 21. CMOS NOR Gate Layout
Fig 25. 2PASCL NOR Gate Layout
Fig 22. CMOS NOR Output at 10kHz
Fig 26. 2PASCL NOR Output at 10kHz
PFAL:
2PADCL:
Fig 23. PFAL NOR Gate Layout
Fig 27. 2PADCL NOR Gate Layout
Fig 24. PFAL NOR Output at 10kHz
Fig 28. 2PADCL NOR Output at 100Hz
VI. Results and Observations:
Power consumption of various logic families is compared for the following parameters:
1.
2.
3.
Transition Frequency Variation
Load Capacitance Variation
Supply Voltage Variation
1. Transition Frequency Variation:
For the transition frequency variation, the load capacitance and the supply voltage are kept constant.
Here we observed that when the transition frequency is low, the gap between CMOS and the
adiabatic logic is small. However over a large range of frequencies, adiabatic logic shows large
power savings. We observed that as the frequency is increased beyond a certain value, the
behaviour is no more adiabatic in nature. The readings obtained by the frequency variation are as
follows:
Fig 29. Power Consumption per Cycle versus Frequency for an Inverter at Vdd = 5V and Load Capacitance = 50fF
Fig 30. Power Consumption per Cycle versus Frequency for a NAND gate at Vdd = 5V and Load Capacitance = 100fF
Fig 31. Power Consumption per Cycle versus Frequency for a NOR gate at Vdd = 5V and Load Capacitance = 1pF
2. Load Capacitance Variation:
For the load capacitance variation, the transition frequency and the supply voltage are kept constant.
We varied the load capacitance over a wide range and observed that 2PASCL logic shows better
energy savings than other adiabatic logic gates. The readings obtained by the load capacitance
variations are as follows:
Fig 32. Power Consumption per Cycle versus Load Capacitance for an Inverter at Vdd = 5V and Frequency = 1kHz
Fig 33. Power Consumption per Cycle versus Load Capacitance for a NAND gate at Vdd = 5V and Frequency = 500Hz
Fig 34. Power Consumption per Cycle versus Load Capacitance for a NOR gate at Vdd = 5V and Frequency = 1kHz
3. Supply Voltage Variation:
For the supply voltage variation, the transition frequency and the load capacitance are kept constant.
We observed the supply voltage variation over a range of 3.5V to 5 V. All the adiabatic logic
families show considerable power savings over the entire range. The readings obtained by varying
the supply voltage are as follows:
Fig 35. Power Consumption per Cycle versus Supply Voltage for an Inverter at Load Capacitance = 10fF and
Frequency = 100Hz
Fig 36. Power Consumption per Cycle versus Supply Voltage for a NAND gate at Load Capacitance = 10fF and
Frequency = 500Hz
Fig 37. Power Consumption per Cycle versus Supply Voltage for a NOR gate at Load Capacitance = 1fF and Frequency
= 100Hz
Table showing comparison of the power consumption by various logic families at VDD = 5V:
CMOS
PFAL
2PASCL
2PADCL
Inverter
at 10kHz, CL = 50fF
1.665e-9 W
Worst
7.965e-10 W
6.304e-10 W
Best
9.811e-10 W
NAND Gate
at 1kHz, CL = 100fF
3.9068e-10 W
Worst
1.6022e-10 W
9.8329e-11 W
Best
1.559e-10 W
NOR Gate
at 1kHz, CL = 1pF
2.12e-9 W
Worst
9.79e-10 W
4.421e-10 W
Best
1.706e-9 W
VII. Conclusion:
In this project, we implemented the Inverter, NAND, NOR gates of CMOS logic family and the
three adiabatic families (PFAL, 2PASCL, 2PADCL) to study the power efficient adiabatic logic for
digital circuits. The comparison of these logic families has been done for different parametric
variations, i.e. the transition frequency, the load capacitance and the voltage supply. The results
show that these adiabatic logic families have less power dissipation when compared to the
conventional CMOS logic family. However, these adiabatic logic families are affected by the
variation of the parameters. We have observed that the 2PASCL logic circuits consumed less
energy than the others in all the parametric variations. However, this logic does not have a perfect
VOL. This logic family can be used for low power logic design.
VIII. Future Work:
The 2PASCL logic may be designed at different technologies to further reduce the power
consumption and improve the voltage swing. The transition frequency range of operation can also
be improved. The noise margin of this logic can also be improved. Minimization of chip area can
also be done using various technologies.
References:
1. Anu Priya and Amrita Rai , “Adiabatic Technique for Power Efficient Logic Circuit Design”, IJECT, Vol.
5, 2014
2. A.Anitha, S. Rooban and M. Sujatha, “ Implementation of Energy Efficient gates using Adiabatic Logic
for Low Power Applications”, International Journal of Recent Technology and Engineering, Volume-8,
Issue-3, 2019
3. Abhishek Rai, Amit Shukla, Mayank Gupta, “ Study and Comparison of Two Phase Clocked Adiabatic
logic (2PASCL) for Low Power VLSI Applications: A Review ”, International Journal of Advanced
Research in Electronics and Communication Engineering (IJARECE) ,Volume 2, Issue 6, June 2013
4. Pragati Upadhyay, Vishal Moyal, “Implementation of Low Power Inverter using Adiabatic
Logic”,International Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering, Vol. 5, Issue 6, June 2016