LiU-ITN-TEK-A--19/012--SE
Design and implementation of a
high-speed PCI-Express bridge
Mandus Börjesson
Håkan Gerner
2019-06-05
Department of Science and Technology
Linköping University
SE- 6 0 1 7 4 No r r köping , Sw ed en
Institutionen för teknik och naturvetenskap
Linköpings universitet
6 0 1 7 4 No r r köping
LiU-ITN-TEK-A--19/012--SE
Design and implementation of a
high-speed PCI-Express bridge
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid
Linköpings universitet
Mandus Börjesson
Håkan Gerner
Handledare Qin-Zhong Ye
Examinator Adriana Serban
Norrköping 2019-06-05
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© Mandus Börjesson , Håkan Gerner
Abstract
This master thesis will cover the prestudy, hardware selection, design and implementation of a PCI Express bridge in the M.2 form factor. The thesis subject was proposed
by WISI Norden who wished to extend the functionality of their hardware using an M.2
module.
The bridge fits an M-Key M.2 slot and has the dimensions 80x22 mm. It is able to
communicate at speeds up to 8 Gb/s over PCI Express and 200 Mbit/s on any of the 20
LVDS/CMOS pins. The prestudy determined that an FPGA should be used and a Xilinx
Artix-7 device was chosen. A PCB was designed that hosts the FPGA as well as any power,
debugging and other required systems.
Associated proof-of-concept software was designed to verify that the bridge operated
as expected. The software proves that the bridge works but requires improvement before
the bridge can be used to translate sophisticated protocols.
The bridge works, with minor hardware modifications, as expected. It fulfills all design requirements set in the master thesis and the FPGA firmware uses a well-established
protocol, making further development easier.
Acknowledgments
We would like to thank the supervisor and examiner who took part in this Master thesis.
Your feedback has proven valuable throughout the entire thesis work, not only helping us
overcome obstacles but also helping us improve the quality of the final report.
We are grateful of our fellow students who helped motivate us, gave valuable input and were
always eager to discuss ways to overcome our engineering challenges.
We also wish to extend a special thank you to our mentor Jonas Åberg. You have shared your
many years of experience in hardware design and helped us boost the quality of the project
beyond our expectations.
ii
Contents
Abstract
i
Acknowledgments
ii
Contents
iii
List of Figures
v
List of Tables
1 Introduction
1.1 Aim . . . . . . . . . .
1.2 Background . . . . .
1.3 Research questions .
1.4 Design requirements
1.5 Delimitations . . . .
vii
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2 Prestudy
2.1 System sketch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Possible solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
6
3 Selection of hardware
3.1 FPGA selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Non-volatile memory selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Regulator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
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13
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4 System Description
4.1 M.2 Connector . . . . . . . . .
4.2 FPGA . . . . . . . . . . . . . .
4.3 Programming and debugging
4.4 Power management . . . . . .
4.5 External connectors . . . . . .
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16
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5 Hardware design and implementation
5.1 Stackup and design rules . . . . . . . . .
5.2 M.2 connector . . . . . . . . . . . . . . .
5.3 FPGA configuration banks . . . . . . . .
5.4 FPGA I/O banks . . . . . . . . . . . . .
5.5 FPGA transceivers and PCI Express nets
5.6 Power management . . . . . . . . . . . .
5.7 Programming and debugging interface
5.8 Decoupling . . . . . . . . . . . . . . . . .
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22
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6 Manufacturing
33
iii
6.1
6.2
6.3
Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly and soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tests and inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Software
7.1 EEPROM memory verification
7.2 Flash memory interfacing . . .
7.3 FPGA firmware . . . . . . . . .
7.4 Platform application . . . . . .
33
33
33
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37
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8 Results
8.1 PCB Layout . . . . . . . . . . . . . .
8.2 Bridge performance . . . . . . . . . .
8.3 Summary of hardware modifications
8.4 Software design . . . . . . . . . . . .
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44
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9 Discussion and conclusion
9.1 Design requirements and research questions . . . . . . . . . . . . . . . . . . . .
9.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
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Bibliography
51
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iv
List of Figures
2.1
2.2
2.3
2.4
High level sketch of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System sketch of the solution using a CPU with native PCI Express support. . . . .
System sketch of the solution when using a CPU without native support for PCI
Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System sketch of the solution when using a FPGA. . . . . . . . . . . . . . . . . . . .
7
8
3.1
Total accumulated price for N number of units, assuming 100 units/year. . . . . .
12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
System layout on the M.2 module. . . . . . . . . .
M.2 connector system connections. . . . . . . . . .
FPGA system connections. . . . . . . . . . . . . . .
Programming and debugging system connections.
Power management system connections. . . . . .
Power hierarchy option considered in the design.
M.2 connector system connections. . . . . . . . . .
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5.1
5.2
23
5.4
5.5
5.6
5.7
5.8
5.9
Illustration of design rules used during layout. . . . . . . . . . . . . . . . . . . . . .
Open-drain logic level conversion. HV indicates High (3.3 V) logic level, LV indicates low (1.8 V) logic level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout surrounding the M.2 connector on the top layer of the PCB. Notice the
fencing and return path vias as well as the ground plane (yellow) on the layer
below the PCI Express lanes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fanout of the SPI and JTAG nets (highlighted) under the Artix-7. . . . . . . . . . .
Power-on sequencing using RC networks. . . . . . . . . . . . . . . . . . . . . . . . .
I/O voltage sequencing and selectable I/O voltage solution. . . . . . . . . . . . . .
Characteristic change of capacitance according to DC-voltage. . . . . . . . . . . . .
Artix-7 FPGA power pin mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming and debugging interface with related components marked. . . . . .
25
25
27
28
29
30
31
6.1
6.2
6.3
Load switch schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference clock differential signal measured on the bridge. . . . . . . . . . . . . . .
PCI Express link lists the capabilities of the bridge. . . . . . . . . . . . . . . . . . . .
34
36
36
7.1
7.2
38
7.3
7.4
7.5
7.6
7.7
Console output after a successful write to the EEPROM. . . . . . . . . . . . . . . . .
Enumeration of the SMBus of the bridge. Notice the SMBus-SPI bridge at ’0x28’
and the EEPROM at ’0x50’ and ’0x51’. . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal SPI data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI data transfer using the built-in CS pin feature. . . . . . . . . . . . . . . . . . . .
Final SPI data transfer implementation. . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the VHDL block design. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Platform application writing to register and validates its value. . . . . . . . . . . .
38
39
40
40
41
43
8.1
Layout – Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
5.3
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6
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8.2
8.3
8.4
8.5
8.6
8.7
Layout – Inner Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout – Inner Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout – Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output signal at 100 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output signal at 200 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
the nPor fix. Right: Altium designer screenshot with the modifications, Left: Same
modification on the PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8 The CLKREQ fix. Right: Altium designer screenshot with the modification, Left:
Same modification on the PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9 Signals; TX ready, data request, data in, data out, clock and state. . . . . . . . . . .
8.10 Output signals; data and clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
45
45
45
46
46
47
47
48
48
List of Tables
1.1
PCI Express transfer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
Product series candidates. . . . . . . . . . . . . . . .
Selected devices from the different product families.
Artix-7 - Recommended DC and AC characteristics.
Texas Instruments LM26480 internal regulators. . .
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10
11
14
15
4.1
4.2
Current flow and power loss in hierarchy option A. . . . . . . . . . . . . . . . . . .
Current flow and power loss in hierarchy option B. . . . . . . . . . . . . . . . . . .
21
21
5.1
5.2
5.3
5.4
5.5
23
24
27
28
5.6
JLC7628 layer stackup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing rules used during the design of the bridge. . . . . . . . . . . . . . . . . . .
Optimum and designed power-on sequence for the different power nets. . . . . . .
Regulator SET_IO state to voltage relation. . . . . . . . . . . . . . . . . . . . . . . .
Calculated values for Peak Current through the inductor and voltage ripple on
the output, using: Vin = 3.3V, η = 0.85, Iout,max = 0.8A, Cout = 10µF, L = 2.2µH,
f = 2MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Artix-7 Decoupling network for XC7A12T and XC7A35T . . . . . . . . . . . . . . .
8.1
Summary of bridge dimensions and performance . . . . . . . . . . . . . . . . . . .
44
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2
29
31
List of Tables
Abbreviations
Abbreviation
AC
BGA
BOM
DC
CAD
CLK
CMOS
CPU
DLL
DSP
EEPROM
ESR
FPGA
GPIO
GT/s
I2 C
I/O
IDE
IP
JTAG
LDO
LE
LUT
LVDS
MCU
MISO
MMCM
MOSI
NC
NO
NVS
PCB
PCI Express
PHY
PISO
PLL
PMIC
RAM
SerDes
SIPO
SMBus
SMPS
SPI
SPDT
SSI
SSTL
TL
TLP
TTL
UI
USB
VHDL
Meaning
Alternating Current
Ball Grid Array
Bill Of Materials
Direct Current
Computer Aided Design
Clock
Complementary Metal Oxide Semiconductor
Central Processing Unit
Data link layer
Digital Signal Processor
Electronically Erazable Programmable Read Only Memory
Equivalent Series Resistance
Field Programmable Gate Array
General Purpose Input/Output
Gigatransfers per second
Inter-Integrated Circuit
Input/Output
Integrated Development Environment
Intellectual Property
Joint Test Action Group
Low Drop-Out regulator
Logic Elements
Look-Up Table
Low Voltage Differential Signaling
Micro Controller Unit
Master In Slave Out
Mixed-Mode Clock Manager
Master Out Slave In
Normally Closed
Normally Open
Non-Volatile Storage
Printed Circuit Board
Peripheral Component Interconnect Express
PHYsical
Parallel In - Serial Out
Phase-Locked Loop
Power Management Integrated Circuit
Random Access Memory
Serializer/Deserializer
Serial In - Parallel Out
System Management Bus
Switch-Mode Power Supply
Serial Peripheral Interface
Single Pole Double Throw
Synchronous Serial Interface
Stub-Series Terminated Logic
Transaction Layer
Transaction Layer Package
Transistor-Transistor Logic
Unit interval
Universal Serial Bus
Very High-speed Integrated Circuit Hardware Description Language
1
Introduction
As modern technology develops, high-speed interfaces and expandable design are becoming
more prominent. Currently, one of the most widespread standards for expansion modules in
personal computers is the Peripheral Component Interconnect Express (PCI Express) interface.
The interface is usually accessible through expansion slots on the device and is, for example,
used to improve performance or allow communication over interfaces that are not natively
supported. Examples of modules that typically fit in expansion slots are hard drives, graphics
processors, and ethernet cards.
While a variety of boards which extend the functionality of master devices through the
M.2 connector already exist, most of them are focused on hardware acceleration of algorithms
with limited connectivity options. They, therefore, lack the necessary outputs needed to interface with other hardware. The main objective of this project is to add interface functionality
to PCI Express capable devices with adaptability and upgradability in mind.
The purpose of this Master Thesis’s work is to create an expansion board to extend the
functionality of WISI Norden’s current hardware. WISI Norden provides services for distribution of TV transmissions. They are currently using hardware that features an M.2 connector
with a PCI Express interface. Throughout the report, two words will be used frequently when
referring to the different hardware:
• Bridge refers to the the final product of the master thesis. This includes the PCB and
components mounted on it as well as any software written.
• Platform refers to the board or contact that the bridge is supposed to be connected to.
The bridge should act as a translator between PCI Express and any other protocol defined
by the user. In other words, PCI Express is converted to a protocol and transmitted. If any
messages are received, they are converted to PCI Express and sent to the platform.
1.1
Aim
The purpose of the master thesis is to design and implement a bridge that enables communication with hardware that does not have native PCI Express support. The bridge should
convert PCI Express to Low Voltage Differential Signaling (LVDS) and/or CMOS-logic. LVDS
and CMOS covers the most frequently used solutions for communicating between different
1
1.2. Background
hardware; differential and single-ended. Furthermore, the (CMOS/LVDS) side should be
easily re-configurable in order to support different types, amounts and combinations of interfaces.
1.2
Background
This section will describe the theoretical background which is most relevant for understanding the general concepts regarding the M.2 standard as well as the PCI Express protocol.
M.2 connector
M.2 is a specification for connectors associated to computer mounted expansions cards. It
defines a standard for physical dimensions. It also defines different keying-notches in order
to prevent cards from being used in incompatible hosts. The M.2 standard is available in
different configurations which are capable of PCI Express Gen 3.0, USB 3.0 and Serial ATA
3.0.
The PCI Express protocol
PCI Express is an interface designed for expansion boards such as video-, sound- and ethernet cards. It consists of one or multiple data lanes, where each lane can transfer data in both
directions. Multiple data lanes can be utilized to improve the data throughput of a PCI Express link. However, more lanes correspond to a larger footprint and more complex design.
Transfer rates of the standard are seen in Table 1.1.
Table 1.1: PCI Express transfer characteristics.
Standard version
Transfer rate
PCI Express 1.0
PCI Express 2.0
PCI Express 3.0
PCI Express 4.0
PCI Express 5.0
2.5 GT/s
5 GT/s
8 GT/s
16 GT/s
32 GT/s
Full duplex bandwidth
x1
x2
250 MB/s 500 MB/s
500 MB/s 1 GB/s
1 GB/s
2 GB/s
2 GB/s
4 GB/s
4 GB/s
8 GB/s
x4
1 GB/s
4 GB/s
4 GB/s
8 GB/s
16 GB/s
The PCI Express interface is communicating through a link between a root-complex (master) and an endpoint (slave) device. The platform that this project is developed against is a
root-complex. Hence, the bridge has to function as an endpoint device.
Layers
PCI Express is a layered protocol which consists of a physical layer, data link layer, and a
transaction layer.
Transaction Layer
PCI Express relies on request and completion transactions to transfer data between devices.
This is the primary task of the Transaction Layer (TL). The layer transmits requests and completion transactions from the logic core and turns them into outgoing PCI Express packets. It
receives incoming transactions from the Data Link Layer (DLL) and sends them to the core.
2
1.3. Research questions
Data Link Layer
The data link layer’s purpose is to detect and correct faults in the PCI Express data transmission. It continually monitors each PCI Express link and checks the data integrity of Transaction
Layer Packets (TLP’s) exchanged by devices.
Physical Layer
The Physical Layer (PHY) refers to the physical properties of the PCI Express link. Upon link
establishment, the highest number of mutual lanes is selected to allow for the maximum compatible data rate. Each lane consists of a unidirectional transmitting and receiving differential
pair, resulting in a total of 4 wires.
The physical layer should be able to determine the clock frequency from the data transmission. PCI Express Gen 1 and 2 utilizes an 8B/10B encoding/decoding scheme which
converts every 8 bits into 10 bits. The additional bits are placed where they generate a sufficient amount of rising and falling edges to properly establish the clock signal. The encoding/decoding scheme adds 20 % to the package overhead. PCI Express Gen 3.0 and above
implement a 128B/130B scheme with scrambling, which is far more efficient at « 1.5 % additional overhead.
1.3
Research questions
The master thesis is based on a set of questions presented below.
1. What are the alternatives to achieving PCI Express to LVDS/CMOS conversion?
2. Which alternative is expected to give the best result considering:
• Signal propagation delay.
• Data throughput.
• Component cost.
• Physical size of the design.
• Complexity.
3. What signal propagation delay and throughput can be expected of the system?
1.4
Design requirements
This section will cover the requirements for the design. The solution that is chosen should
fulfill all of the requirements.
PCI Express interface
The design should be able to interface with at least a PCI Express Gen1 x2 interface, meaning
that there are two data lanes at 2.5 GT/s. Later generations are desirable but not necessary.
The lane configuration (x2) must not change. The design should act as a PCI Express endpoint.
LVDS/CMOS interface
The interface should be able to support both LVDS and CMOS interfaces. The number of
interfaces should be configurable to suit the application. Furthermore, each interface should
be able to transmit data at up to 150 MHz.
3
1.5. Delimitations
Physical size and characteristics
The circuit board should have the dimensions 22x80x0.8 mm, which follows the standard size
of M.2 expansion cards. If the size criteria is not possible to fulfill, the circuit board should
be able to fit in WISI Nordens hardware. The M.2 Connector should be M-key and the PCB
should be 0.8 mm thick.
Power dissipation
The design will be housed in a small area with limited cooling options. The solutions should
not require active cooling.
1.5
Delimitations
The delimitations for this thesis are:
• The firmware for the solution should be seen as a demo-code, meaning all features do
not have to be implemented.
• The CMOS/LVDS side of the bridge does not have to convert PCI Express to a known
protocol, only show the differential/single-ended signals and their correspondence to
the user input.
4
2
Prestudy
The prestudy consists of an analysis of available options that support the previously described functionality. The study includes an investigation of pros and cons with the different
solutions as well as a decision of which of the solutions is to be implemented.
The PCI Express standard and data flow between devices were studied in order to get an
understanding of what solutions were possible. When enough knowledge about the standard
had been gained, different alternatives for achieving the desired functionality were investigated. The alternatives are presented below and compared in order to determine which one
is best suited.
Aspects that weigh into the decision include, but are not limited to:
• The price of components
• Physical size of components
• Complexity of the solution
• Life cycle of key components
• Power requirements
2.1
System sketch
Conversion between PCI Express and CMOS/LVDS can be achieved through different techniques. The focus of the prestudy is to determine the most suitable method of acquiring the
desired result while considering cost, complexity, physical dimensions and longevity.
The data will be transferred to the bridge via a high-speed PCI Express link where the
following actions are performed:
1. PCI Express overhead is stripped from the data and sent as LVDS/CMOS to the recipients over a user-defined protocol.
2. The recipient answers, the overhead is reinserted into the data and sent to the root
complex.
5
2.2. Possible solutions
The bridge should have the ability to communicate with multiple devices with low latency. A sketch of the system is illustrated in Fig. 2.1, where the Bridge block represents the
system that handles the PCI Express to LVDS/CMOS conversion.
Figure 2.1: High level sketch of the system.
The PCI Express endpoint requirement greatly limits the number of available solutions
since a large portion of available devices only supports root complex mode. Moreover, all
alternatives must be able to perform some sort of data manipulation in order to convert data
between the interfaces, further limiting the choices.
One idea was to use a PCI Express switch with multiple hardware bridges. A benefit
of such a solution is that all interfaces would show up as separate endpoints. However,
the concept was discarded since such a solution would be very difficult to reconfigure after
construction and the number of hardware bridges that support different interfaces is limited.
With all things considered, the pool of solutions was reduced to either a Central Processing
Unit (CPU) or a Field Programmable Gate Array (FPGA).
2.2
Possible solutions
The focus of this section is to describe the alternative solutions and their advantages/disadvanteges.
CPU
A CPU is often a good choice when data acquisition and processing is required. They are
proven to work reliably and offer high clock-speeds, which is required for the implementation
of the bridge. A system sketch of a bridge using a CPU is shown in Fig. 2.2. The light
gray block SSI to LVDS/CMOS Bridge symbolizes an optional interface that allows the CPU to
communicate with the external contact, if it is not able to do so directly.
Figure 2.2: System sketch of the solution using a CPU with native PCI Express support.
Many CPUs allow the use of an operating system such as Linux. This means that there
are more alternatives when it comes to programming languages.
6
2.2. Possible solutions
A drawback is that, while many CPUs support PCI Express, few of them can be used
in an endpoint configuration. Two manufacturers that produce endpoint capable CPUs are
Texas Instruments and Broadcomm. Another drawback is that CPUs commonly lack LVDS output functionality. Fortunately, many CPUs feature high-speed serial interfaces such as Quad
SPI that allow them to be connected to external components that can act as LVDS/CMOS
interfaces. The summary of the pros and cons of this system is presented below.
Pros
- Easy to work with.
- Features an operating system
Cons
- Limited availability for endpoint capable CPUs
- Boot time
- Uncommon, limited amount of sources
- Real-time system, possibly introduces latency
- Might requre external hardware on LVDS/CMOS side
- Complexity (design)
PCI Express to PHY interface
If the desired device does not support PCI Express, an Integrated Circuit (IC) with PCI Express
to PHY bridge functionality can be employed between the PCI Express interface and the
computing device, as illustrated in Fig. 2.3.
Figure 2.3: System sketch of the solution when using a CPU without native support for PCI
Express.
The IC is used as an endpoint device to establish a link with the root-complex. It includes
a Serializer/Deserializer (SerDes), consisting of a Parallel In Serial Out (PISO) block and a Serial
In Parallel Out (SIPO) block. The block converts data from a serial to a parallel interface in
both directions.
The use of a PCI Express PHY bridge greatly improves the assortment of available CPUs
as the existing layers within the PCIe standard are software based. However, there are a
limited amount of PHY bridges and the available options from the researched manufacturers
are currently limited to PCI Express Gen 1. The summary of the pros and cons of this system
is presented below.
Pros
- Easy to exchange physical layer
Cons
- Requires PCI Express to PHY IC to operate in
endpoint mode
- Need to implement DLL and TL
- Not possible to upgrade physical layer if
manufacturers stop produce new solutions.
7
2.2. Possible solutions
Programmable logic
Programmable logic, such as FPGAs are commonly used for high-speed applications and
computation acceleration. Many manufacturers offer value-line and low-power FPGAs that
are suited for digital processing. The system sketch when using a FPGA is shown in Fig. 4.3.
Figure 2.4: System sketch of the solution when using a FPGA.
One benefit of using a FPGA is that they usually feature a large amount (100+) of GPIOs
and the majority of them support differential termination options as well as single ended termination. Some FPGAs also feature full hardware support for all PCI Express layers and are
able to behave as endpoints. Due to their nature, a FPGA without hardware PCI Express support can be programmed to support it. The requirement is that they are able to communicate
at PCI Express speeds, for example with the help of a transceiver. The transceiver are used in
conjunction with Intellectual Property (IP) cores that implement the higher layers. While such
a solution is highly configurable, it is at the expense of logic elements in the FPGA.
The boot times are determined by the FPGA configuration size as well as the programming interface speed. As a result, many smaller FPGAs are able to boot faster than the 100
ms start up time criterion described by the PCI Express Base Specification[1].
Since FPGAs are usually programmed to perform very specific tasks, low and predictable
latency is achievable in a FPGA-based system as well as high throughput. Both of these
aspects are desirable since the bridge should allow the root complex to communicate with
multiple LVDS/CMOS interfaces at high speeds.
The main benefit compared to other solutions is that FPGAs can be programmed to support almost any interface. However, FPGAs lack the rich set of peripherals or software implementation of the interfaces.
One design consideration when using a FPGA is that a Non- Volatile Storage (NVS) is required for storing the configuration. Another important consideration is that since the operating principle of FPGAs is quite a bit different from MPUs and CPUs, the programming
also differs a lot. FPGAs are commonly programmed using Hardware Description Languages
(HDLs) such as Verilog or Very High Speed Integrated Circuit HDL (VHDL), both languages differ a lot from sequential programming languages. The summary of the pros and cons of this
system is presented below.
Pros
- High number of GPIOs.
- Fast boot time.
- Many manufacturers provide fully functional
PCI Express IP cores.
- Low latency and high throughput.
- Capable of supporting different types of interfaces.
Cons
- Requires external memory.
- Less intuitive programming.
8
2.2. Possible solutions
Conclusion
Based on the previous analysis, a few key points can be made to rule out the different solutions:
CPUs: Powerful, but are unnecessarily complex and may have long boot times. The lack
of connectivity options also makes this solution poorly suited for the design. Another drawback is the lack of endpoint-capable CPUs, severely limiting the selection of possible hardware.
CPUs without endpoint support suffer from the same drawbacks, with the addition of
relying on external PHYs. In short, none of the two CPU solutions are suitable for the application.
Programmable logic: Programmable logic such as FPGAs may not be as intuitive for developers who are accustomed to CPU development, they do have a lot of features desired in
the application. FPGAs are commonly used in endpoint configuration and many manufacturers offer endpoint IP cores. The requirement of an external memory is compensated for by
the large amount of connectivity options of a FPGA.
With consideration to the information gathered in this prestudy, it was decided that the
bridge should be implemented using a FPGA.
9
3
Selection of hardware
Multiple manufacturers and product lines were compared to find a suitable FPGA as well
as peripheral components. This section will discuss the process of finding, comparing and
choosing the different hardware.
3.1
FPGA selection
In order to find the best-suited FPGA for the design, several product series from multiple
manufacturers were compared. Four FPGA manufacturers were considered: Intel (previously
knows as Altera), Lattice semiconductor, Microsemi and Xilinx. Initially, the different product
series were investigated and later specific device packages. In order to qualify as a possible
candidate for the initial selection, the product series should feature support for at least PCI
Express Gen 1 x2. A list of candidates was compiled and is presented in Table 3.1.
Table 3.1: Product series candidates.
Manufacturer
Intel
Intel
Intel
Intel
Lattice
Lattice
Lattice
Microsemi
Microsemi
Xilinx
Xilinx
Xilinx
Xilinx
Xilinx
Xilinx
Product family
Cyclone IV
Cyclone 10
Arria V GX/GZ
Stratix V GX
ECP2
ECP3
ECP5/ECP5-5G
IGLOO2
SmartFusion 2
Spartan-6
Artix-7
Kintex-7
Virtex-7 XT
Kintex Ultrascale Plus
Virtex Ultrascale Plus
10
3.1. FPGA selection
Product family
The device selection process focused on three main aspects: the amount of transceivers, the
number of logic elements (LE’s) and the device speed grade. Transceivers are high-speed serial/parallel interfaces that operate at a higher frequency than the FPGA fabric. They are
essential for PCI Express communications since the fabric itself is usually not capable of handling PCI Express speeds.
The device used must have at least two transceiver channels and if the package is a ball
grid array (BGA), it should have a ball pitch equal or larger than 0.8 mm. The reason is that
while a smaller pitch device features more pins in a smaller package, the design tolerances
become stricter which in turn increases the PCB production cost.
The number of LE’s determines how much application logic can be implemented on the
FPGA. PCI Express IP cores usually take a portion of the logic cells, depending on the manufacturer so they need to be taken into consideration1 .
For some manufacturers, speed grade limits performance. Components need to have a
speed grade high enough to support PCI Express in order to qualify for the selection. A list
was compiled with possible candidates that fulfilled the requirements. The complete list is
presented in Appendix A, Table 3.2 shows a summary of the list.
Table 3.2: Selected devices from the different product families.
Product family
Cyclone IV[6]
Cyclone 10 GX[7]
Arria V GX[8]
Arria V GZ[8]
Stratix V GX[9]
ECP2[10]
ECP3[11]
ECP5[11]
ECP5-5G[11]
IGLOO2[12]
SmartFusion2[13]
Spartan-6[14]
Artix-7[15]
Kintex-7[15]
Virtex-7 XT[15]
Device code
EP4CGX30CF19C8N
10CX085YU484I6G
10CX220YF780E5G
5AGXMA5G4F35C4G
5AGZME1E3H29C4N
5SGXMA3E3H29C4N
LFE2M20E-5FN256C
LFE3-17EA-6FTN256C
LFE5UM-25F-8BG381C
LFE5UM-45F-8BG381C
LFE5UM5G-25F-8BG381C
LFE5UM5G-45F-8BG381C
M2GL010T-1VF400
M2GL025T-1VF400
M2S010T-1VF400
XC6SLX25T-N3CSG324C
XC7A12T-2CSG325
XC7A15T-2CSG325
XC7A25T-2CSG325
XC7A100T-1FGG484
XC7K70T-1FBG484
XC7VX330T-1FFG1157C
Footprint
F324
U484
F780
F672
H780
F780
F256
ftBGA256
csBGA381
csBGA381
csBGA381
csBGA381
VF400
VF400
VF400
CSG324
CSG325
CSG325
CSG325
FGG484
FBG484
FFG1157
LE’s
30k
85k
220k
75k
220k
340k
19k
17k
25k
45k
25k
45k
12k
25k
12k
24k
13k
16k
25k
101k
65k
326k
Transceivers
6
6
12
9
12
12
4
4
2
4
2
4
4
4
4
2
2
4
4
4
4
20
Device selection
The initial seperation was done by putting a price cap at 100 USD/Unit. The limit was chosen
since the final design should be as cheap as possible. Any FPGA that was more expensive
usually featured higher performance than what was necessary or had poor price-performance
ratio. This removed all Intel devices except the Cyclone IV and all Kintex/Virtex devices.
1 Each manufacturer provides a separate PCI Express IP Core, Intel and Microsemi implements the core in hard
logic so no resources are required[2][3], Lattice requires 12-16k LUTs[4], Xilinx requires 1k LUTs[5, p.10-11].
11
3.1. FPGA selection
Secondly, devices were removed if they were larger than 22x22 mm since they would
not fit on the PCB. Older-generation devices such as the Lattice ECP3, Intel Cyclone IV and
Xilinx Spartan 6 were also removed. The reason was that the newer generations are about as
expensive but featured more modern hardware.
The remaining product series were the Lattice ECP5/ECP5-5G, Xilinx Artix-7 and Microsemi
IGLOO2/Smartfusion 2. The ECP5 device was removed since it only supports PCI Express gen
1. The Smartfusion 2 device was removed because it is essentially the same device as the
IGLOO2 but with an integrated microcontroller which was not needed.
In order to compare the remaining devices, an assumption was made that the bridge
would require at most 10K Logic elements (not including the PCI Express interface). Choosing the smallest possible device from each family, the choice is narrowed down to three devices:
Device
Lattice LFEUM-25F-8BGC381C
Microsemi M2GL010T-1VF400
Xilinx XC7A12T-2CSG325
Unit price [USD]
19
37
36
The Lattice device stands out from the rest since it is significantly cheaper compared to
the other devices. However, the ECP5-5G family requires a software license for both the IDE
and the PCI express IP Core. The IDE cost 895 USD/year and the IP Core is a one-time cost
of 1800 USD. It also requires an external PLL for its transceivers, adding around 4 USD to the
unit price. The Xilinx and Microsemi both require no license for the IDE or PCI Express IP
Core.
Figure 3.1 shows the accumulated price for each of the devices. The comparison assumes
100 units/year, meaning that any yearly licence is required every 100 units.
Figure 3.1: Total accumulated price for N number of units, assuming 100 units/year.
As seen in Fig. 3.1, the price break between the Lattice and Microsemi devices are at about
500-600 units. The Xilinx device has a marginally lower cost/device when compared to the
others. Since the price difference was so small, any of the devices was a good choice for the
design. To be able to make a decision, another aspect had to be taken into account.
The Xilinx Artix-7 XC7A12T-2CSG325 was considered the best candidate. The reason is
that the developers where the master’s thesis is carried out all use Xilinx FPGAs, meaning
that there is a great knowledge base for both hardware and software. The device naming
parameters can be split-up to describe the features of the unit. The name indicates that it
12
3.2. Non-volatile memory selection
is an Artix-7 Series FPGA with 12K LUTs, speed grade 2 and package type C325 [15, p.16].
It is Xilinx smallest Artix-7 FPGA but features the necessary components to accomplish the
assignment. The C325 package is available in many configurations and is easily upgraded
due to its pin compatibility with higher-end models of the same family. Speed grade 2 is
required to communicate using PCI Express Gen 2.
3.2
Non-volatile memory selection
Since the FPGA fabric commonly consist of volatile memory, FPGAs are unable to retain their
configuration when powered off. To resolve this problem, an external Non-volatile memory
(NVM) is commonly used to store the configurations when power is lost. Other alternatives
include loading the configuration from an external processor, or a hybrid of the two.
For the bridge design, an external memory was used for loading the configuration. The
reason is that the physical size of the design is restricted and a processor would not add any
extra functionality other than the configuration loading.
Flash memories are either NOR- or NAND-based. The techniques differ vastly in their
operation. NOR flash provides sufficient addresses to map the entire memory range, which
makes it possible to access random data within the memory. They feature quick read-times
but have relatively high write and erase speeds. 100 % bit correctness is ensured, making
them excellent to use in a code execution applications. NAND-flash has a high bit-failure and
requires error correction to determine if the data is valid. The advantages of NAND-flash is
high storage-density and low cost. They are therefore primarily used in applications where
large capacity storage is required. The most reasonable flash technique to use as firmware
storage in conjunction with an FPGA is, consequently, a NOR-flash.
The flash memory parameters were chosen based on price, capacity, and footprint.
MT25QL128 was a satisfactory choice since it features multiple storage sizes and a standard
footprint. It communicates using SPI which is directly compatible with the FPGA. NOR-flash
with the same pin-out and footprint are available with a capacity up to 256 Mb. The chosen
Artix-7 with 12 kLUTs has a Bitstream size of 10 Mb while the 35 kLUTs has a size of 18 Mb
[16, p.14] which will easily fit in the NVM.
WISI Norden desired a small I2C EEPROM with device information, tied directly to the
SMBus (I2C compatible) interface. The information on the EEPROM should include enough
information for the main device to identify the PCI Express Bridge. AT24CXXD is a small and
cheap EEPROM with 1-16 Kb capacity in a SOT23-5 package. It complied with the necessary
requirements and featured a Write Enable (WE) pin, used to protect the user from accidentally
overwriting the memory.
3.3
Regulator selection
The Artix-7 FPGA requires several different voltages to operate. It is usually achieved by
a series of Switch Mode Power Supply (SMPS) or Low-dropout Regulator (LDO) ICs. SMPS are
highly efficient but induce electrical noise as a side effect. Low-dropout regulators are linear,
which effectively means that they convert excessive power to heat by altering the resistance
relative to the load. It results in an ineffective power regulator but provides a clean voltage
to the load.
Most voltage inputs of the FPGA are tolerant of the noise-levels produced by switching
regulators. However, analog voltages related to the transceivers often require isolated and
electrically clean power. SMPS are therefore mostly used when high currents are present or
where the input to output voltage difference is high. An effective option to achieve clean, yet
efficient, power conversion is to use a switching regulator in series with an LDO.
Typically, FPGAs require around 3-4 different voltages, with current draw varying greatly
depending on FPGA size and application. It is, therefore, a demanding task to select a suit13
3.3. Regulator selection
able voltage network which efficiently powers FPGAs. Since the current draw of the FPGA
is directly related to the resources used in the user application, Xilinx provides a Power Estimator application. The application is used to calculate the estimated current draw based on
resources selected by the user.
The number of different voltages is related to the peripherals used within the device. For
example, the transceiver channels require an isolated and stable source, while the core and
other auxiliary circuits within the FPGA are more resistant to noise and voltage fluctuations.
The recommended voltage levels for the Artix-7 FPGA, along with their tolerances and estimated current consumption, is presented in Table 3.3.
Table 3.3: Artix-7 - Recommended DC and AC characteristics.
The following values were calculated using: PCI Express Gen 2, 1x2 configuration, I/O
Bank: 40 LVDS (2.5V) pairs @ 150 MHz, 100% LUT usage.
Symbol
Voltage [V]
Current [mA] Tolerance
Supply description
˘3% [17]
VCCI NT
1.0
600
Internal power.
VCCBRAM
1.0
4
Block RAM.
˘10 mVpp [18, p.228]
200
GTP transceivers.
VMGTAVCC 1.0
˘5% [17]
1.8
100
Auxiliary supply.
VCCAUX
˘30 mVpp [17]
150
GTP termination.
VMGTAVTT 1.2
VCCO_15
1.14 to 3.465 300
HR I/O banks.
1.14 to 3.465 300
HR I/O banks.
VCCO_34
The current estimation is derived from Xilinx Power Estimator (XPE). The combination of
high current consumption for the core and low noise requirements for the transceiver peripherals demands an effective yet flexible power solution. To conform with the requirements, a
combination of switching regulators and low dropout linear regulators were regarded as the
best solution.
The sensitive and low power transceiver peripherals (VMGTAVTT and VMGTAVCC ) are supplied from LDOs which provides an electrically clean output, while the VCCI NT and VCCAUX
are supplied from the SMPS. To simplify the task of selecting a suitable power solution,
mainly for FPGAs and processors, manufacturers have developed Power Management Integrated Circuits (PMICs). PMICs can refer to any IC which performs power conversion but
generally, they are intended to include all of the necessary SMPS and LDOs within a single
IC.
A fitting candidate is the TI LM26480, which is an IC consisting of two switching regulators and two low dropout linear regulators[19]. The key features of LM26480 are:
• Small footprint of 4x4 mm.
• Low Price.
• Hardware adjustable voltage levels on all regulators.
• Power good indicator.
• 2 MHz switching frequency, allowing the use of small external inductors and capacitors.
The voltage and current capabilities of the built-in regulators in the LM26480 can be seen
in Table 3.4.
14
3.3. Regulator selection
Table 3.4: Texas Instruments LM26480 internal regulators.
Regulator type
Switching
Switching
Low Dropout
Low Dropout
Output voltage [V]
0.8 to 2
1 to 3.3
1 to 3.5
1 to 3.5
Current [A]
1.5
1.5
0.3
0.3
Voltage drop
25 mV (typical)
25 mV (typical)
The I/O banks of the Artix-7 FPGA may be powered separately from each other. The
idea is to power the I/O banks from their own LDO which provides the ability to handle
multiple I/O standards. An example is to communicate with a 2.5 V interface on I/O bank 15
while I/O bank 34 runs on 3.3 V simultaneously, enabling the use of different I/O interface
standards per bank.
All LDOs suffers from a small dropout voltage, Vdrop , which means that the maximum
output voltage is limited to Vin ´ Vdrop . This is problematic when a 3.3 V output standard is
desired and Vout needs to equal Vin . However, Texas Instruments TLV758P solves this issue.
Once Vin ă (Vout ´ Vdrop ), it goes into a "dropout mode", where the output voltage tracks the
input voltage. It features a small footprint, low price and acceptable output current of 300
mA, along with an adjustable output voltage which is configured through a voltage divider.
15
4
System Description
This chapter will present an overview of the bridge architecture. The goal is to provide the
reader with an easy reference as to how each part of the bridge operates and integrates with
other parts. The design is composed of many smaller systems that operate independently
or alongside other systems. A rough sketch of an M.2-module with a possible layout of the
systems is shown in Fig. 4.1. The complete schematic, layout, BOM and mounting guides are
presented in Appendix B.
Each system, left to right, will be presented in a separate section. In general, thicker lines
represent buses or groups of signals and thinner lines represent single signals. Gray symbols
represent physical parts, such as PCBs and components. Each internal pattern in Fig. 4.1
represents a separate system and the pattern for each section is consistent throughout the
chapter.
Note that power nets are only shown in the M.2 and Power management system sketches.
l M.2 connector, FPGA, a Programming and debugging interface, Power management,
External connectors.
Figure 4.1: System layout on the M.2 module.
4.1
M.2 Connector
The M.2 connector serves as the main interface with the platform. It is a finger-edge connector
which provides both power and signaling to the bridge. The M.2 connector connects to the
16
4.2. FPGA
FPGA system, Power management system as well as the programming and debugging interface
system as shown in Fig.4.2.
FPGA, a Programming and debugging interface, Power management.
Figure 4.2: M.2 connector system connections.
The PCI Express bus is the high-speed interface that is used for data exchange between
the platform and bridge. It consists of two transmitting lanes, two receiving lanes and a clock
lane. The PCI Express bus connects directly from the M.2 connector to the FPGA system.
The platform provides a SMBus on the M.2 connector. Since the platform SMBus operates
at 1.8 V logic level and the programming and debugging interface SMBus operates at 3.3 V logic
level, a logic level converter is required. The converter needs to convert 1.8 V signals to 3.3 V
and vice versa.
The M.2 connector also provides 3.3 V power that is used to generate stable voltages for
the bridge. The 3.3 V power from the card edge connector directly connects to the Power
management system.
4.2
FPGA
The FPGA system interfaces with all other systems on the bridge. The main component of
the system is the Artix-7 FPGA, which consists of several smaller parts such as transceivers
and configuration banks. This section will describe how the FPGA system interfaces with the
other systems according to the diagram in Fig. 4.3. A more in-depth description of the Artix-7
and its parts is presented in chapter 5.
l M.2 connector, FPGA, a Programming and debugging interface, Power management,
External connectors.
Figure 4.3: FPGA system connections.
17
4.3. Programming and debugging
The SPI interface is used for loading new bitstreams to the FPGA. It is a 1x Synchronous
Serial Interface (SSI), meaning it utilizes a single data channel in each direction. The bus connects to the Programming and debugging system along with the Done and Configure signals.
The Done signal is used to verify that bitstreams successfully load into the FPGA and can
be read over SMBus. The Configure signal triggers the loading of a new bitstream when
pulsed low.
The SET_IO_X_N bus is used by the FPGA to control the LDO which regulates bank
voltage for the LVDS/CMOS I/O banks. This is done by pulling the signals low och putting
the respective pins in High-Z mode. Chapter 5 describes the process in greater detail.
The LVDS/CMOS bus consists of 10 differential signal pairs. Each pair may be reconfigured to function as two independent single-ended signals allowing for a maximum of 20
individually controllable signal pins. The LVDS/CMOS bus connects to the External connectors
system.
4.3
Programming and debugging
For the programming interface, different paths for configuration were investigated. The first
was to use the PCI Express interface in conjunction with a solution provided by Xilinx called
PCI Express tandem. The solution was initially only named tandem and was designed to allow
large bitstream devices to load the PCI Express core before loading the rest of the bitstream
into the device. The entire bitstream is loaded in two stages from an external NVM and the
idea was that the device should fulfill the 100 ms criterion set in the PCI Express specification.
PCI Express tandem allows the user to load the first stage from a NVM and the second
stage to be sent to the device over PCI Express. The solution appeared promising since there
was a limited amount of interfaces on the M.2 connector and it would allow easy exchange of
the bitstream in the device. Unfortunately, this solution is not available in all Artix-7 devices.
The smallest device that supports it is the XC7A75T[5, p.157]. The solution was abandoned
since the device is not available in the chosen package.
The second path for configuration was the SMBus present on the M.2 connector. The
interface is not fast enough to allow bitstream loading upon start up1 but it can be used to
load new configurations to an on-board NVM. The FPGA can boot from the flash when it is
powered on and if a different configuration is desired, it can be loaded into the NVM and the
FPGA reloaded with the bitstream.
The third path of configuration is a JTAG interface. It can be used not only for loading
images to the FPGA and NVM, but also provides debugging functionality. The drawback of
the interface is that it is not present on the M.2 connector meaning that it will be used mainly
for debugging.
Fig. 4.4 shows a sketch of signals present in the programming and debugging system. The
SMBus connects to a ID NVM. The purpose is to provide a way of identifying the bridge, even
if the system does not boot. It is connected directly to the SMBus with nothing between it and
the M.2 connector in order to minimize the risk of failure. The NVM is write-protected and
the protection can only be disabled by shorting a test pad on the PCB to ground.
The SMBus is also connected to a SMBus to SPI converter. The SPI bus of the converter is
connected to the Normally closed (NC) pins of a quad Single-pole, double throw (SPDT) analog
switch. The Normally open (NO) pins of the SPDT is connected to the FPGA and the Common
(COM) pins are connected to a NVM. In order to select what device is connected to the NVM,
a GPIO on the converter is used to control the SPDT through the IN signal.
1 SMBus
@100 kHz requires 100+ seconds to load an entire XC7A12T bitstream of 10 Mb.
18
4.4. Power management
l M.2 connector, FPGA.
Figure 4.4: Programming and debugging system connections.
4.4
Power management
The power management system is shown in Fig. 4.5. The Power good signal indicates
that all of the PMIC voltages are stable. When pulled low, the LDO and switch are enabled,
powering the last sections of the bridge.
l M.2 connector, FPGA, a Programming and debugging interface.
Figure 4.5: Power management system connections.
Power tree
The goal of using SMPS’s and LDOs in conjunction is to minimize the total power loss of
the bridge, allowing it to run without active cooling. This section will present two possible
hierarchies for the power supplies and discuss the differences between them.
19
4.4. Power management
The first two voltage domains are the 1.0 V VCCI NT /VCCBRAM and 1.8 V VCCAUX . All
systems connected to these voltages are larger than 3 % tolerance to noise, as seen in Table 3.3,
meaning they can be sourced from the SMPS in the PMIC. In Fig. 4.6, these are represented
by regulator 1 and 2.
Since the transceivers in the Artix-7 are sensitive to noise, it is preferable to use LDOs for
their voltage feeds, VMGTAVCC and VMGTAVTT . The two LDOs present in the PMIC will be
used, represented by regulator 3 and 4 in Fig. 4.6.
Note that regulator 5 is omitted from the power loss calculations. This is partly because it
is a separate regulator, but also because the current and voltage for the I/O banks may vary
greatly depending on the standard used as well as the speed and number of pins. The power
hierarchy is illustrated in Fig. 4.6a and 4.6b.
(a) Option A, VMGTAVCC and VMGTAVTT sourced (b) Option B, VMGTAVCC and VMGTAVTT
sourced from 3.3 V.
from 1.8V.
Figure 4.6: Power hierarchy option considered in the design.
Option A and B in Fig. 4.6 mainly differ in the amount of power wasted during operation.
An overview of the power loss and current within the LM26480 is presented in Table 4.1 and
4.2.
The SMPS regulator efficiency was chosen as 80 % to simulate a worst-case scenario and
to provide some headroom if the current draw estimations are inaccurate. Typically, the efficiency should be between 85-90 % for SMPS’s. For LDOs, Iin is the same as Iout . Rewriting
the formula for efficiency, E f f , in (4.1), the efficiency of an LDO is given by Vout /Vin .
Ef f =
Vout ¨ Iout
Vin ¨ Iin
(4.1)
For SMPS’s, Iin is given by rewriting (4.1) to (4.2):
Iin =
Vout ¨ Iout
Vin ¨ E f f
(4.2)
Since Iin , Iout , Vin and Vout are now known for each regulator, the power loss can be calculated using the expected current draw presented in Table 3.3:
Ploss = Pin ´ Pout = Iin ¨ Vin ´ Iout ¨ Vout
(4.3)
Using (4.1) to (4.3), all currents, power losses and the total power loss can be calculated
for each of the two options presented in Fig. 4.6. The results for option A and B are presented
in Table 4.1 and 4.2, respectively.
20
4.5. External connectors
Type
Vin [V]
Vout [V]
Iin [A]
Iout [A]
Efficiency [%]
Ploss [W]
Regulator 1
SMPS
3.3
1.0
0.23
0.6
80
0.15
Regulator 2
SMPS
3.3
1.8
0.31
0.45
80
0.20
Regulator 3
LDO
1.8
1.0
0.20
0.20
56
0.16
Regulator 4
LDO
1.8
1.2
0.15
0.15
67
0.09
Total
1.14
0.60
Table 4.1: Current flow and power loss in hierarchy option A.
Type
Vin [V]
Vout [V]
Iin [A]
Iout [A]
Efficiency [%]
Ploss [W]
Regulator 1
SMPS
3.3
1.0
0.23
0.6
80
0.15
Regulator 2
SMPS
3.3
1.8
0.07
0.1
80
0.05
Regulator 3
LDO
3.3
1.0
0.20
0.20
30
0.46
Regulator 4
LDO
3.3
1.2
0.15
0.15
32
0.32
Total
1.25
0.97
Table 4.2: Current flow and power loss in hierarchy option B.
As seen in Tables 4.1 and 4.2, option A is the best when considering power loss. The hierarchy was simulated using Texas Instruments Tina-TI and the provided model for the LM26480.
During simulation, the LDO appeared to reverse feed the SMPS, causing unpredictable behaviour. Since the design should work and it was unknown if the problem was caused by the
simulation model, the final design will include an option that allows switching between the
two hierarchies using 0 ohm resistor.
4.5
External connectors
The bridge has two sets of external connectors, each connected to a group of differential pairs
as shown in Fig. 4.7. All pairs connect to the FPGA system. The external connectors also
feature mounting pads for external termination at the connector since testing equipment may
not be terminated correctly.
FPGA
Figure 4.7: M.2 connector system connections.
21
5
Hardware design and
implementation
This chapter will present the ideas and considerations during the design process of the bridge.
5.1
Stackup and design rules
JLCPCB was chosen for manufacturing the PCB. While they may not have as many options
as other manufacturers in their PCB stackup, they simplify the design process by providing
tools for calculating line impedance both for single-ended and differential traces for all of
their stackups.
In order to ensure that the PCB can be produced, the design has to follow the manufacturers rules and use a stackup that JLCPCB can produce. This section will present the stackup
and rules that were used for the design.
Stackup
The design uses the JLCPCB 0.8 mm JLC7628 stackup shown in Table 5.1. While the manufacturer offers other stackups with higher Dielectric constant and thinner prepregs, JLC7628
was chosen due to its thin core, which increases the inter-plane capacitance between the two
inner planes where the majority of the ground and power planes are located. The tradeoff is a poorer coupling between the outer and inner layers, slightly increasing the width of
impedance matched traces.
22
5.1. Stackup and design rules
Table 5.1: JLC7628 layer stackup.
Layer
Top solder mask
Top copper
Prepreg
Inner copper 1
Core
Inner copper 2
Prepreg
Bottom copper
Bottom solder mask
Material type
Solder mask
Copper
7628
Copper
Copper
7628
Copper
Solder mask
Thickness (mm)
0.0127-0.0203
0.035
0.2
0.0175
0.265
0.0175
0.2
0.035
0.0127-0.0203
Dielectric constant
3.8
4.6
4.6
3.8
Design rules
The rules that were used in the design are presented in Table 5.2. The majority are the recommendations from the manufacturer, with the exception of the rules related to differential
pairs.
The Differential trace width and Differential pair gap was calculated using the manufacturers
online tool, all differential lines on the PCB are designed for a nominal differential impedance
of 100 Ohm.
The Length difference within pair rule was chosen small because the line-to-line skew directly influences signal integrity. While perfect length matching is desirable, it is not always
possible due to manufacturing defects, etc. The designer should strive for perfect length
matching, but realize that minor differences are negligible. Another important note is that
any differences that appear as a result of turns or connections should be fixed as close to the
source of the difference as possible, as shown by point I in Fig. 5.1. The reason is that the
noise rejection of differential signals is best when the two signals are in phase.
The Copper-Differential pair clearance rule ensures that the high speed differential pairs have
proper signal integrity. As a rule of thumb, a clearance larger than 2 times the pair gap should
be used to ensure that the coupling to nearby copper is negligible. The design has a 3 times
larger clearance compared to the gap.
[A] Via hole size
[B] Via annular
[C] Copper-Differential pair clearance
[D] Differential trace width
[E] Differential trace gap
[F] Copper-Copper clearance
[G] Routing trace width
[H] Solder mask sliver
[I] Length difference within pair
Figure 5.1: Illustration of design rules used during layout.
23
5.2. M.2 connector
Table 5.2: Routing rules used during the design of the bridge.
Rule
Clearance
Trace width
Vias
Differential pairs
Solder mask
5.2
Copper-Differential pair
Copper-Copper
Routing trace
Via hole size
Via annular size
Trace gap
Trace width
Length difference
within pair
Sliver
min
12
4
4
8
18
4
4.96
mil
nom
6
16
31
4.5
5.54
max
5
6.05
min
0.3
0.1
0.1
0.2
0.45
0.1
0.126
mm
nom
0.15
0.4
0.8
0.114
0.141
max
0.127
0.154
-
-
5
-
-
0.127
4
-
-
0.1
-
-
M.2 connector
As discussed earlier, the SMBus logic level of the platform is lower than the logic level of the
programming interface so a level converter must be used. Since SMBus operates on an opendrain configuration1 , the circuit in Fig. 5.2 can be used for the conversion. The solution was
used since it required a small number of components, resulting in a small overall footprint.
Figure 5.2: Open-drain logic level conversion. HV indicates High (3.3 V) logic level, LV indicates low (1.8 V) logic level.
Layout
The main consideration during layout was to keep the high-speed traces isolated from other
signals such as the SMBus as well as any other high-speed signals in order to maintain signal
integrity. For the PCI Express signals, the metal directly below the signals is a ground plane
as seen in Fig.5.3. Vias were also added in close proximity to layer changes of the signals to
provide a good return path for the signal. Additionally, fencing vias were added around the
traces where possible to further shield the high speed signals.
1 In
an open-drain configuration, the signal is driven low and pulled high through a resistor.
24
5.3. FPGA configuration banks
Figure 5.3: Layout surrounding the M.2 connector on the top layer of the PCB. Notice the
fencing and return path vias as well as the ground plane (yellow) on the layer below the PCI
Express lanes.
5.3
FPGA configuration banks
The configuration banks refer to Bank 0 and 14 in the Artix-7. These banks are used for
configuration of the FPGA as well as setting the voltage levels for the I/O banks.
The JTAG interface on Bank 0 is used for debugging and loading new bitstreams to the
NVM through the SPI interface. This interface has a separate connector on the PCB and is not
connected to the M.2 connector.
The SPI interface is used for loading bitstreams from the NVM. The default interface is set
through the Mx pins on Bank 0. In the design, M [2..0] = 001, corresponding to Master SPI[16,
p.21]. This interface is used at power-on, but may be overridden by the JTAG interface.
Three IOs on Bank 14 are used to control the voltage level of the remaining I/O banks.
This is achieved by altering the feedback loop of an LDO by pulling the respective IOs low or
putting them in a high-Z state. This is described in greater detail in section 5.6.
Layout
Since most of the configuration pins on the Artix-7 have fixed positions in the pinout, the
main consideration was to avoid layer changes as much as possible. Examples of how the
nets were fanned out under the Artix-7 are shown in Fig. 5.4. The LDO control pins that had
no fixed position were moved close to the LDO to make routing easier.
Figure 5.4: Fanout of the SPI and JTAG nets (highlighted) under the Artix-7.
25
5.4. FPGA I/O banks
5.4
FPGA I/O banks
The I/O banks refer to Bank 15 and 34 in the Artix-7. These banks are both connected to the
LVDS/CMOS connectors. Each bank has 10 pins available at the connector that may be used
as either 10 single-ended pins or 5 differential pairs. Due to space constraints, one of the pairs
on Bank 34 was only routed to a terminating resistor close to the Artix-7.
Layout
All pairs were routed and pairwise length-matched within 0.127 mm (5 mil) with a nominal
differential impedance of 100 Ohm. The clearance between pairs was kept to a minimum of
3 times the spacing within a pair to reduce cross-talk.
5.5
FPGA transceivers and PCI Express nets
The PCI Express lanes 0 and 1 of the M.2 connector were connected to the transceivers of
the Artix-7. To simplify the routing, lane 0 was connected to transceiver 1 and lane 1 to
transceiver 0.
To reduce the complexity and number of external components of the system, the PCI
Express reference clock will not only be used for the transceivers, but also to clock the core
logic of the FPGA.
For the PCI Express lanes, the PCI Express Base specification states that any transmitting element should have AC coupling capacitors in the range 75 ´ 265 nF for 5 GT/s applications[1,
p.357]. 100 nF capacitors were added to the TX and CLK lanes.
Layout
Since the PCI Express lanes and reference clock are both differential signals, special consideration must be taken to their relative length. The most important consideration is the difference between the positive and negative signal inside a lane, since it directly influences signal
integrity.
The largest allowed lane-to-lane skew is 1.3 ns for TX and 8 ns for RX when UI is the
nominal unit interval 200 ps[p.357,p.378,p.380][1]. Assuming a phase velocity of 0.67 c, this
corresponds to 18/160 cm for TX/RX, respectively. TX lanes are completely independent
from RX lanes, so they need not be matched. The characteristic impedance for all lanes are
80-120 Ohm according to the PCI Express base specification[1, p.355, p.379]. During layout,
pairs were designed to the nominal differential impedance 100 Ohm.
5.6
Power management
The Artix-7 datasheet provides the optimal power-on sequence[20, p.8] to minimize current
consumption. Turn-on sequencing of the regulators was, therefore, added to minimize FPGA
start-up current draw. The sequencing was accomplished by RC networks connected to the
regulator enable pins, seen in Fig. 5.5, where the delay is determined by the rise-time of the
supply voltage, calculated using (5.1). The optimal turn-on sequence is shown beside the
designed turn-on sequence in table 5.3.
τr = R ¨ C
(5.1)
26
5.6. Power management
Table 5.3: Optimum and designed power-on sequence for the different power nets.
1
2
3
4
5
6
Optimum
VCCI NT
VMGTAVCC
VGTAVTT
VCCBRAM
VCCAUX
VCCO
Design
VCCI NT , VCCBRAM
VCCAUX
VMGTAVCC
VGTAVTT
VCCO
The designed sequence does not follow the optimum sequence but intends to solve the
most critical parts which are the transceiver analog supply voltage, VMGTAVCC , and its termination voltage, VMGTAVTT .
Figure 5.5: Power-on sequencing using RC networks.
The nPOR pin of the PMIC is a power-good indicator. It is driven low when either of the
buck regulators is below 92 % of their desired output voltage. When the output is considered
stable, there is a 60 ms delay until nPOR is pulled high. The power-good signal is used to
enable the two FPGA I/O bank voltages through an N-MOS transistor and an enable signal,
illustrated in Fig. 5.6.
27
5.6. Power management
Figure 5.6: I/O voltage sequencing and selectable I/O voltage solution.
I/O voltage regulation
FPGA I/O voltage is regulated by a stand-alone adjustable LDO. The adjustability is achieved
using software controlled feedback networks, illustrated in Fig. 5.6. The voltage of the I/O
regulator is controlled by resistor dividers, where the voltage is calculated using (5.2).
R1
), Vre f = 0.55
(5.2)
R2
The divider network essentially alters the R2 value. Since the GPIOs are tri-state capable,
a single resistor divider can be selected by setting one output to LOW while the rest are high
impedance (High-Z), resulting in the pattern described in Table 5.4.
Vout,LDO = Vre f ¨ (1 +
Table 5.4: Regulator SET_IO state to voltage relation.
SET_IO_1V8_N
High-Z
High-Z
High-Z
LOW
SET_IO_2V5_N
High-Z
High-Z
LOW
High-Z
SET_IO_3V3_N
High-Z
LOW
High-Z
High-Z
VCCO_15_34_ADJ [V]
1.2
1.8
2.5
3.3
Passive components
The PMIC circuit and selection of external components was based on the Typical Application
design provided in its datasheet. The datasheet also presents a formula for calculating the
output voltages of the four individually controlled regulators, seen in (5.3) [21].
Vout = Vre f ¨
R2
, V = 0.5
R1 + R2 re f
(5.3)
External components were selected to suit the output voltages and their approximated
current draw. Special consideration were taken into capacitor DC-bias and inductor current
saturation. The ripple and peak currents of the SMPS are highly dependent on the output
28
5.6. Power management
filtering components. Equations (5.4)-(5.8) are provided by TI[21, p.27]. They allow the designer to predict the current and voltage ripple based on filtering components selection, expected current draw and switch frequency. Table 5.5 shows the current ripple that can be
presumed for the design.
IL,peak = Iout,max +
Iripple =
Iripple
2
(5.4)
Vout Vin ´ Vout
¨
Vin ¨ η
L¨F
(5.5)
Iripple
8 ¨ F ¨ Cout
(5.6)
VCout =
(5.7)
VRout = Iripple ¨ ESRCout
Vout,p´ p =
b
2
2
VCout
+ VRout
(5.8)
Table 5.5: Calculated values for Peak Current through the inductor and voltage ripple on the
output, using: Vin = 3.3V, η = 0.85, Iout,max = 0.8A, Cout = 10µF, L = 2.2µH, f = 2MHz.
Parameter
IL,peak
Vout
Condition
Vout
Vout
Vout
Vout
= 1.0V
= 1.2V
= 1.0V
= 1.2V
ESRCout [Ω]
0.05
0.01
0.89
0.90
18.67 9.39
2.20
20.46 10.29 2.41
0.1
Unit
A
mV
Another aspect that was considered was the effect of DC-bias on the capacitors in the
system. DC-bias causes the capacitance of a capacitor to decline. The extent of the effect
varies greatly between different types of capacitors but a ceramic X5R capacitor usually has
a curve similar to Fig. 5.7[22]. The main difference is where the capacitance starts declining
rapidly, this is not necessarily related to the voltage rating of the capacitor. To reduce the
overall amount of different components in the system, any capacitor used in the design had
to maintain at least 90 % of its nominal capacitance at 3.3 V. This makes it possible to use the
same value capacitors anywhere in the design.
Figure 5.7: Characteristic change of capacitance according to DC-voltage.
The Equivalent Series Resistance (ESR) of the capacitors was also examined. However, since
all capacitors were of relatively small capacitance, ceramic capacitors with naturally low ESR
were selected. The ESR could, consequently, be neglected in this application.
29
5.7. Programming and debugging interface
Layout
The four copper layers of the PCB were divided into multiple sections to distribute the voltages efficiently. Power pins of the FPGA with the same voltage are often grouped together in
the footprint, illustrated in Fig. 5.8.
VCCI NT , VMGTAVTT , VMGTAVCC , VCCO , VCCBRAM , VCCAUX , GND
b Bank 0, b Bank 14, b Bank 15, b Bank 34, b Bank 216 (Transceivers)
Figure 5.8: Artix-7 FPGA power pin mapping.
A suitable solution was to form a number of voltage planes confined in the inner layers
of the PCB. Sections where a specific voltage was frequently used, were made larger to maximize inter-plane capacitance to adjacent ground planes. Vias connect the inner and outer
layers together to distribute the power between connectors and components. Ground planes
on multiple layers provide a low impedance connection to the regulator.
The layout of the PMIC and the LDO originates from the Layout Examples provided by TI
[23][21].
5.7
Programming and debugging interface
There are two parts tied to the programming interface. Firstly, JTAG, which is connected directly to the programming pins of the FPGA. It is used for configuration as well as debugging.
Secondly, the SMBus interface, which is used to program the NVM through a SMBus to SPI
bridge. Upon start-up of the FPGA, it reads the NVM and loads the stored bitstream into its
volatile memory. It was desired to have the possibility to program the memory through the
SMBus, so that the bridge bitstream may be updated through the platform it is connected to.
30
5.8. Decoupling
Layout
The components of the programming interface that were connected to the SMBus were placed
close to the M.2 connector together with the SMBus level converter, marked by the orange box
in Fig 5.9. The flash memory, SPDT and JTAG connector were all placed close to the FPGA to
reduce the routing complexity, marked by a red box.
Figure 5.9: Programming and debugging interface with related components marked.
5.8
Decoupling
In order to ensure that the design operates as expected, proper decoupling is required. The
decoupling network consists of capacitors and provides a temporary energy reservoir during
current surges. A general rule of thumb when designing decoupling networks is to place
smaller value capacitors closer to the circuit and to increase the amount when the capacitance
decreases (the amount of capacitors is usually doubled when the capacitance is decreased by
a factor 10).
Xilinx provides recommendations for decoupling networks when designing with their
FPGAs. The amount of capacitors depend on the footprint and number of LUTs. The design
should be compatible with devices as dense as XC7A35T, the footprint is however considered constant since a change in footprint would require redesigning the PCB. The PCB was
designed to accommodate the XC7A35T since the XC7A12T requires less decoupling and any
extra components can be omitted during mouting.
Table 5.6: Artix-7 Decoupling network for XC7A12T and XC7A35T
The recommended decoupling networks for 80 % of LUTs and registers at 245 MHz, 80 %
block RAM and DSP at 491 MHz, 50 % MMCM and 25 % PLL at 500 MHz, 100 % I/O at SSTL
1.2/1.35 at 1,200/800 MHz[24, p.15-16].
VCCO
VCCO
VCCI NT
VCCBRAM VCCAUX
Bank 0 (Others, per bank)
Capacitance,
100 4.7 0.47 47 0.47 47 4.7 0.47 47
47 4.7 0.47
uF
XC7A12T
1
1
2
1
1
1
1
2
1
1
2
4
XC7A35T
1
2
3
1
1
1
2
3
1
1
2
4
The PCB Design Guidelines also state that banks that share a common voltage feed may
also share bulk (47 uF) capacitor[24, p.15, note 3]. This reduces the total amount since the I/O
banks share feed. In order to reduce the amount of different components, all 47 uF capacitors
31
5.8. Decoupling
were replaced with 100 uF since changing the bulk capacitor to a larger value should not
affect the performance notably.
The VMGTAVCC and VMGTAVTT supplies are described in a separate guide targeted specifically at the GTP transceivers. Xilinx recommend using one 4.7 uF and two 0.1 uF 10 % ceramic
capacitors for power supply filtering for each of the supplies[18, p.230].
Layout
The main consideration during layout of the decoupling network was that small value capacitors should have a low-impedance connection to its related power pin. This was achieved by
moving the capacitors under the FPGA and having a dedicated set of vias for each capacitor.
The latter consideration may not seem like it would matter much, but sharing vias between
several capacitors increases the impedance of the path. It generally considered bad practice
for high frequency designs.
32
6
Manufacturing
Manufacturing is a key phase of this degree project. In this chapter, main aspects of this
process are presented and discussed. They will cover the manufacturing and testing of the
PCB, as well as the electrical interfaces.
6.1
Bill of materials
A Bill of Materials (BOM) is a list of components used to manufacture a product. The list
includes the necessary data to correctly designate every part in a project, which involve designator, value and part number. The most convenient solution to successfully generate the BOM
is to supply every component with the required information and let the PCB CAD software
compile it automatically.
6.2
Assembly and soldering
The first prototypes were assembled and soldered at Linköping University. A solder stencil
was used in combination with solder paste to deploy a thin layer onto the pads of the PCB.
The components were placed on the PCB and solder in a soldering oven.
During assembly, the XC7A12T was exchanged for a larger variant, XC7A35T. The devices are pin-compatible and the larger device was used to ensure that there was enough
configuration space. In the final design, the bridge may be fitted with whatever device fits
the implementation bitstream.
6.3
Tests and inspection
During and after assembly, the board had to be tested to verify that all components functioned as expected. A test plan was created in order to ensure that no important functionality
remained untested. Since every design is different, the test plan is usually tailored to the design. The test plan used is presented in Appendix C. This section will discuss the tests, with
focus on tests that were skipped or failed.
33
6.3. Tests and inspection
Pre-component mounting
It was to no surprise that the PCB passed all 1.1.x tests since the manufacturer tests the PCB
using a flying-probe technique. The trace impedance test was skipped since it required more
advanced measuring equipment than what was at hand during testing.
Post-component mount
The purpose of these tests was to verify that no nets had been shorted during component
soldering and that the regulators would present the correct voltage when power is applied to
the board.
PCB under power
These test were designed to verify that the design performed as expected when not configured. The current draw is measured to see if it is reasonable. An excessive current draw, over
1 A, could indicate that something is shorted or malfunctioning. Point 1.3.1 was passed with
a standby current of around 86 mA. All voltages except VCCO_0_3V3 was within a couple mV
of spec. The cause and solution of the deviation is described later in this section.
A few problems were encountered during the tests. The first was that the sequencing was
not as expected. Both bank voltages VCCO_0_3V3 and VCCO_14_35_ADJ briefly started at poweron, powering off after a few milliseconds. The cause was believed to be the nPOR signal being
pulled high before the core logic in the PMIC had drawn it low. To remedy the problem, a
shunt capacitor was added to the nPOR net, the charge time for the capacitor was long enough
to hold the signal low until the PMIC could pull it low.
The second problem was that VCCO_0_3V3 only reached about 2.5 V. The cause was that
when the NMOS which lets power through to the net does not fully open since the source
node reaches the same potential as the gate. The fix was to connect VCCO_0_3V3 directly to
VCC_3V3 . The drawback is that the power sequence is no longer correct, causing a slightly
higher current draw at power on. The problem could also be fixed by using a load switch circuit, such as the one shown in Fig. 6.1. Such a solution would work as intended but requires
more components. For testing, connecting VCCO_0_3V3 to V3V3 was considered adequate.
Figure 6.1: Load switch schematic
A third problem was that the four voltages sourced from the PMIC started simultaneously.
The cause was most likely that the capacitors used for power sequencing charged to logic
HIGH before the PMIC had started. Since the only consequence of powering on all nets at the
same time is a higher current draw at power on, no action was taken to correct the problem.
34
6.3. Tests and inspection
In order to improve the power sequencing in future designs, a power sequencer could be
used. The drawback is that the design becomes more complex and requires more components.
FPGA system
These tests aimed to verify that all important signal connections to the FPGA had been properly soldered. Note that this section does not cover the PCI Express nets, as they were tested
separately.
The JTAG connectivity was verified by connecting a debugger and seeing that the device
appears in the debug environment.
To verify that all LVDS/CMOS pins were connected to their respective pins, a shift register was implemented in VHDL. By connecting the shift register to the pins and sending a
single ’1’ through it, all pins could be set high one at the time. By measuring the voltage at
the LVDS/CMOS header, it was possible to verify that all pins were properly isolated and
connected.
To verify the LDO voltage level control, each state of the configuration presented in Table 5.4 was tested.
All 2.1.x points were passed.
SMBus
For the SMBus tests, a SMBus master was connected to the 3.3 V side of the level converter.
The reason for not connecting it to the 1.8 V side was that the conversion had already been
verified and the masters at hand during testing operated at 3.3 V.
Point 2.2.1 and 2.2.3 were done by performing an enumeration of the SMBus and verifying
that the devices were being properly enumerated. Both passed.
Point 2.2.2 was tested by writing data to the EEPROM and reading it back. If the write
and read data is identical, the point was passed. The same test was done the check point
2.2.5, the difference being that the communication to the FLASH memory is done through
the SMBus-SPI bridge.
2.2.4 was verified by writing to the registers on the bridge that control the GPIOs and
checking that they behave as expected.
PCI Express
The PCI Express connection was verified by inserting the bridge in an M.2 connector and
uploading the "AXI Memory mapped to PCI Express" IP core to the FPGA through JTAG. If
the device was recognized by the operating system, the test was passed.
Initially, the device did not appear in the OS, indicating that there was something wrong
with either the IP core or the electrical connections. The PCI Express signals related to the
reference clock were probed on both the bridge and a third party M.2 module that was known
to function. It was immediately apparent that the reference clock was absent on the bridge.
The fault was that the CLKREQ pin on the M.2 connector of the bridge had been left floating
during design, when it should have been shorted to ground. The problem was corrected by
soldering a jumper from the pin to an exposed ground pad on the bridge.
After the fix, the reference clock appeared on the bridge and the platform was able to
enumerate it properly. The differential reference clock signal that was measured on the bridge
after the fix is shown in Fig. 6.2.
35
6.3. Tests and inspection
Figure 6.2: Reference clock differential signal measured on the bridge.
The Linux command lspci -vv was used to verify that the device had been enumerated
by the system. The console output is displayed in Fig. 6.3, where the LnkSta field shows that
the link operates at 5 GT/s in an x2 configuration.
Figure 6.3: PCI Express link lists the capabilities of the bridge.
36
7
Software
This chapter describes the developed software for each subsystem of the bridge. Each component requires a certain software coded in a certain programming language. These parts of
the bridge must work together to deliver the desired functionality within specifications.
7.1
EEPROM memory verification
The purpose of this software was to verify that the ID memory could be written and read
back by a SMBus master. The software was developed mainly in Python targeted towards a
Raspberry Pi. The code attempts to clear the memory and rewrite it with a text string. The
memory is then read back to show if it was properly programmed. In order to program the
ID memory, the write protect test pad in the design should be pulled to ground potential. The
program flow can be broken down to three major actions:
1. Clear ID Memory by writing ’0xFF’ to all memory addresses
2. While address is smaller than memory size and not at end of file:
• Send a packet of data to the memory
• Increment address counter
3. Read back memory
If the write protect pin was pulled low, and the EEPROM functions as intended, the data
that is read back should be the same as what was sent. If the write protect is not pulled low, the
read back data will be whatever was present on the memory prior to the write. The console
output following a successful write to the EEPROM is shown in Fig. 7.1.
37
7.2. Flash memory interfacing
Figure 7.1: Console output after a successful write to the EEPROM.
An interesting point, related to the functionality of the EEPROM is how it presents itself
on the SMBus. Read/write operations on SMBus usually consist of two bytes, followed by
the actual data that is to be sent to the device. The first byte is an address and read/write bit,
telling the devices on the SMBus what device the master wants to interface with. The second
byte is a command whose function is usually defined by the manufacturer and provided in
the device-specific datasheet. In the case of the EEPROM, the second Byte is the address that
the master wants to read from or write to. However, since it is a 4 kBit / 512 Byte memory
it cannot be addressed using a single command Byte. Instead the memory presents itself at
two addresses, one for each half of the memory. This is confirmed by running i2cdetect
on the Raspberry Pi when the bridges SMBus is connected. i2cdetect attempts to write to
all possible device addresses and displays the devices that respond, meaning that they are
present on the bus. The result is shown in Fig. 7.2.
Figure 7.2: Enumeration of the SMBus of the bridge. Notice the SMBus-SPI bridge at ’0x28’
and the EEPROM at ’0x50’ and ’0x51’.
7.2
Flash memory interfacing
As with the ID Memory, the flash memory interface software is also written on a Raspberry
Pi. The purpose of the software is to write an entire bit stream to the configurations memory
over SMBus. As described earlier, the SMBus does not connect directly to the configuration
38
7.2. Flash memory interfacing
memory. Instead, it communicates through a SMBus-to-SPI converter. The bridge introduces
some limitations that need to be taken into consideration during read/write of the configuration memory. The first is that the bridge only has a buffer size of 256 bytes, limiting the
amount of data that can be received before a transmission is required. The second limitation
is that while the bridge has multiple signal pins that may be used as both chip select (CS) or
as a GPIO, it required that at least one is configured as chip select in order for the bridge to
transmit any data. The fact that the CS pin is automatically pulled low and high when transmitting data in conjunction with the small buffer size causes problems when interfacing with
the configuration memory since it expects large (256+ bytes) packets.
Ideal transfer
Ideally, the buffer size of the bridge would not influence the transfers. Commands and data
transfers would be sent as complete packages, regardless of the size of the package. The
signal for such a solution is displayed in Fig. 7.3. This solution would greatly decrease the
complexity of the configuration procedure. However, since the bridge is limited by its fixed
buffer size and the CS pin is automatically controlled, such a solution is only possible for
sub-256 Byte packages. Note that the DONE signal is not used and should be configured as an
input on the bridge. The SPI signal symbolizes that there is ongoing activity on the MISO,
MOSI and CLK signals.
Figure 7.3: Ideal SPI data transfer.
1. IN pulled LOW, connecting bridge to configuration memory.
2. CS pulled LOW, to indicate start of transfer.
3. The entire data package is sent over SPI interface.
4. CS pulled HIGH, indicating end of transfer.
5. IN pulled HIGH, reconnecting FPGA to configuration memory.
6. (optional ) Program_B pulsed LOW, loads new configuration to FPGA.
Using the built-in CS pin
The second solution would be to transfer data in smaller packets. This eliminates the problem
of the buffer size but significantly increases the amount of overhead needed for addressing
and command declaration to the memory. The signal timing for such a solution is shown
in Fig. 7.4. Note that package size is limited to a maximum of 256 bytes by the bridge, but
may be further limited by SMBus buffer size in the SMBus master. Again, the DONE signal is
unused and should be configured as an input on the bridge.
39
7.2. Flash memory interfacing
Figure 7.4: SPI data transfer using the built-in CS pin feature.
1. IN pulled LOW, connecting bridge to configuration memory.
2. Data packages are transferred over SPI, with the CS pin going HIGH between packages.
3. IN pulled HIGH, reconnecting FPGA to configuration memory.
4. (optional ) Program_B pulsed LOW, loads new configuration to FPGA.
Final solution
The solution that was implemented was to use one of the other GPIO pins as a "dummy" CS,
specifically the DONE signal. This solution strives to replicate the ideal transfer solution as
closely as possible from a signal perspective. The signal timing is displayed in Fig. 7.5.
Figure 7.5: Final SPI data transfer implementation.
1. IN pulled LOW, connecting bridge to configuration memory.
2. Program_B pulled LOW, unloading any configuration from the FPGA.
3. CS pulled LOW, to indicate start of transfer.
4. Data packages are sent over SPI interface.
5. CS pulled HIGH, indicating end of transfer.
6. IN pulled HIGH, reconnecting FPGA to configuration memory.
7. Program_B pulled HIGH, loads new configuration to FPGA.
The DONE pin was a good candidate because it has a series resistor that limits any currents and it has no effect on the system when the Program_B signal is LOW. The real CS can
then be configured as a GPIO, and controlled manually through software allowing much
larger continuous transactions to the configuration memory. The drawback is that the FPGA
loses its configuration when new bit streams are loaded into memory. This trade-off was
considered acceptable since uploading a new bit stream to the configuration memory implies
that the "old" configuration will no longer be used.
40
7.3. FPGA firmware
7.3
FPGA firmware
The VHDL developing environment used to create the FPGA firmware was Xilinx Vivado Design Suite HLx 2018.3. It features simulation, debugging and numerous Intellectual Property
(IP) cores, which are pre-programmed blocks that may be used to accelerate development. A
block design structure was used to create the firmware in VHDL. A simplified view of the
block design is shown in Fig. 7.6
Figure 7.6: Overview of the VHDL block design.
AXI4 Protocol
The AXI protocol is a part of ARM AMBA, which is a series of microcontroller bus standards
initially introduced in 1996 and developed by ARM. AXI4 is the second version of the protocol and exist in three variations [25]:
• AXI4, High-performance memory mapped
• AXI4-Lite, Simple, low throughput memory mapped
• AXI4-Stream, High-speed data streaming
Xilinx adapted AXI4 when they introduced the Spartan-6 and Virtex-6 family devices as
the preferred communication protocol between IP cores. The VHDL solution developed in
this thesis uses a combination of AXI4 and AXI4-Lite interfaces. Each block that utilizes the
AXI-bus gets a dedicated address span. The AXI protocol is used for point to point communication, from master to slave, with a focus on high performance. If it is desired to connect
multiple slaves to a single master, or vice versa, an AXI interconnect can be used to separate
the transmissions.
PCI Express
The PCI Express functionality was implemented using the IP core AXI Memory Mapped to PCI
Express. The core functions as an interface between PCI Express and AXI4. It translates the
PCI Express transaction layer packets (TLPs) to AXI4 memory read and writes. Likewise, PCI
Express memory read or write TLPs are translated to AXI4 interface commands [26]. Data is
mapped to the platform memory using Block Address Registers (BARs). A BAR holds the
address to the data of a particular VHDL block. The BAR contains the necessary information
to accurately route the data from PCI Express to AXI4 through the address translation and
ensures that the data ends up at the correct destination.
The IP core has a series of inputs and outputs which has to be constrained to the physical
ports of the FPGA associated with the M.2 PCI Express pins. Once the device is programmed
and the platform device requests a PCI Express enumeration, the device’s PCI Express Endpoint functionality is detected. The correct configuration (PCI Express Gen 2 x2), reported by
the platform system, indicates that the link operates as anticipated.
41
7.3. FPGA firmware
Clock Buffers
The PCI Express link requires a reference clock, provided through the M.2 as a part of the PCI
Express standard. The clock signal originates from a differential source and needs additional
buffers to bring the off-chip signals to the internal circuitry. A Utility Buffer IP is used to
convert the differential inputs into a buffered single-ended clock signal. This signal can be
connected directly to the reference clock input of the PCI Express IP.
Block RAM
A block RAM (BRAM) is used to store data. It is part of the FPGA and has varying sizes
between FPGAs. The purpose of the BRAM in this thesis is to act as a FIFO buffer. The
BRAM is configured to have two ports, Port A and Port B. Both ports have access to the same
data with individual clocks. The idea is to connect the writing interface to Port A, while Port
B is used to read the data to the GPIOs. The data is loaded through the PCI Express to AXI4
link, on an address location specified by the user. The Block RAM is generated by the IP Block
RAM Generator, which allocates a set amount of space and automates memory optimizations.
The BRAM connects to the AXI4 interface through a Block RAM Controller IP, which translates
AXI4 to the BRAM interface and provides direct access to the memory via AXI4.
Custom IP
A custom IP block was needed to test the functionality of the PCI Express Bridge. The logic of
the IP block has three main objectives; read a control register from the AXI-bus, read the data
register and shift the data on the output. The implementation, therefore, requires AXI communication with custom logic. Fortunately, Vivado includes a utility to easily create custom
AXI peripherals, which takes care of the AXI communication and leaves the user to implement the custom logic.
The data rate of the output is selectable through a configurable PLL. This clock output is
synchronized with the data, resulting in synchronous serial communication, perfectly fitted
for a test application. The selectable output frequency is used to test the maximum transmission rate on the GPIO outputs.
By setting a high data rate and modifying the transmitted data, it was possible to
measure the performance of the LVDS/CMOS side. By having a 400 MHz data rate
and sending 1111000011110000..., the bridge would generate a 50 MHz square wave.
110011001100... would generate a 100 MHz square wave. The maximum frequency that
was tested was 200 MHz.
Constraints
Constraints exist to inform the FPGA of each pin’s behavior. They are used to constrain the
internal ports to the external pins of the FPGA. Additionally, they can be used to set direction, terminations, and voltage levels. Certain pins are designed to operate certain functions.
Constraints covering these pins are, therefore, restricted.
Simulation and Debug
The Vivado design suite offers the creator to simulate individual blocks or the entire firmware
without synthesizing or implementing the design, which enables faster developing. The simulation utility interprets the behavior of the blocks and presents the input and output signals
and their values. The debug core displays the signal values in a similar style but are instead
running on the actual FPGA instead of in a simulator. An IP called Virtual Input/Output
(VIO) is a part of the debug utility and lets the user set or read specific ports in real time.
42
7.4. Platform application
Test application
The functionality is going to vary based on future applications, but the device should have
the capability to output Serial based protocols at reasonable speeds. Consequently, as a test
application, the user should enter data to a register on the platform system. Once the data
is set, the user defines the number of bytes to be clocked out and triggers the event through
a control register. The FPGA uses a separate clock signal to clock out the data, bit by bit, at
the desired rate. The application should read the data on a separate pin and verify that the
input matches the output. The result should present an indication of the maximum obtainable
throughput possible on the GPIO side.
7.4
Platform application
Every PCI Express device retrieves a base address upon enumeration. The base address
spans the necessary length to include all addressable memory as defined within the FPGA.
If the BAR is configured to point to a specific block at address 0x00001000 and the base
address defined by the platform system is 0x80300000, the resulting memory location is
0x80301000. This memory corresponds to the physical memory of the platform, rather
than the virtual memory. The location of the physical memory is on the platform’s RAM,
while the virtual memory is located at the hard drive. The capacity is, therefore, limited by
the RAM volume on the platform device. The physical memory is directly accessible from
Linux through \dev\mem, as seen in Fig. 7.7. An operation which writes a value to the
resulting address above can be used to trigger an event inside the FPGA. Once a value to
a specific register is written, the FPGA can respond to the operation and perform an action
based on the content of the value.
Figure 7.7: Platform application writing to register and validates its value.
43
8
Results
This chapter will present the results of this thesis. The results cover the PCB layout and
the measured performance of the bridge. The chapter will also summarize the hardware
modifications that were made to the bridge after the components had been mounted. A brief
summary of the bridge size and performance is presented in Table 8.1.
Table 8.1: Summary of bridge dimensions and performance
Property
Dimensions (Width x Length)
M.2 connector keying
Height (above PCB)
Height (below PCB)
Max transfer rate (PCI Express)
Link width
Max data rate (PCI Express)
Max data rate (LVDS/CMOS)
Number of GPIOs
8.1
Value
22x80 mm
M-key
4.9 mm
0.9 mm
5 GT/s
x2
8 Gb/s
200 Mb/s per pin
20 Single ended or 10 Differential
PCB Layout
The PCB consists of a 4 layer stackup. The layers are presented below.
Figure 8.1: Layout – Top Layer
44
8.2. Bridge performance
Figure 8.2: Layout – Inner Layer 1
Figure 8.3: Layout – Inner Layer 2
Figure 8.4: Layout – Bottom
8.2
Bridge performance
The PCI Express side of the bridge behaves as expected with it being recognized by the platform as a PCI Express 5GT/s x2 device. With the 8/10 bit encoding employed by PCI Express,
this results in a max transfer rate of 8 Gb/s. The temperature of the Artix-7 as measured by
the Vivado IDE was consistently lower than 75o C.
As seen in Fig. 8.5-8.6 the LVDS/CMOS side was able to output waveforms at up to 200
MHz.
45
8.3. Summary of hardware modifications
Figure 8.5: Output signal at 100 MHz.
Figure 8.6: Output signal at 200 MHz.
Unfortunately, it proved difficult to measure the latency of the bridge. The main reason
being that the PCI Express link frequency at 5 GHz was too high to measure using any of the
instruments at hand.
8.3
Summary of hardware modifications
This section will summarize the hardware modifications that were done to the bridge after
it had been assembled. These changes were necessary for the bridge to boot and behave as
expected.
46
8.4. Software design
The nPor fix
The first hardware modification was the "nPor fix". It included fixing the VCCO,3V3 voltage
level as well as modifying the power-up sequence. The problem and cause is described in
greater detail under section 6.3. Fig. 8.7 displays the fix both in Altium designer and on the
PCB.
Figure 8.7: the nPor fix. Right: Altium designer screenshot with the modifications, Left: Same
modification on the PCB.
The reference clock fix
The second modification will be referred to as the reference clock. During design, the CLKREQ
pin on the M.2 connector was left floating. Its purpose is to tell the master device that there
is a PCI Express device connected and that it requires a reference clock. The pin should have
been connected directly to ground. A small wire was soldered to the pin and an unused
ground pad on the bridge. The fix is shown in Fig. 8.8. The two black wires at the bottom left
of Fig. 8.8 are for SMBus debugging and are not necessary in the final product.
Figure 8.8: The CLKREQ fix. Right: Altium designer screenshot with the modification, Left:
Same modification on the PCB.
8.4
Software design
PCI Express commands are sent from the platform through PCI Express, translated to AXI
and stored in a FIFO buffer. A series of control register bits are used to initiate a transmission
which forwards data to the GPIOs. Fig. 8.9 shows a simulated signal of the output signals
from Vivado. The real output signals, measured by a logic analyzer, is illustrated in Fig. 8.10
47
8.4. Software design
Figure 8.9: Signals; TX ready, data request, data in, data out, clock and state.
Figure 8.10: Output signals; data and clock.
48
9
Discussion and conclusion
This chapter will discuss the component choices, implementation, and future improvements
of the PCI Express Bridge.
9.1
Design requirements and research questions
The final design manages to fulfill all design requirements with the exception of the latency,
which was not measured. It has a PCI Express Gen 2 x2 interface, one generation better than
the specified Gen 1. The LVDS/CMOS interface is capable of communicating at speeds up to
200 MHz on multiple pins simultaneously and independently. As for the physical size of the
bridge, it is within the 22x80x0.8 mm requirement and fits any standard M.2 expansion slot.
The bridge runs at a slightly high 75o C without air flow but the temperature does not appear
to rise further under load.
It was unfortunate that the latency proved difficult to measure. Since both the PCI Express and internal AXI are high-speed interfaces, the latency through the system should be
low. It may be possible to measure the delay using internal signals in the FPGA or with better measuring equipment, but it was of greater interest focus on the software and enhance
functionality.
As for the research questions, the prestudy concluded that the use of an FPGA was the
best solution since it introduces very little delay and allows for high throughput on multiple
channels.
9.2
Implementation
The bridge works, with minor modifications, as expected. The bridge can accept commands
sent through PCI Express and perform pre-programmed actions specified in its firmware.
The minor modifications are related to the power sequence functionality and PCI Express
clock reference request. They are solved by performing the fixes described in Section 8.3.
The software is implemented to test the bridges functionality. Further development, to
fully implement the desired protocols, is required. The current firmware can load and transmit data sent over PCI Express. A desired improvement would be to add the ability to receive
data on the LVDS/CMOS interface and sent it over PCI Express.
49
9.2. Implementation
The bridge is using a general purpose pin header for the inputs and outputs. The solution
is universal, adaptable, and works for low to medium speed applications. Applications which
operate at a high frequency might require special connectors with sufficient shielding and
controlled impedance to improve the signal integrity and noise sensitivity. Changes to the
bridge layout should be made to suit specific requirements or applications.
A benefit of the current design is that the interface that is used internally is the well established AXI interface. Any further development on the bridge can be targeted towards
AXI, rather than a device specific PCI Express implementation. This greatly decreases the
complexity of the solution.
50
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[15] [DS180] 7 Series FPGAs Data Sheet: Overview, v2.6. Page 3-6. Xilinx Inc. 2018.
[16] [UG470] 7 Series FPGAs Configuration User Guide, v1.13.1. Xilinx Inc. 2018.
51
Bibliography
[17] Power-Supply Solutions for Xilinx FPGAs. Maxim Integrated. URL: https : / / www .
maximintegrated.com/en/app-notes/index.mvp/id/5132.
[18] [UG482] 7 Series FPGAs GTP Transceivers User Guide, v1.9. Xilinx Inc. 2016.
[19] [SNVS543N9] LM26480 Dual 2-MHz, 1.5-A Buck Regulators and Dual 300-mA LDOs With
Individual Enable and Power Good. Texas Instruments. URL: www . ti . com / lit / ds /
symlink/lm26480.pdf.
[20] [DS181] Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics, v.1.25. Xilinx Inc.
2018.
[21] [SNVS543N] LM26480Dual 2-MHz,1.5-A Buck Regulators and Dual 300-mA LDOs With
Individual Enable and Power Good, Rev. N. Page 25-27, 28-30. Texas Instruments Inc. 2016.
[22] Murata. Ceramic Capacitors FAQ. URL: https : / / www . murata . com / en - sg /
support/faqs/products/capacitor/mlcc/char/0005.
[23] [SBVS351C] TLV758P 500-mA, high-accuracy, adjustable LDO in a small size package, Rev.
C. Texas Instruments Inc. 2019.
[24] [UG483] 7 Series FPGAs PCB Design Guide, v1.13. Xilinx Inc. 2017.
[25] AXI Reference Guide. Xilinx Inc. URL: https : / / www . xilinx . com / support /
documentation/ip_documentation/ug761_axi_reference_guide.pdf.
[26] AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8. Xilinx Inc. URL: https://www.
xilinx.com/support/documentation/ip_documentation/axi_pcie/v2_
8/pg055-axi-bridge-pcie.pdf.
52
Appendix A
Comparison Chart
Manufacturer
Product name
Price (USD)
PCIe support
Logic element/cells
Footprint (Pitch & Type)
Size (BxH)
GPIOs
I/O-voltage
GPIO Speed
(Single-ended)
Lattice
ECP2 (LFE2M20E-5FN256C)
41
Gen1 x4
19K
1 mm BGA
17x17
140
1.2V-3.3V
311 MHz
Lattice
ECP3 (LFE3-17EA-6FTN256C)
18
Gen1 x4
17K
1 mm BGA
17x17
133
1.2V-3.3V
500 MHz
Lattice
ECP5 (LFE5UM-25F-8BG381C)
15
Gen1 x4
24,000
0.8 mm BGA
17x17
197
1.2V-3.3V
150 MHz
400 MHz
Lattice
ECP5 (LFE5UM-45F-8BG381C)
26
Gen1 x4
44K (Upp till 85K)
0.8 mm BGA
17x17
203
1.2V-3.3V
150 MHz
400 MHz
4
No
Lattice
ECP5-5G (LFE5UM5G-25F-8BG381C)
19
Gen2 x2 soft
24K (Upp till 85K)
0.8 mm BGA
17x17
203
1.2V-3.3V
150 MHz
400 MHz
4
Yes
Lattice
ECP5-5G (LFE5UM5G-45F-8BG381C)
31
Gen2 x2 soft
44K (Upp till 85K)
0.8 mm BGA
17x17
203
1.2V-3.3V
150 MHz
400 MHz
2
Yes
Xiilinx
Artix-7 (XC7A12T-2CSG325)
36
Gen2 x2
8k
0.8 mm BGA
15x15
150
1.2V-3.3V
200 MHz
1250 Mbps
2
Yes
Xilinx
Artix-7 (XC7A25T-2CSG325I)
47
Gen2 x4
25K (Upp till 50K)
0.8 mm BGA
15x15
150
1.2V-3.3V
200 MHz
1250 Mbps
4
Yes
Xilinx
Artix-7 (XC7A15T-2CSG325C)
47
Gen2 x4
16K (Upp till 50K)
0.8 mm BGA
15x15
150
1.2V-3.3V
200 MHz
1250 Mbps
4
Yes
Xilinx
Artix-7 (XC7A100T-1FGG484)
70
Gen2 x4
101K (Upp till 215K)
1 mm BGA
23x23
250
1.2V-3.3V
200 MHz
1250 Mbps
4
No
Xilinx
Spartan-6 (XC6SLX25T-N3CSG324C)
46
Gen1 x2
24K
0.8 mm BGA
15x15
190
1.5V-3.3V
1060 Mbps
2
No
Cheaper alternative with better
performance
Xilinx
Kintex-7 (XC7K70T-1FBG484)
150
Gen2 x8
65K (Upp till 160K)
1 mm BGA
23x23
285
1.2V-3.3V
4
No
Expensive, Too big
Xilinx
Kintex Ultrascale Plus (XCKU3P-1SFVB784E)
1,000
Gen3 x16
356K
0.8 mm BGA
23x23
304
1.0V-3.3V
16
No
Expensive, Too big
Xilinx
Virtex Ultrascale Plus (XCVU3P-1FFVC1517E)
9,000
Gen3 x16
862K
1 mm BGA
40x40
520
1.0V-3.3V
40
No
Expensive, Too big
Xilinx
Virtex-7 XT (XC7VX330T-1FFG1157C)
2,500
Gen3 x8
326K
1 mm BGA
35x35
600
1.2V-3.3V
20
No
Expensive, Too big
Intel
Cyclone IV (EP4CGX30CF19C8N)
64
Gen1 x4
29K
1 mm BGA
19x19
150
1.2V-3.3V
200 MHz
848 Mbps
4
No
Expensive price/performance
(Gen1 PCIe)
Intel
Cyclone 10 GX (10CX085YU484I6G)
100
Gen2 x4
85K
0.8 mm BGA
19x19
188
1.2V-3.0V
200 MHz
1.4 Gbps
6
No
Expensive
Intel
Cyclone 10 GX (10CX220YF780E5G)
260
Gen2 x4
220K
1 mm BGA
29x29
284
1.2V-3.0V
200 MHz
1.4 Gbps
12
No
Expensive, Too big
Intel
Arria V GX (5AGXMA5G4F35C4G)
1,000
Gen2 x4
75K (Upp till 504K)
1 mm BGA
27x27
336
1.2V-3.3V
200 MHz
1.6 Gbps
9
No
Expensive, Too big
Intel
Stratix V GX ( 5SGXMA3E3H29C4N )
2,000
Gen3 x8
340K
1 mm BGA
29x29
360
1.2V-3.0V
167 MHz
1.6 Gbps
12
No
Expensive, Too big
Intel
Arria V GZ (5AGZME1E3H29C4N)
1,500
Gen3 x8
220K (Upp till 450K)
1 mm BGA
29x29
342
1.2V-3.3V
200 MHz
1.6 Gbps
12
No
Expensive, Too big
Microsemi
SmartFusion2 (M2S010T-1VF400)
36
Gen2 x4
12K
0.8 mm BGA
17x17
195
1.2V-3.3V
400 MHz
700 Mbps
4
No
Complicated, Hard to source
Microsemi
IGLOO2 (M2GL025T-1VF400)
63
Gen2 x4
25K
0.8 mm BGA
17x17
195
1.2V-3.3V
400 MHz
700 Mbps
4
Yes
Microsemi
IGLOO2 (M2GL010T-1VF400)
37
Gen2 x4
12K
0.8 mm BGA
17x17
195
1.2V-3.3V
400 MHz
700 Mbps
4
No
Hard to source
Microsemi
IGLOO2 (M2GL005-VFG256)
30
Gen1 x4
12K
0.8 mm BGA
17x17
195
1.2V-3.3V
400 MHz
700 Mbps
2
No
Cant do PCIe
Intressanta serier
Utvecklings
IDE
Licenskrav
Lattice ECP5-5G Series
Diamond
Ja
Xilinx Artix-7 Series
Vivado
Nej
Intel Cyclone 10 Series
Quartus
Pro
Microsemi IGLOO2 Series
Libero
Gold
GPIO Speed
(Differential)
SerDes Channels
Candidate?
Motivation
4
No
Expensive price/performance
4
No
Expensive price/performance
2
No
Next gen hardware available for
almost the same price
Next gen hardware available for
almost the same price
Requires Speed Grade 2 for PCIe
Gen 2
Requires Speed Grade 2 for PCIe
Gen 2
Requires Speed Grade 2 for PCIe
Gen 2
Too big
1
2
3
4
Appendix B
A
A
B
B
C
C
D
Rev. 1.0
Sheet 1 of 8
System Sketch
Project: PCIe Bridge
File:
system_sketch.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
2
3
4
D
1
2
VCC_3V3
VCC_3V3
PIR2302
PIR2401
VCC_3V3
PIC20 2
PIC20 1
A
PIC2102
COC20
C20
0.47uF PIC2101
3
PIR2301
COC21
C21
COR23
R23
10K
COU3
U3
16
VCC
COR24
R24
PIU3016
10K
15
PIU3015
EN#
1
PIU301
IN1
PIR2402
4
0.47uF
TS3A5018
4 x SPDT
NO1
NO2
NO3
NO4
COU4
U4
VCC_3V3
8
PIU408
GND
1
3
7
PIU401
PIU403
PIU407
4
PIU404
NOR Flash
CE#
WP#/SIO2
HOLD#/SIO3
GND
FLASH_CS_N
16 kb, SPI
VDD
SI/SIO0
SO/SIO1
SCK
4
PIU304
5 FLASH_MOSI
PIU405
2 FLASH_MISO
PIU402
7
PIU307
9
PIU309
6 FLASH_CLK
12
PIU3012
PIU406
8
PIU308
GND
17
PIU3017
SST26VF016B
GND
2
5
11
14
PIU3014
PIU302
PIU305
PIU3011
GND
DAP
GND
DAP = Die Attached Pad, Not used
B
I2C to SPI Bridge
PIR2502
COR25
R25
10K
PIR2501
FPGA_CFG_MOSI
FPGA_CFG_CLK
COU5
U5
VCC_3V3
RESET_N
NC1
NC2
NC3
NC4
A
FPGA_CFG_CS_N
PIU306
TS3A5018
Common MISO since there is only one driving node (FLASH memory),
reduces number of used SPDTs (easier to route)
B
COM1
COM2
COM3
COM4
3
6
10
PIU3010
13
PIU3013
PIU303
12
PIU5012
3
PIU503
9
PIU509
6 PROG_MOSI
MOSI
5
MISO PIU505
11 PROG_CLK
SPICLK PIU5011
VDD
PIU506
RESET#
INT#
FPGA_CFG_MISO
8
SCL
7
SDA PIU507
SMB_CLK
SMB_DATA
PIU508
SS0#/GPIO0
SS1#/GPIO1
SS2#/GPIO2
SS3#/GPIO3
4
PIU504
A2
A1
A0
GND
1
PIU501
2
PIU502
10
13
PIU5010
FPGA_PROGRAM
FPGA_DONE
16
PIU5016
15
PIU5015
VCC_3V3
14
PIU5014
PIR2601
COR26
R26
SC18IS602B
C
GND
PROG_CS_N
PIU5013
I2C address: 0101[A2][A1][A0][R/W]
GND
PITP901
PIR2602
10K
COU6
U6
4
PIU604
5
PIU605
COTP9
TP9
VCC
SCL
SDA
1
C
PIU601
3
PIU603
WP
EEPROM
4 kb, I2C
2
PIU602
GND
AT24C04D
VCCO_0_3V3
GND
PIR2702
COR27
R27
10K
PIR2701
COP1
P1
1
PIP101
4
7
8
PIP108
PIP104
PIP107
D
VREF
GND
GND
GND
TMS
TCK
TDO
TDI
3
PIP103
2
6
5
PIP105
PIP102
PIP106
PIR2802
PIR2902
PIR2801
PIR2901
COR28
R28
10K
COR29
R29
10K
JTAG_TMS
JTAG_TCK
JTAG_TDO
JTAG_TDI
GND
Project: PCIe Bridge
File:
Programming.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
JTAG
1
Rev. 1.0
Sheet 2 of 8
Programming Interface
JTAG
2
3
4
D
1
2
3
4
Requirements:
PUDC_B = HIGH to force IO's to HIGH-Z (For SET_IO regulation to work as expected
PROGRAM_B: Reloads configuration when pulsed LOW.
INIT_B: Initialization, Can be held low to stall initialization on power-up,
external <4.7k Pullup.
DONE: Goes HIGH when a configuration is complete, internal 10k
Pullup.
CFGBVS: Configuration bank voltage select, HIGH -> 3.3V or 2.5V.
U7B
BANK 14
Artix-7 CSG325 FPGA
A
K16
IO_L1P_T0_D00_MOSI_14 PIU70K16
L17
IO_L1N_T0_D01_DIN_14 PIU70L17
J15
IO_L2P_T0_D02_14 PIU70J15
J16
IO_L2N_T0_D03_14 PIU70J16 COR45
J18
IO_L3P_T0_DQS_PUDC_B_14 PIU70J18PIR4502
K18
IO_L3N_T0_DQS_EMCCLK_14 PIU70K18 330
L15
IO_L6P_T0_FCS_B_14 PIU70L15
T18
IO_L15N_T2_DQS_DOUT_CSO_B_14 PIU70T18
FPGA_CFG_MOSI
FPGA_CFG_MISO
B
C
A
[UG470] - 7 Series FPGAs Configuration User Guide, v1.13.1, p.27-28.
PIR4501
VCCO_0_3V3
PUDC_B: When PUDC_B is [LOW/HIGH], internal pull-up resistors are
[ENABLED/DISABLED] on each SelectIO pin.
EMCCLK: Optional external configuration clock, <1k pull to
LOW/HIGH.
CSO: For serial modes: CSO_B is a multi-purpose pin that functions as
the DOUT pin.
FPGA_CFG_CS_N
SET_IO_3V3_N
L14
PIU70L14
K17
PIU70K17
IO_0_14
IO_L4P_T0_D04_14
L18
IO_L4N_T0_D05_14 PIU70L18
J14
IO_L5P_T0_D06_14 PIU70J14
K15
IO_L5N_T0_D07_14 PIU70K15
M15
IO_L6N_T0_D08_VREF_14 PIU70M15
M16
IO_L7P_T1_D09_14 PIU70M16
M17
IO_L7N_T1_D10_14 PIU70M17
M14
IO_L8P_T1_D11_14 PIU70M14
N14
IO_L8N_T1_D12_14 PIU70N14
N16
IO_L9P_T1_DQS_14 PIU70N16
N17
IO_L9N_T1_DQS_D13_14 PIU70N17
N18
IO_L10P_T1_D14_14 PIU70N18
P18
IO_L10N_T1_D15_14 PIU70P18
P15
IO_L11P_T1_SRCC_14 PIU70P15
P16
IO_L11N_T1_SRCC_14 PIU70P16
P14
IO_L12P_T1_MRCC_14 PIU70P14
R15
IO_L12N_T1_MRCC_14 PIU70R15
T14
IO_L13P_T2_MRCC_14 PIU70T14
T15
IO_L13N_T2_MRCC_14 PIU70T15
R16
IO_L14P_T2_SRCC_14 PIU70R16
R17
IO_L14N_T2_SRCC_14 PIU70R17
R18
IO_L15P_T2_DQS_RDWR_B_14 PIU70R18
T17
IO_L16P_T2_CSI_B_14 PIU70T17
U17
IO_L16N_T2_A15_D31_14 PIU70U17
U15
IO_L17P_T2_A14_D30_14 PIU70U15
U16
IO_L17N_T2_A13_D29_14 PIU70U16
V16
IO_L18P_T2_A12_D28_14 PIU70V16
V17
PIU70V17
IO_L18N_T2_A11_D27_14
R13
IO_L19P_T3_A10_D26_14 PIU70R13
T13
IO_L19N_T3_A09_D25_VREF_14 PIU70T13
U14
IO_L20P_T3_A08_D24_14 PIU70U14
V14
IO_L20N_T3_A07_D23_14 PIU70V14
V12
IO_L21P_T3_DQS_14 PIU70V12
V13
IO_L21N_T3_DQS_A06_D22_14 PIU70V13
T12
IO_L22P_T3_A05_D21_14 PIU70T12
U12
IO_L22N_T3_A04_D20_14 PIU70U12
U11
IO_L23P_T3_A03_D19_14 PIU70U11
V11
IO_L23N_T3_A02_D18_14 PIU70V11
U9
IO_L24P_T3_A01_D17_14 PIU70U9
V9
IO_L24N_T3_A00_D16_14 PIU70V9
U10
IO_25_14 PIU70U10
[UG470] - 7 Series FPGAs Configuration User Guide, p.25-26:
M[2:0] = 001 SPI Master Mode
COU7A
COU7B
U7A
VCCO_0_3V3
BANK 0
B
Artix-7 CSG325 FPGA
M2_0
M1_0
M0_0
SET_IO_2V5_N
F13
PIU70F13
R11
PIU70R11
R12
PIU70R12
PIR4602
CCLK_0
DONE_0
SET_IO_1V8_N
CFGBVS_0
TDI_0
TMS_0
TCK_0
TDO_0
E11
PIU70E11
VCCBATT_0
GND
XADC
VCCAUX_1V8
J10
PIU70J10
VCCADC_0
J9
PIU70J9 GNDADC_0
PIR4702
COR46
R46 COR47
R47
GND
T10
INIT_B_0 PIU70T10
P10
PROGRAM_B_0 PIU70P10
4.7K 4.7K
PIR4601
PIR4701
FPGA_PROGRAM
E8
FPGA_CFG_CLK
PIU70E8
R48
F12 COR48
PIR4801
10K
PIU70F12
PIR4802
E12
PIU70E12
FPGA_DONE
DONE: Short-circuit protection
I2C bridge output default HIGH
VCCO_0_3V3
T9
R8
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
PIU70T9
PIU70R8
F8
PIU70F8
T8
PIU70T8
C
M10
DXP_0 PIU70M10
M9
DXN_0 PIU70M9
VREFP_0
VREFN_0
VP_0
VN_0
L10
K9
PIU70L10
PIU70K9
K10
PIU70K10
L9
PIU70L9
Artix-7 FPGA
GND
GND
Artix-7 FPGA
D
Artix-7 Configuration Banks
Project: PCIe Bridge
File:
Bank_0_14.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
2
3
4
Rev. 1.0
Sheet 3 of 8
D
1
2
COU7C
COU7E
U7C
B
C
4
COP2
P2
1
3
5
PIP205
7
PIP207
9
PIP209
Pin Header
11
PIP2011
1.27 mm
13
PIP2013
15
PIP2015
17
PIP2017
19
PIP2019
U7E
BANK 15
BANK 34
Artix-7 CSG325 FPGA
Artix-7 CSG325 FPGA
D10
IO_0_15 PIU70D10
D8
IO_L1P_T0_AD0P_15 PIU70D8
C8
IO_L1N_T0_AD0N_15 PIU70C8
D9
IO_L2P_T0_AD8P_15 PIU70D9
C9
IO_L2N_T0_AD8N_15 PIU70C9
B9
IO_L3P_T0_DQS_AD1P_15 PIU70B9
A9
IO_L3N_T0_DQS_AD1N_15 PIU70A9
C11
IO_L4P_T0_AD9P_15 PIU70C11
B11
IO_L4N_T0_AD9N_15 PIU70B11
B10
IO_L5P_T0_AD2P_15 PIU70B10
A10
IO_L5N_T0_AD2N_15 PIU70A10
D11
IO_L6P_T0_15 PIU70D11
C12
IO_L6N_T0_VREF_15 PIU70C12
B12
IO_L7P_T1_AD10P_15 PIU70B12
A12
IO_L7N_T1_AD10N_15 PIU70A12
A13
IO_L8P_T1_AD3P_15 PIU70A13
A14
IO_L8N_T1_AD3N_15 PIU70A14
C14
IO_L9P_T1_DQS_AD11P_15 PIU70C14
B15
IO_L9N_T1_DQS_AD11N_15 PIU70B15
B14
IO_L10P_T1_AD4P_15 PIU70B14
A15
IO_L10N_T1_AD4N_15 PIU70A15
D13
IO_L11P_T1_SRCC_AD12P_15 PIU70D13
C13
IO_L11N_T1_SRCC_AD12N_15 PIU70C13
E13
IO_L12P_T1_MRCC_AD5P_15 PIU70E13
D14
IO_L12N_T1_MRCC_AD5N_15 PIU70D14
E15
IO_L13P_T2_MRCC_15 PIU70E15
D15
IO_L13N_T2_MRCC_15 PIU70D15
E16
IO_L14P_T2_SRCC_15 PIU70E16
D16
IO_L14N_T2_SRCC_15 PIU70D16
B16
IO_L15P_T2_DQS_15 PIU70B16
A17
IO_L15N_T2_DQS_ADV_B_15 PIU70A17
C16
IO_L16P_T2_A28_15 PIU70C16
B17
IO_L16N_T2_A27_15 PIU70B17
E17
IO_L17P_T2_A26_15 PIU70E17
D18
PIU70D18
IO_L17N_T2_A25_15
C17
IO_L18P_T2_A24_15 PIU70C17
C18
IO_L18N_T2_A23_15 PIU70C18
G17
IO_L19P_T3_A22_15 PIU70G17
F18
PIU70F18
IO_L19N_T3_A21_VREF_15
H16
IO_L20P_T3_A20_15 PIU70H16
G16
IO_L20N_T3_A19_15 PIU70G16
G15
IO_L21P_T3_DQS_15 PIU70G15
F15
IO_L21N_T3_DQS_A18_15 PIU70F15
G14
IO_L22P_T3_A17_15 PIU70G14
F14
IO_L22N_T3_A16_15 PIU70F14
H17
IO_L23P_T3_FOE_B_15 PIU70H17
H18
IO_L23N_T3_FWE_B_15 PIU70H18
F17
IO_L24P_T3_RS1_15 PIU70F17
E18
IO_L24N_T3_RS0_15 PIU70E18
H14
IO_25_15 PIU70H14
A
3
J6
IO_0_34 PIU70J6
K6
IO_L1P_T0_34 PIU70K6
K5
IO_L1N_T0_34 PIU70K5
J5
IO_L2P_T0_34 PIU70J5
J4
IO_L2N_T0_34 PIU70J4
K2
PIU70K2
IO_L3P_T0_DQS_34
K1
IO_L3N_T0_DQS_34 PIU70K1
K3
IO_L4P_T0_34 PIU70K3
L2
IO_L4N_T0_34 PIU70L2
L4
PIU70L4
IO_L5P_T0_34
L3
IO_L5N_T0_34 PIU70L3
L5
IO_L6P_T0_34 PIU70L5
M5
IO_L6N_T0_VREF_34 PIU70M5
M2
IO_L7P_T1_34 PIU70M2
M1
IO_L7N_T1_34 PIU70M1
M6
IO_L8P_T1_34 PIU70M6
N6
IO_L8N_T1_34 PIU70N6
N1
IO_L9P_T1_DQS_34 PIU70N1
P1
IO_L9N_T1_DQS_34 PIU70P1
M4
IO_L10P_T1_34 PIU70M4
N4
IO_L10N_T1_34 PIU70N4
N3
IO_L11P_T1_SRCC_34 PIU70N3
N2
IO_L11N_T1_SRCC_34 PIU70N2
P4
IO_L12P_T1_MRCC_34 PIU70P4
P3
IO_L12N_T1_MRCC_34 PIU70P3
R2
IO_L13P_T2_MRCC_34 PIU70R2
R1
IO_L13N_T2_MRCC_34 PIU70R1
R3
IO_L14P_T2_SRCC_34 PIU70R3
T2
IO_L14N_T2_SRCC_34 PIU70T2
U2
IO_L15P_T2_DQS_34 PIU70U2
U1
IO_L15N_T2_DQS_34 PIU70U1
V3
IO_L16P_T2_34 PIU70V3
V2
IO_L16N_T2_34 PIU70V2
T4
IO_L17P_T2_34 PIU70T4
T3
IO_L17N_T2_34 PIU70T3
U4
IO_L18P_T2_34 PIU70U4
V4
IO_L18N_T2_34 PIU70V4
P6
IO_L19P_T3_34 PIU70P6
P5
IO_L19N_T3_VREF_34 PIU70P5
U6
IO_L20P_T3_34 PIU70U6
U5
IO_L20N_T3_34 PIU70U5
R5
IO_L21P_T3_DQS_34 PIU70R5
T5
IO_L21N_T3_DQS_34 PIU70T5
R7
IO_L22P_T3_34 PIU70R7
T7
IO_L22N_T3_34 PIU70T7
U7
IO_L23P_T3_34 PIU70U7
V6
IO_L23N_T3_34 PIU70V6
V8
IO_L24P_T3_34 PIU70V8
V7
IO_L24N_T3_34 PIU70V7
R6
IO_25_34 PIU70R6
4_P
4_N
3_P
3_N
2_P
2_N
1_P
1_N
0_P
0_N
Artix-7 FPGA
0_P
0_N
1_P
1_N
2_P
2_N
3_P
3_N
4_P
4_N
PIP201
PIP203
2
4
6
8
PIP208
10
PIP2010
12
PIP2012
14
PIP2014
16
PIP2016
18
PIP2018
20
PIP2020
PIP202
PIP204
PIP206
M50-361
PIR3501
0_P
PIR3601
COR35
R35
1_P
PIR3701
2_P
PIR3801
3_P
COR36
R36
PIR3901
COR37
COR38
R37
R38
DNM DNM DNM DNM
PIR3502 0_N PIR3602 1_N PIR3702 2_N PIR3802 3_N PIR3902
4_P
GND
COR39
R39
DNM
4_N
100 Ohm LVDS Termination (For test equipment)
B
PIR40 1
9_P
PIR4101
8_P
PIR4201
7_P
PIR4301
5_P
COR40
R40
PIR40 2
5_P
5_N
6_P
6_N
7_P
7_N
COR41
COR42
COR43
R41
R42
R43
DNM DNM DNM DNM
9_N PIR4102 8_N PIR4202 7_N PIR4302 5_N
COP3
P3
2
4
6
PIP306
8
PIP308
10
PIP3010
Pin Header
12
PIP3012
1.27 mm
14
PIP3014
16
PIP3016
18
PIP3018
20
PIP3020
9_P
9_N
8_P
8_N
7_P
7_N
PIP302
PIP304
5_P
5_N
1
3
5
7
PIP307
9
PIP309
11
PIP3011
13
PIP3013
15
PIP3015
17
PIP3017
19
PIP3019
PIP301
PIP303
PIP305
C
M50-361
PIR4 02
GND
6_P
COR44
R44
8_P
8_N
9_P
9_N
PIR4 01
DNM
6_N
Artix-7 FPGA
D
Rev. 1.0
Sheet 4 of 8
Artix-7 IO Bank 15&34
Project: PCIe Bridge
File:
Bank_15_34.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
A
2
3
4
D
1
2
3
4
A
A
VMGTAVTT_1V2
COU7D
U7D
PIR3401
BANK 216, GTP
COR34
R34
Artix-7 CSG325 FPGA
MGTRREF_216
B
MGTREFCLK0P_216
MGTREFCLK0N_216
MGTREFCLK1P_216
MGTREFCLK1N_216
MGTPTXP0_216
MGTPTXN0_216
MGTPRXP0_216
MGTPRXN0_216
MGTPTXP1_216
MGTPTXN1_216
MGTPRXP1_216
MGTPRXN1_216
MGTPTXP2_216
MGTPTXN2_216
MGTPRXP2_216
MGTPRXN2_216
C
MGTPTXP3_216
MGTPTXN3_216
MGTPRXP3_216
MGTPRXN3_216
A6
PIU70A6
PIR3402 100
D6
PIU70D6
B
D5
B6
B5
PIU70D5
PCIE_CLK_P
PCIE_CLK_N
PIU70B6
PIU70B5
H2
PIU70H2
H1
PIU70H1
PCIE_TX1_P
PCIE_TX1_N
PCIE_RX1_P
PCIE_RX1_N
E4
E3
PIU70E3
PIU70E4
PCIE_TX0_P
PCIE_TX0_N
PCIE_RX0_P
PCIE_RX0_N
F2
PIU70F2
F1
PIU70F1
A4
A3
PIU70A3
PIU70A4
PCIE_CLK_P
PCIE_CLK_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_TX0_P
PCIE_TX0_N
PCIE_RX0_P
PCIE_RX0_N
D2
PIU70D2
D1
PIU70D1
C4
C3
PIU70C4
PIU70C3
C
B2
PIU70B2
B1
PIU70B1
G4
G3
PIU70G3
PIU70G4
Artix-7 FPGA
GND
GND
D
Rev. 1.0
Sheet 5 of 8
Artix-7 GTP Transcievers
Project: PCIe Bridge
File:
Transcievers.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
2
3
4
D
1
2
3
4
A
A
VCC_3V3
COP4
P4
1
GND
3.3 V
3
PIP403
GND
3.3 V
5
PIP405 PETn3
N/A
7
PIP407 PETp3
N/A
9
PIP409
GND
DAS/DSS
11
PIP4011
PERn3
3.3 V
13
PIP4013 PERp3
3.3 V
15
PIP4015
GND
3.3 V
17
PIP4017 PETn2
3.3 V
19
PIP4019
PETp2
N/A
21
PIP4021
GND
N/A
23
PIP4023 PERn2
N/A
25
PIP4025
PERp2
N/A
27
PIP4027 GND
N/A
29
PIP4029
PETn1
N/A
31
PIP4031 PETp1
N/A
33
PIP4033
GND
N/A
35
PIP4035 PERn1
N/A
37
PIP4037 PERp1 M.2 Connector DEVSLP
Finger
Edge
39
PIP4039 GND
SMB_CLK
Module 3 (M key)
41
PIP4041 PETn0
SMB_DATA
43
PIP4043
PETp0
ALERT#
45
PIP4045 GND
N/A
47
PIP4047 PERn0
N/A
49
PIP4049
PERp0
PERST#
51
PIP4051
GND
CLKREQ#
53
PIP4053
REFCLKN
PEWAKE#
55
PIP4055 REFCLKP
MFG1
57
PIP4057 GND
MFG2
PIP401
COC22
C22
B
PCIE_TX1_N
PCIE_TX1_P
PCIE_RX1_N
PCIE_RX1_P
PCIE_TX0_N
PCIE_TX0_P
PCIE_RX0_N
PCIE_RX0_P
PCIE_CLK_P
PCIE_CLK_N
COC23
C23 PIC2201
PIC2301 PIC2302
PIC2202
M2_TX1_N
M2_TX1_P
100nF
100nF
COC24
C24
COC25
C25 PIC2401 PIC2402
PIC2501 PIC2502
M2_TX0_N
M2_TX0_P
100nF
100nF
COC26
C26
COC27
C27 PIC2601 PIC2602 M2_CLK_N
PIC2701
PIC2702
M2_CLK_P
100nF
100nF
2
4
PIP404
6
PIP406
8
PIP408
10
PIP4010
12
PIP4012
14
PIP4014
16
PIP4016
18
PIP4018
20
PIP4020
22
PIP4022
24
PIP4024
26
PIP4026
28
PIP4028
30
PIP4030
32
PIP4032
34
PIP4034
36
PIP4036
38
PIP4038
40
PIP4040
42
PIP4042
44
PIP4044
46
PIP4046
48
PIP4048
50
PIP4050
52
PIP4052
54
PIP4054
56
PIP4056
58
PIP4058
PIP402
SMBUS Specification:
Pull-up resistors to 1.8V (SMB_CLK, SMB_DATA) on platform.
Logic Level Converter (1.8V to 3.3V)
VCCAUX_1V8
VCC_3V3
PIR30 2
DNM
COR30
R30
10K
PIR30 1
VCCAUX_1V8
PIR3202
DNM
PIR3 02
PIQ301
COR32
R32
10K
PIR3201
PIQ202
VCC_3V3
PIQ302
PIR3102
PIQ201
COR31
R31
10K
PIQ203
PIR3101
B
SMB_CLK
COQ2
Q2
BSS806
COR33
R33
10K
PIQ303
PIR3 01
SMB_DATA
COQ3
Q3
BSS806
RESET_N
C
C
67
69
71
PIP4071
73
PIP4073
75
PIP4075
PIP4067
PIP4069
N/A
PEDET
GND
GND
GND
SUSCLK
3.3 V
3.3 V
3.3 V
68
70
72
PIP4072
74
PIP4074
PIP4068
PIP4070
M.2 PCIe
GND
D
Rev. 1.0
Sheet 6 of 8
PCI Express Connector
Project: PCIe Bridge
File:
PCIe.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
2
3
4
D
1
2
COU1
U1
1
VINLDO12
10
AVDD
6
10uF PIU106 VIN1
13
PIU1013 VIN2
VCC_3V3
PIC102
PIC101
COC1
C1
1uF
PIC202
PIC201
PIC302
PIC301
COC2
C2
1uF
COC3
C3
10uF
SW1
PIU101
PIC402
PIC401
COC4
C4
3
COL1
L1
5
PIU105
PIL102
PIL101
PIC501 COC5
C5
A
FB1
COC7
C7
DNM
VCC_3V3
PIR302
PIR402
COR3
PIR301
0
COR4
DNM
PIR401
0
PIC10 2
PIC10 1 COC10
C10
PIC1 01 COC11
C11
1uF
1uF
FB2
VCC_3V3
PIR702
COR7
R7
SW2
Vin_LDO PIU1019
19
VINLDO1
PIC1 02
24
PIU1024
VINLDO2
10uF
GND
PIC802
COC8
C8
8.2pF PIC801
11
PIU1011
COC12
C12
DNM
PIC1202
PIC1201
PIR502
NPOR - Power On Reset, default 60 ms PG delay
NPOR is pulled to ground when the voltages on SW1 and SW2 are not good
COQ1
Q1
VCC_3V3
PIC902 VCCAUX_1V8
COR5
R5 PIC901 COC9
C9
PIR501 390K
PIR602
A
Used to sequence VCCO.
PIR201 100K
PIL202
2.2uH
PMIC
PIC601 COC6
C6
COR2
R2
COL2
L2
14
PIU1014
PIL201
2x Switching regulator
2x Low drop-out regulators
GND
PIR202
PIC702
PIC701
VCCINT_1V0
PIC602
COR1
R1
15pF PIR101 100K
8
PIU108
GND
VCCAUX_1V8
PIR102
PIC502
2.2uH
PIU1010
4
10uF
PIQ103
VCCO_0_3V3
PIQ102
PIQ10
NPOR
BSS806
COR6
R6
PIR601 150K
100K
PIR701
B
VCC_3V3
PIR10 1
COR10
R10
PIR10 2
10K
PIC1602
PIC1601 COC16
C16
100nF
GND
NPOR
VCC_3V3
VCC_3V3
PIR1 01
LDO1
20
PIU1020
PIR902
COR9
R9
COR12
R12
15K
PIR1202
PIC1702
PIC1701 COC17
C17
4.7K
7
PIU107
12
17
PIU1017
16
PIU1016
PIU1012
PIC1802
PIC1801 COC18
C18
100nF
GND
GND
NPOR
PIR1201
COR11
R11
PIR1 02
3
PIU103
VCC_3V3
100nF
GND
FBL1
PIR901 47K
PIR1302
21
PIU1021
ENSW1
ENSW2
ENLDO1
ENLDO2
PIC1301
PIC1302
COR13
R13
GND
PIU104
23
LDO2
PIU1023
1uF 0603
GRT188R71E105KE13D
15pF 0402
GCM1555C1H150JA16D
D
8.2pF 0402
GJM1555C1H8R2CB01D
OUT
B
1
PIU201
COR8
R8
39K
FB
FBL2
PIU1022
PIR2102
COR21
R21
PIR2101 100K
PIR2 02
22
PIC1902
PIC1901 COC19
C19
2
PIU202
PIR801
PIR1602
PIR1702
PIR1801
PITP201
COTP2
TP2
PITP301
COTP3
TP3
PITP401
COTP4
TP4
VCCAUX_1V8
VCC_3V3
VCCO_0_3V3
PITP601
COTP6
TP6
PITP701
COTP7
TP7
PITP801
COTP8
TP8
33K
PIR1501
PIR1902
15K
COR19
R19
2.7K
PIR1901
1.5K
COR16
R16
PIR1601
PIR20 2
COC15
C15
1uF
COR17
R17
33K
10K
PIR1701
COR20
R20
PIR20 1
220
GND
GND
SET_IO_2V5_N
SET_IO_1V8_N
GND
PITP501
COTP5
TP5
COR15
R15
PIC1501
PIC1502
1uF
COR22
R22
VCCINT_1V0
PIR1502
COR18
R18
PIR2 01 100K
PITP101
COTP1
TP1
PIR1402
VCCO_15_34_ADJ
PIR802
LDO
PIR1401
PIR1802
VMGTAVCC_1V0
C
SET_IO_3V3_N
Software configurable voltage divider
LOW on selected voltage
HIGH-Z on others
BUCK1, BUCK2 Startup time: 500us
LDO1, LDO2 Startup time: 300us
R = 5K: 500us
R = 10K: 1000us
R = 15K: 1500us
IN
4
EN
7
PIU207
DAP
3
PIU203
GND
PIU204
COR14
R14
GND
2
SYNC
4
GND_SW1
15
PIU1015
GND_SW2
9
PIU109
GND_C
18
PIU1018
GND_L
25
PIU1025 DAP
PIU102
Optimal power-on seq: Vccint, Vmgtavcc, Vgtavtt, Vccbram, Vccaux, Vcco
(VGTAVCC before VGTAVTT most critical)
Capacitors:
10uF 0805
GRM21BR61C106KE15
COC13
C13
1uF
1uF
PIR1301 33K
GND
RC Sequencing:
tau_r = R*C
C = 100nF ->
6
PIU206
TLV75801
LM26480
C
COU2
U2
VCC_3V3
PIC1402 VMGTAVTT_1V2
C14
PIC1401 COC14
VMGTAVTT_1V2
VMGTAVCC_1V0
VCCO_15_34_ADJ
GND
Rev. 1.0
Sheet 7 of 8
Power Distribution
Project: PCIe Bridge
File:
regulator.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
1
2
3
4
D
1
2
3
4
U7G
VCCINT_1V0
BANK VCCINT
VCCINT_1V0
COU7F
COU7G
COU7H
COU7I
COU7J
COU7K
COU7L
U7F
Artix-7 CSG325 FPGA
F7
PIU70F7
F9
G8
H7
PIU70H7
H9
PIU70H9
J8
PIU70J8
J12
PIU70J12
K7
PIU70K7
K11
PIU70K11
PIU70F9
A
PIU70G8
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
L8
PIU70L8
L12
M7
M11
PIU70M11
N8
PIU70N8
N10
PIU70N10
N12
PIU70N12
P9
PIU70P9
P11
PIU70P11
VCCAUX_1V8
BANK VCCAUX
Artix-7 CSG325 FPGA
PIU70L12
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
PIU70M7
Artix-7 CSG325 FPGA
VCCINT_1V0
Artix-7 CSG325 FPGA
VCCBRAM
VCCBRAM
VCCBRAM
BANK GND
Artix-7 CSG325 FPGA
C
D
V18
V10
PIU70V10
V1
PIU70V1
U13
PIU70U13
U3
PIU70U3
T16
PIU70T16
T6
PIU70T6
R9
PIU70R9
P12
PIU70P12
P8
PIU70P8
P2
PIU70P2
N15
PIU70N15
N13
PIU70N13
N11
PIU70N11
N9
PIU70N9
N7
PIU70N7
N5
PIU70N5
M18
PIU70M18
M12
PIU70M12
M8
PIU70M8
L13
PIU70L13
L11
PIU70L11
L7
PIU70L7
L1
PIU70L1
K14
PIU70K14
K12
PIU70K12
K8
PIU70K8
K4
PIU70K4
J17
PIU70J17
J13
PIU70J13
J11
PIU70J11
J7
PIU70J7
J3
PIU70J3
J2
PIU70J2
J1
PIU70J1
H12
PIU70H12
A1
PIU70A1
PIU70V15
VCCO_15
VCCO_15
VCCO_15
VCCO_15
VCCO_15
VCCO_15
VCCO_15
PIU70V18
Artix-7 FPGA
GND
VCCO_14
VCCO_14
VCCO_14
VCCO_14
VCCO_14
VCCO_14
VCCO_14
F11
G10
U7H
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIU70E10
PIU70G10
Artix-7 FPGA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_0_3V3
E10
R10
PIU70R10
VCCO_0
VCCO_0
PIU70F11
H11
PIU70H11
COC28
C28
100uF
DNM
PIC2902
PIC2901
COC29
C29
4.7uF
PIC30 2
PIC30 1
DNM
COC30
C30
4.7uF
COC31
C31
0.47uF
PIC3202
PIC3201
COC32
C32
0.47uF
PIC3 02
PIC3 01
COC33
C33
0.47uF
Crossed out:
Mount if XC7A35T is used, otherwise DNM.
V15
U18
U8
PIU70U8
T11
PIU70T11
R14
PIU70R14
P17
PIU70P17
L16
PIU70L16
PIU70U18
VCCO_15_34_ADJ
H15
G18
E14
PIU70E14
D17
PIU70D17
C10
PIU70C10
B13
PIU70B13
A16
PIU70A16
PIU70H15
PIU70G18
COC34
C34
100uF
PIC3502
PIC3501
COC35
C35
4.7uF
PIC3602
PIC3601
COC36
C36
4.7uF
PIC3702
PIC3701
COC37
C37
0.47uF
PIC3802
PIC3801
COC38
C38
0.47uF
DNM
PIC3902
PIC3901
COC39
C39
0.47uF
DNM
GND
VCCO_0_3V3
VCCINT_1V0
PIC40 2
PIC40 1
PIC4102
PIC4101
COC40
C40
100uF
GND
COC41
C41
100uF
PIC4202
PIC4201
COC42
C42
0.47uF
B
GND
VCCO_0_3V3
PIC4302
PIC4301
COC43
C43
100uF
PIC4 02
PIC4 01
COC44
C44
PIC5102
PIC5101
COC51
C51
4.7uF
PIC4502
PIC4501
COC45
C45
PIC5202
PIC5201
COC52
C52
4.7uF
PIC4602
PIC4601
COC46
C46
PIC5302
PIC5301
COC53
C53
0.47uF
PIC4702
PIC4701
COC47
C47
PIC5402
PIC5401
COC54
C54
0.47uF
PIC4802
PIC4801
COC48
C48
PIC5 02
PIC5 01
COC55
C55
0.47uF
PIC4902
PIC4901
COC49
C49
PIC5602
PIC5601
COC56
C56
0.47uF
GND
VCCO_15_34_ADJ
VCCO_34
VCCO_34
VCCO_34
VCCO_34
VCCO_34
VCCO_34
V5
PIU70V5
T1
R4
P7
M3
PIU70M3
L6
PIU70L6
PIU70T1
PIU70R4
PIC50 2
PIC50 1
COC50
C50
100uF
4.7uF
4.7uF
0.47uF
0.47uF
0.47uF
0.47uF
PIU70P7
Artix-7 FPGA
GND
C
VCCO_15_34_ADJ
U7K
BANK MGTAVTT
Artix-7 CSG325 FPGA
MGTAVTT
MGTAVTT
MGTAVTT
MGTAVTT
MGTAVTT
VMGTAVTT_1V2
A2
PIU70A2
C1
PIU70C1
E1
PIU70E1
F3
PIU70F3
G2
PIU70G2
U7J
BANK MGTAVCC
MGTAVCC
MGTAVCC
MGTAVCC
MGTAVCC
VMGTAVCC_1V0
B4
C5
PIU70C5
E5
PIU70E5
F5
PIU70F5
PIC5802
COC58
C58
PIC5801 4.7uF
PIC6202
PIC5902
PIC60 2
PIC6102
COC59
COC60
COC61
COC62
C59
C60
C61
C62
PIC5901 0.47uF PIC60 1 0.47uF PIC6101 0.47uF PIC6201 0.47uF
GND
VMGTAVTT_1V2
PIC6302
COC63
C63
PIC6301 4.7uF
Artix-7 FPGA
Artix-7 CSG325 FPGA
PIC5702
COC57
C57
PIC5701 4.7uF
VMGTAVCC_1V0
PIC6402
PIC6502
COC64
COC65
C64
C65
PIC6401 0.47uF PIC6501 0.47uF
GND
PIC6702
PIC6802
COC67
COC68
C67
C68
PIC6701 0.47uF PIC6801 0.47uF
GND
Artix-7 Power & Decoupling
Project: PCIe Bridge
File:
Decoupling.SchDoc
Linköping University
2019-03-27
Author(s): Håkan Gerner
Mandus Börjesson
Artix-7 FPGA
2
PIC6 02
COC66
C66
PIC6 01 4.7uF
PIU70B4
GND
1
PIC3102
PIC3101
A
GND
PIC3402
PIC3401
BANK VCCIO
BANK VCCBRAM
PIC2802
PIC2801
VCCINT_1V0
U7L
U7I
H10
PIU70H10
H8
PIU70H8
H6
PIU70H6
H5
PIU70H5
H4
PIU70H4
H3
PIU70H3
G13
PIU70G13
G11
PIU70G11
G9
PIU70G9
G7
PIU70G7
G6
PIU70G6
G5
PIU70G5
G1
PIU70G1
F16
PIU70F16
F10
PIU70F10
F6
PIU70F6
F4
PIU70F4
E9
PIU70E9
E7
PIU70E7
E6
PIU70E6
E2
PIU70E2
D12
PIU70D12
D7
PIU70D7
D4
PIU70D4
D3
PIU70D3
C15
PIU70C15
C7
PIU70C7
C6
PIU70C6
C2
PIU70C2
B18
PIU70B18
B8
PIU70B8
B7
PIU70B7
B3
PIU70B3
A18
PIU70A18
A11
PIU70A11
A8
PIU70A8
A7
PIU70A7
A5
PIU70A5
G12
H13
PIU70H13
K13
PIU70K13
M13
PIU70M13
P13
PIU70P13
PIU70G12
Artix-7 FPGA
Artix-7 FPGA
B
VCCAUX_1V8
3
4
Rev. 1.0
Sheet 8 of 8
D
COC34
COP2
COR35
PAP201
COR36
PAP203
PAP205
COR37
PAP209
COR38
PAP2011
PAP2013
COR39
PAP2015
PAP202
PAP204
PAP206
PAR3501
PAR3502
PAR3601
PAR3602
PAP207
PAR3701
PAR3702
PAR3801
COP3
COR40
COC50
PAP301
PAP303
PAP305
PAP302
PAR4001
COR41
PAP304
PAR4002
PAP306
PAR4101
PAP208 PAC3401 PAC4101
PAP307
PAP2010
PAP2012
PAP2014
PAP2016
PAP2018
PAP3013
PAP3015
PAP3017
PAP3014
PAP3016
PAP3018
PAR4301
PAP3019
PAR4302
PAP3020
COR42
PAP309 PAP3010
COC13
PAP3012
PAR4102
PAP308
PAP3011
PAC3402COC40
PAC4102COC41
PAC5001 PAC4001
PAR4201
PAR4202
COR43
COC28
PAP300
COTP7
PAC5002 PAC4002
COC15
PATP701COR20
COR19
COR18
COC43
COU2
COR21
COR22
COR13
COR9 COR4
PAC1301COC14
PAC1501
COC2
COC11
COC19
COC10
COR8
301 PAC4302
PAC2801 PAC2802 COR14
PAU207 PAC1302 PAC4COR3
PAC1502
COR17
COR16
COR15
COR7
PAC101
COC18
COR10
COTP1
COC3COU1 COC4
PAL202 PAL201
PAL101
COR12
COC6 PAC102 PAL102 COC9
COC16
PAC1802 PAC1801 PAU1012PAU101 PAU1010 PAU109 PAU108 PAU107
PAC402
PAC302 PATP101
COR11
PAC602
PAC902
COC17
COL1
PAC401 PAU1025 COL2
PAC301
COQ1
COTP2
COC1
COR23
PAC601
PAC901COR5
PAC1702 PAC1701 PAU1019PAU1020PAU1021 PAU102 PAU1023 PAU1024
PAQ103
COR2
COTP3PAC1002 PAC1402 PAC1902 PAC1102 PAC202
PATP201
COC8
COC7
COC5
COR1
PAQ101
PAQ102
COTP5PAC1001 PAC1401 PAC1901 PAC1101
PATP301
PAC201
COTP6
COR6
COC12
PATP501COU4
COP1
COTP4
PATP601
COR28
COC20
PAP107 PATP401
PAC2002
COR27
PAP101
COR29
PAC2001
PAP102
COC45
COU3
PAP103
COC52
COC51
COC30
COC29 COC44
PAP104
COR24
PAP105
COTP8
PAP106
COR45
PAC4502 PAC4501
PAC2901 PAC3001
COC47
PAC5101 PAC5201
PATP801
PAP108
COU7 PAC5102 PAC5202 PAC2902 PAC3002 PAC4402 PAC4401
COC49
COC56
COC48
COC55
COC32
COC31 PAC4701 PAC4901
PAC5602
PAC4801
PAC5501COC53
PAC4702
COC46
PAC3201
PAC3101
COC33
PAC4902
PAC5601
PAC4802
PAC5502
PAC3102
PAC4602
PAC5301 PAC5302 PAC3202
COC54
COC37
PAC4601
COC67PAC3301 PAC3302
COR47
COC66 COC38
PAC5401 PAC5402
PAC3701 PAC3702
COC68
COC59
PAC3801
PAC6602 PAC6702 PAC6701COC39
PAC5901
PAC6801 PAC3802
COC60
PAC6601
COC62
COC61
COR44
PAC3902 PAC3901COC42 PAC5902
PAC6802
PAC6002 COR46
COC65 COC64
PAR4402
PAC6202 PAC6102
COU5
PAC6001
COC36
COC35
PAC6502 COC63
PAC6402
PAR4401
PAC6201 PAC6101
PAR3802
PAP2017
PAR3901
PAR3902
PAP2019
PAP200
PAP2020
PAR801 PAR1701 PAR1601 PAR1501 PAR1401
PAR802 PAR1702 PAR2002
PAR1602 PAR1902
PAR1502 PAR1402
PAR1802
PAR2001 PAR1901
PAU206 PAR1801
PAU201
PAU202
PAU203
PAR1202
PAR1201
PAR1002 PAC1602
PAR1001 PAC1601
PAR1102PAR302 PAR301
PAR1101PAR402 PAR401
PAU205
PAU204
PAU1013
PAU1014
PAU106
PAU105
PAU1015
PAU1016
PAU104
PAU103
PAU1017
PAU1018
PAU102
PAU101
PAR701
PAR702
PAR502 PAC802
PAC502 PAR102
PAR501 PAC801
PAC501 PAR101
PAR602 PAC1202
PAC702 PAR202
PAR601 PAC1201 PAR902 PAR901 PAR1302 PAR1301 PAR2201 PAR2202 PAR2101 PAR2102 PAC701 PAR201
PAU405
PAU406
PAU407
PAU409
PAU404
PAU403 PAR2302
PAR2802
PAR2801
PAU402 PAR2301
PAU401
PAR2702
PAR2701
PAU309
PAU308
PAU3010
PAU3011
PAU3012
PAU307
PAU306
PAU305
PAR2902
PAU3013
PAU304
PAR2401 PAR2402 PAU303
PAU408
PAU3014
PAU3015
PAU3016
PAR2901
PAU302
PAU301
PAR4501
PAR4502
PAU70A18 PAU70B18 PAU70C18 PAU70D18 PAU70E18 PAU70F18 PAU70G18 PAU70H18 PAU70J18 PAU70K18 PAU70L18 PAU70M18 PAU70N18 PAU70P18 PAU70R18 PAU70T18 PAU70U18 PAU70V18
PAU70A17 PAU70B17 PAU70C17 PAU70D17 PAU70E17 PAU70F17 PAU70G17 PAU70H17 PAU70J17 PAU70K17 PAU70L17 PAU70M17 PAU70N17 PAU70P17 PAU70R17 PAU70T17 PAU70U17 PAU70V17
PAU70A16 PAU70B16 PAU70C16 PAU70D16 PAU70E16 PAU70F16 PAU70G16 PAU70H16 PAU70J16 PAU70K16 PAU70L16 PAU70M16 PAU70N16 PAU70P16 PAU70R16 PAU70T16 PAU70U16 PAU70V16
PAU70A15 PAU70B15 PAU70C15 PAU70D15 PAU70E15 PAU70F15 PAU70G15 PAU70H15 PAU70J15 PAU70K15 PAU70L15 PAU70M15 PAU70N15 PAU70P15 PAU70R15 PAU70T15 PAU70U15 PAU70V15
PAU70A14 PAU70B14 PAU70C14 PAU70D14 PAU70E14 PAU70F14 PAU70G14 PAU70H14 PAU70J14 PAU70K14 PAU70L14 PAU70M14 PAU70N14 PAU70P14 PAU70R14 PAU70T14 PAU70U14 PAU70V14
PAR4702
PAR4701
PAU70A13 PAU70B13 PAU70C13 PAU70D13 PAU70E13 PAU70F13 PAU70G13 PAU70H13 PAU70J13 PAU70K13 PAU70L13 PAU70M13 PAU70N13 PAU70P13 PAU70R13 PAU70T13 PAU70U13 PAU70V13
PAU70A12 PAU70B12 PAU70C12 PAU70D12 PAU70E12 PAU70F12 PAU70G12 PAU70H12 PAU70J12 PAU70K12 PAU70L12 PAU70M12 PAU70N12 PAU70P12 PAU70R12 PAU70T12 PAU70U12 PAU70V12
PAR4602
PAU70A11 PAU70B11 PAU70C11 PAU70D11 PAU70E11 PAU70F11 PAU70G11 PAU70H11 PAU70J11 PAU70K11 PAU70L11 PAU70M11 PAU70N11 PAU70P11 PAU70R11 PAU70T11 PAU70U11 PAU70V11
PAR4601
PAU70A10 PAU70B10 PAU70C10 PAU70D10 PAU70E10 PAU70F10 PAU70G10 PAU70H10 PAU70J10 PAU70K10 PAU70L10 PAU70M10 PAU70N10 PAU70P10 PAU70R10 PAU70T10 PAU70U10 PAU70V10
PAU70A9 PAU70B9 PAU70C9 PAU70D9 PAU70E9 PAU70F9 PAU70G9 PAU70H9 PAU70J9 PAU70K9 PAU70L9 PAU70M9 PAU70N9 PAU70P9 PAU70R9 PAU70T9 PAU70U9 PAU70V9
PAU70A8 PAU70B8 PAU70C8 PAU70D8 PAU70E8 PAU70F8 PAU70G8 PAU70H8 PAU70J8 PAU70K8 PAU70L8 PAU70M8 PAU70N8 PAU70P8 PAU70R8 PAU70T8 PAU70U8 PAU70V8
PAU70A7 PAU70B7 PAU70C7 PAU70D7 PAU70E7 PAU70F7 PAU70G7 PAU70H7 PAU70J7 PAU70K7 PAU70L7 PAU70M7 PAU70N7 PAU70P7 PAU70R7 PAU70T7 PAU70U7 PAU70V7
PAU70A6 PAU70B6 PAU70C6 PAU70D6 PAU70E6 PAU70F6 PAU70G6 PAU70H6 PAU70J6 PAU70K6 PAU70L6 PAU70M6 PAU70N6 PAU70P6 PAU70R6 PAU70T6 PAU70U6 PAU70V6
PAU70A5 PAU70B5 PAU70C5 PAU70D5 PAU70E5 PAU70F5 PAU70G5 PAU70H5 PAU70J5 PAU70K5 PAU70L5 PAU70M5 PAU70N5 PAU70P5 PAU70R5 PAU70T5 PAU70U5 PAU70V5
PAU70A4 PAU70B4 PAU70C4 PAU70D4 PAU70E4 PAU70F4 PAU70G4 PAU70H4 PAU70J4 PAU70K4 PAU70L4 PAU70M4 PAU70N4 PAU70P4 PAU70R4 PAU70T4 PAU70U4 PAU70V4
PAU70A3 PAU70B3 PAU70C3 PAU70D3 PAU70E3 PAU70F3 PAU70G3 PAU70H3 PAU70J3 PAU70K3 PAU70L3 PAU70M3 PAU70N3 PAU70P3 PAU70R3 PAU70T3 PAU70U3 PAU70V3
PAU70A2 PAU70B2 PAU70C2 PAU70D2 PAU70E2 PAU70F2 PAU70G2 PAU70H2 PAU70J2 PAU70K2 PAU70L2 PAU70M2 PAU70N2 PAU70P2 PAU70R2 PAU70T2 PAU70U2 PAU70V2
PAU70A1 PAU70B1 PAU70C1 PAU70D1 PAU70E1 PAU70F1 PAU70G1 PAU70H1 PAU70J1 PAU70K1 PAU70L1 PAU70M1 PAU70N1 PAU70P1 PAU70R1 PAU70T1 PAU70U1 PAU70V1
PAR3402PAC6501
PAR3401
PAC6302
PAC6401
PAC5702 PAC5802
PAU501
PAC4202
PAU5016
PAU5015
PAU5014
PAC4201
COQ3
COR33
PAC3601 PAC3501
COC58
COC57
COR25
COR31
PAQ303
COR48
COQ2
COR34
COC21
COU6
COR32
PAQ302PAR4801PAQ203PAR4802COTP9
PAQ301
PAC2101 COR30
COC27
COC26
COC25
COC24
COC23PAR3201 PAR3202
PAC3602 PAC3502PAU502
PAC5701 PAC5801
PAU503
PAC6301
PAU504
PAU5013
PAU505
PAU506
PAU507
PAU5012
PAU5011
PAU5010
PAU508
PAU509
PAR3302 PAR3301
PAR2501 PAR2502 PAR3102 PAR3101
COP4
PAC2701 PAC2601
PAC2702 PAC2602
PAC2501 PAC2401
PAC2502 PAC2402
PAU604
PAU603
PAC2102 PAR3001 PAR3002 PAU602
PAC2301 PAC2201 PAR2601 PAU605 PAQ202
PAU601
PAC2302 PAC2202 PAR2602
COC2 COR26
PATP901
PAQ201
PA 4P0A7P54A074P0A7P34A074P20A714P0A7P40A694P0A684067 PA 4P0A5P480A574P0A5P64A054P0A54P0A5P34A0524P0A5P14A054P0AP94A084P0A74P0AP460A54P0A40PA3P4A024P0AP14A0 4P0A394P0A3P480A374P0A3P460A354P0A3P4A034P0A324P0A3P14A034P0A2P94A024P80A2P74A024P60A254P0A2P40A234P0A2P4A024P10A24P0A1P940A184P0A1P74A014P60A154P0A1P40A134P0A1420P1AP40A1P4A09P4A084P0AP7A4046PA05P4A0 4P0A3P4A02401
COC34
COP2
COR35
PAP201
COR36
PAP203
PAP205
COR37
PAP209
COR38
PAP2011
PAP2013
COR39
PAP2015
PAP202
PAP204
PAP206
PAR3501
PAR3502
PAR3601
PAR3602
PAP207
PAR3701
PAR3702
PAR3801
COP3
COR40
COC50
PAP301
PAP303
PAP305
PAP302
PAR4001
COR41
PAP304
PAR4002
PAP306
PAR4101
PAP208 PAC3401 PAC4101
PAP307
PAP2010
PAP2012
PAP2014
PAP2016
PAP2018
PAP3013
PAP3015
PAP3017
PAP3014
PAP3016
PAP3018
PAR4301
PAP3019
PAR4302
PAP3020
COR42
PAP309 PAP3010
COC13
PAP3012
PAR4102
PAP308
PAP3011
PAC3402COC40
PAC4102COC41
PAC5001 PAC4001
PAR4201
PAR4202
COR43
COC28
PAP300
COTP7
PAC5002 PAC4002
COC15
PATP701COR20
COR19
COR18
COC43
COU2
COR21
COR22
COR13
COR9 COR4
PAC1301COC14
PAC1501
COC2
COC11
COC19
COC10
COR8
301 PAC4302
PAC2801 PAC2802 COR14
PAU207 PAC1302 PAC4COR3
PAC1502
COR17
COR16
COR15
COR7
PAC101
COC18
COR10
COTP1
COC3COU1 COC4
PAL202 PAL201
PAL101
COR12
COC6 PAC102 PAL102 COC9
COC16
PAC1802 PAC1801 PAU1012PAU101 PAU1010 PAU109 PAU108 PAU107
PAC402
PAC302 PATP101
COR11
PAC602
PAC902
COC17
COL1
PAC401 PAU1025 COL2
PAC301
COQ1
COTP2
COC1
COR23
PAC601
PAC901COR5
PAC1702 PAC1701 PAU1019PAU1020PAU1021 PAU102 PAU1023 PAU1024
PAQ103
COR2
COTP3PAC1002 PAC1402 PAC1902 PAC1102 PAC202
PATP201
COC8
COC7
COC5
COR1
PAQ101
PAQ102
COTP5PAC1001 PAC1401 PAC1901 PAC1101
PATP301
PAC201
COTP6
COR6
COC12
PATP501COU4
COP1
COTP4
PATP601
COR28
COC20
PAP107 PATP401
PAC2002
COR27
PAP101
COR29
PAC2001
PAP102
COC45
COU3
PAP103
COC52
COC51
COC30
COC29 COC44
PAP104
COR24
PAP105
COTP8
PAP106
COR45
PAC4502 PAC4501
PAC2901 PAC3001
COC47
PAC5101 PAC5201
PATP801
PAP108
COU7 PAC5102 PAC5202 PAC2902 PAC3002 PAC4402 PAC4401
COC49
COC56
COC48
COC55
COC32
COC31 PAC4701 PAC4901
PAC5602
PAC4801
PAC5501COC53
PAC4702
COC46
PAC3201
PAC3101
COC33
PAC4902
PAC5601
PAC4802
PAC5502
PAC3102
PAC4602
PAC5301 PAC5302 PAC3202
COC54
COC37
PAC4601
COC67PAC3301 PAC3302
COR47
COC66 COC38
PAC5401 PAC5402
PAC3701 PAC3702
COC68
COC59
PAC3801
PAC6602 PAC6702 PAC6701COC39
PAC5901
PAC6801 PAC3802
COC60
PAC6601
COC62
COC61
COR44
PAC3902 PAC3901COC42 PAC5902
PAC6802
PAC6002 COR46
COC65 COC64
PAR4402
PAC6202 PAC6102
COU5
PAC6001
COC36
COC35
PAC6502 COC63
PAC6402
PAR4401
PAC6201 PAC6101
PAR3802
PAP2017
PAR3901
PAR3902
PAP2019
PAP200
PAP2020
PAR801 PAR1701 PAR1601 PAR1501 PAR1401
PAR802 PAR1702 PAR2002
PAR1602 PAR1902
PAR1502 PAR1402
PAR1802
PAR2001 PAR1901
PAU206 PAR1801
PAU201
PAU202
PAU203
PAR1202
PAR1201
PAR1002 PAC1602
PAR1001 PAC1601
PAR1102PAR302 PAR301
PAR1101PAR402 PAR401
PAU205
PAU204
PAU1013
PAU1014
PAU106
PAU105
PAU1015
PAU1016
PAU104
PAU103
PAU1017
PAU1018
PAU102
PAU101
PAR701
PAR702
PAR502 PAC802
PAC502 PAR102
PAR501 PAC801
PAC501 PAR101
PAR602 PAC1202
PAC702 PAR202
PAR601 PAC1201 PAR902 PAR901 PAR1302 PAR1301 PAR2201 PAR2202 PAR2101 PAR2102 PAC701 PAR201
PAU405
PAU406
PAU407
PAU409
PAU404
PAU403 PAR2302
PAR2802
PAR2801
PAU402 PAR2301
PAU401
PAR2702
PAR2701
PAU309
PAU308
PAU3010
PAU3011
PAU3012
PAU307
PAU306
PAU305
PAR2902
PAU3013
PAU304
PAR2401 PAR2402 PAU303
PAU408
PAU3014
PAU3015
PAU3016
PAR2901
PAU302
PAU301
PAR4501
PAR4502
PAU70A18 PAU70B18 PAU70C18 PAU70D18 PAU70E18 PAU70F18 PAU70G18 PAU70H18 PAU70J18 PAU70K18 PAU70L18 PAU70M18 PAU70N18 PAU70P18 PAU70R18 PAU70T18 PAU70U18 PAU70V18
PAU70A17 PAU70B17 PAU70C17 PAU70D17 PAU70E17 PAU70F17 PAU70G17 PAU70H17 PAU70J17 PAU70K17 PAU70L17 PAU70M17 PAU70N17 PAU70P17 PAU70R17 PAU70T17 PAU70U17 PAU70V17
PAU70A16 PAU70B16 PAU70C16 PAU70D16 PAU70E16 PAU70F16 PAU70G16 PAU70H16 PAU70J16 PAU70K16 PAU70L16 PAU70M16 PAU70N16 PAU70P16 PAU70R16 PAU70T16 PAU70U16 PAU70V16
PAU70A15 PAU70B15 PAU70C15 PAU70D15 PAU70E15 PAU70F15 PAU70G15 PAU70H15 PAU70J15 PAU70K15 PAU70L15 PAU70M15 PAU70N15 PAU70P15 PAU70R15 PAU70T15 PAU70U15 PAU70V15
PAU70A14 PAU70B14 PAU70C14 PAU70D14 PAU70E14 PAU70F14 PAU70G14 PAU70H14 PAU70J14 PAU70K14 PAU70L14 PAU70M14 PAU70N14 PAU70P14 PAU70R14 PAU70T14 PAU70U14 PAU70V14
PAR4702
PAR4701
PAU70A13 PAU70B13 PAU70C13 PAU70D13 PAU70E13 PAU70F13 PAU70G13 PAU70H13 PAU70J13 PAU70K13 PAU70L13 PAU70M13 PAU70N13 PAU70P13 PAU70R13 PAU70T13 PAU70U13 PAU70V13
PAU70A12 PAU70B12 PAU70C12 PAU70D12 PAU70E12 PAU70F12 PAU70G12 PAU70H12 PAU70J12 PAU70K12 PAU70L12 PAU70M12 PAU70N12 PAU70P12 PAU70R12 PAU70T12 PAU70U12 PAU70V12
PAR4602
PAU70A11 PAU70B11 PAU70C11 PAU70D11 PAU70E11 PAU70F11 PAU70G11 PAU70H11 PAU70J11 PAU70K11 PAU70L11 PAU70M11 PAU70N11 PAU70P11 PAU70R11 PAU70T11 PAU70U11 PAU70V11
PAR4601
PAU70A10 PAU70B10 PAU70C10 PAU70D10 PAU70E10 PAU70F10 PAU70G10 PAU70H10 PAU70J10 PAU70K10 PAU70L10 PAU70M10 PAU70N10 PAU70P10 PAU70R10 PAU70T10 PAU70U10 PAU70V10
PAU70A9 PAU70B9 PAU70C9 PAU70D9 PAU70E9 PAU70F9 PAU70G9 PAU70H9 PAU70J9 PAU70K9 PAU70L9 PAU70M9 PAU70N9 PAU70P9 PAU70R9 PAU70T9 PAU70U9 PAU70V9
PAU70A8 PAU70B8 PAU70C8 PAU70D8 PAU70E8 PAU70F8 PAU70G8 PAU70H8 PAU70J8 PAU70K8 PAU70L8 PAU70M8 PAU70N8 PAU70P8 PAU70R8 PAU70T8 PAU70U8 PAU70V8
PAU70A7 PAU70B7 PAU70C7 PAU70D7 PAU70E7 PAU70F7 PAU70G7 PAU70H7 PAU70J7 PAU70K7 PAU70L7 PAU70M7 PAU70N7 PAU70P7 PAU70R7 PAU70T7 PAU70U7 PAU70V7
PAU70A6 PAU70B6 PAU70C6 PAU70D6 PAU70E6 PAU70F6 PAU70G6 PAU70H6 PAU70J6 PAU70K6 PAU70L6 PAU70M6 PAU70N6 PAU70P6 PAU70R6 PAU70T6 PAU70U6 PAU70V6
PAU70A5 PAU70B5 PAU70C5 PAU70D5 PAU70E5 PAU70F5 PAU70G5 PAU70H5 PAU70J5 PAU70K5 PAU70L5 PAU70M5 PAU70N5 PAU70P5 PAU70R5 PAU70T5 PAU70U5 PAU70V5
PAU70A4 PAU70B4 PAU70C4 PAU70D4 PAU70E4 PAU70F4 PAU70G4 PAU70H4 PAU70J4 PAU70K4 PAU70L4 PAU70M4 PAU70N4 PAU70P4 PAU70R4 PAU70T4 PAU70U4 PAU70V4
PAU70A3 PAU70B3 PAU70C3 PAU70D3 PAU70E3 PAU70F3 PAU70G3 PAU70H3 PAU70J3 PAU70K3 PAU70L3 PAU70M3 PAU70N3 PAU70P3 PAU70R3 PAU70T3 PAU70U3 PAU70V3
PAU70A2 PAU70B2 PAU70C2 PAU70D2 PAU70E2 PAU70F2 PAU70G2 PAU70H2 PAU70J2 PAU70K2 PAU70L2 PAU70M2 PAU70N2 PAU70P2 PAU70R2 PAU70T2 PAU70U2 PAU70V2
PAU70A1 PAU70B1 PAU70C1 PAU70D1 PAU70E1 PAU70F1 PAU70G1 PAU70H1 PAU70J1 PAU70K1 PAU70L1 PAU70M1 PAU70N1 PAU70P1 PAU70R1 PAU70T1 PAU70U1 PAU70V1
PAR3402PAC6501
PAR3401
PAC6302
PAC6401
PAC5702 PAC5802
PAU501
PAC4202
PAU5016
PAU5015
PAU5014
PAC4201
COQ3
COR33
PAC3601 PAC3501
COC58
COC57
COR25
COR31
PAQ303
COR48
COQ2
COR34
COC21
COU6
COR32
PAQ302PAR4801PAQ203PAR4802COTP9
PAQ301
PAC2101 COR30
COC27
COC26
COC25
COC24
COC23PAR3201 PAR3202
PAC3602 PAC3502PAU502
PAC5701 PAC5801
PAU503
PAC6301
PAU504
PAU5013
PAU505
PAU506
PAU507
PAU5012
PAU5011
PAU5010
PAU508
PAU509
PAR3302 PAR3301
PAR2501 PAR2502 PAR3102 PAR3101
COP4
PAC2701 PAC2601
PAC2702 PAC2602
PAC2501 PAC2401
PAC2502 PAC2402
PAU604
PAU603
PAC2102 PAR3001 PAR3002 PAU602
PAC2301 PAC2201 PAR2601 PAU605 PAQ202
PAU601
PAC2302 PAC2202 PAR2602
COC2 COR26
PATP901
PAQ201
PA 4P0A7P54A074P0A7P34A074P20A714P0A7P40A694P0A684067 PA 4P0A5P480A574P0A5P64A054P0A54P0A5P34A0524P0A5P14A054P0AP94A084P0A74P0AP460A54P0A40PA3P4A024P0AP14A0 4P0A394P0A3P480A374P0A3P460A354P0A3P4A034P0A324P0A3P14A034P0A2P94A024P80A2P74A024P60A254P0A2P40A234P0A2P4A024P10A24P0A1P940A184P0A1P74A014P60A154P0A1P40A134P0A1420P1AP40A1P4A09P4A084P0AP7A4046PA05P4A0 4P0A3P4A02401
COC34
COP2
COR35
PAP201
COR36
PAP203
PAP205
COR37
PAP209
COR38
PAP2011
PAP2013
COR39
PAP2015
PAP202
PAP204
PAP206
PAR3501
PAR3502
PAR3601
PAR3602
PAP207
PAR3701
PAR3702
PAR3801
COP3
COR40
COC50
PAP301
PAP303
PAP305
PAP302
PAR4001
COR41
PAP304
PAR4002
PAP306
PAR4101
PAP208 PAC3401 PAC4101
PAP307
PAP2010
PAP2012
PAP2014
PAP2016
PAP2018
PAP3013
PAP3015
PAP3017
PAP3014
PAP3016
PAP3018
PAR4301
PAP3019
PAR4302
PAP3020
COR42
PAP309 PAP3010
COC13
PAP3012
PAR4102
PAP308
PAP3011
PAC3402COC40
PAC4102COC41
PAC5001 PAC4001
PAR4201
PAR4202
COR43
COC28
PAP300
COTP7
PAC5002 PAC4002
COC15
PATP701COR20
COR19
COR18
COC43
COU2
COR21
COR22
COR13
COR9 COR4
PAC1301COC14
PAC1501
COC2
COC11
COC19
COC10
COR8
301 PAC4302
PAC2801 PAC2802 COR14
PAU207 PAC1302 PAC4COR3
PAC1502
COR17
COR16
COR15
COR7
PAC101
COC18
COR10
COTP1
COC3COU1 COC4
PAL202 PAL201
PAL101
COR12
COC6 PAC102 PAL102 COC9
COC16
PAC1802 PAC1801 PAU1012PAU101 PAU1010 PAU109 PAU108 PAU107
PAC402
PAC302 PATP101
COR11
PAC602
PAC902
COC17
COL1
PAC401 PAU1025 COL2
PAC301
COQ1
COTP2
COC1
COR23
PAC601
PAC901COR5
PAC1702 PAC1701 PAU1019PAU1020PAU1021 PAU102 PAU1023 PAU1024
PAQ103
COR2
COTP3PAC1002 PAC1402 PAC1902 PAC1102 PAC202
PATP201
COC8
COC7
COC5
COR1
PAQ101
PAQ102
COTP5PAC1001 PAC1401 PAC1901 PAC1101
PATP301
PAC201
COTP6
COR6
COC12
PATP501COU4
COP1
COTP4
PATP601
COR28
COC20
PAP107 PATP401
PAC2002
COR27
PAP101
COR29
PAC2001
PAP102
COC45
COU3
PAP103
COC52
COC51
COC30
COC29 COC44
PAP104
COR24
PAP105
COTP8
PAP106
COR45
PAC4502 PAC4501
PAC2901 PAC3001
COC47
PAC5101 PAC5201
PATP801
PAP108
COU7 PAC5102 PAC5202 PAC2902 PAC3002 PAC4402 PAC4401
COC49
COC56
COC48
COC55
COC32
COC31 PAC4701 PAC4901
PAC5602
PAC4801
PAC5501COC53
PAC4702
COC46
PAC3201
PAC3101
COC33
PAC4902
PAC5601
PAC4802
PAC5502
PAC3102
PAC4602
PAC5301 PAC5302 PAC3202
COC54
COC37
PAC4601
COC67PAC3301 PAC3302
COR47
COC66 COC38
PAC5401 PAC5402
PAC3701 PAC3702
COC68
COC59
PAC3801
PAC6602 PAC6702 PAC6701COC39
PAC5901
PAC6801 PAC3802
COC60
PAC6601
COC62
COC61
COR44
PAC3902 PAC3901COC42 PAC5902
PAC6802
PAC6002 COR46
COC65 COC64
PAR4402
PAC6202 PAC6102
COU5
PAC6001
COC36
COC35
PAC6502 COC63
PAC6402
PAR4401
PAC6201 PAC6101
PAR3802
PAP2017
PAR3901
PAR3902
PAP2019
PAP200
PAP2020
PAR801 PAR1701 PAR1601 PAR1501 PAR1401
PAR802 PAR1702 PAR2002
PAR1602 PAR1902
PAR1502 PAR1402
PAR1802
PAR2001 PAR1901
PAU206 PAR1801
PAU201
PAU202
PAU203
PAR1202
PAR1201
PAR1002 PAC1602
PAR1001 PAC1601
PAR1102PAR302 PAR301
PAR1101PAR402 PAR401
PAU205
PAU204
PAU1013
PAU1014
PAU106
PAU105
PAU1015
PAU1016
PAU104
PAU103
PAU1017
PAU1018
PAU102
PAU101
PAR701
PAR702
PAR502 PAC802
PAC502 PAR102
PAR501 PAC801
PAC501 PAR101
PAR602 PAC1202
PAC702 PAR202
PAR601 PAC1201 PAR902 PAR901 PAR1302 PAR1301 PAR2201 PAR2202 PAR2101 PAR2102 PAC701 PAR201
PAU405
PAU406
PAU407
PAU409
PAU404
PAU403 PAR2302
PAR2802
PAR2801
PAU402 PAR2301
PAU401
PAR2702
PAR2701
PAU309
PAU308
PAU3010
PAU3011
PAU3012
PAU307
PAU306
PAU305
PAR2902
PAU3013
PAU304
PAR2401 PAR2402 PAU303
PAU408
PAU3014
PAU3015
PAU3016
PAR2901
PAU302
PAU301
PAR4501
PAR4502
PAU70A18 PAU70B18 PAU70C18 PAU70D18 PAU70E18 PAU70F18 PAU70G18 PAU70H18 PAU70J18 PAU70K18 PAU70L18 PAU70M18 PAU70N18 PAU70P18 PAU70R18 PAU70T18 PAU70U18 PAU70V18
PAU70A17 PAU70B17 PAU70C17 PAU70D17 PAU70E17 PAU70F17 PAU70G17 PAU70H17 PAU70J17 PAU70K17 PAU70L17 PAU70M17 PAU70N17 PAU70P17 PAU70R17 PAU70T17 PAU70U17 PAU70V17
PAU70A16 PAU70B16 PAU70C16 PAU70D16 PAU70E16 PAU70F16 PAU70G16 PAU70H16 PAU70J16 PAU70K16 PAU70L16 PAU70M16 PAU70N16 PAU70P16 PAU70R16 PAU70T16 PAU70U16 PAU70V16
PAU70A15 PAU70B15 PAU70C15 PAU70D15 PAU70E15 PAU70F15 PAU70G15 PAU70H15 PAU70J15 PAU70K15 PAU70L15 PAU70M15 PAU70N15 PAU70P15 PAU70R15 PAU70T15 PAU70U15 PAU70V15
PAU70A14 PAU70B14 PAU70C14 PAU70D14 PAU70E14 PAU70F14 PAU70G14 PAU70H14 PAU70J14 PAU70K14 PAU70L14 PAU70M14 PAU70N14 PAU70P14 PAU70R14 PAU70T14 PAU70U14 PAU70V14
PAR4702
PAR4701
PAU70A13 PAU70B13 PAU70C13 PAU70D13 PAU70E13 PAU70F13 PAU70G13 PAU70H13 PAU70J13 PAU70K13 PAU70L13 PAU70M13 PAU70N13 PAU70P13 PAU70R13 PAU70T13 PAU70U13 PAU70V13
PAU70A12 PAU70B12 PAU70C12 PAU70D12 PAU70E12 PAU70F12 PAU70G12 PAU70H12 PAU70J12 PAU70K12 PAU70L12 PAU70M12 PAU70N12 PAU70P12 PAU70R12 PAU70T12 PAU70U12 PAU70V12
PAR4602
PAU70A11 PAU70B11 PAU70C11 PAU70D11 PAU70E11 PAU70F11 PAU70G11 PAU70H11 PAU70J11 PAU70K11 PAU70L11 PAU70M11 PAU70N11 PAU70P11 PAU70R11 PAU70T11 PAU70U11 PAU70V11
PAR4601
PAU70A10 PAU70B10 PAU70C10 PAU70D10 PAU70E10 PAU70F10 PAU70G10 PAU70H10 PAU70J10 PAU70K10 PAU70L10 PAU70M10 PAU70N10 PAU70P10 PAU70R10 PAU70T10 PAU70U10 PAU70V10
PAU70A9 PAU70B9 PAU70C9 PAU70D9 PAU70E9 PAU70F9 PAU70G9 PAU70H9 PAU70J9 PAU70K9 PAU70L9 PAU70M9 PAU70N9 PAU70P9 PAU70R9 PAU70T9 PAU70U9 PAU70V9
PAU70A8 PAU70B8 PAU70C8 PAU70D8 PAU70E8 PAU70F8 PAU70G8 PAU70H8 PAU70J8 PAU70K8 PAU70L8 PAU70M8 PAU70N8 PAU70P8 PAU70R8 PAU70T8 PAU70U8 PAU70V8
PAU70A7 PAU70B7 PAU70C7 PAU70D7 PAU70E7 PAU70F7 PAU70G7 PAU70H7 PAU70J7 PAU70K7 PAU70L7 PAU70M7 PAU70N7 PAU70P7 PAU70R7 PAU70T7 PAU70U7 PAU70V7
PAU70A6 PAU70B6 PAU70C6 PAU70D6 PAU70E6 PAU70F6 PAU70G6 PAU70H6 PAU70J6 PAU70K6 PAU70L6 PAU70M6 PAU70N6 PAU70P6 PAU70R6 PAU70T6 PAU70U6 PAU70V6
PAU70A5 PAU70B5 PAU70C5 PAU70D5 PAU70E5 PAU70F5 PAU70G5 PAU70H5 PAU70J5 PAU70K5 PAU70L5 PAU70M5 PAU70N5 PAU70P5 PAU70R5 PAU70T5 PAU70U5 PAU70V5
PAU70A4 PAU70B4 PAU70C4 PAU70D4 PAU70E4 PAU70F4 PAU70G4 PAU70H4 PAU70J4 PAU70K4 PAU70L4 PAU70M4 PAU70N4 PAU70P4 PAU70R4 PAU70T4 PAU70U4 PAU70V4
PAU70A3 PAU70B3 PAU70C3 PAU70D3 PAU70E3 PAU70F3 PAU70G3 PAU70H3 PAU70J3 PAU70K3 PAU70L3 PAU70M3 PAU70N3 PAU70P3 PAU70R3 PAU70T3 PAU70U3 PAU70V3
PAU70A2 PAU70B2 PAU70C2 PAU70D2 PAU70E2 PAU70F2 PAU70G2 PAU70H2 PAU70J2 PAU70K2 PAU70L2 PAU70M2 PAU70N2 PAU70P2 PAU70R2 PAU70T2 PAU70U2 PAU70V2
PAU70A1 PAU70B1 PAU70C1 PAU70D1 PAU70E1 PAU70F1 PAU70G1 PAU70H1 PAU70J1 PAU70K1 PAU70L1 PAU70M1 PAU70N1 PAU70P1 PAU70R1 PAU70T1 PAU70U1 PAU70V1
PAR3402PAC6501
PAR3401
PAC6302
PAC6401
PAC5702 PAC5802
PAU501
PAC4202
PAU5016
PAU5015
PAU5014
PAC4201
COQ3
COR33
PAC3601 PAC3501
COC58
COC57
COR25
COR31
PAQ303
COR48
COQ2
COR34
COC21
COU6
COR32
PAQ302PAR4801PAQ203PAR4802COTP9
PAQ301
PAC2101 COR30
COC27
COC26
COC25
COC24
COC23PAR3201 PAR3202
PAC3602 PAC3502PAU502
PAC5701 PAC5801
PAU503
PAC6301
PAU504
PAU5013
PAU505
PAU506
PAU507
PAU5012
PAU5011
PAU5010
PAU508
PAU509
PAR3302 PAR3301
PAR2501 PAR2502 PAR3102 PAR3101
COP4
PAC2701 PAC2601
PAC2702 PAC2602
PAC2501 PAC2401
PAC2502 PAC2402
PAU604
PAU603
PAC2102 PAR3001 PAR3002 PAU602
PAC2301 PAC2201 PAR2601 PAU605 PAQ202
PAU601
PAC2302 PAC2202 PAR2602
COC2 COR26
PATP901
PAQ201
PA 4P0A7P54A074P0A7P34A074P20A714P0A7P40A694P0A684067 PA 4P0A5P480A574P0A5P64A054P0A54P0A5P34A0524P0A5P14A054P0AP94A084P0A74P0AP460A54P0A40PA3P4A024P0AP14A0 4P0A394P0A3P480A374P0A3P460A354P0A3P4A034P0A324P0A3P14A034P0A2P94A024P80A2P74A024P60A254P0A2P40A234P0A2P4A024P10A24P0A1P940A184P0A1P74A014P60A154P0A1P40A134P0A1420P1AP40A1P4A09P4A084P0AP7A4046PA05P4A0 4P0A3P4A02401
COC34
COP2
COR35
PAP201
COR36
PAP203
PAP205
COR37
PAP209
COR38
PAP2011
PAP2013
COR39
PAP2015
PAP202
PAP204
PAP206
PAR3501
PAR3502
PAR3601
PAR3602
PAP207
PAR3701
PAR3702
PAR3801
COP3
COR40
COC50
PAP301
PAP303
PAP305
PAP302
PAR4001
COR41
PAP304
PAR4002
PAP306
PAR4101
PAP208 PAC3401 PAC4101
PAP307
PAP2010
PAP2012
PAP2014
PAP2016
PAP2018
PAP3013
PAP3015
PAP3017
PAP3014
PAP3016
PAP3018
PAR4301
PAP3019
PAR4302
PAP3020
COR42
PAP309 PAP3010
COC13
PAP3012
PAR4102
PAP308
PAP3011
PAC3402COC40
PAC4102COC41
PAC5001 PAC4001
PAR4201
PAR4202
COR43
COC28
PAP300
COTP7
PAC5002 PAC4002
COC15
PATP701COR20
COR19
COR18
COC43
COU2
COR21
COR22
COR13
COR9 COR4
PAC1301COC14
PAC1501
COC2
COC11
COC19
COC10
COR8
301 PAC4302
PAC2801 PAC2802 COR14
PAU207 PAC1302 PAC4COR3
PAC1502
COR17
COR16
COR15
COR7
PAC101
COC18
COR10
COTP1
COC3COU1 COC4
PAL202 PAL201
PAL101
COR12
COC6 PAC102 PAL102 COC9
COC16
PAC1802 PAC1801 PAU1012PAU101 PAU1010 PAU109 PAU108 PAU107
PAC402
PAC302 PATP101
COR11
PAC602
PAC902
COC17
COL1
PAC401 PAU1025 COL2
PAC301
COQ1
COTP2
COC1
COR23
PAC601
PAC901COR5
PAC1702 PAC1701 PAU1019PAU1020PAU1021 PAU102 PAU1023 PAU1024
PAQ103
COR2
COTP3PAC1002 PAC1402 PAC1902 PAC1102 PAC202
PATP201
COC8
COC7
COC5
COR1
PAQ101
PAQ102
COTP5PAC1001 PAC1401 PAC1901 PAC1101
PATP301
PAC201
COTP6
COR6
COC12
PATP501COU4
COP1
COTP4
PATP601
COR28
COC20
PAP107 PATP401
PAC2002
COR27
PAP101
COR29
PAC2001
PAP102
COC45
COU3
PAP103
COC52
COC51
COC30
COC29 COC44
PAP104
COR24
PAP105
COTP8
PAP106
COR45
PAC4502 PAC4501
PAC2901 PAC3001
COC47
PAC5101 PAC5201
PATP801
PAP108
COU7 PAC5102 PAC5202 PAC2902 PAC3002 PAC4402 PAC4401
COC49
COC56
COC48
COC55
COC32
COC31 PAC4701 PAC4901
PAC5602
PAC4801
PAC5501COC53
PAC4702
COC46
PAC3201
PAC3101
COC33
PAC4902
PAC5601
PAC4802
PAC5502
PAC3102
PAC4602
PAC5301 PAC5302 PAC3202
COC54
COC37
PAC4601
COC67PAC3301 PAC3302
COR47
COC66 COC38
PAC5401 PAC5402
PAC3701 PAC3702
COC68
COC59
PAC3801
PAC6602 PAC6702 PAC6701COC39
PAC5901
PAC6801 PAC3802
COC60
PAC6601
COC62
COC61
COR44
PAC3902 PAC3901COC42 PAC5902
PAC6802
PAC6002 COR46
COC65 COC64
PAR4402
PAC6202 PAC6102
COU5
PAC6001
COC36
COC35
PAC6502 COC63
PAC6402
PAR4401
PAC6201 PAC6101
PAR3802
PAP2017
PAR3901
PAR3902
PAP2019
PAP200
PAP2020
PAR801 PAR1701 PAR1601 PAR1501 PAR1401
PAR802 PAR1702 PAR2002
PAR1602 PAR1902
PAR1502 PAR1402
PAR1802
PAR2001 PAR1901
PAU206 PAR1801
PAU201
PAU202
PAU203
PAR1202
PAR1201
PAR1002 PAC1602
PAR1001 PAC1601
PAR1102PAR302 PAR301
PAR1101PAR402 PAR401
PAU205
PAU204
PAU1013
PAU1014
PAU106
PAU105
PAU1015
PAU1016
PAU104
PAU103
PAU1017
PAU1018
PAU102
PAU101
PAR701
PAR702
PAR502 PAC802
PAC502 PAR102
PAR501 PAC801
PAC501 PAR101
PAR602 PAC1202
PAC702 PAR202
PAR601 PAC1201 PAR902 PAR901 PAR1302 PAR1301 PAR2201 PAR2202 PAR2101 PAR2102 PAC701 PAR201
PAU405
PAU406
PAU407
PAU409
PAU404
PAU403 PAR2302
PAR2802
PAR2801
PAU402 PAR2301
PAU401
PAR2702
PAR2701
PAU309
PAU308
PAU3010
PAU3011
PAU3012
PAU307
PAU306
PAU305
PAR2902
PAU3013
PAU304
PAR2401 PAR2402 PAU303
PAU408
PAU3014
PAU3015
PAU3016
PAR2901
PAU302
PAU301
PAR4501
PAR4502
PAU70A18 PAU70B18 PAU70C18 PAU70D18 PAU70E18 PAU70F18 PAU70G18 PAU70H18 PAU70J18 PAU70K18 PAU70L18 PAU70M18 PAU70N18 PAU70P18 PAU70R18 PAU70T18 PAU70U18 PAU70V18
PAU70A17 PAU70B17 PAU70C17 PAU70D17 PAU70E17 PAU70F17 PAU70G17 PAU70H17 PAU70J17 PAU70K17 PAU70L17 PAU70M17 PAU70N17 PAU70P17 PAU70R17 PAU70T17 PAU70U17 PAU70V17
PAU70A16 PAU70B16 PAU70C16 PAU70D16 PAU70E16 PAU70F16 PAU70G16 PAU70H16 PAU70J16 PAU70K16 PAU70L16 PAU70M16 PAU70N16 PAU70P16 PAU70R16 PAU70T16 PAU70U16 PAU70V16
PAU70A15 PAU70B15 PAU70C15 PAU70D15 PAU70E15 PAU70F15 PAU70G15 PAU70H15 PAU70J15 PAU70K15 PAU70L15 PAU70M15 PAU70N15 PAU70P15 PAU70R15 PAU70T15 PAU70U15 PAU70V15
PAU70A14 PAU70B14 PAU70C14 PAU70D14 PAU70E14 PAU70F14 PAU70G14 PAU70H14 PAU70J14 PAU70K14 PAU70L14 PAU70M14 PAU70N14 PAU70P14 PAU70R14 PAU70T14 PAU70U14 PAU70V14
PAR4702
PAR4701
PAU70A13 PAU70B13 PAU70C13 PAU70D13 PAU70E13 PAU70F13 PAU70G13 PAU70H13 PAU70J13 PAU70K13 PAU70L13 PAU70M13 PAU70N13 PAU70P13 PAU70R13 PAU70T13 PAU70U13 PAU70V13
PAU70A12 PAU70B12 PAU70C12 PAU70D12 PAU70E12 PAU70F12 PAU70G12 PAU70H12 PAU70J12 PAU70K12 PAU70L12 PAU70M12 PAU70N12 PAU70P12 PAU70R12 PAU70T12 PAU70U12 PAU70V12
PAR4602
PAU70A11 PAU70B11 PAU70C11 PAU70D11 PAU70E11 PAU70F11 PAU70G11 PAU70H11 PAU70J11 PAU70K11 PAU70L11 PAU70M11 PAU70N11 PAU70P11 PAU70R11 PAU70T11 PAU70U11 PAU70V11
PAR4601
PAU70A10 PAU70B10 PAU70C10 PAU70D10 PAU70E10 PAU70F10 PAU70G10 PAU70H10 PAU70J10 PAU70K10 PAU70L10 PAU70M10 PAU70N10 PAU70P10 PAU70R10 PAU70T10 PAU70U10 PAU70V10
PAU70A9 PAU70B9 PAU70C9 PAU70D9 PAU70E9 PAU70F9 PAU70G9 PAU70H9 PAU70J9 PAU70K9 PAU70L9 PAU70M9 PAU70N9 PAU70P9 PAU70R9 PAU70T9 PAU70U9 PAU70V9
PAU70A8 PAU70B8 PAU70C8 PAU70D8 PAU70E8 PAU70F8 PAU70G8 PAU70H8 PAU70J8 PAU70K8 PAU70L8 PAU70M8 PAU70N8 PAU70P8 PAU70R8 PAU70T8 PAU70U8 PAU70V8
PAU70A7 PAU70B7 PAU70C7 PAU70D7 PAU70E7 PAU70F7 PAU70G7 PAU70H7 PAU70J7 PAU70K7 PAU70L7 PAU70M7 PAU70N7 PAU70P7 PAU70R7 PAU70T7 PAU70U7 PAU70V7
PAU70A6 PAU70B6 PAU70C6 PAU70D6 PAU70E6 PAU70F6 PAU70G6 PAU70H6 PAU70J6 PAU70K6 PAU70L6 PAU70M6 PAU70N6 PAU70P6 PAU70R6 PAU70T6 PAU70U6 PAU70V6
PAU70A5 PAU70B5 PAU70C5 PAU70D5 PAU70E5 PAU70F5 PAU70G5 PAU70H5 PAU70J5 PAU70K5 PAU70L5 PAU70M5 PAU70N5 PAU70P5 PAU70R5 PAU70T5 PAU70U5 PAU70V5
PAU70A4 PAU70B4 PAU70C4 PAU70D4 PAU70E4 PAU70F4 PAU70G4 PAU70H4 PAU70J4 PAU70K4 PAU70L4 PAU70M4 PAU70N4 PAU70P4 PAU70R4 PAU70T4 PAU70U4 PAU70V4
PAU70A3 PAU70B3 PAU70C3 PAU70D3 PAU70E3 PAU70F3 PAU70G3 PAU70H3 PAU70J3 PAU70K3 PAU70L3 PAU70M3 PAU70N3 PAU70P3 PAU70R3 PAU70T3 PAU70U3 PAU70V3
PAU70A2 PAU70B2 PAU70C2 PAU70D2 PAU70E2 PAU70F2 PAU70G2 PAU70H2 PAU70J2 PAU70K2 PAU70L2 PAU70M2 PAU70N2 PAU70P2 PAU70R2 PAU70T2 PAU70U2 PAU70V2
PAU70A1 PAU70B1 PAU70C1 PAU70D1 PAU70E1 PAU70F1 PAU70G1 PAU70H1 PAU70J1 PAU70K1 PAU70L1 PAU70M1 PAU70N1 PAU70P1 PAU70R1 PAU70T1 PAU70U1 PAU70V1
PAR3402PAC6501
PAR3401
PAC6302
PAC6401
PAC5702 PAC5802
PAU501
PAC4202
PAU5016
PAU5015
PAU5014
PAC4201
COQ3
COR33
PAC3601 PAC3501
COC58
COC57
COR25
COR31
PAQ303
COR48
COQ2
COR34
COC21
COU6
COR32
PAQ302PAR4801PAQ203PAR4802COTP9
PAQ301
PAC2101 COR30
COC27
COC26
COC25
COC24
COC23PAR3201 PAR3202
PAC3602 PAC3502PAU502
PAC5701 PAC5801
PAU503
PAC6301
PAU504
PAU5013
PAU505
PAU506
PAU507
PAU5012
PAU5011
PAU5010
PAU508
PAU509
PAR3302 PAR3301
PAR2501 PAR2502 PAR3102 PAR3101
COP4
PAC2701 PAC2601
PAC2702 PAC2602
PAC2501 PAC2401
PAC2502 PAC2402
PAU604
PAU603
PAC2102 PAR3001 PAR3002 PAU602
PAC2301 PAC2201 PAR2601 PAU605 PAQ202
PAU601
PAC2302 PAC2202 PAR2602
COC2 COR26
PATP901
PAQ201
PA 4P0A7P54A074P0A7P34A074P20A714P0A7P40A694P0A684067 PA 4P0A5P480A574P0A5P64A054P0A54P0A5P34A0524P0A5P14A054P0AP94A084P0A74P0AP460A54P0A40PA3P4A024P0AP14A0 4P0A394P0A3P480A374P0A3P460A354P0A3P4A034P0A324P0A3P14A034P0A2P94A024P80A2P74A024P60A254P0A2P40A234P0A2P4A024P10A24P0A1P940A184P0A1P74A014P60A154P0A1P40A134P0A1420P1AP40A1P4A09P4A084P0AP7A4046PA05P4A0 4P0A3P4A02401
Designator
C1
C2
C3
C4
C5
C6
C8
C9
C10
C11
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C31
C32
C34
C35
C37
C38
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
L1
L2
P1
P2
P3
Q1
Q2
Q3
R1
R2
R3
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R31
R33
R34
R45
R46
R47
R48
U1
U2
U3
U4
U5
U6
U7
Value
1uF
1uF
10uF
10uF
15pF
10uF
8.2pF
10uF
1uF
1uF
1uF
1uF
1uF
100nF
100nF
100nF
1uF
0.47uF
0.47uF
100nF
100nF
100nF
100nF
100nF
100nF
100uF
4.7uF
0.47uF
0.47uF
100uF
4.7uF
0.47uF
0.47uF
100uF
100uF
0.47uF
100uF
4.7uF
4.7uF
0.47uF
0.47uF
0.47uF
0.47uF
100uF
4.7uF
4.7uF
0.47uF
0.47uF
0.47uF
0.47uF
4.7uF
4.7uF
0.47uF
0.47uF
0.47uF
0.47uF
4.7uF
0.47uF
0.47uF
4.7uF
0.47uF
0.47uF
2.2uH
2.2uH
Manufacturer
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Murata Electronics
Sumida
Sumida
JST Sales America Inc.
Harwin
Harwin
Infineon Technologies
Infineon Technologies
Infineon Technologies
Part Number
GRT188R71E105KE13D
GRT188R71E105KE13D
GRM21BR61C106KE15
GRM21BR61C106KE15
GCM1555C1H150JA16D
GRM21BR61C106KE15
GJM1555C1H8R2CB01D
GRM21BR61C106KE15
GRT188R71E105KE13D
GRT188R71E105KE13D
GRT188R71E105KE13D
GRT188R71E105KE13D
GRT188R71E105KE13D
GCM155R71C104KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GRT188R71E105KE13D
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GCM155R71C104KA55D
GRM32ER61A107ME20
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM32ER61A107ME20
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM32ER61A107ME20
GRM32ER61A107ME20
GCM188R71C474KA55D
GRM32ER61A107ME20
GRM188R61C475KE11J
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM32ER61A107ME20
GRM188R61C475KE11J
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM188R61C475KE11J
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
GRM188R61C475KE11J
GCM188R71C474KA55D
GCM188R71C474KA55D
CDRH2D14NP-2R2N
CDRH2D14NP-2R2N
B6B-ZR-SM3-TF
M50-3611042
M50-3611042
BSS806NEH6327XTSA1
BSS806NEH6327XTSA1
BSS806NEH6327XTSA1
Provider
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
Provider Number
Comment
81-GRT188R71E105KE3D
81-GRT188R71E105KE3D
81-GRM21BR61C106KE15
81-GRM21BR61C106KE15
81-GCM1555C1H150JA6D
81-GRM21BR61C106KE15
81-GJM1555C1H8R2CB01
81-GRM21BR61C106KE15
81-GRT188R71E105KE3D
81-GRT188R71E105KE3D
81-GRT188R71E105KE3D
81-GRT188R71E105KE3D
81-GRT188R71E105KE3D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GRT188R71E105KE3D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GCM155R71C104KA5D
81-GRM32ER61A107ME0L
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM32ER61A107ME0L
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM32ER61A107ME0L
81-GRM32ER61A107ME0L
81-GCM188R71C474KA5D
81-GRM32ER61A107ME0L
81-GRM188R61C475KE1J
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM32ER61A107ME0L
81-GRM188R61C475KE1J
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM188R61C475KE1J
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
81-GRM188R61C475KE1J
81-GCM188R71C474KA5D
81-GCM188R71C474KA5D
851-CDRH2D14NP-2R2NC
851-CDRH2D14NP-2R2NC
JTAG
855-M50-3611042
M50-361
855-M50-3611042
M50-361
726-BSS806NEH6327XTS BSS806
726-BSS806NEH6327XTS BSS806
726-BSS806NEH6327XTS BSS806
Mouser
Mouser
Mouser
Mouser
Mouser
Mouser
926-LM26480QSQCFNOPB
595-TLV75801PDRVR
595-TS3A5018PWR
579-ST26VF016B104IMF
771-SC18IS602BIPW8HP
556-AT24C04D-STUM-T
100K
100K
0
390K
150K
100K
39K
47K
10K
15K
4.7K
33K
33K
15K
10K
33K
2.7K
1.5K
220
100K
100K
10K
10K
10K
10K
10K
10K
10K
10K
10K
100
330
4.7K
4.7K
10K
Texas Instruments
LM26480QSQ-CF/NOPB
Texas Instruments
TLV75801PDRVR
Texas Instruments
TS3A5018PWR
Microchip Technology
SST26VF016B-104I/MF
NXP Semiconductors
SC18IS602BIPW/S8HP
Microchip Technology / AtmelAT24C04D-STUM-T
Xilinx Inc.
XC7A12T-2CSG325C
LM26480
TLV75801
TS3A5018
SST26VF016B
SC18IS602B
AT24C04D
Artix-7 FPGA
A
B
C
D
E
Line #
1
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4
20
21
22
26
27
28
Designator
C1, C2, C10, C11, C13, C14,
C15, C19
C3, C4, C6, C9
C5
C8
C22, C23, C24, C25, C26, C27
C21, C49, C59
C28, C34, C40, C41, C43, C50
C63
L1, L2
P1
P2, P3
Q1
R1, R2, R7, R21, R22
R3
R5
R6
R8
R9
R16, R23, R26, R27, R28,
R29, R48
R15
R46, R47
R13, R14, R17
R34
R45
U1
A
1
13
1
13
1
2
1
4
15
C12
16
1
19
6
21
R44
33
32
21
10
6
19
5
5
19
34
5
5
27
8
5
5
26
1
6
19
30
1
19
31
13
2
2
7
11
2
2
19
13
C7
22
7
1
9
7
7
1
29
7
22
20
19
22
17
13
3
28
9
2
18
7
11
14
R4
1
12
View from Top side (Scale 3)
Value
Part Number
1uF
GRT188R71E105KE13D
10uF
15pF
8.2pF
100nF
0.47uF
100uF
4.7uF
2.2uH
GRM21BR61C106KE15
GCM1555C1H150JA16D
GJM1555C1H8R2CB01D
GCM155R71C104KA55D
GCM188R71C474KA55D
GRM32ER61A107ME20
GRM188R61C475KE11J
CDRH2D14NP-2R2N
B6B-ZR-SM3-TF
M50-3611042
BSS806NEH6327XTSA1
100K
0
390K
150K
39K
47K
Comment
Line #
29
30
31
32
33
34
Designator
U2
U3
U4
U5
U6
U7
Value
Part Number
TLV75801PDRVR
TS3A5018PWR
SST26VF016B-104I/MF
SC18IS602BIPW/S8HP
AT24C04D-STUM-T
XC7A12T-2CSG325C
Comment
TLV75801
TS3A5018
SST26VF016B
SC18IS602B
AT24C04D
Artix-7 FPGA
3
JTAG
M50-361
BSS806
10K
15K
4.7K
33K
100
330
4
LM26480QSQ-CF/NOPB
B
LM26480
C
D
E
A
B
C
D
E
View from Bottom side (Scale 3)
R39
6
C30
8
8
2
R40
R41
R42
6
6
6
6
Designator
C16, C17, C18
C20, C31, C32, C37, C38,
C42, C46, C47, C48, C53,
C54, C55, C56, C60, C61,
C62, C64, C65, C67, C68
C29, C35, C44, C45, C51,
C52, C57, C58, C66
Q2, Q3
R10, R24, R25, R31, R33
R11
R12
R18
R19
R20
6
8
12
19
20
21
23
24
25
Value
100nF
Part Number
GCM155R71C104KA55D
0.47uF
GCM188R71C474KA55D
C36
6
8
6
6
R43
Line #
5
3
6
8
23
8
19
24
6
6
25
8
R32
R30
8
6
6
6
12
6
8
19
19
6
12
20
5
1
6
C39
19
6
21
6
8
6
C33
R38
19
R37
5
R36
5
R35
1
2
Comment
GRM188R61C475KE11J
4.7uF
BSS806NEH6327XTSA1
10K
15K
4.7K
2.7K
1.5K
220
BSS806
3
4
4
A
B
C
D
E
A
B
C
D
E
View from Top side (Scale 3)
1
1
TP9
TP8
TP4
TP1
TP6
TP7
2
3
2
TP2 TP3 TP5
Test point Net name
Voltage
TP1
VCCINT_1V0
1.0V
TP2
VCCAUX_1V8
1.8V
TP3
VCC_3V3
3.3V
TP4
VCCO_0_3V3
3.3V
TP5
VMGTAVTT_1V2
1.2V
TP6
VMGTAVCC_1V0
1.0V
TP7
VCCO_15_34_ADJ
Adjustable
TP8
GND
GND
TP9
EEPROM_WP
3.3V (Pull-up)
Top Layer (Scale 1:1)
3
Bottom Layer (Scale 1:1)
4
4
A
B
C
D
E
Bibliography
Appendix C - Test plan
Nr.
1
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
2
2.1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.3
2.3.1
Test
Manufacturing and mounting
Pre-component mounting
Perform brief visual inspection of
PCB
Measure continuity on sample nets
Test for short circuit on power nets
Measure trace impedance
Post-component mount
Test for short circuit on power nets
Verify resistor values on power supply
Visual inspection of solder joints
PCB under power
Measure current draw (limit supply)
Check supply voltage levels
Check power on sequence
Measure SMBus logic level before/after level conversion
Verify unused pins on M.2 connector
are not live
Debug test procedure
FPGA system
Check JTAG connectivity
Test setting LVDS/CMOS pins HIGH
one at a time
Test LDO voltage level control
SMBus
Identify EEPROM
Write data to EEPROM
Identify I2C-SPI Bridge
Set/read pins on bridge
Write test data to Flash memory and
read back
Write FPGA bitstream to flash memory
Boot FPGA from Flash memory
PCI Express
Upload small skecth with PCI Express IP core and verify that the device is detected by the platform
Pass
Fail
Comment
71