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JFET Common Drain Load-Line and Biasing

The common-drain (CD) amplifier is comparable to the common-collector BJT amplifier.the
common-drain amplifier is called a source-follower because the voltage at the source is
approximately the same amplitude as the input (gate) voltage and is in phase with it. In other
words, the source voltage follows the gate input voltage. A common-drain amplifier is one in
which the input signal is applied to the gate and the output is taken from the source, making
the drain common to both. Because it is common, there is no need for a drain resistor. A
common-drain amplifier is shown below:
Fig.1 In a CD amplifier circuit configuration the input is on the gate , but the output is
from the source.
The controlled source and terminal output impedance of the JFET are tied to ground at one
end and Rs on the other , with VO across RS. Since gm , Vgs , rd and Rs are connected to the
same terminal and ground they can all be placed in parallel . The current source reversed
direction but VGS is still define between the gate and source terminal .
The source follower configuration provides a high level of buffering and a high input
impedance. The actual input resistance of the FET itself is very high as it is a field effect
device. This means that the source follower circuit is able to provide excellent
performance as a buffer.
let us consider an n channel JFET with applied input biasing voltage VGG and output biasing
voltage VDD. VDS and ID are the drain to source voltage across the JFET element and drain
current through the JFET respectively. Applying Kirchhoff Voltage Law we get,
From here, we can say that VDS gets its maximum value when current ID is zero and the
maximum VDS is,
The maximum drain current occurs when VDS becomes zero and then the maximum value of
drain current is,
Now we will connect the coordinate of maximum VDS and maximum ID in JFET characteristic
by a straight line. This line is called dc load line. This line is so called because during
determining the line no ac signal present in the circuit only dc components are there for
biasing purpose.
During operation of a JFET as an amplifier operating point can be chosen somewhere well
within the active zone of the characteristic. But when it is determined by dc load line analysis
it would be the most optimized position of Q point.
The characteristic curve of JFET for a dc gate bias voltage VG (VG = 4 V as shown in the given
characteristic above) cuts the load line at point Q. At that Q the corresponding drain current
world be ID and drain to source voltage VDS min , VDSQ and VDS max as indicated by dotted
lines in the characteristic graph above.
Here one resistance RS is inserted between source terminal and ground.
The voltage across RS would be
Here the gate terminal is also grounded through a resistance RG. As there is no gate current,
zero ground potential appears at the gate terminal.
The voltage between the gate and source is VGS.
This equation tells us that here the gate terminal always gets negative potential than the
source terminal.
After determining the value of ID, and VDS from above relation, we can put the operating
point on the characteristic graph at the coordinate (VDS, ID).
Gate Biasing is done by inserting a battery in the gate circuit. The negative terminal of the
battery is connected to the gate terminal. As the gate current in JFET is almost zero, there
would be no voltage drop across the input gate resistance. Hence the negative potential of
the battery directly reaches to gate terminal. The corresponding drain current and drain to
source voltage would be the output operating point of the transistor.
As, in JFET there is no gate current,
We can find the value of drain current ID from the relation given below as IDSS and VGS(off)
(= – VP) are given in transistor data sheet.
The value of VDS can be found by applying KVL at output circuit
The operating point of the JFET is located at the coordinate (VDS, ID) on the characteristic
Usually it is favorable to bias junction field transistor at the midpoint of transfer characteristic cure at point
ID 
For signal conditions midpoint bias offers the maximum amount of drain current to flow between IDSS and
From equation denoted as ‘a’ is current ID is half to the IDSS when:
VGS (off )
 1 - VGS 
   VGS ( off )   
 
 
 
ID = IDSS 1  
  VGS  
 
So by using VGS=VGS(off )/3.4 we can get midpoint bias in the form of ID
Two series connected resistors form a voltage divider circuit. The voltage at the gate
terminal can be calculated by voltage division rule. In this way, the applied drain voltage is
utilized to get the gate terminal voltage. A resistance is inserted into source terminal in
series. The device current flows through the resistance and causes a voltage drop. If this
source voltage drop is greater than voltage appears at the gate terminal, the gate to source
voltage has a negative value which is desired for JFET operation. Let us consider the
following circuit.
The current source bias is a technique used to increase Q point stability of self-biased
junction field-effect transistor through making ID independent on the VGS.It can be formed
by connecting constant current source in series with the source of junction field effect
transistor. It is shown in the below figure denoted as ‘a’.In this circuitry BJT is operating as a
constant current source since its emitter current will be constant if
The FET can also be used as constant current source.
ID 
In figure denoted as ‘b’ current ID is constant for any transfer characteristic curve as denoted
through the horizontal load line.