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Electric Power Systems Research 86 (2012) 122–130
Contents lists available at SciVerse ScienceDirect
Electric Power Systems Research
journal homepage: www.elsevier.com/locate/epsr
Symmetric and asymmetric multilevel inverter topologies with reduced
switching devices
Ebrahim Babaei ∗ , Mohammad Farhadi Kangarlu, Farshid Najaty Mazgar
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
a r t i c l e
i n f o
Article history:
Received 3 August 2011
Received in revised form
23 November 2011
Accepted 19 December 2011
Available online 5 January 2012
Keywords:
Multilevel inverter
Symmetric multilevel inverter
Asymmetric multilevel inverter
Reduced switching devices
a b s t r a c t
Multilevel inverters have been developed to handle high power and high voltage in the flexible power
systems. These inverters offer some inherent advantages over conventional 2-level inverters. High quality
of the output voltage of the multilevel inverters is one of the most important advantages. In this paper,
new symmetric and asymmetric multilevel inverter topologies are proposed. The proposed multilevel
inverters use reduced number of switching devices for a specified number of output voltage levels in
comparison with the conventional multilevel inverters and other non-conventional topologies. Hybrid
topologies extracted from the proposed topologies are proposed for operating in higher voltage levels.
In order to validate the proposed topologies, the simulation results with PSCAD/EMTDC software as well
as the experimental results from a laboratory prototype are presented.
© 2011 Elsevier B.V. All rights reserved.
1. Introduction
The general function of a multilevel inverter is to synthesize a
desired output voltage from several levels of dc voltages as inputs
[1]. Multilevel inverters receive more and more attention from both
academy and industry. This is because of some inherent advantageous features such as ability to operate in higher voltage/power
condition and improved quality of the output waveform and better electromagnetic compatibility [2]. The concept of multilevel
inverter is to produce a staircase output voltage using the available dc voltage sources. The higher the number of voltage level the
better the output voltage quality. There are three well-known types
of multilevel inverters. These are the cascaded H-bridge (CHB) multilevel inverter, the flying capacitor (FC) multilevel inverter and the
neutral point clamped (NPC) multilevel inverter [3].
The CHB multilevel inverter can be symmetric in which the values of the dc voltage sources are equal or asymmetric in which the
values of the dc voltage sources are not equal. The symmetric CHB
multilevel inverter offers the advantage of high modularity. However, this topology uses high number of switches. Increase in the
number of switches results in high cost and control complexity. In
order to get higher number of output voltage levels, the dc voltage sources that are used in the CHB multilevel inverter can have
∗ Corresponding author. Tel.: +98 411 3300819; fax: +98 411 3300819.
E-mail addresses: [email protected], [email protected]
(E. Babaei).
0378-7796/$ – see front matter © 2011 Elsevier B.V. All rights reserved.
doi:10.1016/j.epsr.2011.12.013
different values (asymmetric topology). However, the topology
looses modularity.
The NPC inverter was based on a modification of the classic 2level inverter topology adding two new power semiconductors per
phase. Using this topology, each power device has to stand, at the
most, half voltage in comparison with the two-level case with the
same dc-link voltage. So, if these power semiconductors have the
same characteristics as the 2-level case, the voltage can be doubled.
However, the NPC inverters require clamping diodes and are prone
to voltage imbalances in their dc capacitors [4] which have kept the
industrial acceptance of the NPC topology up to three levels only
[5].
The FC inverter has attracted a great deal of interest in recent
years mainly due to a number of advantageous features. For
instance, it seems that the extension of the inverter to higher than
three levels is possibly easier than the NPC alternative in commercial applications. However, a number of drawbacks need to be
further addressed. These include large capacitor banks, additional
precharging circuitry, and in particular voltage imbalance amongst
FCs [6].
The above-mentioned topologies are the basic topologies. Many
modified topologies have been introduced. A multilevel inverter
using bidirectional switches has been presented in Ref. [7]. This
topology can be both symmetric and asymmetric. However, when
it is symmetric it does not have any advantage. Even if it is asymmetric, the number of power electronic components remains high
since it uses bidirectional switches. Moreover, it cannot generate
all the expected voltage steps. Another topology using bidirectional
switches has been presented in Ref. [8]. This topology is slightly
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
Table 1
States of the switches for different output voltage levels in the proposed symmetric
multilevel inverter.
Vdc
S nu 1
S nu
2
Vdc
S nu
123
S nu
3
4
S 3u
Vdc
T1
S1u
S 2u
vo
S 2l
T3
T4
S 3l
S nl
3
−nVdc
.
.
.
n−2
n−1
n
n+1
n+2
n+3
n+4
.
.
.
2n + 4
.
.
.
u
T2 , T3 , S2 , S2l , S3u , S3l
T2 , T3 , S1l , S2u , S3u
T2 , T3 , S1u , S1l
(T1 ,T2 ) or (T3 ,T4 )
T1 , T4 , S1u , S1l
T1 , T4 , S1l , S2u , S3u
T1 , T4 , S2u , S2l , S3u , S3l
.
.
.
u
l
u
l
u
l
T1 , T4 , S2 , S2 . . . , Sn−3 , Sn−3
, Sn−1
, Sn−1
.
.
.
−3Vdc
−2Vdc
−Vdc
0
Vdc
2Vdc
3Vdc
.
.
.
nVdc
1
S nl
4
2
Level creator part
A new topology is proposed for both symmetric and asymmetric multilevel inverters. The proposed topologies for symmetric
and asymmetric multilevel inverters are quite different. They are
described in the following subsections.
2.1. Proposed symmetric multilevel inverter
Vdc
Vdc
Output voltage
u
l
u
l
T2 , T3 , S2u , S2l . . . , Sn−3
, Sn−3
, Sn−1
, Sn−1
2. The proposed multilevel inverters
iL
S1l
Vdc
S nl
On switches
1
vL
Vdc
S nl
T2
State
H
bridge
Fig. 1. Proposed symmetric multilevel inverter.
better than the previous, from the view point of the number of
switches. As a result of using bidirectional switches, the number of
switches used in this topology is still high. A 5-level inverter has
been presented in Ref. [9]. The topology uses four high frequency,
four low frequency isolated gate bipolar transistors (IGBTs) and a dc
voltage source. The topology has not been extended to higher levels. Other multilevel inverter using series and parallel connection
of dc voltage sources has been introduced in Ref. [10]. In this topology the number of IGBTs is lower than the CHB multilevel inverter.
Beside these topologies, many other topologies can be found in the
literature [11–22]. These topologies consider improvement in the
performance of the multilevel inverters rather than reduction in the
number of switching devices. A regenerative multilevel inverter
based on cascaded bridges has been presented in Ref. [12]. The
inverter is the same as the CHB multilevel inverter in its inverter
side. However, this topology reduces the number of switches in
its rectifier side using cascaded half bridge inverters instead of full
bridge inverters.
In this paper, new topologies for symmetric and asymmetric
multilevel inverters and hybrid topologies resulted from them with
reduced number of switches are proposed. The principle operation
and power circuit topology of the proposed multilevel inverters
are discussed in the next section. Then a comparison between the
proposed topologies and the other topologies is given. After that,
the hybrid topologies are investigated. Finally, the simulation and
experimental results are illustrated to validate the capability of the
proposed topology in generation of desired output voltage.
Fig. 1 shows the proposed topology for symmetric multilevel
inverter. As the figure shows, the multilevel inverter is composed
of two parts: the level creator part and the H-bridge. The level creator part generates the voltage levels using a specific arrangement
of dc sources and power electronic switches. The dc sources used
in the proposed topology have the same values equal to Vdc (symmetric topology). The dc sources are separated from each other by
a switch so that each dc source can be conducted to the output
or bypassed leading to a multilevel output voltage. It is obvious
that the output voltage of the level creator part is always positive.
To change the polarity of the output voltage in every half cycle,
an H-bridge is used at the output of the level creator part. The Hbridge is also required to produce the zero voltage level. Based on
the states of the switches, different levels of output voltage are
V1
S1
S2
V2
T1
S3
S4
T2
vL
V3
S6
Vn
S5
vo
iL
T3
1
S2n
S2n
3
S 2n
1
T4
2
Vn
S 2n
Fig. 2. Proposed asymmetric multilevel inverter.
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E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
Table 2
States of the switches for different output voltage levels in the proposed asymmetric
multilevel inverter.
State
On switches
Output voltage
1
T1 , T4 , S2 , S4 , S6 , . . ., S2n−2 , S2n
−
.
.
.
2n − 5
2n − 4
2n − 3
2n − 2
2n − 1
2n
2n + 1
2n + 2
2n + 3
2n + 4
2n + 5
2n + 6
2n + 7
.
.
.
.
.
.
T1 , T4 , S2 , S4 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S1 , S4 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S3 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S1 , S3 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S4 , S5 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S3 , S5 , . . ., S(2n−3) , S(2n−3)
S1 , S3 , S5 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S3 , S5 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S4 , S5 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S1 , S3 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S3 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S1 , S4 , S6 , . . ., S(2n−3) , S(2n−3)
T1 , T4 , S2 , S4 , S6 , . . ., S(2n−3) , S(2n−3)
.
.
.
.
.
.
−(V1 + V2 + V3 )
−(V2 + V3 )
−(V1 + V3 )
−V3
−(V1 + V2 )
−V1
0
V1
V1 + V2
V3
V1 + V3
V2 + V3
V1 + V2 + V3
.
.
.
4n + 1
T1 , T4 , S2 , S4 , S6 , . . ., S2n−2 , S2n
40
Vi
N IGBT
i=1
n
20
Proposed symmetric
0
0
generated by proper switching between the switches. For instance,
if the switches S1u and S1l are turned on, the output voltage of ±Vdc is
obtained depending on the state of the H-bridge switches. Similarly,
to generate the output voltage of ±2Vdc the switches S1l , S2u and S3u
are turned on. Table 1 shows the switching states of the proposed
symmetric multilevel inverter. It is noticeable that the difference
between the states of the switches in positive and negative values of
the output voltage is related to the states of the H-bridge switches.
In this Table, n shows the number of the dc voltage sources.
For the symmetric multilevel inverter with n dc sources, the
following equations can be written:
Nlevel = 2n + 1
(1)
NIGBT = 2n + 2
(2)
vo, max = nVdc
(3)
where, Nlevel , NIGBT , and vo,max denote the number of output voltage
levels, number of IGBTs and maximum output voltage, respectively.
Using (1) and (2), the relation between Nlevel and NIGBT can be
obtained as follows for the proposed symmetric topology:
Fig. 2 shows the proposed asymmetric multilevel inverter. As
like as the symmetric one, the asymmetric topology is also composed of two parts, the level creator part and the H-bridge part.
The H-bridge part is as the same as the symmetric topology. But,
the other part is quite different. Unlike the symmetric topology,
the asymmetric topology must be able to bypass or conduct the dc
voltage sources separately. This is necessary to generate all of the
desired voltage levels. For this purpose, two additional switches are
used to fulfill the requirement of an asymmetric multilevel inverter.
As an example, when V2 is required at the output, the other dc
voltage sources must be bypassed.
Table 2 indicates the states of the switches to produce different
levels of output voltage.
10
15
20
25
30
35
Fig. 3. Comparison of the IGBTs used for a given number of voltage levels for the
symmetric topologies.
For the asymmetric multilevel inverter, the relation between the
values of the dc sources is considered as follows:
i = 1, 2, · · ·, n
(5)
Eq. (5) shows a binary increasing of the value of the dc sources.
With these values for the dc sources, all of the possible voltage levels
can be generated at the output. The number of output voltage levels
and IGBTs can be written as follows:
Nlevel = 2(n+1) − 1
(6)
NIGBT = 2n + 4
(7)
The maximum achievable output voltage can be written as follows in terms of the number of the dc sources:
vo,max = (2n − 1)Vdc
(8)
For the proposed asymmetric topology, using (6)–(7), the relation between Nlevel and NIGBT can be obtained as follows:
Nlevel = 2(NIGBT −2)/2 − 1
(9)
Comparing (4) and (9), the asymmetric multilevel inverter produces much higher number of output voltage levels for the same
number of IGBTs or the asymmetric multilevel inverter uses much
lower number of IGBTs for the same number of output voltage
levels. This is the advantage of the asymmetric topology over
the symmetric topology. However, this kind of multilevel inverter
requires dc voltage sources with different values, providing of the
dc voltage sources with different values can be a challenging issue.
35
(4)
2.2. Proposed asymmetric multilevel inverter
5
NL
Vi = 2(i−1) Vdc
Vi
i=1
Nlevel = NIGBT − 1
[10]
CHB
Number of devices in current path
n
60
30
CHB
25
[10]
20
15
10
5
0
Proposed symmetric
5
10
15
20
25
30
35
NL
Fig. 4. Number of semiconductor devices in current path in any instant of time for
the symmetric topologies versus the number of levels.
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
125
30
[8]
[7]
Proposed
Topology
v o1
Fig.1 or Fig.2
25
iL
20
N IGBT
AsymmetricCHB
vL
15
T1b
10
Vd
Proposed asymmetric
vo2
T3b
5
0
20
40
60
80
100
T2b
T4b
120
NL
Fig. 7. Hybrid multilevel inverters based on the proposed topologies.
Fig. 5. Comparison of the IGBTs used for a given number of voltage levels for the
asymmetric topologies.
3. Comparison of the proposed multilevel inverters with
other topologies
The objective in this section is to compare the number of IGBTs
used for a given number of voltage levels in the proposed topologies
and other existing topologies. In order to have the same condition, the proposed symmetric topology is compared with the
conventional symmetric CHB multilevel inverter and the symmetric topology presented in Ref. [10]. The symmetric multilevel
inverter presented in Ref. [10] uses the series and parallel connection of the dc voltage sources. It is important to mention that for this
comparison, to have the same comparison condition, the cascaded
H-bridge cell of the topology in Ref. [10] is neglected. However,
if an H-bridge is cascaded with the proposed topology, the proposed topology will be superior to that presented in Ref. [10] in
terms of the number of IGBTs used. Fig. 3 shows the number of
IGBTs used in the proposed symmetric multilevel inverter and that
of symmetric CHB multilevel inverter and the topology presented
in Ref. [10]. As the figure shows, the proposed symmetric multilevel inverter uses much lower number of IGBTs in comparison with
the other topologies. For instance, for a 15-level inverter, the proposed topology uses 18 IGBTs whereas the presented topology in
Ref. [10] and the symmetric CHB multilevel inverter use 24 and 28
IGBTs, respectively. Another comparison has been made between
the topologies from the view point of the number of semiconductor
devices that are in current path in any instant of time. This comparison is indicated in Fig. 4. As the figure shows, the number of devices
Number of devices in current path
12
AsymmetricCHB
8
vo1
4Vdc
3Vdc
2Vdc
Vdc
2
t
Vdc
2Vdc
3Vdc
4Vdc
[7]
10
in current path is lower for the proposed topology. The lower number of devices in current path implies the lower voltage drop on the
devices and lower conduction losses.
In Refs. [7,8] two asymmetric multilevel inverters have been
introduced using cascaded basic units. Fig. 5 shows the number of
IGBTs used versus the number of voltage levels in the proposed
asymmetric topology, the asymmetric CHB multilevel inverter and
that presented in Refs. [7,8]. The proposed asymmetric multilevel
inverter uses considerable lower number of IGBTs. For instance, for
the 31-level asymmetric inverter, the proposed topology and the
asymmetric CHB multilevel inverter use 12 and 16 IGBTs, respectively. The topology presented in Ref. [7] utilizes 20 IGBTs for a
21-level inverter and the topology presented in Ref. [8] produces a
35-level output voltage with 20 IGBTs. The number of devices that
are in current path in any instant of time versus the number of voltage levels for the asymmetric topologies has been indicated in Fig. 6.
This figure clearly shows that in the proposed asymmetric topology,
the number of devices in current path is considerably lower than
that of the other topologies. As stated before, this reduces the voltage drop on the semiconductor devices as well as the conduction
losses.
vo 2
5Vdc
[8]
6
Proposed asymmetric
4
2
0
20
40
60
80
100
120
2
t
5Vdc
NL
Fig. 6. Number of semiconductor devices in current path in any instant of time for
the asymmetric topologies versus the number of levels.
Fig. 8. Upper figure: typical output voltage of the proposed symmetric topology
(with four dc voltage sources) in the hybrid topology, lower figure: the output
voltage of the added H-bridge.
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E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
n s1
Vdc ,1
S 4u
ns 2
np
25V
S 3u
Vdc , 2
25V
ns 3
Vdc ,3
S
T1
S
u
2
T2
u
1
nsn
Vdc , n
Fig. 9. Providing of the multiple dc voltage sources via transfomers and rectifiers.
4. Hybrid topologies
Considering Figs. 1 and 2, the switches of the H-bridge part
(T1 − T4 ) have to withstand a voltage equal to sum of all of the dc
voltage sources. Nowadays, power electronic switches with high
voltage and high power capabilities are available which can be used
in the H-bridge part of the proposed topologies. In spite of this fact,
the high standing voltage of the H-bridge switches can restrict the
application of the proposed topologies for high voltage levels. In
order to mitigate this problem, the proposed topologies can be
used in hybrid forms. Fig. 7 shows a possible hybrid multilevel
inverter topology using the series-connected proposed topology
and an H-bridge.
The dc voltage of the added H-bridge (Vd ) can be determined
for several purposes. It can be equal to the sum of the dc voltage sources used
the first dc voltage
n in the proposed topology plus
n
V + V1 ) or can be as Vd = 2 i=1 Vi + V1 to get
source (Vd =
i=1 i
the maximum number of output voltage levels. Beside these values, Vd can have any other value depending on the availability of
the
n dc voltage source or design purposes. However, when Vd =
V + V1 , the voltage on the switches of the H-bridge part of the
i=1 i
proposed topology and the switches of the added H-bridge is almost
equally distributed making it possible to use the same switches for
them. Moreover, this selection of Vd is more suitable for mitigating
the high voltage switch requirements. Supposing a specific rated
vL
25V
vo
S 2l
S1l
25V
S 4l
iL
T3
T4
S 3l
25V
Fig. 11. The symmetric 11-level inverter based on the proposed topology.
output voltage, with this value of Vd , the voltage on the switches
of the H-bridge of the proposed topologies is halved which makes
them more suitable for higher voltage applications. It is important
to note that this technique is applicable for both symmetric and
asymmetric topologies.
Fig. 8 shows the typical output voltage of the series-connected
units for the case of the proposed symmetric topology where upper
figure is the output voltage of the proposed symmetric topology and
lower figure is the output voltage of the added H-bridge. The figure also indicates a possible modulation scheme to get the desired
output voltage. Considering the figure, it can be stated that the proposed symmetric topology is responsible for creating the voltage
levels and the added H-bridge decreases the voltage rating requirements of the switches for a specific output voltage rating. It is worth
noting that the similar discussion can be done for the asymmetric
topology.
5. Simulation and experimental results
Fig. 10. Block diagram of the control system.
This section deals with the simulation and experimental study of
the proposed symmetric, asymmetric and hybrid multilevel inverters. For simulation, the PSCAD/EMTDC software is used. In the
simulations all of the switches are considered to be ideal. The load
is a series connected resistance and an inductance with the value
of 35 and 55 mH, respectively. The output voltage frequency
is assumed 50 Hz. It is important to note that the experimental
results are given only for the asymmetric topology. The dc voltage
sources used in the simulation studies are separated dc sources. In
practice, these dc voltage sources may be available via distributed
energy resources like photovoltaic panels. However, if an ac source
is available, the required dc voltage sources can be achieved by a
transformer with multiple secondary windings and rectifiers [23]
as shown in Fig. 9. Another solution to provide the required multiple
dc voltage sources is given in Refs. [24,25]. This method is based on
a combination of using high-frequency and line-frequency transformers. In this method, the multilevel inverter is divided to two
parts, i.e. the main part and the auxiliary parts. The main part is
responsible for the main fraction of the output power and uses a
line-frequency transformer. In the auxiliary parts firstly the available dc voltage source is converter to a high-frequency waveform.
The high-frequency waveform is passed from a high-frequency
transformer with multiple secondary windings and then they are
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
127
25V
S1
S2
T1
T2
vL
50V
S4
S3
vo
iL
T3
100V
S6
T4
S5
Fig. 14. The asymmetric 15-level inverter based on the proposed asymmetric topology.
converter to dc voltage using rectifiers providing the required multiple dc voltage sources.
It is noticeable that many different modulation strategies can
be applied for multilevel inverters. In this paper the fundamental
frequency modulation is used. Although in this method, the switching angles can be obtained to eliminate some selected harmonics or
minimization of total harmonics distortion, these are not the objective of this paper. The control method used in this paper is based on
generating an output voltage waveform which has minimum error
with its reference value. Fig. 10 shows the block diagram of this control method. The available voltage sources are compared with the
output voltage reference value (vL,ref ). The decision unit determines
that the reference output voltage is nearest to which of the available
voltage levels and then, selects the switches in a way that if they
are turned on, the corresponding voltage level will be produced at
Fig. 12. Simulation results of the proposed 11-level symmetric topology, (a) output
voltage, (b) output current, (c) output voltage of the level creator part.
100
Efficiency
95
90
85
80
75
70
0. 6
0.65
0. 7
0.75
0. 8
0.85
0.9
0.9 5
1
M
Fig. 13. Efficiency versus the modulation ratio for the proposed symmetric topology
and symmetric CHB.
Fig. 15. (a) Simulation output voltage for the asymmetric 15-level inverter, (b)
experimental output voltage for the asymmetric 15-level inverter (Time/div = 5 ms).
128
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
98
96
Efficiency
94
92
90
88
86
84
82
Fig. 18. Efficiency versus the modulation ratio for the proposed asymmetric topology and asymmetric CHB.
the output. It is worth noting that the output voltage in different
permissible switching combination is given to the decision unit as a
look-up table. This control method is known as nearest level control
method [26]. This control method is not effective for inverters with
low number of levels, since the approximation error becomes relevant. Hence it is aimed to be used in converters with relatively high
number of levels to avoid important low-order harmonics at the
ac side. The main advantage is its conceptual and implementation
simplicity and the efficiency achieved with this method [5].
Fig. 16. (a) Simulation output current for the asymmetric 15-level inverter, (b)
experimental output current for the asymmetric 15-level inverter (Time/div = 5 ms).
Fig. 17. (a) Simulation output voltage of the level creator part for the asymmetric
15-level inverter, (b) experimental output voltage of the level creator part for the
asymmetric 15-level inverter (Time/div = 5 ms).
5.1. Results for the proposed symmetric topology
The simulation results are presented for the proposed 11-level
symmetric inverter as shown in Fig. 11. The symmetric 11-level
inverter based on the proposed topology requires 5 dc voltage
sources. Each dc voltage source is 25 V so that the maximum output
voltage is equal to 125 V. For this example of symmetric multilevel
inverter, the proposed topology requires 12 IGBTs. This is much
lower than that of conventional CHB multilevel inverter which uses
20 IGBTs for a symmetric 11-level inverter.
Fig. 12(a) shows the output voltage of the proposed symmetric
multilevel inverter. The figure clearly shows that all of the desired
voltage levels are generated. The THD of the output voltage is 6.46%.
The output current is shown in Fig. 12(b). As shown in this figure,
the output current waveform is smoother than the output voltage
and its phase angle lags the output voltage phase angle because
of the inductive characteristic of the load. The THD of the output
current is 0.94%.
As mentioned before, the level creator part in the proposed symmetric multilevel inverter can only generate the positive voltage
levels. This is indicated in Fig. 12(c) which shows the output voltage
of the level creator part. The zero and negative voltage levels in the
output voltage are generated by proper switching of the H-bridge
part.
In order to investigate the efficiency of the proposed topology
in comparison with that of the CHB topology, their efficiencies are
obtained based on simulation. Fig. 13 shows the efficiency of the
proposed 11-level symmetric topology and that of the symmetric CHB versus the modulation ratio (M). The modulation ratio is
the ration of the output voltage peak to the sum of dc voltages. As
the figure shows, the proposed topology has higher efficiency. This
is because of the fact that in the proposed topology there are less
switching devices in current path in any instant of time. Considering
Fig. 11, in the proposed 11-level inverter maximum 6 semiconductor devices are in current path simultaneously. However, for the
11-level symmetric CHB, 10 semiconductor devices are in current
path simultaneously.
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
50V
S 4u
100V
S 3u
S2
T1a
50V
S 2u
S1
T1a
T2a
T2a
200V
S1u
S4
v o1
S3
v o1
50V
400V
S 2l
S1l
S6
T3a
50V
S 4l
129
T4a
T3a
T4a
iL
S5
vL
iL
vL
S 3l
50V
T1b
T1b
800V
T2b
300V
vo2
T3b
T2b
vo2
T3b
T4b
T4b
(a)
(b)
Fig. 19. Hybrid topologies used for simulation studies, (a) based on the symmetric topology, (b) based on the asymmetric topology.
5.2. Results for the proposed asymmetric topology
For the experimental studies, the 15-level inverter based on
the proposed asymmetric multilevel inverter as shown in Fig. 14
is implemented. The proposed asymmetric 15-level inverter uses
3 dc voltage sources and 10 IGBTs. The dc voltage sources have
values 25 V, 50 V and 100 V. So that, maximum 175 V output voltage
is obtainable.
The IGBTs of prototype are BUP306D with internal anti-parallel
diodes. The 89C52 microcontroller by ATMEL Company has been
used to generate the switching patterns. For the experimental setup
the data as same as the data used in the simulations has been used.
Fig. 20. Simulation results for the proposed symmetric hybrid topology.
Fig. 21. Simulation results for the proposed asymmetric hybrid topology.
130
E. Babaei et al. / Electric Power Systems Research 86 (2012) 122–130
However, the switches have some forward voltage drop in practice
which has not been considered in the simulations. To provide the
required dc voltage sources, the dc supplies in the laboratory have
been used.
Fig. 15(a) and (b) shows the simulated and experimental output
voltage, respectively. As the figures show, the expected voltage levels are generated and the experimental output voltage has a good
similarity to that of simulation. Any difference in terms of the magnitude of the output voltage is resulted from the forward voltage
drop on the switches in practice. Based on simulation, the THD of
the output voltage is 4.63%.
The simulation and experimental output currents are depicted
in Fig. 16(a) and (b), respectively. The results show a good
accordance between the simulation and experimental results. Considering the current waveforms, the output current has phase
difference in respect to the output voltage. This is due to the inductive load. In addition, as a result of operating of the inductive load
as a low pass filter against current, the output current is more sinusoidal than the output voltage. Based on simulation, the THD of
the output voltage is 0.54%. The simulation and experimental output voltages of the level creator part are shown in Fig. 17(a) and
(b), respectively. Unlike the symmetric topology, in the asymmetric topology the zero voltage level can be generated by the level
creator part.
Fig. 18 shows the efficiency of the proposed 15-level asymmetric
topology and that of the asymmetric CHB versus M. As shown in the
figure, the efficiency of the proposed topology is higher.
5.3. Results for the proposed hybrid topologies
Fig. 19(a) and (b) shows the hybrid topology based on the proposed symmetric and asymmetric topology, respectively. These
multilevel inverters are used for simulation studies of the hybrid
topologies. As shown in Fig. 19(a), the proposed symmetric hybrid
topology uses 5 dc voltage sources, each of which 50 V, and a 300 V
dc voltage source for the added H-bridge. Therefore, the maximum
output voltage will be 550 V for the proposed symmetric hybrid
topology, 4 dc voltage sources of 100 V, 200 V, 400 V and 800 V have
been used so that the maximum output voltage will be 1500 V.
Fig. 20 shows the simulation results for the proposed symmetric
hybrid topology (Fig. 19(a)). In this figure, from top to bottom the
traces are vo1 , vo2 , the load voltage and the load current. As the figure shows the rated load voltage (550 V) is divided almost equally
between the two parts of the multilevel inverter.
The simulation results for the proposed asymmetric hybrid
topology (Fig. 19(b)) are shown in Fig. 21. The figure shows the output voltage of the two series-connected parts, the load voltage and
the load current. As the figure shows the rated load voltage (1500 V)
is divided almost equally between the two parts of the multilevel
inverter leading to reduction in the voltage rating of the switches
used in the H-bridge parts. Therefore, the hybrid topologies will be
more suitable for higher voltage applications.
6. Conclusion
In this paper, two new topologies are proposed for multilevel
inverters. One of the proposed topologies is a symmetric multilevel and the other is asymmetric multilevel inverter. The proposed
multilevel inverters use reduced number of switching devices in
comparison with the other topologies. For instance, a 15-level
inverter based on the proposed symmetric topology uses 18 IGBTs
where the CHB multilevel inverter uses 28 IGBTs. An 11-level
inverter based on the proposed asymmetric topology uses 10 IGBTs.
An 11-level asymmetric CHB multilevel inverter uses 12 IGBTs.
Also, two hybrid topologies based on the proposed topologies have
been presented which are more suitable for higher voltage applications. Simulation results as well as experimental results are given
to verify the proposed topologies.
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