Xiaolin Xu ( xuxiaolin@hfut.com
)
School of Electronic Science & Applied Physics,
Hefei University of Technology

Qualitative understanding of MOS devices
Simple component models for manual analysis
Detailed component models for SPICE

• The pn-junction diode is the simplest of the semiconductor devices.
B
Al
A
SiO
2 p n
(a) Cross section of pn-junction in an IC process
A
Al
A p n
B
(b) One-dimensional representation
B
(c) Diode symbol
Figure 3-1 Abrupt pn-junction diode and its schematic symbol
The Devices. 3

3.2.1 A First Glance at the Diode-The Depletion Region hole diffusion electron diffusion
(a) Current flow.
p n hole drift electron drift
Charge
Density

+
-
Distance x
(b) Charge density.
Electrical
Field
 x
(c) Electric field.
Potential
V
-W
1
W
2

 x
(d) Electrostatic potential.
The Devices. 4

• The Ideal Diode Equation
I
D

I
S
 e
V
D

T

1

Deviation due to recombination
• The most important property of the diode current is its exponential dependence upon the applied bias voltage.
The Devices. 5

• A conducting diode is replaced by a fixed voltage source, and a nonconducting diode is replaced by an open circuit.
I
D
= I
S
(e
VD /

T – 1)
+ +
I
D
V
D
V
D
+
–
V
Don
– –
(a) Ideal diode model (b) First-order diode model
The Devices. 6

• Depletion-Region Capacitance
– Look the depletion region as a capacitance
– It act as an insulator with a dielectric ε si of the semiconductor material. The n- and p-regions act as the capacitor plates.
• Junction capacitance as a function of the applied bias voltage
C j
 dQ dV
D j 
C

1

V
D j 0

0
 m
C j 0

A
D


 si q
2 N
N
A
A

N
D
N
D



0

1
– A strong nonlinear dependence can be observed.
The Devices. 7

• Large-signal Depletion-Region Capacitance
– An equivalent, linear capacitance C eq voltage swing from voltages V high to V is defined for a given low
, the same amount of charge is transferred as would be predicted by the nonlinear model.
C eq

K eq
C j 0
The Devices. 8

The Devices. 9
0.1
0
–0.1
–25.0
–15.0
V
D
(V)
–5.0
0 5.0
Avalanche breakdown

• The steady-state characteristic of the diode is modeled by the nonlinear current source I
D
I
D

I
S
 e
V
D n

T

1

• The resistor R s models the series resistance contributed by the neutral regions on both sides of the junction
• The dynamic behavior of the diode is modeled by the nonlinear capacitance C
D
C
D

C

1

V
D j 0

0
 m


T
I

T
S e
V
D

T R
S
+
V
D
-
I
D
C
D
The Devices. 10

The Devices. 11

Polysilicon
Aluminum
• Good switch performance
• Small parasitical effects
The Devices. 12
• High integration
• “Simple” process

The Devices. 13

The Devices. 14
S
S
G G
D S D
B
G
B
G
D S D
NMOS PMOS

• The Threshold Voltage
• Resistive Operation
• The Saturation Region
• Channel-Length Modulation
• Velocity Saturation
• Subthreshold Conduction
• In summary-Models for Manual Analysis
• Dynamic Behavior - Capacitive Device Model
The Devices. 15

• The Value of V
GS where strong inversion occurs is called the threshold voltage V
T
V
GS
G
+
S
D
n+ n+ depletion region n channel p substrate
B
• Effect of body-bias on threshold
– γis called the body-effect coefficient. It expressed the impact of changes in V
SB
.
V
T

V
T 0
 

 

F

V
SB

2

F

The Devices. 16

0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2 -1.5
V
BS
(V)
-1 -0.5
0
Example 3.5 Threshold Voltage of a PMOS Transistor
V
Tp0
＝－ 0.4V
， γ ＝－ 0.4V
， V
SB
V
T

－ 2 .
5 V

 
0 .
4

0 .
4

＝－ 2.5V
， 2φ
F
＝ 0.6V
，求 V
Tp
2 .
5

0 .
6

0 .
6

 － 0 .
79 V
It is twice the threshold under zero-bias conditions!
The Devices. 17

• Assume now that V
GS
> V
T
， and that a small voltage V
DS applied between drain and source.
V
GS
S
G
V
DS is
D
I
D n+ -
V(x)
+ n+ x
I
D
 k
' n
W
L



V
GS

V
T

V
DS

2
V
DS
2


B
 k n



V
GS

V
T

V
DS

2
V
DS
2


• One of its main properties is that it displays a continuous conductive channel between source and drain regions.
The Devices. 18

• Assume V
GS
> V
T
， V
GS
V
GS
S
- V
DS
< V
T
G
V
DS
> V
GS
-V
T
D
I
D n+
-
V
GS
- V
T
+ n+
Pinch-off
B
I
D
 k n
'
2
W
L

V
GS

V
T

2
• The squared dependency of the drain current with respect to the control voltage V
GS
.
The Devices. 19

• Increasing V
DS causes the depletion region at the drain junction to grow, reducing the length of the effective channel
– λis the parameter of channel-length modulation, and is proportional to the inverse of the channel length.
I
D

I
D

1
 
V
DS

• In shorter transistors, channel-modulation effect is more pronounced
– It is therefore advisable to resort to long-channel transistors if a high-impedance current source is needed.
The Devices. 20

• The main culprit for this deficiency is the velocity saturation effect .
• When the electrical field along the channel reaches a critical value, the velocity of the carriers tends to saturate due to scattering effects.
The Devices. 21
 c

(V/
 m)

For short-channel devices
• The Resistive Region:
I
D
 
 
DS
 n
C ox


W
L






V
GS

V
T

V
DS

V
DS
2
2



– where ， 
(V) = 1/(1 + (V/
 c saturation
L)) measures the degree of velocity
• The Saturated Region:
I
DSAT
 

V
DSAT

 n
C ox


W
L






V
GS

V
T

V
DSAT

V
DSAT
2
2



The Devices. 22

For a short-channel device and for large enough values of V
GT
• V
DSAT
< V
GS
– V
T
， the device enters saturation before V
DS reachs
V
GS
- V
T
.
They tend to operate more often in saturation conditions than their long-channel counterparts.
• The saturation current I
DSAT displays a linear dependence with respect to the gate-source voltage V
GS
, which is in contrast with the squared dependence in the long-channel device.
I
D
Long-channel device
Short-channel device
V
DS
The Devices. 23


10 -4
6
V
GS
= 2.5V
V
DS
= V
GS
- V
T 5
4
V
GS
= 2.0V
3
2
Linear Saturation
V
GS
= 1.5V
1
V
GS
= 1.0V
0 cut-off
0 0.5
1 1.5
V
DS
(V)
2 2.5
NMOS, 0.25um, L d
= 10  m, W/L = 1.5, V
DD
= 2.5V, V
T
= 0.4V
The Devices. 24

2.5

10 -4
Early Velocity
V
GS
= 2.5V
Saturation
2
V
GS
= 2.0V
1.5
1
Linear Saturation
V
GS
= 1.5V
0.5
V
GS
= 1.0V
0
0 0.5
1 1.5
V
DS
(V)
2 2.5
NMOS, 0.25  m, L d
= 0.25  m, W/L = 1.5, V
DD
= 2.5V, V
T
= 0.4V
The Devices. 25

• The difference in dependence upon between long- and short-channel devices: quadratic vs. linear dependence
• Velocity saturation effect results in a substantial drop in current drive for high voltage levels.

10 -4
6
5
4
3
2
1
0
0 0.5
1
V
GS
(V)
1.5
2 2.5
(V
DS
= 2.5V, W/L = 1.5)
The Devices. 26

0

10 -4
-0.2
-0.4
V
GS
= -1.0V
V
GS
= -1.5V
Notice that the effects of velocity saturation are less pronounced than in the NMOS devices.
-0.6
V
GS
= -2.0V
-0.8
-1
V
GS
= -2.5V
-2
V
DS
(V)
-1 0
PMOS, 0.25
 m, L d
= 0.25
 m, W/L = 1.5, V
DD
= 2.5V, V
T
=
－
0.4V
The Devices. 27

• It becomes apparent that the MOS transistor is already partially conducting for voltages below the threshold voltage. This effect is called subthreshold or weak-inversion conduction .
10
-2
Linear
10
-4
10
-6
Quadratic
10
-8
10
-10
10
-12
0
Exponential
V
T
0.5
1
V
GS
(V)
1.5
2 2.5
The Devices. 28

S
G
I
D
B
D
I
D

0 for V
GT

0
I
D
V
GT
 with
K '
W
L


V
GT
V min
－
V min
＝ min

V
GT
,
V
2 min
2
V
DS



1 ＋
, V
DSAT

V
DS

,

V
GS

V
T
, and V
T

V
T 0
 


2

F

V
SB

 for

2

F

V
GT

0
• Besides being a function of the voltages at the four terminals of the transistor, the model employs a set of five parameters:
NMOS
PMOS
V
T0
(V)

(V 0.5
) V
DSAT
(V)
0.43
0.4
0.63
-0.4
-0.4
-1 k’(A/V 2
115 x 10
-30 x 10
)
-6
-6

(V -1
0.06
-0.1
)
The Devices. 29

Example 3.7 Mannual Analysis Model for 0.25  m CMOS Process
Based on the simulated I
D
-V
DS and I
D
-V
GS plots of a (W=0.375
 m,
L=0.25
 m) transistor implemented in our generic 0.25
 m CMOS process, we have derived a set of device parameters to match well in the
(V
DS
=2.5V, V
GS
=2.5V) region. The resulting characteristics are plotted in figure 3-25 for the NMOS transistor, and compare with the simulated values.
2.5
x 10
-4
V
DS
=V
DSAT
2
Velocity Saturated
1.5
Linear
1
V
DSAT
=V
GT
0.5
V
DS
=V
GT Saturated
0
0 0.5
1
V
DS
(V)
1.5
2 2.5
The Devices. 30

• The transistor is nothing more than a switch with an infinite “off” resistance, and a finite “on” resistance R on
V
GS

V
T
R on
S D
Figure 3-26 NMOS transistor modeled as a switch
• The main problem with this model is that R on nonlinear.
is
– Use the average value of the resistance at the end points of the transition.
R eq
= ½ (R on
(t
1
) + R on
(t
2
))
The Devices. 31

Example 3.8 Equivalent Resistance when (Dis)Charging a
Capacitor
The case of an NMOS discharging a capacitor from V
DD to V
DD
/2.
I
D
V
GS
= V
D D
R mid
R
0
V
DD
/2 V
DD
V
DS
The Devices. 32

3
2
1
7 x10 5
6
5
4
R eq

1
2


I
DSAT
V

1
DD
 
V
DD
 ＋
I
DSAT
V

1
DD
 
2
V
DD

3 V
DD
4 I
DSAT
其中 I
DSAT
 k '
W
L



V
DD

V
T

V
DSAT

V
2
DSAT
2


0
0.5
1 1.5
V
DD
(V)
2
(V
GS
= V
DD
， V
DS
= V
DD

V
DD
/2)
1

5
6

V
DD
2.5
2



• The resistance is inversely proportional to the (W/L) ratio of the device. Doubling the transistor width cuts the resistance in half.
• For V
DD
>>V
T
+V
DSAT
/2, R on becomes virtually independent of V
DD
• Once V
DD approaches V
T
， the resistance dramatically increases
The Devices. 33

• A function of the time it takes to (dis)charge the parasitic capacitances that are intrinsic to the device and the extra capacitance introduced by the interconnecting lines and load.
• These intrinsic capacitances originate from 3 sources:
– The basic MOS structure
– The channel charge
– The depletion regions of the reverse-biased pn-junctions of drain and source
G
S
C
GS
C
SB
C
GB
C
GD
D
C
DB
B
The Devices. 34

• Lateral diffusion gives rise to a parasitic capacitance between gate and source (drain) that is called the overlap capacitance (linear).
C
GSO
= C
GDO
= C ox x d
W = C o
W lateral diffusion
Poly Gate
Source n+ x d x d W
Drain n+
L drawn n+ t ox n+
L eff
The Devices. 35

• The most significant MOS parasitic circuit element
• The gate-to-channel capacitance depends on the operation region and terminal voltages.
C
GS
= C
GCS
+ C
GSO
S
V
GS +
G
C
GD
D
= C
GCD
+ C
GDO
n+ n+ n channel
C
GB
= C
GCB p substrate depletion region
B
The Devices. 36

S
G
C
GC
D
S
G
C
GC
D
G
C
GC
D S
(a) cut-off (b) resistive (c) saturation
Figure 3-30 the gate-to-channel capacitance and how the operation region influences its distribution over the three other device terminals.
Operation Region
Cutoff
Resistive
Saturation
C
GCB
C ox
WL eff
0
0
C
GCS
0
C ox
WL eff
/2
(2/3)C ox
WL eff
C
GCD
0
C ox
WL eff
/2
0
The Devices. 37

WLC
OX
WLC
OX
2
C
GCB
C
GC
WLC
OX
C
GCS
＝ C
GCD
WLC
OX
2
C
GC
C
GCS
C
GCD
2WLC
OX
3
V
GS
(a) C
GC as a function of V
GS
VDS=0)
(with
0
V
DS
/(V
GS
-V
T
)
(b) C
GC as a function of the degree of saturation
1
Figure 3-31 Distribution of the gate-channel capacitance as a function of V
GS and V
DS
Note: The large fluctuation of the channel capacitance around is worth remembering. A designer looking for a well-behaved linear capacitance should avoid operation in this region.
The Devices. 38

Example 3.9 Using a Circuit Simulator to Extract Capacitance
It plots the simulated gate capacitance of a minimum-size 0.25m NMOS transistor as a function of V
GS
.
3 10
2 16
10
V
GS
9
8
I
7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0
V
GS
(V)
0.5
1 1.5
2
Note: The graphs clearly show the drop of the capacitance when V
GS approaches V
T and the discontinuity at V
T
.
The Devices. 39

Table 3-4 Average distribution of channel capacitance of MOS transistor
Operation region
C
GCB
Cutoff C ox
WL
Resistive 0
Saturation 0
C
GCS
0
C
GCD
0 C
C ox
GC
WL C
C
G ox
WL + 2C o
W
C ox
WL/2 C ox
WL/2
(2/3)C ox
WL 0
C ox
WL C ox
WL + 2C o
W
(2/3)C ox
WL (2/3)C ox
WL + 2C o
W
• The gate-capacitance components are nonlinear and varying with the operating voltages.
• To make a first-order analysis possible, we adopt a simplified piecewise-linear model with a constant capacitance value in each region of operation.
The Devices. 40

• A final capacitive component is contributed by the reverse-biased source-body and drain-body pn-junction.
• It is nonlinear and decreses when the reverse bias is raised.
G
S
V
GS +
D
n+ n+
C
SB
= C
Sdiff n channel p substrate
B
The Devices. 41 depletion region
C
DB
= C
Ddiff

The Devices. 42 x j
W
Channel-stop implant
N
A
+
Side wall
Source
ND
Bottom
L
Side wall
S
Substrate N
A
Channel
C diff

C bottom

C sw

C j
 area

C

C j
L
S
W

C jsw
(2L
S

W) jsw
 perimeter

C
GS
= C
GCS
+ C
GSO
C
GS
S
C
SB
C
SB
= C
Sdiff
G
C
GB
B
C
GB
= C
GCB
C
GD
= C
GCD
+ C
GDO
C
GD
D
C
DB
C
DB
= C
Ddiff
The Devices. 43

Example 3.10 MOS Transistor Capacitances
Consider an NMOS transistor with the following parameters: t ox
0.24
 m, W = 0.36
 m, L
D
C jsw0
= L
S
= 0.625
 m, C o
=3

10 -10 F/m, C j0
=2
=6nm, L =

=2.75

10 -10 F/m. Determine the zero-bias value of all relevant
10 -3 F/m2, capacitances.
NMOS
PMOS
C ox
(fF/
 m 2 )
6
6
C o
(fF/
 m)
0.31
0.27
C j
(fF/
 m 2 )
2
1.9
m j
 b
(V)
C jsw
(fF/
 m) m jsw
 bsw
(V)
0.5
0.9
0.28
0.44
0.9
0.48
0.9
0.22
0.32
0.9
C
GSO
= C
GDO
= C ox x d
W = C o
W = 0.105 fF C
GC
= C ox
WL = 0.49 fF
C gate_cap
= C ox
WL + 2C o
W = 0.7 fF
C bp
= C j
L
S
W = 0.45 fF C sw
= C jsw
(2L
S
+ W) = 0.44 fF
C diffusion_cap
= 0.89 fF
The diffusion capacitance seems to dominate the gate capacitance. This is a worst case condition. In general, the contribution of diffusion capacitances is at most equal to, and very often smaller than the gate capacitance.
The Devices. 44

• This effect becomes more pronounced when transistors are scaled down, because this lead to shallower junctions and smaller contact openings.
• Solutions: Silicidation; making the transistor wider than needed
G
S
D
R
S, D

L
S, D
R


R
C
W
R
S
R
D
L
S,D is the length of the source or drain region
R
 is the sheet resistance per square of the drain-source diffusion, and ranges from 20 to 100

/ 
R
C is the contact resistance
Note: that the resistance of a square of material is constant, independent of its size.
The Devices. 45

3.3.3 The Actual MOS Transistor-Some Secondary
Effects
• V
T0 decreases with L for short-channel devices.
• V
T0 decreases with increasing V
DS for short-channel devices.
( drain-induced barrier lowering, DIBL )
V
T
V
T
Long-channel threshold
Low V
DS threshold
L
A. Threshold as a function of the length (for low V
DS
)
The Devices. 46
B. DIBL (for low L)
V
DS

• The resulting increase in the electrical field strength causes an increasing velocity of the electrons, which can leave the silicon and tunnel into the gate oxide upon reaching a sufficiently high level of energy. Electrons trapped in the oxide change the threshold voltage.
• The hot-carrier phenomenon can lead to a long-term reliability problem
• Solutions:
– Use specially engineered drain and source regions to ensure that the peaks in the electrical fields are bounded, thus preventing carriers from reaching the critical values necessary to become hot
– Reduce the supply voltage
The Devices. 47

• MOS technology contains a number of intrinsic bipolar transistor
• The combination of wells and substrates results in the formation of parasitic n-p-n-p structures. Triggering these devices leads to a shorting of the V
DD of the chip.
and V
SS lines, usually resulting in a destruction
• Solutions:
– R nwell and R psubs should be minimized.
– Devices carrying a lot of current should be surrounded by guard rings
The Devices. 48

Example 3.11 SPICE Description of a CMOS Inverter
In this example, a SPICE description of a CMOS inverter consisting of an
NMOS and a PMOS transistor is given.
M1 nvout nvin 0 0 nmos.1 W=0.375U L=0.25U
+AD=0.24P PD=1.625U AS=0.24P PS=1.625U NRS=1 NRD=1
M2 nvout nvin nvdd nvdd pmos.1 W=1.125U L=0.25U
+AD=0.7P PD=2.375U AS=0.7P PS=2.375U NRS=0.33 NRD=0.33
.lib ‘ c:\Design\Models\cmos025.1
’
The Devices. 49