Implementation of high speed 24-bit vedic multiplier Kanak Kujur, Mayuri Dave, Pradnya Patil, Sakthivel R. School of Electronics Engineering (SENSE), VIT, Vellore -632014 (FFT) is widely used for DSP processes. Which represents signal in frequency domain reducing the computation time required to do a computation vastly. But the FFT Algorithm uses greater number of complex multiplications to generate an output leading to complex circuit and delay. To overcome this vedic multiplication technique is implemented to increase the speed and efficiency of multiplication. The [2] IEEE Floating-Point Arithmetic Standard (IEEE754) found in 1985 for Floating-Point calculation presented by IEEE. which determines arithmetic formats and techniques for binary and decimal floatingpoint number arithmetic’s in computers. This standard indicates special case conditions and their default taking handling. This [3] reduced the problem of reliability and portability issues introduced by conventional methods. Today is the most widely recognized representation for genuine numbers on PCs. Vedic Mathematics [4] is a combination of Techniques/Sutras to solve mathematical arithmetic in simple and quicker manner. It comprises of 16 Sutras (Formulae) and 13 subsutras (Sub Formulae). The [5] UrdhvaTiryakbhyam Sutras and Nikhilam Sutras give least demanding method for mental computation when performing multiplication. Be that as it may, Urdhva-Tiryakbhyam utilizes parallel multiplication and shows high parallelism contrasted with other parallel multipliers. UT [6] is the general technique appropriate to all form of multiplication and furthermore in the division of a huge number by another huge number. In this paper we are going to see usage of 24-bit floating point vedic multiplier dependent on Urdhva-Tiryakbhyam Algorithm which is called as vedic math Algorithm the architecture and implementation of the multiplier is elaborated further below and compared with nominal multiplication method which also use floating point representation. Abstract: - In this age of technology, where large amount of work is based on computation of digital data the computation capability and complexity of various data processing devices and applications is vastly reduced as signals are represented in frequency domain with the help of FFT technique. As large amount of application use FFT processing technique for processing data at high rate with efficiency the process deals with multiplication which takes large time for computation. To improve this an ancient mathematic technique called Vedic Multiplication technique is implemented. The Vedic Multiplication technique from Urdhva Tiryakbhyam Sutra which is one of the ancient Indian mathematic method for solving multiplication, showing a high efficiency than conventional multiplication. Here we have implemented IEEE754 Floating Point Representation to represent the numbers. The vedic multiplication is used to do multiplication of mantissa part within this paper 24-bit floating point in IEEE754 floating point representation multiplication is implemented using vedic multiplication. All the work is carried out on Quartus Prime v18.1 a programmable logic device design software and synthesis is done using modelsim v10.5b software. Keywords–Fast Fourier Transform (FFT), (UT) Urdhva-Tiryakbhyam, Vedic mathematics INTRODUCTION The rapid growth of the science and technology lead to huge sum of invention and discover and digital devices is one of them becoming a large step toward automated device and easing the daily work. These [1] devices require to computation in digital format consisting of arithmetic and logical process as the technology advanced new techniques are introduced from which Fast Fourier Transform 1 ARCHITECTURE input N digit multiplicand a and multiplier b 1. Vedic Math’s: - It is a method based on reasoning and mathematical working based on old Indian teaching called Veda. To be increasingly explicit, it has begun from "Atharva Vedas" the fourth Veda. Which is conceivable because of the endeavors of Jagadguru Swami Bharathi Krishna Tirtha Ji of Govardhan Peeth, Puri Jaganath (1884-1960). Vedic Math's gives answer in one line where as ordinary strategy requires a few stages. It is an antiquated system, which simplifies multiplication, divisibility, complex numbers, squaring, cubing, square and cube roots. In any event, repeating decimals and auxiliary fraction can be taken care of by Vedic Mathematic. The Sutras Urdhava-Tiryakbhyam and Nikilam Sutras shows most effortless method for mental estimation when performing multiplication. multiply a0 and b0 multiply a0 & b0 and multiply a1 & b0 and store the result multiply a1 and b1 2. UT Algorithm:- "Urdhva-Tiryakbhyam" signifies "Vertically- crosswise" in Sanskrit. Urdhva Tiryakbhyam (Urdhva Tiryak) is Shortcut (General) Method of multiplication in Vedic Mathematic for a wide range of numbers. UT Sutra utilizes parallel multiplication and shows high level of parallelism contrasted with other parallel multipliers. In nominal parallel multiplication technique fractional part get summed after getting all partial product. On account of UT, multiplication vertically and transversely implies summation will occur soon after partial products gets created. final result is obtained by grouping all the result Fig 2: - Flow Chart The above implementation shows how to multiply ‘N’ large bit (N-bits x N-bits) by 𝑁 breaking it in smaller parts ( 2 = 𝑛 𝑒𝑎𝑐ℎ) and this are further sub-divided into smaller part till it reaches the smallest value i.e. 2-bit (2-bit x 2bit) hence simplifying the multiplication process as shown in above picture. 3. IEEE 754 floating point standard: - It is widely used today for DSP application. IEEE754 floating point Standard is the widely applied representation for non-complex numbers on computers, including Intel PC’s, Macs, and other platforms. Institute of Electrical and Electronics Engineer [IEEE] introduced a Standard for floating point representation and arithmetic techniques. This IEEE754 standard is the generally acknowledged representation for floating numbers even though presence of many other representations but IEEE 754 is the most preferred one. The IEEE754 representation is divided into three parts they are: Fig 1: - Line Diagram/implementation of UT Algorithm 2 3. Add exponent bits; i.e. (E1 + E2 – Bias). 4. To generate the sign bits, apply XORing to two sign bits; i.e. S1 ^ S2. 5. Normalize the result; 6. Truncate the results to fit in the available bits of applied representation. 7. Check the underflow and overflow cases. 1. The Sign of Mantissa 2. The Biased exponent 3. The Normalized Mantissa b) Vedic Multiplier implementation: The proposed design implements vedic mathematics based on Urdhva Tiryakabhyam (UT) sutra for the multiplication of the mantissa in IEEE754 single precision floating point format. In this proposed multiplier the base block used as first stage/base level implementation is 3x3 block which is shown in figure 6. Here we need 24bit vedic multiplier for the multiplication of mantissa part. The block diagram of 24-bit multiplier is shown in figure 5. Fig 3: - Pattern of Single Precision Floating Point representation (IEEE-754) METHODOLOGY In this paper a Single precision(16-bit) floating point multiplier is designed which overcomes some basic problems. Below figure shows the same. The 3x3 block consists of three half adders, three full adders as shown in figure 5. From 3x3 block, 6x6 multiplier block is designed. From this 6x6 multiplier block, 12x12 multiplier block is designed and similarly from this 12x12 multiplier block, 24x24 multiplier block is designed and implemented using structural approach in Verilog. These blocks require vedic multipliers and carry look ahead adders (fast adder) for getting the final output. a) Floating point Multiplication Algorithm Below figure shows the multiplication format of two floating point binary digits in IEEE 754 representation, Fig 4: - IEEE-754 Floating Point multiplier diagram [1] Fig 5: - Main 24-Bit vedic multiplier block diagram The steps for floating point number (two no.) multiplication is given below: The above figure shows the main block and below are the hieratical figure of internal block showing the implementation of multiplier 3-bit to the 24-bit 1. Multiply the two mantissas; i.e.(A*B). 2. Give a decimal point in the generated result. 3 Fig 6: - 3-Bit vedic multiplier block diagram Fig 9: - 24-Bit vedic multiplier block diagram RESULT The proposed 24-bit multiplier is implemented in Verilog HDL and synthesized & simulated using Quartus Modelsim simulator and verified for possible inputs given below. Inputs are generated using Verilog HDL test bench. The simulation result for 24-bit vedic multiplier. CASE - 1: Binary Value Inputs a = 101010101010101010101010, b = 110111011101110111011101 Product p = 10010011111010010011110101 1011000001011011000010 Fig 7: - 6-Bit vedic multiplier block diagram Decimal value: 11184810 × 14540253 = 162629967156930 Here the RTL-Schematic, test bench waveform is shown, which are generated using Modelsim Fig 8: - 12-Bit vedic multiplier block diagram Fig 10: - 3-Bit vedic multiplier output 4 References: [1] A. M. M and R. R. J, “Implementation of 24 bit high speed floating point vedic multiplier,” 2017 International Conference on Networks & Advances in Computational Technologies (NetACT), 2017. [2] P. B. S. , S. S. Pai, S. B. , and S. S. Bhat, “Design and Implementation of 8-Bit Vedic Multiplier,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 02, no. 12, Dec. 2013 Fig 11: - 6-Bit vedic multiplier output [3] A. Nanda and S. Behera, “Design and Implementation of Urdhva- Tiryakbhyam Based Fast 8×8 Vedic Binary Multiplier,” International Journal of Engineering Research & Technology (IJERT), vol. 03, no. 03, Mar. 2014. [4] A. D. Subudhi, K. C. Gauda, A. K. Pala, and J. Das , “Design and Implementation of High Speed 4x4 Vedic Multiplier ,” International Journal of Advanced Research in Computer Science and Software Engineering, vol. 04, no. 11, Nov. 2014. [5] P. Mehta and D. Gawali, “Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier,” 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009. Fig 12: - 24-Bit vedic multiplier output Fig 13: - 24-Bit vedic multiplier output CONCLUSION A highly efficient method of vedic multiplication, “Urdhva Tiryakbhyam Sutra” based on Vedic mathematics is presented in this paper. The code has been simulated on Modelsim. The proposed Vedic multiplier is faster than Nikilam Sutrams in terms of execution time. The number of logic levels and delay is being reduced using the UT sutra. Vedic mathematics is a mental calculation method that provides worldwide acceptance because of its easiness and advantages. 5