INTEGRATION the VLSI journal 57 (2017) 45–51
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All-digital background calibration technique for timing mismatch of timeinterleaved ADCs
⁎
Hongmei Chena,b, , Yunsheng Pana, Yongsheng Yina, Fujiang Linb
a
b
Institute of VLSI Design, Hefei University of Technology, Hefei 230009, China
Department of Electronic Science & Technology, University of Science and Technology of China, 443 Huangshan Road, Hefei, Anhui, China
A R T I C L E I N F O
A BS T RAC T
Keywords:
Time-interleaved ADC
All digital calibration
Timing mismatch
Farrow filter
An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is
presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The
estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch
in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which
requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and
effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is
further implemented and validated on the Altera FPGA board. The synthesized design consumes a few
percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration
technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of
TIADC system.
1. Introduction
challenge due to its frequency dependent detection.
A number of recent works have been focused on timing mismatch
mitigation. In Ref. [7,8], the author employed a filter-bank structure to
reconstruct a class of non-uniform sampled signals of the TIADC
system at the price of additional oversampling and high hardware
resource consumption. In Ref. [9], the author detected the timing error
by counting the input zero crossings among samples. The calibration
was achieved by digital logic at the cost of additional samplers in each
channel. In addition, the zero-crossing comparators themselves will
introduce extra errors. In Ref. [10], the method based on chopping
technique can calibrate simultaneously the gain and timing mismatch,
but the input signal could be modulated and the range of the input
signal is greatly limited. In Ref. [11], the author realized the timing
mismatch calibration using the time-varying filters. The calibration
algorithm can detect and correct in real time. However, the algorithm
needed a look-up table to preserve the filter coefficients. To avoid the
use of a look-up table, Ref. [12] adopts a filter based on Farrow
structure, and the order of Farrow filter does not require very high. It
uses the timing mismatch error as one of the filter input, even if the
timing error changes, it dosed not need to update the filter order or
filter coefficients.
In this work, an adaptive background calibration technique with
fully digital circuitry for time-interleaved ADC timing mismatch is
Modern signal processing applications need high-speed and highresolution Analog-to-Digital Converters (ADCs). A single ADC in a
traditional architecture cannot simultaneously achieve high resolution
and high speed performance because of process limitations [1,2]. The
time-interleaved ADCs provide an effective way to achieve high
sampling rate maintaining high resolution [3]. A block diagram and a
timing diagram of an M-channel TIADC are shown in Fig. 1. Each
channel consists of a sub-ADC with its own sampling and holding (S/
H) circuit. The sampling period of each channel is MTs, but the TIADC
equivalent sampling period is Ts, with its sampling rate M times higher
than that of the sub-ADC. An analog input signal x(t) is sequentially
sampled and digitized by the sub-ADCs to produce digital streams,
which are then multiplexed to generate a final TIADC digital output
signal y[n].
However, the performance of TIADCs is sensitive to the channel
mismatches, which will cause spurious spectrum and degrade the
signal-to-noise ratio [4]. There are three main different types of
mismatch which are the offset mismatch, the gain mismatch, and the
timing mismatch [5]. The calibration of offset and gain mismatch is
fairly straightforward, which can be done by simple adders and
multipliers [5,6], but the timing mismatch presents much more
⁎
Corresponding author at: Institute of VLSI Design, Hefei University of Technology, Hefei 230009, China.
E-mail address: hmchen@hfut.edu.cn (H. Chen).
http://dx.doi.org/10.1016/j.vlsi.2016.11.003
Received 15 April 2016; Received in revised form 26 September 2016; Accepted 8 November 2016
Available online 17 November 2016
0167-9260/ © 2016 Elsevier B.V. All rights reserved.
INTEGRATION the VLSI journal 57 (2017) 45–51
H. Chen et al.
Fig. 1. M-channel time-interleaved ADC. (a) Block diagram. (b) Timing diagram.
proposed. The calibration technique makes use of the autocorrelation
characteristics of the input signal, and performs the correlation
calculation of the sub-channels’ output in the background to estimate
mismatch errors. The correction scheme uses an improved fractional
delay filter based on Farrow structure, and the filter is shared by all
channels. The rest of this brief is organized as follows: Section 2
introduces the principle of the proposed timing mismatch estimation
and correction scheme. Section 3 provides the simulation results.
Lastly, Section 4 is devoted to the conclusion.
2. Timing mismatch calibration algorithm
Fig. 3. Time domain description of non-uniform sample in a two-channel TIADCs.
The overall framework of the proposed timing mismatch calibration
scheme is shown in Fig. 2, where↓M is the down-sampling times, x[n]
is the digital output of the M-channel TIADC required to be calibrated,
and y[n] is the output after calibration. The mismatch estimation
module is realized by performing the correlation calculation of the subchannels’ outputs in the background. Hα(z) is the improved fractional
delay filter based on Farrow structure, whose coefficients change along
with the estimated time mismatch to achieve a real-time error
correction.
written as
E[(x 2 − x1)2 ] = E[x 22] + E[x12] − 2E[x 2x1] = δx22 + δx21
− 2E[x (t1 + Ts + Δt )x (t1)]
(2)
2
where Ts denotes the nominal sampling period and δ is the average
power. With a cross-correlation function R (T) introduced, it can be
rewritten as
E[(x 2 − x1)2 ] = 2δx2 − 2R[Ts + Δt ]
2.1. Timing mismatch estimation
Similarly, the expectation of (x3−x2) can be written as
E[(x3 − x 2 )2 ] = 2δx2 − 2R[Ts − Δt ]
Fig. 3 shows the time domain description of non-uniform sample in
a two-channel TIADC. Ideally, when there is no timing mismatch
between the two channels, the sampling clocks of the two sub-ADCs are
CK1 and Ideal CK2, and channel 2 are respectively x1, x′2. When there
exits a timing mismatch Δt between CK1 and Ideal CK2, and the
sampled point of channel 2 changes to x2. To illustrate the relationship
between the sampled values with the timing mismatch Δt, one can
subtract the outputs of channels to get x3-x2 and x2-x1, where x3 is the
sampled point of the next cycle of channel 1. From a statistical point of
view, when the size of samples is large enough, the average difference
between |x3-x2| and | x2-x1| is proportional to Δt, as shown in (1)
E (|x3 − x 2| − |x 2 − x1|) ∝ Δt
(3)
2
(4)
For a small Δt, the difference between them is
eerror = E[(x3 − x 2 )2] − E[(x 2 − x1)2] ≈ 4Δt
dR
dt
(5)
where dR/dt is computed at t=Ts, in Ref. [13], the author has proved
that the autocorrelation's derivative cannot be zero at t=Ts for a signal
whose bandwidth is limited to fs/2. So the difference eerror is proportional to Δt. Since eerror is not the actual timing mismatch error, a
Least Mean Square (LMS) algorithm can be used to estimate the timing
mismatch between the two channels, which can be written as in (6)
(1)
α[n + 1] = α[n] + μ(|x3[n] − x 2[n]| − |x 2[n] − x1[n]|)
It is not easy to prove the formula (1) directly, an indirect
verification is to derivate the relationship between the expectation
value of (x3-x2)2-(x2-x1)2 and Δt. The expectation of (x2-x1)2 can be
(6)
where α=Δt/Ts, μ is the iterative step, x1[n] and x2[n] are the digital
outputs of channel 1 and channel 2, respectively, x3[n] is the output of
channel 1 of the next cycle with x3[n]=x1[n+2Ts]. The specific
estimation scheme for a two-channel time-interleaved ADC is shown
in Fig. 4, where z−1 and z−2 are both delay units, abs is the absolute
function, acc is an accumulator, and y[n] is the calibrated output.
Assuming a four-channel TIADC is considered, we choose the
channel 1 as a reference channel, and calibrate the timing mismatches
of channel 2, 3, 4 with respect to channel 1. The error extraction steps
are as follows:
(1) The mismatch errors between channel 3 and channel 1 are firstly
estimated, and the estimated error is proportional to
|x5 − x3| − |x3 − x1|.
(2) When the channel 3 is calibrated, it can be considered as a
reference channel, and the mismatch errors of channel 2 and
channel 4 can be estimated. The estimated errors are proportional
Fig. 2. Block diagram of the proposed calibration scheme.
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INTEGRATION the VLSI journal 57 (2017) 45–51
H. Chen et al.
where Δt=α Ts.
Assuming the input signal x(t)=e jϖ0t , and its Fourier transform is
X (ω) = 2πδ (ω − ω0 )
(13)
Finally, the Fourier transform of the output of TIADC is
Y (ω ) =
M −1
⎛
ω⎞
2πδ ⎜ω − ω0 − r s ⎟e−jω0αTse−jki2π / M
⎠
⎝
M
k =−∞
∞
∑ ∑
i =0
(14)
where M is the number of channels of TIADC, Y(ω) is the Fourier
transform of the input signal x(t), α is the timing mismatch between
channels. The formula (14) shows that the effect caused by the timing
mismatch can be corrected by multiplying Y(ω) with ejω0ɑTs which can
be realized by an ideal all-pass filter. In the design, a finite-impulse
response (FIR) filter is used to approximate the ideal all-pass filter.
Supposing that an N-order FIR filter is used, the transfer function is
Fig. 4. Time mismatch calibration technique for a two-channel TIADC.
to |x3 − x 2| − |x 2 − x1| and |x5 − x4| − |x4 − x3| respectively.
So the estimation formula of a four-channel TIADC can be written
N
as
Hα (z ) =
α21[n + 1] = α21[n] + μ(|x3[n] − x 2[n]| − |x 2[n] − x1[n]|)
α31[n + 1] = α31[n] + μ(|x5[n] − x3[n]| − |x3[n] − x1[n]|)
α41[n + 1] = α41[n] + μ(|x5[n] − x4[n]| − |x4[n] − x3[n]|)
1
MTs
∑ hα(n)z−n
(15)
n =0
Since the timing mismatch α=|Δt/Ts| < 1, the FIR filter is actually a
fractional delay filter. The polynomial expansion of hα(n) is
(7)
p
where α21, α31 and α41 are the timing mismatch of channel 2, 3, 4 with
respect to channel 1, respectively. xi[n] (i=1,2,3,4) corresponds to the
output of the channel i. x5[n] is the output of the next cycle of channel
1 with x5[n]=x1[n+4Ts].
hα (n ) =
∑ ck (n)α k
(16)
k =0
and
N
p
Hα (z ) = ∑n =0 (∑k =0 ck (n )α k )z−n
2.2. Timing mismatch correction
p
N
= ∑k =0 (∑n =0 ck (n )z−n )α k
Since the parallel alternate sampling time delay of TIADC can not
be precisely controlled, the timing mismatch errors have been a major
system error. Commonly, a method that use a programmable delay line
or PLL can realize a precise clock delay adjustment, but this is not
enough to meet the ps level clock precision for GHz sampling
frequency. In this work, the timing mismatch correction is realized
by an all-pass digital filter. Timing mismatch correction use the delay
characteristic of filter to achieve timing mismatch compensation.
We assume that the channel-k sub-ADC has a timing mismatch Δtk,
the sampling sequence of the k-channel sub-ADC will be
(17)
Assume that
N
Ck (z ) =
∑ ck (n)z−n
(18)
n −0
The transfer function of the fractional delay filter based on Farrow
structure can be realized in (19)
p
Hα (z ) =
∑ Ck (z )α k
(19)
k =0
∞
pk (t − Δtk ) =
∑
δ (t − Δtk − nMTs − kTs )
According to the above formula, the filter is divided into many subfilters Ck(z), k=0,1,…,p. In the mean time, α is made variable, a
fractional delay filter based on Farrow structure can therefore be easily
implemented as shown Fig. 5.
(8)
n =−∞
and the output of the channel-k sub-ADC will be
yk (t ) = pk (t − Δtk )x (t )
(9)
According to the shift characteristics of the Fourier transform, we
2.2.1. Lagrange polynomial approximation of the filter coefficients
The filter coefficients of the fractional delay filter can be obtained
through Lagrange interpolation algorithm. The Eq. (20) shows the
Lagrange interpolation formula of a N-order fractional delay filter.
get
FT [pk (t − Δtk )] = e−jωΔtk Pk (jω)
(10)
Then the system sampling sequence spectrum that contains timing
mismatch is
P(jω) =
2π
Ts
⎛⎛
⎜⎜ 1
⎜⎜ M
r =−∞ ⎝⎝
∞
∑
M −1
2π
⎞ ⎛
∑ e−jωΔtk e−jr M k ⎟⎟δ⎜⎝ω − r
⎠
k =0
ωs ⎞⎞⎟
⎟
M ⎠⎟⎠
N⎛α − l⎞
Hk (α ) = Hk (MTs + αTs ) = Π ⎜
⎟, 0 ≤ k ≤ N
l =0 ⎝ k − l ⎠
l≠k
The TIADC output after interpolation filter can be expressed as
(11)
Combined with the frequency domain convolution theorem, the
output spectrum of TIADC sampled by the sampling sequence is
∞
1
1
P(jω)*X (jω) =
X (jτ )
2π
Ts −∞
M −1
∞ ⎛⎛
⎞⎞
2π ⎞ ⎛
ω
∑ ⎜⎜⎜⎜ 1 ∑ e−j(ω−τ )Δtk e−jr M k ⎟⎟δ⎜ω − r s − τ ⎟⎟⎟dτ
⎠⎠
⎝
M
M
⎠
r =−∞ ⎝⎝
k =0
⎛
M −1
∞ ⎛⎡
⎞
ω ⎞
⎤ ⎡⎛
2π
−j ⎜ω − r s ⎟Δt
ω ⎞⎤
1
=
∑ ⎜⎜⎢ 1 ∑ e ⎝ M ⎠ k e−jr M k ⎥X ⎢j⎜ω − r s ⎟⎥⎟⎟
⎥⎦ ⎣ ⎝
M ⎠⎦⎠
Ts r =−∞ ⎝⎢⎣ M k =0
Y (jω) =
(20)
∫
(12)
Fig. 5. Block diagram of a filter based on Farrow structure.
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INTEGRATION the VLSI journal 57 (2017) 45–51
H. Chen et al.
N
xcorr (n ) =
∑ Hk (α )x(n − k )
Table 1
Hardware consumption comparison of the traditional filter and the improved filter.
(21)
k =0
Finally, the output can be rewritten as
− l⎞
⎟x ( n − k )
k − l⎠
Channels of TIADC
Adder units
Multiplier units
N⎛α
N
xcorr (n ) =
Π⎜
∑ l =0
⎝
k =0 l ≠ k
(22)
We have the formula (22) unfold, and recombined according to
similar items of ɑ, then the filter coefficients can be obtained. Take N=3
for example, then
3
3
The proposed Farrow filter
2
30
35
2
30
35
4
90
105
8
210
245
4
40
45
8
70
75
the proposed structure is much less than the traditional one. In
addition, since the filter is put at the output of TIADC, the bandwidth
of the input signal will be greatly improved.
α−l
xcorr (n ) = ∑k =0 Π ( k − l )x (n − k )
l =0
l≠k
(α − 1)(α − 2)(α − 3)
(α − 1)(α − 2)(α − 3)
x (n ) +
x (n −
−6
2
α(α − 1)(α − 3)
α(α − 1)(α − 2)
x (n − 2) +
x (n − 3)
+
−2
6
=
Traditional Farrow filter [12]
3. Experiment results
1)
3.1. Simulation results
(23)
A behavioral model of a four-channel TIADC based on the proposed
timing mismatch estimation and correction scheme is designed and
simulated in MATLAB. The sub-ADC of the TIADC is an ideal
quantizer, and the resolution is 8 bits. The order of the designed
Farrow filter is 5, and the coefficients of the sub-filters are [a0, b0, c0, d0
e0, f0]={1/120, 15/120, 85/120, 225/120, 274/120, 1}；[a1, b1, c1, d1
e1, f1]={−1/24，−14/24, −71/24，−154/24，120/24，0}；[a2, b2, c2,
d2,e2, f2]={ 1/12，13/12，59/12，107/12, 60/12，0}；[a0, b3, c3, d3
e3, f3]={−1/12，−12/12，−49/12，−78/12, −40/12，0}；[a4, b4, c4,
d4, e4, f4]={1/24，11/24，41/24，61/24，30/24, 0}；[a5, b5, c5, d5,
e5, f5]={ −1/120, −10/120， −35/120，−50/120，−24/120, 0}. To
evaluate the performance of the proposed calibration scheme, the gain
and offset mismatches between channels are both ignored. The added
timing mismatch is α=[α11, α21, α31, α41]=[0, −0.02,0.01, −0.015].
With a normalized input frequency fin/fs=0.3875, an iterative step
μ=2–19, the timing mismatch convergence plot is shown in Fig. 7,
which shows that the proposed calibration method can achieve
accurate and fast timing mismatch estimation, and the convergence
time is approximately 1.0×104 samples. Fig. 8 shows the output
spectrum of the TIADC. Before calibration, the distortion caused by
channel timing mismatch limits the SNR of the TIADC to 33.8 dB. After
calibration, the spurious spectral due to the timing mismatch is
reduced to the level under the noise floor and SNR is improved to
48.9 dB which is nearly equal its value without mismatch.
Table 2 shows that SNR versus the number of the order of the filter,
according to the simulation results, a 5th-order filter is enough to
complete the calibration performance.
Fig. 9 shows the SNR/SNDR/SFDR versus the standard deviation
of timing skew with and without calibration. Both of them are
simulated with the normalized input frequency fin/fs=0.3875. After
calibration, the proposed calibration technique can effectively improve
the dynamic performance of TIADC in various timing skew.
Fig. 10 shows the SNR versus the input frequency both before and
According to similar items of ɑ, it can be rewritten as:
xcorr (n ) = α 3[a1x (n ) + b1x (n − 1) + c1x (n − 2) + d1x (n − 3)]
+α 2[a 2x (n ) + b2x (n − 1) + c2x (n − 2) + d 2x (n − 3)]
+α[a3x (n ) + b3x (n − 1) + c3x (n − 2) + d3x (n − 3)]
+[a4x (n ) + b4x (n − 1) + c4x (n − 2) + d4x (n − 3)]
(24)
So, amx(n)+bmx(n-1)+cmx(n-2)+dmx(n-3)(m=1,2,3,4) is the subfilters, am, bm, cm, dm are the coefficients of sub-filters.
2.2.2. The improved fractional delay filter based on Farrow structure
Traditional calibration scheme with the Farrow filter placed in each
sub-channel of TIADC tends to have poor calibration effect when the
input signal frequency exceeds the sub-channel Nyquist sampling rate.
In addition, the number of the filters increases with the channels of
TIADC, which is required large hardware resource. Taking into account
the identity of these filters, one solution is based on the sharing of the
Farrow filter by adopting some extra adders and multipliers. The
structure of the improved fractional delay filter is shown in Fig. 6. The
filter is placed on the digital output of TIADC, which can be shared by
all channels. αi(i=2,3,…,M) is the timing mismatch between channel i
and channel 1. x[n] is the digital output of TIADC without calibration
and xcorri[n] represents the output of TIADC where channel i is
calibrated. Compared with the traditional calibration method, the
hardware resources consumption of the proposed scheme is greatly
reduced. Furthermore, the proposed solution does not need Farrow
filters of high order, a 3th to 5th order filter will meet the accuracy
requirement. Table 1 shows the comparison of the hardware consumption of the traditional filter and the proposed filter. Both filters are 5thorder. It can be seen that the hardware consumptions of the two
schemes are almost the same in a two-channel TIADC case. However,
with the increase of channels number, the hardware consumption of
Fig. 6. Block diagram of the proposed improved fractional delay filter based on Farrow
structure.
Fig. 7. Convergence plot of timing mismatch in the four channel TIADC.
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INTEGRATION the VLSI journal 57 (2017) 45–51
H. Chen et al.
Fig. 10. SNR versus normalized input frequency.
after calibration. Before calibration, the SNR is inversely proportional
to the input signal frequency as the timing mismatch has more
influence for higher input frequencies, when the input signal frequency
approaching to Nyquist frequency, the SNR decreases to 24 dB. After
calibration, the spurious spectrum is greatly disappeared, and SNR
improves. It can see that a good calibration effect can be obtained with
SNR above 48 dB with a normalized input frequency lower than 0.4.
However, with the continued increase of the normalized input frequency, the calibration effect is decreased. The reason for the decline is
that the compensation Farrow filter is realized by Lagrange interpolation approximation, and the interpolation effect will be reduced when
the input signal frequency close to the Nyquist frequency.
Previous analyses are based on a single frequency input signal.
Since the nature signal is not a single frequency, and is often
complicated by a number of different frequency components. Here,
we further verify the proposed calibration techniques with a multifrequency input signal. The multi-frequency input signal are composed
with normalized frequency 0.064, 0.129, and 0.194, where fs is
400 MHz. In order to prevent exceeding the ADC conversion range,
the input signal magnitude is reduced to 0.9. Fig. 11 is TIADC output
spectrum before and after calibration. It can be clearly seen that the
spurs caused by channel mismatch errors of TIADC have been greatly
depressed after calibration.
In Table 3, a comparison between this work with other calibration
papers is presented. Compared with other digital calibration techniques like Ref. [12] and Ref. [13], the proposed digital calibration
technique can achieve the fastest convergence rate while have the least
hardware consumption. The calibration method in Ref. [13] uses
analog delay cells to compensate the timing mismatch and it does
not need a filter, however, this method is not suited for high resolution
TIADCs. The reason is that its analog compensation step will becoming
very small with the increase of the resolution of TIADC, what's more,
its calibration effect may suffer from thermal noises and clock jitters.
Fig. 8. Output spectrum of the four-channel TIADC (a) before calibration (b) after
calibration.
Table 2
SNR vs. orders of the Farrow filter.
Order
SNR (dB)
3
4
5
6
40.8
42.2
48.8
48.9
3.2. Hardware validation
In order to more fully verify the reliability and effectiveness of the
calibration technique, the calibration algorithm is executed in the
FPGA board which houses the Altera Stratix IV FPGA chip
EP4SE820H40C4N. After downloading on the FPGA board, we can
perform a reset button to reset the entire program, and grab the output
data by the logic analyzer. As shown in Table 4, the synthesized results
shows that the design can operate on the FPGA at the clock frequency
of 150 MHz and consumes only few percentages of the hardware
resources in the FPGA chip. Fig. 12 shows the FPGA verification results
of the proposed calibration algorithm with fin/fs=0.2811 and timing
mismatch is the same as the MATLAB simulation condition, the SNR is
enhanced from 33 dB to 49 dB, which indicates the effectiveness of the
Fig. 9. SNR/SNDR/SFDR versus the standard of timing skew with and without
calibration.
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H. Chen et al.
Fig. 11. Dynamic analysis results with Multi-frequency input signal.
Table 3
Performance summary.
Channels
Mismatch type
Calibration method
Effective within
freq.range
Filters
Convergence
time(samples)
Ref. [8]
Ref. [12]
Ref. [13]
This work
4
Timing
Digital and
analog
0–0. 5fs
4
Timing
Digital
8
Timing
Digital
4
Timing
Digital
0–0.25fs
0–0.44fs
0–0.45fs
0
8×105
3(11taps)
4×104
7(8taps)
1.5×105
1(5taps)
1.0×104
Fig. 12. Output spectrum of FPGA verification before and after calibration.
Table 4
FPGA synthesis results.
Family
Stratix IV
Device
Logic utilization
Combinational ALUTs
Memory ALUTs
Dedicated logic registers
Total registers
DSP block 18-bit elements
Fmax
EP4SE820H40C4N
2%
3473/182400(2%)
20/91200( < 1%)
639/182400( < 1%)
639
128/1288(10%)
164 MHz
Fig. 13. SNR/SNDR/SFDR versus normalized input frequency in FPGA.
proposed calibration method. The SNR/SNDR/SFDR as a function of
the normalized input frequency after calibration in FPGA are plotted in
Fig. 13, and the results indicate that the proposed calibration technique
can mitigate the effect of timing mismatch with the effective input
frequency range.
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4. Conclusion
References
This paper proposes an efficient all-digital background calibration
scheme for timing mismatch of TIADCs. By only using some adders
and registers, the timing mismatch is estimated. The correction scheme
is realized by an improved fractional delay filter based on Farrow
structure, and the filter is shared by all channels of TIADC. The
hardware implementation of the proposed architecture is developed
and is validated on the FPGA. The synthesized results shows that the
calibration technique is effective to reduce the distortion errors of
timing mismatch and improves the SNR/SNDR/SFDR of TIADC
system while using only few percentages of FPGA hardware resources.
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Acknowledgement
The authors would like to thank the Institute of VLSI Design, Hefei
University of Science and Technology, Hefei, China, for EDA tools
support. H. Chen would thank Dr X. Tang from the Institute of CETC
38, for valuable comments and constructive suggestions. H. Chen
would thank Jian Maochen, Huang chao and Wu jinsheng from the
Institute of VLSI Design, for their hard experimental working.
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