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Chapter 4
Fixed-bias circuit
Emitter-stabilized bias circuit
Collector-emitter loop
Voltage divider bias circuit
DC bias with voltage feedback
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All analysis of circuits in Ch. 4 will be in DC
(f=0 Hz)
So…
All capacitors replaced with
And all inductors are replaced with
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All circuits shown in the slides and in the book
for Chapter 4 are npn transistors.
The analysis for pnp transistor biasing circuits is
the same as that for npn transistor circuits. The
only difference is that the currents are flowing in
the opposite direction.
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Applying DC voltages to a transistor in
order to turn it on so that it can amplify AC
signals.
≅ 0.7
=
+1
≅
=
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

DC input
establishes an
operating or
quiescent (Q)
point
Defines output
characteristics
based on input
(Ib)
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Active or Linear Region Operation
◦ Base–Emitter junction is forward biased
◦ Base–Collector junction is reverse biased

Cutoff Region Operation
◦ Base–Emitter junction is reverse biased

Saturation Region Operation
◦ Base–Emitter junction is forward biased
◦ Base–Collector junction is forward biased
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

Simplest DC Bias
configuration
determines the base
current for Q-point
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From Kirchhoff’s voltage
law:
+VCC – IBRB – VBE = 0
Solving for base current:
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Collector current:
From Kirchhoff’s voltage law:
affects
, not
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Current through the transistor is at its
maximum possible value.
Will cause distortion in output AC signal
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
Find
◦
◦
◦
◦
◦
and
and
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The load line end points are:
ICsat
IC = VCC / RC
VCE = 0 V
VCEcutoff
VCE = VCC
IC = 0 mA
The Q-point is the operating point where the value of RB sets the
value of IB that controls the values of VCE and IC .
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
Given Fig 4.16
◦ Q-point at 25 µA
◦ VCC = 20 V

Find
◦
◦
◦
◦


VCE
IC
RC
RB
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RE stabilizes the bias
circuit.
Counters changes in
temp and input noise
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The endpoints can be determined from the load line.
VCEcutoff:
ICsat:
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Base Current
Input Resistance (Fig 4.21)
→
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Since IE  IC:
Also:
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Find
◦
◦
◦
◦
◦
◦
◦
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This is a very stable bias circuit.
The currents and
voltages are nearly
independent of any
variations in  based
on temperature.
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
Allows for more exact analysis on any circuit
◦
=
◦
=
◦
◦
=
=
‖
=
(
)
−
(
+
)
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Where IB << IC and IC  IE :
Where  RE > 10R2:
From Kirchhoff’s voltage law:
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Transistor Saturation Level
Load Line Analysis
Cutoff:
Saturation:
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Using General Analysis,
find
◦
◦

Using Approx. Analysis,
find
◦
◦

Conditions dictate which
to use
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
Feedback loop improves
stability
◦ β changes have less impact

Q-point less dependent
on β
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VCE = VCC – IC(RC + RE)
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Transistor Saturation Level
Load Line Analysis
Cutoff
Saturation
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
Find
◦
◦
◦
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Many other bias configurations are possible,
based on the application and the designers
preference.
Review pgs. 186-210 for these combinations
as needed.
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
Pure DC source creates inverting switch
circuit
◦ Used in logic controls
◦ Operates at or above saturation
◦ Shorts Collector to ground
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Saturation current:
To ensure saturation:
Emitter-collector
resistance at
saturation and cutoff:
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
Given
◦

Vcc=12
= 8 mA
Find standard values for
◦
◦
Vi = 10 V
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Transistor switching times:
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Approximate voltages
VBE  .7 V for silicon transistors
VCE  25% to 75% of VCC
Test for opens and shorts with an ohmmeter.
Test the solder joints.
Test the transistor with a transistor tester or a curve tracer.
Note that the load or the next stage affects the transistor
operation.
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