Document Type: Tutorial
NI Supported: Yes
Publish Date: Feb 24, 2011
Getting Started with CompactRIO - Offloading
Signal Processing with LabVIEW FPGA
Table of Contents
1.
2.
3.
4.
Overview
The RIO Architecture
Starting Your CompactRIO Application
View Additional CompactRIO Development Resources
This article is part of a series on developing CompactRIO applications in LabVIEW.
Click here to view the list of other articles
Overview
This tutorial will walk you through one of the LabVIEW shipping examples to help you learn how to do signal processing on the CompactRIO FPGA. The example we will be using is the Windowed
FFT – cRIO project, which generates a signal on the FPGA and then performs a windowed FFT. No C Series modules are necessary for this tutorial.
The RIO Architecture
The National Instruments CompactRIO programmable automation controller is an advanced embedded control and data acquisition system designed for applications that require high performance
and reliability. With the system's open, embedded architecture, small size, extreme ruggedness, and flexibility, engineers and embedded developers can use COTS hardware to quickly build
custom embedded systems. NI CompactRIO is powered by National Instruments LabVIEW FPGA and LabVIEW Real-Time technologies, giving engineers the ability to design, program, and
customize the CompactRIO embedded system with easy-to-use graphical programming tools.
CompactRIO combines an embedded real-time processor, a high-performance FPGA, and hot-swappable I/O modules. Each I/O module is connected directly to the FPGA, providing low-level
customization of timing and I/O signal processing. The FPGA is connected to the embedded real-time processor via a high-speed PCI bus. This represents a low-cost architecture with open access
to low-level hardware resources. LabVIEW contains built-in data transfer mechanisms to pass data from the I/O modules to the FPGA and also from the FPGA to the embedded processor for
real-time analysis, postprocessing, data logging, or communication to a networked host computer.
C Series I/O Modules
A variety of I/O types are available including voltage, current, thermocouple, RTD, accelerometer, and strain gauge inputs; up to ±60 V simultaneous-sampling analog I/O; 12, 24, and 48 V
industrial digital I/O; 5 V/TTL digital I/O; counter/timers; pulse generation; and high voltage/current relays. Because the modules contain built-in signal conditioning for extended voltage ranges or
industrial signal types, you can usually connect wires directly from the C Series modules to your sensors and actuators.
FPGA
The embedded FPGA is a high-performance, reconfigurable chip that engineers can program with LabVIEW FPGA tools. Traditionally, FPGA designers were forced to learn and use complex
design languages such as VHDL to program FPGAs. Now, any engineer or scientist can use graphical LabVIEW tools to program and customize FPGAs. Using the FPGA hardware embedded in
CompactRIO, you can implement custom timing, triggering, synchronization, control, and signal processing for your analog and digital I/O.
Real-Time Processor
The CompactRIO embedded system features an industrial 400 MHz Freescale MPC5200 processor that deterministically executes your LabVIEW Real-Time applications on the reliable Wind River
VxWorks real-time operating system. LabVIEW has built-in functions for transferring data between the FPGA and the real-time processor within the CompactRIO embedded system. Choose from
more than 600 built-in LabVIEW functions to build your multithreaded embedded system for real-time control, analysis, data logging, and communication. You can also integrate existing C/C++
code with LabVIEW Real-Time code to save on development time.
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Size and Weight
Size, weight, and I/O channel density are critical design requirements in many embedded applications. A four-slot reconfigurable embedded system measures 179.6 by 88.1 by 88.1 mm (7.07 by
3.47 by 3.47 in.) and weighs just 1.58 kg (3.47 lb).
Application Examples
With the low cost and reliability of CompactRIO, as well as its suitability for high-volume embedded measurement and control applications, you can adapt it to solve a wide variety of industry and
application challenges. Examples include:
In-vehicle data acquisition, data logging, and control
Machine condition monitoring and protection
Embedded system prototyping
Remote and distributed monitoring
Embedded data logging
Custom multiaxis motion control
Electrical power monitoring and power electronics control
Servo-hydraulic and heavy machinery control
Batch and discrete control
Mobile/portable noise, vibration, and harshness (NVH) analysis
Starting Your CompactRIO Application
1.
After you have launched LabVIEW click on the Find Examples… option on the LabVIEW Getting Started page
2.
This will open the NI Example Finder. The Example Finder has hundreds of examples to help you get started with your application. You can browse the examples by task, or use the search
tool to find examples that have been tagged with your key words. We will be using the search feature to find the Windowed FFT example.
Click on the Search tab and type FFT into the keywords box and click Search. The Example Finder returns all examples that have been tagged with the term FFT. The Icons next to the
examples show which LabVIEW toolkits are necessary to run the example. The example we will use is at the bottom of the list “Windowed FFT – cRIO.lvproj”. Note the Real-Time and FPGA icons
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next to the example. Double click on the Windowed FFT example to open it.
Using This Tutorial With Your Hardware
This example was designed with a generic cRIO-9074 as the basic hardware. In order to run this example, you will need to configure a project to run your specific CompactRIO system. The
following procedure will guide you through the process of creating a new project for your hardware and configuring it with this example.
1.
From the example project explorer, choose File » Save As...
2.
In the Save dialogue that appears, choose the Duplicate .lvproj file and contents radial button and ensure that the Include all dependencies radial button is also chosen. Then click
Continue…
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3.
Select a folder to store your new project and its associated files. Choose an appropriate name for the project file as well. All other project contents will maintain the same name as used in the
original example.
4.
Close the original example project and open the newly saved project.
5.
Right click the top level Project: <Name>, where <Name> is the title of your project. Then choose New » Targets and Devices…
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6.
From the Add Targets and Devices dialogue that appears, choose the Existing target or device radial button and ensure that Discover an existing target(s) or devices(s) radial button is
also chosen if your device is on the same subnet as your development computer.
7.
Expand the Real-Time CompactRIO folder under Targets and devices and choose your CompactRIO from the list.
8.
Press OK.
9.
The Select Programming Mode dialogue box will appear. It is important to choose the correct programming mode for your example.
If the example contains “Scan Mode” in the title, be sure to choose the FPGA Interface radial button. This will place the CompactRIO target into a pre-configured state that enables you develop an
FPGA VI to access module IO and other FPGA resources.
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After the discovery process is complete, the new project will be configured for your specific CompactRIO device. Now you must add the example files to your new target and remove the old target.
10. Drag the Windowed FFT (host).vi under the old RT CompactRIO controller and place it under the new CompactRIO controller you just added to the project in the same relative location.
11. Repeat this drag and drop maneuver for the “Items to Move” folder under the old FPGA target and place it under the new FPGA target.
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12. Remove the old RT CompactRIO Target from the project by right clicking it and selecting Remove from Project.
13. Confirm the permanent removal of the target from the project.
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The example is now ready to use with your hardware, so let’s take a look at what is going on in this example. The first thing to note is that there is both an RT (Windowed FFT (Host).vi) VI as well
as a FPGA (Windowed FFT (FPGA).vi) VI in this example. Most CompactRIO programs will have both a RT and a FPGA component. When starting a CompactRIO application it is best to start
with your FPGA VI, so let’s begin by taking a look at the Windowed FFT (FPGA) VI.
14. Expand the Chassis and FPGA Target items in your project tree and double click on the Windowed FFT (FPGA).vi item to open it.
15. Type Ctrl+E to show the block diagram or click on Window>>Show Block Diagram. We will also want to open Context Help to get detailed information about the various components of this
VI. Open Context Help by typing Ctrl+H or clicking Help>>Show Context Help.
If you now hover over the VI Icon (located in the top right corner of your window just below the Windows X) Context Help will display information about the functionality of this VI.
16. Take some time to read through the context help as well as the comments on the block diagram. Perhaps the most important concept to note in this example is the separation of the high
priority tasks such as signal generation/acquisition and signal processing from low priority display or communication tasks.
By placing these two types of tasks in separate loops we ensure that if communication is interrupted or the consumer of the display/communication data falls behind, that our high priority tasks will
continue to function without interruption.
17. Another important concept is the means available for communication with your FPGA VI from other locations. In this example we use both named Front Panel objects (such as controls and
indicators), and a DMA FIFO (a fixed depth queue that writes directly to the RT controller memory). These are the main two means of communication with your FPGA VI.
18. Now that you have taken a closer look at what is going on in the FPGA it is time to start the process of compiling this example FPGA code for use. There are many ways to start a compile, but
the easiest one is to simply click the run arrow on either the block diagram or front panel of your LabVIEW FPGA VI.
After doing so, you may be prompted to save your VI first, and as soon as you do, LabVIEW starts the process of processing your LabVIEW FPGA diagram and generating the necessary files to
start compiling. This process can take a little time. NOTE: Any changes you make to the FPGA VI after this point will require a recompile, so make sure your VI is final before starting the
compilation process.
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19. Once LabVIEW has finished generating the intermediate files, it starts the LabVIEW FPGA Compile Server. This process will generate the final FPGA bit file that will define the functionality of
your hardware.
This process can take anywhere from 5 to 50 minutes, so it is often useful to disconnect from the compile server so you can continue working on other sections of your application. To do so click
the Close button on the Compilation Status window. This will hide the status window, but you can still watch the compile process in the LabVIEW FPGA Compile Server window.
20. While the compile continues in the background, let’s take a look at our RT host VI. In your project window double click the Windowed FFT (Host).vi item to open the VI. Show the block
diagram (Ctrl+E).
The first thing you will notice upon looking at the block diagram is a lot of broken wires. This is because the FPGA Open node is not configured correctly to use your FPGA VI.
To fix this, right click the FPGA Open node and click on Configure Open FPGA Reference…
21. Click the VI radio button and then browse to the Windowed FFT (FPGA).vi as the VI reference. Select it and click OK. LabVIEW will then fix the broken wires in your RT VI because they are
now associated with the correct FPGA reference.
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22. Take some time to read through the comments on the block diagram as well as the VI overview in the Context Help. Note that the application and communication configuration takes place
before the while loop, and that all of the processing and display actions take place in the while loop. This ensures that your system is configured and ready to run before starting the FPGA VI.
Also note, that while we already did a significant amount of signal processing in the FPGA, we are still doing some processing on the RT host side. This is one of the most power features of the
CompactRIO system in that you can move your processing elements between the FPGA and the RT processor to take advantage of extra bandwidth you may have in either location.
23. Now that you have taken some time looking at the block diagram for the RT Host VI, let’s run our application. The FPGA compile should have completed by this time, but let’s reconnect to the
compile to be sure. From the project window, right click the Windowed FFT (FPGA) VI and select Reconnect to Compilation. The Compile Status window you should display a successful
compile message with the number of FPGA resources your VI used during the compile process.
24. Now reopen the Windowed FFT (Host) VI and click the run button. This will deploy your RT and FPGA applications to your CompactRIO system and start them.
25. When the Deployment Progress window closes your Windowed FFT (Host) VI will be visible and running on your desktop. However you will not be able to see your FPGA VI running (even
though it is deployed and running on your CompactRIO system). The FPGA is running, but in this example your RT host VI is acting as the display and interface for your FPGA VI.
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View Additional CompactRIO Development Resources
Congratulations on completing this tutorial! To continue learning, check out the additional resources on the CompactRIO Setup and Services page.
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