www.silabs.com
Complete Portfolio of XOs, VCXOs and
Any-Rate Clocks
Frequency Flexibility
Engineered to support the widest frequency range for maximum design flexibility. Available in industry
standard RoHS compliant packages.
Ultra-Low Jitter
Based on our patented DSPLL® and MultiSynth technologies, these low jitter products improve
system performance, reduce BOM cost, minimize board space and simplify system design.
Shortest Lead Times
Silicon Labs changes the XO/VCXO manufacturing model, enabling short, predictable lead times for
any frequency oscillator.
2009
Reduce System Cost and Improve System Performance
Silicon Labs’ complete portfolio of XOs, VCXOs and Any-Rate Clocks are highly integrated frequency flexible solutions for datacom,
telecom, storage, computing, broadcast video, wireless, industrial and consumer systems. Based on Silicon Labs’ patented DSPLL
and MultiSynth technologies, these low jitter products eliminate expensive external components while improving performance,
minimizing board space and simplifying system design. Following are several system examples:
Optical Networking
(GbE, 10 GbE, Synchronous Ethernet, OC-48, OC-192, OC-768, OTN)
Silicon Labs offers a complete family of XO/VCXOs, jitter attenuating clock multipliers, clock
generators, and transceivers for 2.5G, 10G, 40G, and 100G applications.
Si5326
Jitter Attenuating
Clock Multiplier
Photodetector
Multi Service Platform
Featured Products
TIA
Laser
Modulator
Laser
Driver
• Si53x/Si55x XO/VCXO
• Si5326/68 Any-Rate Jitter
• Si5338 Clock Generator
G.709
FEC
Processor
Network
Processor
Si5338
Clock
Generator
Attenuating Clock Multiplier
Si5040
10 Gbps
Transceiver
Backplane
Optical
Fiber
Interface
Si55x
VCXO
FPGA
• Si5040 10 Gbps Transceiver
Telecom Access (Converged PBX, DSLAM)
A converged PBX combines a traditional PBX, which connects internal telephone lines to the
PSTN, with soft switch functions for the VoIP network and is capable of handling VoIP phones
alongside traditional business phones. Silicon Labs’ carrier-grade SLIC and DAA technology
are the perfect bridge between traditional and packet-based networks. Silicon Labs’ clock
products simplify the clock architecture in telecom access applications by replacing multiple
discrete XOs with a single IC.
POTS
POTS
POTS
Linefeed
SLIC
Dual
Linefeed
Si32xx
Dual
SLIC
POTS
Linefeed
POTS
Linefeed
POTS
Linefeed
POTS
Linefeed
IP
PHONES
LAN
Ethernet
PHY
Ethernet
MAC
Featured Products
Si5338
Clock Generator
VoIP
DSPs
Si324x
Quad
SLIC
IP PBX
25 MHz
• Si5315 SyncE Clock
T/E Framer
T/E LIU
T/E Framer
T/E LIU
• Si5338 Clock Generator
PSTN
• Si32xx Dual ProSLIC
• Si324x Quad ProSLIC
• Si3200 Linefeed
Si5315
SyncE Clock
• Si320x Dual Linefeed
Storage Area Networking
Storage area networks (SAN) are used to attach remote computer storage devices like disk
arrays to servers. Medium and large enterprises rely on highly reliable and secure data center
networks to manage and secure large volumes of mission-critical data. Silicon Labs’ timing
products simplify the timing architecture in these applications, reducing BOM and simplifying
system design.
Storage Systems
25 MHz
Si500
Silicon
Oscillator
Featured Products
• Si5338 Clock Generator
Si5338
Clock
Generator
• Si500 Silicon Oscillator
disk
disk
12/24/36
Port SAS
Expander
SAS2
4/8 Port
Controller
Ethernet/
Fiber
Channel
disk
PCIe
Switch
disk
disk
12/24/36
Port SAS
Expander
SAS2
4/8 Port
Controller
Network
Processor
disk
Broadcast Video
Broadcast video equipment focuses on image capture, encoding, decoding, processing
and transmission of standard-definition/high-definition (SD/HD) multimedia content for the
professional digital video market. Silicon Labs’ multi-rate XO/VCXOs, clock generators and
precision clock products simplify timing architectures by providing SD/HD clock generation in
compliance with DVI, HD SDI and 3G SDI specifications.
Local Clock Generation
SD/HD Video Card
SD Clock
27/54 MHz
Featured Products
Si5338
or
Si53x/Si55x
XO/VCXO
• Si5326/68 Any-Rate Jitter
Attenuating Clock Multiplier
• Si5338 Clock Generator
HD Clock
74.1758 MHz
• Si532/4 Dual/Quad
Frequency XOs
3G/HD/SD
SDI
Transceiver
(FPGA)
2.97 Gbps
2.97/1.001 Gbps
1.485 Gbps
1.485/1.001 Gbps
270 Mbps
External Clock Source
• Si552/4 Dual/Quad
Frequency VCXOs
HD Clock
74.25 MHz
SDI Out
Analog
Ref In
HSYNC
SD/HD Clock
Sync
Si5326
Separator
Jitter Attenuation/
Clock Multiplication
SDI In
Any-Rate Clock Generators and Buffers
• Industry’s first clock generator capable of synthesizing four low jitter, non-integer related frequencies at the same time
• Leverages Silicon Labs’ MultiSynth technology to provide any-rate frequency synthesis and outstanding jitter performance
Part Number
Si5338A
Si5338B
Si5338C
Si5338D
Si5338E
Si5338F
Si5338G
Si5338H
Si5338J
Si5338K
Si5338L
Si5338M
Si5338N
Si5338P
Si5338Q
Si5334A
Si5334B
Si5334C
Si5334D
Si5334E
Si5334F
Si5334G
Si5334H
Si5334J
Si5334K
Si5334L
Si5334M
Si5330A
Si5330B
Description
Control
1:4 clock generator
I 2C
1:4 clock generator + pin controlled
phase inc/dec
I 2C
1:4 clock generator + pin controlled
frequency inc/dec
I 2C
1:4 clock generator + pin controlled
output enable
I2 C
4:4 clock generator
I 2C
1:4 clock generator
Pin
1:4 clock generator + pin controlled
phase inc/dec
Pin
1:4 clock generator + pin controlled
frequency inc/dec
Pin
1:4 clock generator + pin controlled
spread spectrum
Pin
1:4 differential to LVPECL clock buffer
1:4 differential to LVDS clock buffer
Pin
Pin
Input
Frequency
(MHz)
Output
Frequency
(MHz)
Format
Jitter
Package
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
0.16–700
8–30 (Xtal) or
0.16–350
5–700 (Clock)
0.16–200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
CMOS, LVPECL,
LVDS, HCSL, SSTL,
HSTL
1 ps rms
4x4 mm 24-QFN
5–700
5–700
LVPECL
0.3 ps rms
LVDS
0.3 ps rms
4x4 mm 24-QFN
4x4 mm 24-QFN
5–700
5–700
Si5330C
1:4 differential to HCSL clock buffer
Pin
5–250
5–250
HCSL
0.3 ps rms
4x4 mm 24-QFN
Si5330D
1:8 single-ended to SSTL clock buffer
Pin
5–350
5–350
SSTL
0.3 ps rms
4x4 mm 24-QFN
Si5330E
1:8 single-ended to HSTL clock buffer
Pin
5–350
5–350
HSTL
0.3 ps rms
4x4 mm 24-QFN
Si5330F
1:8 single-ended to CMOS clock buffer
Pin
5–200
5–200
CMOS
0.3 ps rms
4x4 mm 24-QFN
Si5330G
1:8 differential to CMOS clock buffer
Pin
5–200
5–200
CMOS
0.3 ps rms
4x4 mm 24-QFN
Si5330H
1:8 differential to SSTL clock buffer
Pin
5–350
5–350
SSTL
0.3 ps rms
4x4 mm 24-QFN
Si5330J
1:8 differential to HSTL clock buffer
Pin
5–350
5–350
HSTL
0.3 ps rms
4x4 mm 24-QFN
Si5330K
1:4 single-ended to LVPECL clock buffer
Pin
5–350
5–350
LVPECL
0.3 ps rms
4x4 mm 24-QFN
Si5330L
1:4 single-ended to LVDS clock buffer
Pin
5–350
5–350
LVDS
0.3 ps rms
4x4 mm 24-QFN
Si5330M
1:4 single-ended to HCSL clock buffer
Pin
5–250
5–250
HCSL
0.3 ps rms
4x4 mm 24-QFN
One IC Replaces Four Discrete PLLS
From any frequency crystal or reference clock
input, the Si5338 generates four completely
independent output clocks. Based on Silicon
Labs’ breakthrough MultiSynth technology,
each output clock can be user-programmed
to any frequency from 0.16 to 350 MHz and
select frequencies to 700 MHz. This powerful
feature enables the Si5338 to replace four
discrete phase-locked loops (PLLs) with a
single device while eliminating the need to
use custom frequency crystals.
Any-Rate, Any-Output (0.16 to 700 MHz)
Crystal
(8 to 30 MHz)
or
Reference Clock
(5 to 700 MHz)
MultiSynth Technology
Si5338
Silicon Labs’ MultiSynth technology simplifies
clock generation in communication, storage and
broadcast video applications. Clock generators
that employ this innovative technology can
produce multiple non-integer related output
clocks from a single device, eliminating the
need for standalone crystal XOs and clock
generator ICs. The MultiSynth approach
leverages proprietary phase error cancellation
circuitry to provide any-rate frequency synthesis
at very low jitter (1 ps rms).
Input
Clock/
Crystal
MultiSynth
÷M0
Phase
Frequency
Detector
Loop
Filter
VCO
MultiSynth
÷N
Output
Clock 0
MultiSynth
÷M1
Output
Clock 1
MultiSynth
÷M2
Output
Clock 2
MultiSynth
÷M3
Output
Clock 3
MultiSynth
• Fractional-N divider provides precise
frequency division from high frequency VCO
fVCO
• Phase error calculator tracks phase between
fDIV and ideal clock waveform
Fractional-N
Divider
Phase
Adjust
fDIV
fOUT
Phase Error
Calculator
• Phase adjust circuitry dynamically changes
the output clock phase to match the ideal
clock waveform
Divider Select
(DIV1, DIV2)
Simplify Timing Architectures
The any-rate, any-output capability provided by the Si5338 dramatically simplifies timing architectures by replacing fixed frequency
clock generators, multiple crystal oscillators and discrete level translators with a single device, minimizing cost and real estate and
reducing power by 50% compared to traditional solutions.
Silicon Labs Approach
Datacom Line Card
Traditional Approach
25 MHz
1.8 V CMOS
Fast
Ethernet
PHY
25 MHz
1.8 V CMOS
Fast
Ethernet
PHY
Datacom Line Card
25 MHz
1.8 V CMOS
Fast
Ethernet
PHY
25 MHz
1.8 V CMOS
Fast
Ethernet
PHY
Clock
25 MHz
Si5338
Clock
Generator
66.6 MHz +/-5%
3.3 V CMOS
XO
XO
XO
66.6 MHz -5%
100 MHz
2.5 V LVPECL
1.544 MHz/2.048 MHz
3.3 V CMOS
•
•
•
•
•
•
P
66.6 MHz +5%
FPGA
Clock
T1/E1
Framer
Clock
Generates any frequency on any output
Supports any signal format on any output
Excellent jitter performance (1 ps rms)
Frequency margining
User programmable (I2C)
Single device, simplified PCB layout
•
•
•
•
•
•
100 MHz
3.3 V CMOS
Level
Translator
66.6 MHz
3.3 V CMOS
100 MHz
2.5 V LVPECL
1.544 MHz
3.3 V CMOS
2.048 MHz
3.3 V CMOS
Limited output frequencies
Requires external level translators
Poor jitter performance
No output frequency adjustment
Custom frequencies need silicon spin
Multiple devices, non-optimized PCB layout
P
FPGA
T1/E1
Framer
Any-Rate Jitter Attenuating Clock Multipliers
• Jitter attenuating clock multiplier ICs that provide any-rate frequency synthesis
• Easy-to-use integrated solutions simplify design and layout and improve board-level noise immunity
• Frequency flexibility enables replacement of multiple clocks and XOs
Part
Number
Control
Clock
Inputs/
Outputs
Input
Frequency
(MHz)
Output
Frequency
(MHz)
Jitter
(12 kHz to
20 MHz)
Si5315
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Pin
Pin
I2C or SPI
Pin
Pin
I2C or SPI
I2C or SPI
Pin
Pin
I2C or SPI
I2C or SPI
2/2
2/1
1/1
2/2
2/2
2/2
2/2
4/5
4/5
4/5
4/5
0.008 to 644
19 to 710
0.002 to 710
19 to 707
0.008 to 707
10 to 710
0.002 to 710
19 to 707
0.008 to 707
10 to 710
0.002 to 710
0.008 to 644
19 to 710
0.002 to 1417
19 to 1050
0.008 to 1050
10 to 1417
0.002 to 1417
19 to 1050
0.008 to 1050
10 to 1417
0.002 to 1417
0.6 ps rms typ
0.3 ps rms typ
0.3 ps rms typ
0.6 ps rms typ
0.3 ps rms typ
0.6 ps rms typ
0.3 ps rms typ
0.6 ps rms typ
0.3 ps rms typ
0.6 ps rms typ
0.3 ps rms typ
PLL Bandwidth
Hitless
Switching
60 Hz to 8.4 kHz
60 Hz to 8.4 kHz
60 Hz to 8.4 kHz
30 kHz to 1.3 MHz
60 Hz to 8.4 kHz
30 kHz to 1.3 MHz
60 Hz to 8.4 kHz
30 kHz to 1.3 MHz
60 Hz to 8.4 kHz
30 kHz to 1.3 MHz
60 Hz to 8.4 kHz
Yes
—
—
—
Yes
—
Yes
—
Yes
—
Yes
Format
Package
CMOS,
LVDS,
LVPECL,
CML
6x6 mm, 36-QFN
6x6 mm, 36-QFN
6x6 mm, 36-QFN
6x6 mm, 36-QFN
6x6 mm, 36-QFN
6x6 mm, 36-QFN
6x6 mm, 36-QFN
14x14 mm, 100-TQFP
14x14 mm, 100-TQFP
14x14 mm, 100-TQFP
14x14 mm, 100-TQFP
Si53xx Any-Rate Clock Replaces Traditional VCXO/VCSO Based PLLs
Silicon Labs Approach
Traditional Approach
Si53xx Any-Rate Precision Clock
VCXO/VCSO-Based PLLs
• Fully integrated IC; replaces VCXO/VCSO-based PLLs
• Same device can be re-used for all frequencies without
component changes
• Can be easily reconfigured to support multi-rate applications
• Fully integrated PLL
• Short, consistent lead times as short as four weeks
• PLL implemented with discrete VCXO or VCSOs
• New PLL design and components required
for each frequency
• Multi-rate applications require multiple VCXOs
• Requires analog PLL design expertise
• Long, unpredictable lead times up to 14 weeks
Synchronous Ethernet Simplifies Timing Architectures
Silicon Labs’ Si5315 combines integration, frequency flexibility, jitter performance, and ease of use to dramatically simplify line
card timing architectures for SyncE and telecom applications. The Si5315 is the only SyncE clock IC on the market to support 10G
LAN (156.25 MHz), 10G WAN (155.52 MHz) and 10G line encoding, 66/64 (161.13/644.53 MHz). In addition, the Si5315
supports generation of SONET OC-3/12/48/192 and T1/E1/PDH clocks for legacy telecom infrastructure applications.
Innovative DSPLL® Technology
Silicon Labs’ proprietary DSPLL technology
uses digital signal processing (DSP)
techniques to move traditionally analog PLL
functions into the digital domain. The Si53xx
integrates a high-performance, low phase
noise VCO, loop filter, phase detector,
dividers, input clock selection mux, and
flexible output buffers on-chip, replacing
discrete analog PLL implementations.
DSPLL
Optional Crystal/Reference Clock
(required for jitter attenuation)
Input
Clock
N3
Phase
Detector
A/D
Digital
n
Signal
Processing
N1
Output
Clock
DVCO
N2
DSPLLsim Software
DSPLLsim is a PC-based software utility used
to assist users with frequency planning, loop
bandwidth selection, and overall device
configuration. DSPLLsim can be used in
standalone mode or can be used to directly
control the Si53xx in the device evaluation
kit. DSPLLsim provides a listing of pin/
register settings based on the user-specified
configuration, significantly simplifying PLL
design.
Clock and Data Recovery and Serializer/Deserializer ICs
• 2.5/10 Gbps transceivers with integrated DSPLL technology eliminates external jitter attenuation circuitry
Part Number
Description
Si5010
OC-3/12/STM-1/4 SONET/SDH CDR, 2.5 V
Si5013
OC-3/12/STM-1/4 SONET/SDH CDR, with limiting amp, 3.3 V
Si5017
OC-48/STM-16 SONET/SDH CDR, with limiting amp, 3.3 V
Si5018
OC-48/STM-16 SONET/SDH CDR, 2.5 V
Si5020
OC-3/12/48 SONET/SDH, GbE CDR, 2.5 V
Si5023
OC-3/12/48 SONET/SDH, GbE CDR with limiting amp, 3.3 V
Si5040
OC-192/STM-64/10 GbE, Dual CDR XFP Transceiver, 9.9 to 11.4 Gbps
Si5100
OC-48/STM-16 SONET/SDH 1:16 Transceiver, 2.5 to 2.7 Gbps
Si5110
OC-48/STM-16 SONET/SDH 1:4 Transceiver, 2.5 to 2.7 Gbps
SONET/SDH Precision Clocks
• Jitter generation less than 0.3 ps rms (typ 50 kHz to 80 MHz)
• Forward and reverse FEC clock scaling; selectable loop filter bandwidths as low as 800 Hz
Part Number
Description
Si5310
OC-3/OC-12 clock multiplier/regenerator, 155 MHz, 622 MHz
Si5320/21
OC-48/OC-192/10GbE/10GFC/G.709 OTU-1/OTU-2 clock multiplier/jitter attenuator, 19 MHz to 2.5 GHz output, G.709 FEC and 66/64 scaling
Si5364
OC-48/OC-192 clock multiplier/jitter attenuator, auto hitless switching, four outputs at 19 MHz,155 MHz or 622 MHz
Crystal-Based XO/VCXOs
• Jitter generation <0.3 ps rms typical 12 kHz to 20 MHz (Si53x, 55x, 57x)
• Short lead times: two weeks for samples, four weeks for production
Part Number
Type
Control
Frequency
Frequency Range
Stability Options (ppm)
Kv Options (ppm/V)
XO
XO
XO
VCXO
VCXO
VCXO
Pin
Pin
Pin
Pin
Pin
Pin
Single
Dual
Quad
Single
Dual
Quad
10 to 945 MHz
970 to 1134 MHz
1213 to 1417 MHz
±7
±20
±50
N/A
N/A
N/A
10 to 945 MHz
970 to 1134 MHz
1213 to 1417 MHz
±20
±50
±100
33, 45, 90, 135,
180, 356
Si570
XO
I 2C
Any-Rate Programmable
Si571
VCXO
I 2C
Any-Rate Programmable
Si590/1
Si595
XO
VCXO
Pin
Pin
Single
Single
Si530/1
Si532/3
Si534
Si550
Si552
Si554
±20
±50
±20
±50
±100
±50
±100
10 to 280 MHz
10 to 810 MHz
10 to 1417 MHz
10 to 945 MHz
Industry’s Only Quad and Any-Rate Frequency XO/VCXOs
Package
5x7
5x7
5x7
5x7
5x7
5x7
mm
mm
mm
mm
mm
mm
6-pad
6-pad
8-pad
6-pad
6-pad
8-pad
N/A
5x7 mm 8-pad
33, 45, 90, 135,
180, 356
5x7 mm 8-pad
N/A
45, 90, 135, 180
5x7 mm 6-pad
5x7 mm 6-pad
Built to Order Samples
Si534 XO/Si554 VCXO
• Eliminates multiple oscillators,
reduces system cost
• Simplifies BOM and saves board
space and inventory
Silicon Labs offers an
2 WEEK
easy-to-use web utility
LEAD
to build and configure
TIMES
the right XO/VCXO
for your application.
Samples will ship in less
than two weeks.
www.silabs.com/BuyXO
Silicon Oscillators
• Industry’s highest stability, all-silicon oscillator
• Pin-compatible with quartz and MEMS 3.2x5 mm XOs
Part Number
Type
Frequency
Temperature Stability
Total Stability (ppm)*
Output Format
Package
Si500S
XO
0.9 to 200
±10 ppm typ
±150
3.2x4 mm 4-pad
Si500D
XO
0.9 to 200
±10 ppm typ
±150
CMOS, SSTL
LVPECL, LVDS, HCSL, dual output CMOS,
diff CMOS, dual output SSTL, diff SSTL
o
o
3.2x4 mm 6-pad
o
*Inclusive of: initial frequency accuracy at 25 C, operating temperature range, supply voltage change, output load change, first year aging at 25 C, 260 C reflow, shock and vibration
Traditional Approach
Silicon Labs Approach
Si500 Silicon Oscillator
Quartz XO
• Synthesizes all frequencies from a single CMOS oscillator
• Factory-programmable to any frequency from 0.9 to 200 MHz
• Standard IC plastic packaging
• Short lead times: two weeks samples, four weeks production
• Unique resonator required for each output frequency
• Custom frequencies require fabrication/qualification of new resonator
• Costly ceramic or metal hermetically sealed package
• Complex manufacturing flow causes long, unpredictable lead times
Pricing and availability:
www.silabs.com/BuySample
www.silabs.com
© 2009, Silicon Laboratories Inc., DSPLL, ProSLIC, Silicon Laboratories and the Silicon Labs logo are trademarks of Silicon Laboratories Inc. All
other product or service names are the property of their perspective owners. CI, 5000, Jan. 09, Rev A SEL-CLK-2009A
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