LOW POWER HYBRID CMOS-NEMS FOR MICROELECTRONICS:
IMPLEMENTATION IN IMPLANTABLE PACEMAKER
by
SAMARTH ARORA
Submitted in partial fulfillment of the requirements
For the degree of Master of Science
Thesis Advisor: Prof. Daniel G. Saab
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
AUGUST 2011
CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the thesis/dissertation of
____________________Samarth Arora_____________________
candidate for the _____Master of Science_____________degree *.
(signed)______________Daniel G. Saab____________________
(chair of the committee)
____________Marc Buchner______________________
____________Francis "Frank" Merat________________
______________________________________________
______________________________________________
______________________________________________
(date) _______07/13/2011_______
*We also certify that written approval has been obtained for any
proprietary material contained therein.
1
Table of Contents
1
2
3
Introduction
1.1
Motivation ................................................................................................1
1.2
Thesis Outline ..........................................................................................3
CMOS Scaling and Design Trends
2.1
Introduction ..............................................................................................5
2.2
Moore‟s Law ............................................................................................7
2.3
Power: switching and leakage ..................................................................7
2.3.1
Static Dissipation ......................................................................8
2.3.2
Dynamic Dissipation .................................................................8
2.4
Power Supply and Threshold Voltage .....................................................9
2.5
Gate Oxide Tunneling ..............................................................................9
2.6
Summary ................................................................................................10
NEMS Background
3.1
Introduction ............................................................................................12
3.2
Key Points: NEMS Switch.....................................................................13
3.3
Principle of Operation ............................................................................14
3.4
NEMS Device Characteristics ...............................................................15
3.5
Reliability issues in NEMS ....................................................................18
3.5.1
Stiction ....................................................................................19
3.5.2
Wear ........................................................................................20
i
4
3.6
NEM Switch Design ..............................................................................20
3.7
Fabrication and Characterization of NEMS ...........................................22
3.8
Digital Design of Nano-Electro Mechanical Switches (NEMS) ...........24
3.9
Description of NNEM and PNEM configuration ..................................25
3.10
Design of Basic Logic Gates using CNEMS .........................................25
3.5.1
CNEMS Inverter .....................................................................26
3.5.2
NAND Gate ............................................................................27
3.5.3
NOR Gate................................................................................29
3.5.4
AND Gate ...............................................................................30
3.5.5
OR Gate ..................................................................................32
3.5.6
Buffer ......................................................................................33
3.5.7
Memory Design using NEMS .................................................34
3.11
Circuit Simulator of CNEMS.................................................................36
3.12
Design of Digital CNEMS circuit ..........................................................36
3.13
Power Dissipation in NEM Switch ........................................................37
3.14
Power Advantages in CNEMS...............................................................38
3.15
Summary ................................................................................................40
Cardiac Pacing
4.1
Introduction ............................................................................................41
4.2
Overview of Heart Function ..................................................................41
4.3
Implantable Pacemaker ..........................................................................44
4.4
Pacemaker System Overview ................................................................46
4.5
Summary ................................................................................................48
ii
5
6
Literature Review
5.1
Pacemaker Sense Amplifier ...................................................................50
5.2
Unipolar and Bipolar Sensing ................................................................52
5.1
Switched Capacitor Circuits ..................................................................52
Design of Low Power Hybrid CMOS Nano-Electro-Mechanical (NEM) Switches
for Implantable Pacemakers
6.1
Introduction ............................................................................................55
6.2
Design of Switched-Capacitor Bandpass Filters....................................56
6.3
6.4
7
3.5.1
Filter Characteristics ...............................................................57
3.5.2
The Pacemaker Filter ..............................................................59
3.5.3
Results .....................................................................................62
Design of Microcontroller Based Pacemaker System ...........................63
6.3.1
High Level Software Design ...................................................64
6.3.2
Schematic and Symbol of Pacemaker Microcontroller ..........67
6.3.3
Results .....................................................................................68
Summary ................................................................................................70
Conclusions ..........................................................................................................72
iii
List of Tables
3.1
Inverter Operation using CNEMS ...........................................................................27
3.2
NAND Gate Operation using CNEMS ....................................................................28
3.3
NOR Gate Operation using CNEMS .......................................................................30
3.4
AND Gate Operation using CNEMS .......................................................................31
3.5
OR Gate Operation using CNEMS ...........................................................................32
3.6
Buffer Operation using CNEMS ..............................................................................34
6.1
Cardiac Filter Characteristics ...................................................................................62
6.2
Pacemaker Microcontroller Characteristics .............................................................69
iv
List of Figures
1.1
CMOS technology scaling trend and its impact on subthreshold leakage current
(Source: ITRS [1]) .....................................................................................................2
2.1
Gate Oxide vs. Technology [5] ..................................................................................5
2.2
Igate and subthreshold leakage vs. technology [5] .....................................................6
2.3
Moore‟s Law. Source: Intel .......................................................................................7
2.4
Gate oxide tunneling current vs. Gate voltage [6] ...................................................10
3.1
Cross sectional view of CNEMS [4]........................................................................21
3.2
Top view of CNEMS [4]..........................................................................................21
3.3
Fabrication process for metallic Nano-Electro-Mechanical Switch [3] ..................23
3.4
Four-terminal NEMS switch configuration (a) Schematic for NNEMS (b)
Schematic for PNEMS [4] .......................................................................................25
3.5
CNEMS Inverter [4] ................................................................................................27
3.6
NAND Gate using CNEMS [4] ..............................................................................28
3.7
NOR Gate using CNEMS [4] .................................................................................29
3.8
AND Gate using CNEMS [4] ..................................................................................31
3.9
OR Gate using CNEMS [4] .....................................................................................32
3.10 CNEMS Buffer [4]...................................................................................................33
3.11 CMOS D-latch [4]....................................................................................................35
3.12 CNEMS D-latch [4] .................................................................................................35
3.13 Power Advantages (Stand-by mode): Data from [3] ...............................................39
3.14 Power Advantages (Active mode): Data from [3] ...................................................39
v
4.1
Human Heart [10] ....................................................................................................42
4.2
ECG Waveform [12] ................................................................................................43
4.3
Basic Pacemaker functional block diagram [11] .....................................................44
4.4
Placement of pacemaker leads [13] .........................................................................45
4.5
Types of Pacemakers [13]........................................................................................46
4.6
Implantable Pacemaker Block Diagram [14] ...........................................................47
5.1
Components of Pacemaker Sense Amplifier [15]....................................................51
5.2
Unipolar and Bipolar Sensing [15] ..........................................................................52
5.3
Switched-capacitor circuit [15] ................................................................................54
6.1
Human Heart and Implantable Pacemaker [17] .......................................................56
6.2
ECG (Electrocardiogram) waveform [12] ...............................................................57
6.3
Fully-Differential Double Sample Rate Two Op-Amp Bandpass Filter [16] ..........60
6.4
Fully-Differential Operational Amplifier [16] .........................................................61
6.5
Power Advantages of Hybrid CMOS-NEM Switches for Bandpass Filter .............63
6.6
Flow Chart of Simple Pacemaker [18].....................................................................66
6.7
Schematic of Pacemaker Microcontroller ................................................................67
6.8
Symbol of Pacemaker Microcontroller ....................................................................67
6.9
Output Waveform of Pacemaker Microcontroller ...................................................68
6.10
Output Waveform of Pacemaker Microcontroller (Magnified View) ...................69
6.11
Power Advantages of Hybrid CMOS-NEMS for Pacemaker Microcontroller .....70
vi
Acknowledgements
I would like to express my appreciation towards my advisor Prof. Daniel G Saab for his
valuable suggestions and feedback in pursuing this work. His wide ranging knowledge
has been essential in dealing with challenging aspects of work. It has been a great
experience working with him. As a person, his constant encouragement and support
provided me with strong motivation which helped me to accomplish this work.
I express sincere thanks to Prof. Marc Buchner and Prof. Francis Merat for their valuable
support in the capacity of members of defense committee. I would like to thank Prof.
Massood Tabib-Azar for providing me with required inputs, essential for completing this
work.
Finally, I would like to recognize the encouragement and motivation that I have received
from my parents and friends during this endeavor.
vii
LOW POWER HYBRID CMOS-CNEMS IMPLANTABLE PACEMAKER
Abstract
By
SAMARTH ARORA
Low power consumption is a primary goal in biomedical pacemaker design where it is
crucial to increase the battery life of the device. Implantable pacemaker is a real time
embedded system which is surgically placed in the body of the patient and is used to
treat arrhythmia. We present a low power hybrid CMOS-NEMS implementation of the
bandpass filter used within sense system of an implantable pacemaker and the NEMS
Pacemaker Microcontroller. The approach is based on replacing the CMOS switches
with NEMS switches in the hybrid CMOS-NEMS implementation. NEMS (NanoElectromechanical Switches) offers unique characteristics in terms of turn-on voltage (≈
1.5V), switching time (≈ 1ns), virtually zero leakage current, infinite ON current, and a
small footprint size which enables low-power design. Our experimental results reveal
significant power reduction for the hybrid CMOS-NEMS implementation in pacemakers.
viii
Chapter 1:
Introduction
1.1 Motivation
For the past few years, CMOS technology has become very successful because of the
scalability of MOSFET transistor. Potential applied at the gate controls the flow of
current from source to the drain, together with the availability of complementary NMOS
and PMOS, is the underlying basis for the success of CMOS technology. As the process
is continuing to scale down, the CMOS technology is facing serious challenges in terms
of power consumption and variability. Scale down of technology into the deep nanometer
range has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Leakage
current has become a big portion of the total power consumption which under normal
operating conditions, contributes to 30-50% of the overall power consumption in a
device. Sub-threshold leakage power has become a significant fraction of the total power
which arises due to the threshold voltage scaling. The trend is forecasted by the
International Technology Roadmap for Semiconductors (ITRS) [1] is shown in Fig 1.1.
1
Fig 1.1: CMOS technology scaling trend and its impact on subthreshold leakage current
(Source: ITRS [1])
It is necessary to overcome the excess power dissipation in CMOS technology especially
in portable embedded system applications where the energy efficiency, cooling system
and changes in the environment are more important than the speed [2]. The increase in
the costs associated with the scaling of the MOS transistors has motivated a search for
alternative approaches for the IC design. One of the consequences of miniaturization is
that Nano-Electro-Mechanical Switches (NEMS) have started to find a place in
technology.
Nano-Electro-Mechanical Switch (NEMS) offers novel characteristics in terms of
virtually zero leakage current, low operating voltage (~1-1.2 V), high switching speed
(~1-1.4 ns), and nanometer footprint size [3]. Furthermore, this switch can easily be
fabricated and designed by using the modified CMOS fabrication process and equipment.
2
These features make NEM Switch a good candidate to address the energy efficiency
problem in the Nanometer-CMOS technology without extreme cost [2].
1.2 Thesis Outline
Low power consumption is a central priority in the battery operated medical implantable
devices, particularly cardiac pacemakers. Due to the fact that Silicon-based CMOS
technology is facing challenges in terms of power dissipation and variability, we have
introduced Nano-Electro-Mechanical Switch (NEMS) that offers several novel
characteristics. These NEM Switches can easily be hybridized with CMOS at the
metallization level or device level to manage the leakage current and energy efficiency
issues [3]. NEM Switches with its almost ideal switching characteristics and virtually
zero leakage current is explored as a good candidate for implementing in implantable
pacemakers.
In our research work, NEM Switch device characteristics have been investigated and
have designed a hybrid CMOS-NEMS circuit for an implantable pacemaker. The Hybrid
CMOS-NEMS implementation is achieved by replacing the CMOS switches with the
NEM switches. To demonstrate the power advantage of the Hybrid CMOS-NEMS
technology in implementing bandpass filter for sense system of the implantable
pacemaker, circuit simulation experiments were conducted using HSPICE and SPICE
NEMS circuit simulator model [2]. We also designed the microcontroller for a simple
pacemaker using Verilog Hardware Description Language for the Hybrid CMOS/ NEMS
technology. Our main focus of thesis is to depict the power advantages in the NEMS
3
based design as compared to the CMOS based design in an implantable pacemaker.
Hybridization of NEM Switch and Silicon based CMOS devices has shown a theoretical
feasibility for power management.
Though primarily addressed to the pacemaker system in our research work, these
techniques can be used for other applications such as scaled VLSI, programming
interconnect in FPGA‟s, sensors, aerospace applications, in harsh environment where
CMOS cannot operate due to high temperature or radiation [3, 4].
4
Chapter 2:
CMOS Scaling and Design Trends
2.1 Introduction
The down scaling of the process technology where the feature size is in nanometer
requires a change in the design approach to cope with the increased process variation,
exacerbated physical effects and interconnect processing challenges. Scaling of the MOS
transistors causes problems including gate oxide tunneling, threshold voltage constraints
and the power supply. The leakage current in nanometer regime increases which raises
the stand-by power of the circuit. The scaling of the gate oxide (Fig 2.1) also results in
the increased tunneling current [5].
Fig 2.1: Gate Oxide vs. Technology [5]
5
As the technology continues to shrink these parameters also increases as shown in Fig
2.2.
Fig 2.2: Igate and subthreshold leakage vs. technology [5]
The downsizing of the feature size has increased the density and reduced the cost per
function but has resulted in an increase in the stand-by power of the chip [6]. The two
major properties that hinder an ideal scaling are the drift current and the diffusion current.
Drift current varies proportionally with the horizontal and vertical scaling in both linear
and the saturation regions whereas, the diffusion current varies exponentially in the
subthreshold region. The voltage is not scaled linearly as compared to the other
parameters in the subthreshold region which increases the electric field. This results in
decreased mobility of the charge carriers due to the velocity saturation and reduces
improvement on on-current.
6
2.2 Moore’s Law
Moore's law describes a long-term trend in the history of computing and explains the
theory of device scaling from the present generation gate length to the next generation
gate length. Moore‟s law states “The number of transistors that can be placed
inexpensively on an integrated circuit doubles approximately every two years”. This
exponential improvement has dramatically enhanced the impact of digital electronics as
shown in Fig 2.3.
Fig 2.3: Moore‟s Law. Source: Intel
2.3 Power: switching and leakage
With the reduction in the feature size, the power consumption per unit area of the chip
has risen tremendously. Broadly classifying, power dissipation in CMOS circuits can be
divided into two categories: Static dissipation and Dynamic Dissipation.
7
2.3.1 Static dissipation

Sub threshold condition when the transistors are off

Tunneling current through gate oxide

Leakage current through reverse biased diodes

Contention current in ratioed circuit
2.3.2 Dynamic Dissipation
 Charging and discharging of load capacitances
CMOS circuits dissipate power whenever they are switched by charging the load
capacitances which includes gate and wire capacitance, but also drain and some
source capacitances. In one complete cycle of CMOS logic, current flows to the
load capacitance to charge it from VDD and then during the discharge the current
flows from the charged load capacitance to ground. Therefore, a total of
Q=CLVDD is thus transferred from VDD to ground in one cycle. Thus, the switching
power dissipated by a CMOS device is P = CV2f.
 Short circuit power dissipation
Due to the rise time and the fall time for both pMOS and nMOS, during transition,
both the transistors will be on for a small period of time in which current flows
directly from VDD to ground, hence creating a short circuit current. With the
increase in rise and fall time of the transistors, short circuit power dissipation
increases.
8
2.4 Power Supply and Threshold Voltage
The gate oxide is scaled more aggressively than power supply and the threshold voltage
which leads to a high electric field across the oxide. This affects the chip‟s reliability
since this leads to hot electron injection in the gate oxide and the electron migration as
described in [6]. The current does not drop to zero below the threshold voltage (VT) but
exponentially KT/q and is not dependent on the channel and the power supply. The offcurrent in the transistor depends upon the gate capacitance (Cox) and inversely
proportional to the thickness of the gate oxide (tox). Thus the off-current changes with the
technology scaling. The device performance can be improved with reduced threshold
voltage and supply voltage trade off with power consumption. Many circuit leakage
techniques are used to reduce the stand-by power of the device which will be explained in
more detail in the following chapters.
2.5 Gate Oxide Tunneling
The gate oxide thickness should be scaled same as the gate length to reduce the short
channel effects [6]. Gate tunneling leakage becomes dominant than other leakages in the
transistor when the gate oxide thickness is reached to a certain limit. Tunneling currents
for various gate oxide thicknesses is shown in Fig 2.4 below.
9
Fig 2.4: Gate oxide tunneling current vs. Gate voltage [6]
The off-current due to the increased gate leakage current is negligible as compared to the
on-current but it dominates in the stand-by mode. The channel is doped with non-uniform
doping concentration in order to reduce the subthreshold leakage and the gate oxide
leakage [6].
2.6 Summary
This chapter provided detailed explanation about the CMOS technology in terms of
scaling paradigms and the limitations of CMOS technology in the nanometer regime.
With the technology scaling and the advancement into nanometer region, scaling-related
issues become key factors. These issues may include leakage, noise, reliability, power
10
and interconnect delays. These problems have significantly complicated the design
process but have paved a way to look at the new design technologies and trends which
will be discussed in the proceeding chapters.
11
Chapter 3:
NEMS background
3.1 Introduction
Nano-Electro-Mechanical Switches (NEMS) are the gate-controlled on/off switches
characterized with virtually zero leakage current, ~1 Volt operational voltage, ~1ns
switching speed, and nanometer-scale footprint size [3]. Continuous scaling of the CMOS
technology has paved way for NEM Switches which holds great promise for a variety of
scientific and technological applications. Idle power consumption is an important
parameter in nanometer-scale CMOS technology where the excessive power dissipation
may lead to heat generation and reliability issues in the device. The NEM Switches not
only address some of these limitations but can also be dropped in and hybridized with
CMOS at the metallization level or device level to manage the power and leakage
current. Potential areas for application of NEMS include biomedical devices where it is
desirable to reduce the leakage power to prolong the implanted battery life, actuators,
sensors, resonators, switches, aerospace, programming interconnect in FPGA‟s and other
applications in harsh environment where CMOS cannot operate due to high temperature
or radiation [3]. In our research work, NEMS application in the design of bandpass filter
(within the sense system of a pacemaker) and pacemaker microcontroller have been
explored.
12
The p-channel and n-channel switches in the form of complementary NEMS (CNEMS)
are similar to the CMOS. A strong understanding of unforeseen physics concepts that
affect the operation of NEM Switches is required as described in detail in [3]. For
example, Van der Waal and tunneling currents play a major role in the design of NEM
Switches. According to International Technology Roadmap for Semiconductors (ITRS
[1]), CMOS technology for 2015 would be beyond 22 nm (a physical gate length of 10
nm, and a power dissipation of approximately 93 Watt/cm2). There is an immediate need
to migrate from pure down-scaling to new functionality and combined technology-system
innovation for a proper management of power dissipation for these devices. Later in this
chapter the design of NEMS functional devices is discussed where a single device
operates as an entire logic gate.
3.2 Key Points: NEM Switch
Following are the observed potential advantages of Nano-Electro-Mechanical Switches
(NEMS) compared with nano-scale CMOS:
1. Zero Leakage
2. Infinite sub-threshold slope
3. Low operating voltage
4. Fast switching speed
5. Nanometer-scale footprint
6. Compatibility with CMOS in their functionality, structure and fabrication
7. CNEMS can readily use the design methods, circuits, architectures and design
automation techniques from CMOS
13
8. Reliability in terms of its functionality and the durability
9. Low cost
3.3 Principle of Operation
The most common structure for the NEM device consists of an active part (movable
electrode) and the fixed part (fixed electrodes) which are subjected to the electrostatic
force of attraction to perform the desired switching action. The interesting properties of
the NEM device typically arise from the behavior of the active parts (in general,
cantilevers) which makes an abrupt contact with the fixed part to turn ON the switch
when sufficient potential difference between the active and the fixed parts is applied.
Due to this applied potential difference between the cantilever and the fixed part, the
electrostatic force of attraction is resulted which forces the switch to turn ON. In order to
turn the switch OFF from its current state of ON, the potential difference is reduced
which abruptly pulls the cantilever off the contact. The voltage which is required to turn
ON and OFF the device is called pull-in voltage and pull-out voltage respectively.
In the switching mode of operation, a NEM Switch performs its functions by the
displacement of the active part under the influence of applied electrostatic force of
attraction as discussed above. Depending on the contact type, the NEM Switches can be
classified into ohmic and capacitive switches [3]. In the ohmic contact switch (also called
resistive switch), a direct connection between the active and passive part is formed when
the switch is closed. In general, the architecture of the ohmic switch is of the form of the
active part-gap-passive part. In the capacitive switch, the insulating layer between the
14
active part and the static part acts as a capacitor when the switch is closed. In general, the
architecture of the capacitive switch is of the form of an active part-gap-insulator-passive
part.
3.4 NEMS Device Characteristics

The device characteristics of a NEM Switch are based on the device dimensions,
materials and the structure. NEMS is a multi-physics device whose physical
characteristics, phenomenon and the physical quantities must be understood in
order to design and model the electrostatic NEM Switches [3]. The structure of
the NEM Switch movable part is cantilever beam or bridge whose dimensions
Length (L) of the active electrode, Width (W) of the active electrode and Height
(H) of the active electrode and the gap between the NEMS electrodes. The
materials of the NEM Switch are the materials for the movable electrode, fixed
electrode and the dielectric layer between the electrodes. The important material
properties that have a significant impact on the device switching characteristics
are: Young‟s modulus (E) of the moving electrode, conductivity (σ) of the
material of electrode and the emitter work function (φ) of the material of electrode
and the permittivity (ε) of the dielectric material.

When potential difference is applied between the NEMS electrodes the, the
attractive force turns the switch ON whereas, the repulsive force turns the switch
OFF. In a NEMS device, the attractive forces are electrostatic force,
intermolecular force (such as Van der Waals force and Casimir force) and the
15
contact force [4]. Whereas, the damping force, kinetic force and elastic force tend
to turn the switch OFF because of their repulsive nature.

The operating voltages for a NEMS device are: pull-in voltage and pull-out
voltage. Pull-in voltage is the minimum voltage which when applied brings the
electrodes of the NEM Switch forming a contact between them which turns the
switch ON. On the other side, Pull-out voltage is the minimum voltage which
when applied between the switch‟s electrodes turn the switch OFF. The operating
voltages of the NEMS device are a function of the physical quantities of the
device which includes its structure, dimensions, and material. The physical
phenomena affecting the pull-in voltage are electrostatic force, elastic force, and
intermolecular forces. The physical phenomena affecting the pull-out voltage are
the same forces that determined the pull-in voltage with an of addition contact
force.

For a cantilever beam structure, E is the Young„s modulus of the movable part of
the electrode material, υ is the Poisson ratio of the movable part of the electrode
material, ε is the permittivity of vacuum, H is the thickness of the movable part,
g0 is the initial gap, and L is the length of the movable part of the device and c1
and c2 are the device constants. Thus, equation (3.1) computes the pull-in voltage
as a function of the dimensions, Young„s modulus and the structure. The pull-in
voltage is directly proportional to the gap and the thickness of the NEM Switch
16
and is inversely proportional to the length of the movable part of the NEM
Switch.
√

(3.1)
For a NEM Switch, switching time is defined as the amount of time to change the
state of the device from OFF to ON or from ON to OFF. Switching time is the
function of the device physical quantities, device dimensions, material used and
the applied voltage. The switching time of a NEMS switch can be described by
the equation (3.2), where Vpin is the pull-in voltage, Vs (Vs > Vpin) is the applied
voltage and ωo is the angular resonant frequency. Also, the resonant frequency
can be described by the equation (3.3), where E is the young‟s modulus, W is the
width of the movable electrode, L is the length of the movable electrode, ρ is the
material density for the moving electrode.
(
)√
(3.2)
√

(3.3)
Device characteristics in terms of ON resistance and OFF resistance are described
in this section. ON resistance is defined as the resistance offered by the contact
area between the electrodes when the switch is in the ON state. In the Ohmic
switching of the NEMS switch, the contact resistance results in making the
electrical connection between the electrical connections. For the estimation the
17
ON resistance of the NEM Switch, electron transport mechanism is required
(ballistic transport, quasi-ballistic transport, diffusive transport). OFF resistance
of the NEM Switch is determined by the tunneling current that flows between the
flows between the electrodes of the NEM Switch when the switch in in the OFF
state. The tunneling current of the OFF state is calculated by the FowlerNordheim method and is shown in the equations (3.4), (3.5) and (3.6).
√
∫
√
(3.4)
(3.5)
(3.6)
Where A is the overlapping area of the electrodes, E is the electric field
perpendicular to the overlapping surface of NEMS electrode and J is the current
density, φ is the emitter work function.
3.5 Reliability issues in NEMS
In this section, the reliability issues affecting the NEMS are investigated which should be
considered during the device designing and fabrication. The reliability of the NEM
Switch is affected by: stiction and wear.
18
3.5.1 Stiction
Stiction in the Nano-Electro-Mechanical Switches (NEMS) has been a major failure
mode and deserves a careful study. Stiction is a term for an unintentional adhesion of the
movable mechanical electrode to the fixed/movable electrode of the switch. The
experimental observation shows that stiction occurs when the restoring forces are not able
to overcome interracial forces such as capillary, van der Waals, Casimir forces,
electrostatic and other kinds of chemical forces [7]. In general, the problem of stiction is
divided into two categories: manufacturing (release-related) stiction and operational (inuse) stiction. The manufacturing stiction occurs during the production process and is
caused by the capillary forces in the fabrication process while removing the sacrificial
layer. Methods to overcome release-related (manufacturing) stiction are: (1) Texturing
surfaces to reduce the geometrical contact area using the Bumps (Asperities) which
reduces the contact area to the dimensions smaller than the resolution of the
photolithography, or using side wall spacers [8]. (2) Surface modification to suppress the
water bridging causing the capillary force between mechanical and stationary structures of
the switch by using hydrophilic materials (Ti, Al2O3). The in-use (operational) stiction occurs
when the switch is in operation and performing a specific application. In operational stiction,
even after the removal of the external force and voltage potential, the elastic forces are not
able to overcome the adhesion forces. Methods to reduce the operational stiction include
proper design of ohmic switches in order to avoid the stiction during the fabrication and
operation stage of the NEM Switches.
19
3.5.2 Wear
By definition, wear is the erosion of a material from a solid surface by the action of
another solid component. The dominant Wear problem is related to the mechanical wear
such as pitting and hardening which results from repeated impact of two metal contacts
[9]. Factors affecting ohmic NEM Switch durability include contact bouncing motion,
contact area, damping which leads to the degradation of the switch contacts. Whereas, the
capacitive switches suffer from dielectric charging issues.
3.6 NEM Switch Design
The structure of the CNEMS used in this research work consists of a metallic switching
device which can be easily integrated with the CMOS devices. CNEMS logic and
sequential circuits can be realized by using same methods for design and fabrication as
for the CMOS. The CNEMS is configured into N-channel (NNEMS) and P-channel
(PNEMS) similar to the NMOS and PMOS in the CMOS, enabling the realization of
logic gates in Complementary (CNEMS) logic [4].
Fig.3.1 and Fig.3.2 shows the cross-sectional view and the top view respectively of a four
terminal metallic NEM switch which has Gate (G), Source (S), Drain (D) and Body (B)
terminals. The Body terminal is also called the Cantilever terminal which is a moving
terminal while the Gate, Source and Drain terminals are fixed.
20
Fig 3.1: Cross sectional view of CNEMS [4]
Fig 3.2: Top view of CNEMS [4]
To address the CMOS power consumption a low power four terminal metallic NanoElectro-Mechanical Switch (NEMS) is discussed here. CNEMS consists of a conducting
metallic Nickel which has a large Young‟s modulus attached to the Body (or, Cantilever)
via an insulating gate oxide. The large Young‟s modulus of Nickel enables it to withstand
high switching cycle. Other terminals called the Gate, Drain and Source are all metallic
terminals and remain fixed. Contact resistance of the switch between the Body and
Source or Body and Drain is approximately 90 ohms [4]. When the voltage difference
applied (Vgb) between the gate terminal and the body terminal is less than threshold
21
voltage (Vth), the metallic Nickel makes a connection between the Source and the Drain.
In this state, the switch is said to be conducting in nature since there is a low resistance
path between the Source and Drain terminals. When the applied voltage difference (Vgb)
is greater than the threshold voltage (Vth), the electrostatic force overcomes the opposing
elastic force which results in pulling off metallic Nickel connection, towards Gate. In this
state, the switch is said to be in an OFF state since there is no conducting path between
Source and Drain. It is important to note that when the NEM switch is in the OFF state,
the leakage current (tunneling current and surface leakage currents) can be minimized by
surface coating and plasma etching during the fabrication process. Current of the NEM
switch in the OFF state is virtually zero. Working of CNEMS is better explained in 3.8.
3.7 Fabrication and Characterization of NEMS
The fabrication technology for Nano Electro-Mechanical Switches (NEMS) is similar to
the other semiconductor devices. As already discussed, NEM Switches can be fabricated
in the existing semiconductor foundries. Therefore, the ability to miniaturize large
mechanical machines and devices to chip-scale with cost effective processes with the use
of existing CMOS technology/ equipment gives NEMS technology incredible power. In
this section, the fabrication of NEMS is being explained. Fig.3.3 describes the fabrication
process which is briefly explained in the following steps:
22
Fig 3.3: Fabrication process for metallic Nano-Electro-Mechanical Switch [3]
Step (a): N-type Silicon Wafer is cleaned using the RCA-1 process.
Step (b): 400nm Silicon nitride film is deposited by using low pressure chemical vapor
deposition (LPCVD).
23
Step (c): Next, 1.5μm of polysilicon was deposited using LPCVD and doped with
phosphorous from TP-470 dopant source at 1050ºC. In some NEM devices the
polysilicon layer was replaced with sputtered tungsten or platinum.
Step (d): In this step, photolithography is performed along with the reactive ion etching
(RIE) in inductive coupled plasma (ICP) to pattern the fixed parts of the device.
Step (e): Silicon dioxide layer with thickness of 8nm is deposited on the micro patterned
Polysilicon by thermal oxidation.
Step (f): Moving parts themselves were composed of polysilicon, sputtered nickel and
tungsten. In this step, 330 nm of Nickel film is deposited on the 20 nm adhesion layer of
Cr by sputtering.
Step (g): Planarization and polishing of the Ni deposited wafer is done using the
chemical mechanical polishing (CMP) with FCN-560 slurry.
Step (h): In this step, the sacrificial oxide layer and the ALD layer is etched by buffered
oxide etchant and aluminum etchants which do not attack tungsten.
3.8 Digital Design of Nano Electro-Mechanical Switches (NEMS)
Nano Electro-Mechanical Switches (NEMS) can be configured and designed in a similar
fashion as CMOS. The N-channel (NNEMS) and P-channel (PNEMS) are realized by
utilizing CMOS design concepts and methodologies. As already discussed, a four
terminal metallic NEM switch has Gate (G), Source (S), Drain (D) and Body (B) (also
called the Cantilever) terminals. The Body terminal is moving while the Gate, Source and
Drain terminals are fixed. Depending upon the potential difference between the Gate and
the Body terminals, the NEM Switch is either in an ON state (Source is connected to the
24
Drain) or in an OFF state (Source is not connected to the Drain). Both, NNEMS and
PNEMS are bidirectional switches and are used in in the design of complementary logic
as is in synonymous with NMOS and PMOS in CMOS logic.
3.9 Description of NNEM and PNEM configuration
NNEMS (also called N-channel) and PNEMS (also called P-channel) are realized by
utilizing CMOS design technologies and methodologies. The schematic of NNEMS and
PNEMS are shown in Fig 3.4 (a) and (b) respectively. As shown in these figures, In the
PNEMS configuration, the Source and the Body are connected to the VDD (Supply
Voltage). While, in the NNEMS configuration, the Source and the Body are electrically
connected to the GND. With these configurations, CMOS design technology,
architectures, and the tools can be used in the implementation of the CNEMS logic.
Fig 3.4: Four-terminal NEMS switch configuration (a) Schematic for NNEMS (b)
Schematic for PNEMS [4]
3.10 Design of Basic Logic gates using CNEMS
The four-terminal NEM Switch can be configured into NNEMS and PNEMS to enable
the design of NEMS logic gates and flip-flops. This implementation requires the same
25
design concepts and technology used for implementing the CMOS logic gates. In this
section, the design of CNEMS basic logic gates and their functionality are discussed.
This includes design of logic gates such as Inverter, NAND, NOR, AND, OR, Buffer and
memory elements such as D-Latch, 1-bit SRAM. In case of the CMOS logic, PMOS and
NMOS transistors suffers from threshold drop since they pass a strong 1 or a strong 0 ,
but only swing to within threshold voltage (Vth) of the rail in the other direction. On the
other side in case of CNEMS logic, PNEMS and NNEMS do not have preference in
pulling in one direction (since they are bidirectional switches) and hence transmit both
the logics with equal preference. This feature of CNEMS design helps in constructing
efficient AND, OR and BUFFER gates, which is considered inefficient in the CMOS,
when PMOS and NMOS are used.
3.10.1 CNEM Inverter
The inverter is basic building block of all digital designs. Once its operation and
properties are clearly understood, more intricate structures such as NAND gates, adders,
multipliers, and microprocessors can be designed easily. In a CNEM inverter, PNEM and
NNEM are connected in series with the PNEM connected to VDD and NNEM connected
to GND as shown is Fig.3.5 (a). The potential difference between Gate (G) and Bulk (B)
of the PNEM is equal or greater than the device pull-in, if the input voltage is equal to
zero. The device hence turns ON. In case, the potential difference between Gate (G) and
Bulk (B) of the PNEM is equal to zero, the electrostatic force disconnects the connection
between the Source and Drain and hence the device is turned OFF. Here, the output
voltage becomes equal to VDD or logic 1 as shown in Fig.3.5 (c). If the input voltage
26
becomes equal or greater than the device pull-in voltage (logic one), the PNEMS is in the
OFF state and the NNEMS is in the ON state, the output voltage becomes equal to zero as
shown in Fig.3.5 (b). This behavior is very similar to CMOS inverter and is summarized
in the Table 3.1 below.
Fig 3.5: CNEMS Inverter [4]
Table 3.1: Inverter Operation using CNEMS
IN
OUT
N-NEMS
P-NEMS
0
1
OFF
ON
1
0
ON
OFF
3.10.2 NAND Gate
Schematic and symbol for a 2-input CNEMS NAND gate is shown in the Figure 3.6. It
consists of two series N-NEMS between output (Z) and Gnd and two parallel P-NEMS
between output (Z) and Vdd. If either input In1 or In2 is „0‟, at least one of the N-NEMS
27
will be OFF, thus breaking the path from output (Z) to GND. But at least one of the PNEMS will be ON, creating a path from output (Z) to Vdd. Hence, the output (Z) will be
equal to „1‟. If both the inputs are „1‟, both the N-NEMS will be ON and both of the PNEMS will be OFF. Hence in this case, the output will be equal to „0‟. Table 3.2 explains
the working of the NAND gate.
Fig 3.6: NAND Gate using CNEMS [4]
Table 3.2: NAND Gate Operation using CNEMS
IN1
IN2
OUT
N-NEMS1 N-NEMS2
P-NEMS1
P-NEMS2
0
0
1
OFF
OFF
ON
ON
0
1
1
OFF
ON
ON
OFF
1
0
1
ON
OFF
OFF
ON
1
1
0
ON
ON
OFF
OFF
28
3.10.3 NOR Gate
Schematic and symbol for a 2-input CNEMS NOR gate is shown in the Figure 3.7. The
two N-NEMS are in parallel to pull the output low when either input is high. The PNEMS are in series to pull the output high when both the inputs are low, as indicated by
the table 3.3. The behavior of CNEMS NOR gate is similar to the CMOS logic
implementation of NOR gate.
Fig 3.7: NOR Gate using CNEMS [4]
29
Table 3.3: NOR Gate Operation using CNEMS
IN1
IN2
OUT
P-NEMS1
P-NEMS2
N-NEMS1 N-NEMS2
0
0
1
OFF
OFF
ON
ON
0
1
0
OFF
ON
ON
OFF
1
0
0
ON
OFF
OFF
ON
1
1
0
ON
ON
OFF
OFF
3.10.4 AND Gate
Schematic and symbol for a 2-input CNEMS AND gate is shown in the Figure 3.8. It
consists of two series N-NEMS between output (Z) and Vdd and two parallel P-NEMS
between output (Z) and Gnd. Table 3.4 describes the working of the AND gate. Design of
AND gate in CNEMS does not cause any degraded output as observed in static CMOS
because of the absence of threshold drop.
30
Fig 3.8: AND Gate using CNEMS [4]
Table 3.4: AND Gate Operation using CNEMS
IN1
IN2
OUT
N-NEMS1 N-NEMS2
P-NEMS1
P-NEMS2
0
0
0
OFF
OFF
ON
ON
0
1
0
OFF
ON
ON
OFF
1
0
0
ON
OFF
OFF
ON
1
1
1
ON
ON
OFF
OFF
31
3.10.5 OR Gate
Schematic and symbol for a 2-input CNEMS OR gate is shown in the Figure 3.9. It
consists of two parallel N-NEMS between output (Z) and Gnd and two series P-NEMS
between output (Z) and Vdd. Table 3.4 describes the working of the OR gate.
Fig 3.9: OR Gate using CNEMS [4]
Table 3.5: OR Gate Operation using CNEMS
IN1
IN2
OUT
N-NEMS1 N-NEMS2
P-NEMS1
P-NEMS2
0
0
0
OFF
OFF
ON
ON
0
1
1
OFF
ON
ON
OFF
1
0
1
ON
OFF
OFF
ON
1
1
1
ON
ON
OFF
OFF
32
3.10.6 Buffer
Schematic and symbol for a CNEMS Buffer is shown in the Figure 3.10. It consists of a
two NEM switches unlike the cascading of inverters, observed with CMOS logic
implementation. N-NEMS connects the output (OUT) to VDD where as P-NEMS
connects output (OUT) to GND. P-NEMS and N-NEMS pass both logic ‟0‟ and logic ‟1‟
without any degradation. Table 3.6 explains the working of the CNEMS Buffer.
Fig 3.10: CNEMS Buffer
33
Table 3.6: Buffer Operation using CNEMS
IN
OUT
N-NEMS
P-NEMS
0
0
OFF
ON
1
1
ON
OFF
3.10.7 Memory design using NEMS
To construct sequential circuits, sequential elements need to be realized using CNEMS.
Basic building block of sequential circuits is the D-latch. Indefinite latching capability is
an important feature of NEM Switch. Since, there is no leakage in the NEM Switches;
they can remain in the ON or OFF state indefinitely without any feedback mechanism.
Therefore, it can support incessant propagation when used in interconnect design
connecting the right input signal to right output. This property of CNEMS results in high
integration density and low power by getting rid of any feedback circuitry to hold
information in latches [4]. CMOS, on the otherside has feedback circuit in latch design
where information is stored in the form of charge and feedback mechanism is required.
Also, there is no need of the SRAM cells in reconfigurable architectures to hold the
information in CNEMS. ON resistance of CNEMS is less than that of the CMOS
transistors which results in reducing propagation delay for long interconnect. Also,
absence of SRAM configuration results in low power dissipation and die area. Figure
3.11 shows a D latch design using CNEMS constructed out of an Inverter and one NNEM switch. Figure 3.10 shows a D-latch design using CMOS logic style which consists
of feedback network and transmission gates.
34
Fig 3.11: CMOS D-latch [4]
Fig 3.12: CNEMS D-latch [4]
35
3.11 Circuit Simulator of CNEMS
The CNEMS circuit simulation uses mathematical models to replicate the behavior of an
actual device or circuit and allows for modeling of the circuit operation and is an
invaluable analysis tool. Simulating a NEMS circuit behavior before actually building it
can greatly improve design efficiency. The NEMS circuit simulator proposed in [3] has
been used for the estimation of power and delay measurements. The circuit simulator
must perform the following tasks:
1. A circuit simulator should be able to read the circuit description from the Netlist
file.
2. A circuit simulator uses the mathematical models (constitutive equations) to
replicate the behavior of an actual circuit and allows for modeling of the circuit
operation. It formulates a set of equations for a circuit (described in the Netlist
file) based on the circuit topology using the KCL (Kirchhoff„s current laws) and
KVL (Kirchhoff„s voltage laws).
3. A circuit simulator solves the system of equations based on the linear and
nonlinear behavior of the circuits. LU decomposition technique is used to find
linear equations whereas; Newton-Raphson method is used to calculate nonlinear
equations.
3.12 Design of Digital CNEMS circuit
As already discussed, CNEMS logic and sequential circuits are realized by utilizing
CMOS design concepts and methodologies. The design methods, architectures, circuits
and design automation techniques from CMOS can be readily used to implement the
36
CNEMS logic gates. Following procedure results in the generation of the Netlist description
for a digital CNEMS [4].
1. Behavioral of arbitrary digital circuit is described by writing the hardware
description. The most frequently used HDL (hardware description languages)
is Verilog and VHDL.
2. Next, synthesis and optimization of the circuit is done that is described in behavioral
or structural level to gate level using synthesis tools (e.g. - Leonardo). Three files will
be generated after performing synthesis and optimization (file.v, file.vhl, file.sdf).
3. Now the edif program is used to convert the gate level (file.edf) into bench format.
This results in the creation of the file in the bench format (.net).
4. In this step, the CNEMS cell library and the generated bench circuit file are used to
generate the Netlist file for a CNEMS circuit.
3.13 Power Dissipation in NEM Switch
This section discusses the power dissipation in the NEM circuit. Power dissipation in the
NEM Switches can be categorized into two parts: switching power and leakage power
[3]. Significant power is only drawn when the device is switching between on and off
states. This power is known as switching power. Leakage power is the power drawn as a
result of leakage currents during the dynamic and static modes of a NEM switch. The
switching power of the NEM Switch may further be classified into: electrical switching
power and mechanical switching power which is modeled accurately in the constructed
circuit simulator [3]. Electrical switching power is drawn by charging and discharging the
capacitances between the switch electrodes. Mechanical switching power arises from the
movement of mechanical parts of the switch electrodes. Leakage current in the NEM
37
Switch can be categorized into: tunneling leakage current and surface leakage current which
is modeled accurately in the constructed circuit simulator [3].
3.14 Power Advantages in CNEMS
In the research work [3] power advantages of CNEMS circuits is shown over equivalent
CMOS circuits. Benchmark circuits such as iscas85 and iscas89 have been designed
using both CNEMS and CMOS technology. Circuits in the nanometer-CMOS technology
used 45 nm and 65 nm using HSPICE to evaluate the power advantages. Consumed
average power in each benchmark circuit during its two operating modes, active mode
and standby mode, has been calculated. Consumed power in the active mode comprises
of switching power and leakage power whereas, consumed power in the stand-by mode
consists of leakage power only. Fig 3.13 and 3.14 shows the average consumed power in
Nanometer-CMOS and CNEMS iscas85/ iscas89 benchmark circuits and demonstrates
the power saving using CNEMS logic style over using 65 nm or 45 nm CMOS
technology.
38
Figure 3.13: Power Advantages (Stand-by mode): Data from [3]
Figure 3.14: Power Advantages (Active mode): Data from [3]
39
3.15 Summary
Nano-Electro-Mechanical Switches (NEMS) has recently been a highly active area of
research as it holds great promise for a number of scientific and technological
applications. This chapter provided detailed explanation about the NEM Switches and
discussed its operation, factors concerning the reliability and power consumption in the
NEMS device. It also provided an explanation that makes NEM Switches a good
candidate for CMOS technology in implementing logic gates and memories. Finally, the
power advantages of CNEMS technology over Nanometer-CMOS technology have been
highlighted.
Potential areas for application of NEMS include biomedical devices where it is vital to
decrease the leakage power to prolong the implanted battery life, actuators, sensors,
resonators, aerospace, switches, programming interconnect in FPGA‟s and other
applications in harsh environment where CMOS cannot operate due to high temperature
or radiation [3,4].
40
Chapter 4:
Cardiac Pacing
4.1 Introduction
Technology is improving continuously and rapidly contributing to the design and
development of medical therapies and diagnostics around the globe. The quest for
realizing minimum power dissipation medical devices and circuits has been most intense
in implantable pacemakers.
Cardiac pacing is defined as the delivery of very low electrical signals in a continuous
manner to the heart for the initiation and maintenance of the cardiac rhythm. Poor
transportation of oxygen to the tissues occurs in an event of the heart failure which results
in the loss of energy and the patient begins to die. In order to understand cardiac pacing
more completely, this chapter is organized into three sections. In the section 4.2, a brief
overview of the operation of a human heart is discussed. Section 4.3 describes the
functionality of an implantable cardiac pacemaker. Finally, in the section 4.4 the circuit
blocks that are comprised in these devices and the requirements imposed on some of
these circuit blocks is shown.
4.2 Overview of Heart Function
Heart is basically a muscular pump that contracts in regular intervals and controls the
pumping action of the blood to the lungs and other parts of the body. This pumping
41
phenomenon is caused by the flow of electrical signals through the heart which repeats
itself after continuous intervals. In an event of irregular cardiac rhythm called arrhythmia,
this electrical activity gets disturbed which results in improper pumping of the blood.
Human heart as shown in Fig 4.1 has four chambers- two at the top called left atrium and
right atrium and two at the bottom called left ventricle and right ventricle.
Fig 4.1: Human Heart [10]
Sino-atrial (SA) node, called heart‟s natural pacemaker is a nodal tissue which is located
in the upper wall of the right atrium. It is responsible for the normal triggering and sets
the rate of contraction of the heart. The SA node sends the continuous electrical impulse
which causes atrium to contract and pumps blood into the bottom chamber (called,
ventricle). The electrical impulse then passes to the ventricles through the Atrio-
42
Ventricular (AV) node. The electrical signals thus generated spreads into the ventricles
that cause muscles to contract and causes the pumping of the blood to lungs and the body.
The Electrocardiogram (also called ECG) as shown in Fig 4.2 is a recording of the
electrical activity of the cardiac muscle which tracks the electrical impulses along the
conduction system in the heart.
Fig 4.2: ECG Waveform [12]
The electrical impulse stimulates contraction of the heart muscle in a regular manner
which forces the blood out of the heart and around the body. When the impulse ends, the
cardiac muscle relaxes. The various elements of heart‟s electrical activity are shown in
graphical form as the PQRST waves on the ECG. The P-wave is caused by atrial
contraction where the first upward deflection is due to the right atrium and the second
downward deflection is due to the left atrium [12]. The PR interval (P-Q time) extends
from the start of P-wave to the start of the QRS-complex as shown in the Fig 4.2. The
43
excitation is initiated by the left bundle branch and the ventricular septum and is visible
as the Q-wave. Most of the cardiac muscles are activated during the R-phase. The cells of
the atria are depolarized in the ST segment which spans from the end of ventricular
depolarization to the beginning of ventricular repolarization. The T-wave as shown in the
Fig 4.2 represents the ventricle repolarization and is into the same direction as the Rwave.
4.3 Implantable Pacemaker
An implantable pacemaker is a medical device that delivers rhythmic electrical signals in
a controlled manner to the cardiac muscle in order to maintain an effective heart rhythm.
Basic functional block diagram of an artificial pacemaker is shown in Fig 4.3 which
consists of three parts: an electrical pulse generator, a power source (battery) and the lead
system [11].
Fig 4.3: Basic Pacemaker functional block diagram [11]
44
The output electrical stimulus provided by the pulse generator is the electrical charge
transferred during the stimulus. Energy stored in the battery is used by the pacemaker to
stimulate the cardiac muscle and hence it is vital to design the circuit such that it aids in
the minimum power consumption by the device. Factors including pulse amplitude,
pacing rate and duration affect the longevity of the battery.
Fig 4.4: Placement of pacemaker leads [13]
Leads provide the required electrical connection between the heart muscle and the
implanted pulse generator as shown in Fig 4.4. Leads may be unipolar or bipolar. In the
unipolar system, the device has single conductor with an electrode located at the tip,
whereas in a bipolar system, the device has two separate and isolated conductors
connecting the two electrodes (anode and cathode, respectively).
There are two types of pacemakers: single-chamber pacemaker and dual-chamber
pacemaker as shown in Fig 4.5. In a single chamber pacemaker, there is one lead which is
45
placed either in the right atrium or right ventricle to pace the heart. In a dual chamber
pacemaker, there are two leads, one placed in the right atrium and the second one placed
in the right ventricle as shown.
Fig 4.5: Types of Pacemakers [13]
Single chamber pacemakers are typically selected for a person whose SA node sends out
too slow signals. Whereas, Dual chamber pacemakers are selected for a person whose SA
node sends out too slow signals and the electrical pathway to the ventricles gets
completely or partially blocked.
4.4 Pacemaker System Overview
An implantable pacemaker is real time embedded system with hardware/software codesign strategy with a dedicated microcontroller. As it is a battery operated device, low
power design methodology plays a crucial role in the design. Embedded computing
devices are power critical and therefore power constraints form an important part of the
46
design specification. The pacemaker microcontroller is an important computing element
in a battery operated real time system and consumes most of the battery energy.
Fig 4.6: Implantable Pacemaker Block Diagram [14]
Basic building blocks of an implantable pacemaker are shown in the Fig 4.6 above.
These are ECG front-end circuitry, battery, microcontroller and the output circuitry to
trigger the normal heart rhythm. The front-end circuitry senses the voltage generated
due to the pumping action of the heart which is a small signal with noise components.
This front-end circuitry consists of a differential amplifier, bandpass filter, level shifter
and the synchronizing circuit. The heart signal is sensed and amplified by a low noise
pre-amplifier, gain amplifier. It is then filtered by the second order low pass bandpass
filter to remove the noise signals and get the appropriate ECG. This signal is then
applied to the comparator, which is a threshold detector and generates a pulse depending
47
on the threshold voltage level. The output from the comparator is connected to the
microcontroller. The output circuitry consists of a charge pump which is a voltage
multiplier/ pulse generator to stimulate the heart. The amplitude and the pulse width are
customized for each patient. Supply Voltage Supervisor (SVS) monitors the battery
voltage.
4.5 Summary
Cardiac Pacing is explained in detail in this section. This would help the reader to fully
understand the heart operation and the functionality of an implantable pacemaker. The
knowledge of basic pacemaker functionality is vital in order to move into more advanced
stages of research and design, exploring the possibility of new design and applications.
48
Chapter 5:
Literature Review
Heart disease is increasing at a fast pace across the world. Particularly, there has been a
rise in many people developing arrhythmias which is due to cardiac problems producing
abnormal heart rhythms.
The heart beat may be too fast (tachycardia; > 180 bpm) or too slow (bradycardia; < 60
bpm), and may be regular or irregular e.g. due to asynchrony of the cardiac chambers. A
pacemaker can restore the normal cardiac rhythm between the atria and ventricles when a
malfunction occurs in the natural pacing of the heart tissues. Biomedical devices and
instruments are increasing in both complexity and functionality due to increase in heart
disease and subsequent technological improvements. It is crucial to have an
understanding and knowledge of both the human body and electrical engineering in order
to implement such functional systems. The pacemaker in our design implemented with
the hybrid CMOS-NEM Switches is a step in this direction, bridging the gap between
electrical engineering and biology.
Designing mixed-signal integrated circuits for implantable cardiac pacemaker is
challenged by the low power, low frequency and low noise requirements. Power
consumed by such medical device ICs is a single most important design factor.
49
Implantable medical devices are usually powered by a long-lasting battery which remains
inside the body of the patient for several years. When the battery voltage comes to end of
life which is a certain prescribed value, the entire implantable device must be replaced
through surgery. In order to design the pacemaker with the hybrid CMOS-NEM Switches
successfully, we had to research several associated areas which included: normal heart
function, components of a pacemaker, and previously implemented designs in CMOS
technology. The primary motivation for our research work was to develop a conceptual
understanding of pacemaker technology, using various electrical
engineering
fundamentals to implement a successful design which reveal significant power reduction
for the hybrid CMOS-NEMS implementation. The knowledge of basic pacemaker
functions is important in order to move into more advanced stages of research and design,
exploring the possibility of new design and applications.
5.1 Pacemaker Sense Amplifier
Conventional artificial pacemakers were asynchronous pulse generators which delivered
stimulus pulses at a fixed rate, regardless of heart‟s natural electrical activity or
physiological state of the patient. New biomedical pacemakers are responsive to heart‟s
electrical activity for conserving the limited energy available in the pacemaker batteries
and avoid the competition between artificial pacemaker stimulus and natural stimulus.
Such responsive biomedical pacemakers require the ability to not only deliver stimulus to
the cardiac muscle but also sense cardiac electrical events. A pacemaker that senses
heart‟s electrical activity requires some sort of sense-amplifier which amplifies and
detects that activity.
50
Pacemaker topologies are usually divided into an analog part (consisting of a sense
amplifier and a heart stimulator) and the digital part (consisting of a microcontroller).
Sense Amplifiers are one the most critical circuits in the pacemaker design. Figure 5.1
gives a perspective of the sense-amplifier block of an implantable pacemaker. The main
components of the analog sensing system are a bandpass filter, a variable gain amplifier
stage, a window comparator that can be triggered by the signal of sufficient amplitude of
negative/positive polarity to digitize the signal and a blanking circuit to prevent amplifier
overload during pacing stimuli. A reference voltage is used to set the switching threshold
of the comparator. An auxiliary telemetry amplifier is used for the telemetry purposes.
Fig.5.1: Components of Pacemaker Sense Amplifier [15]
The sense amplifier plays a vital role to provide the information about the current state of
the heart. It is designed in such a way that it detects and monitors the intra cardiac signal
51
events. After the signal is sensed, the signal is fed to the microprocessor that decides the
required pacing to be delivered by the stimulator to the heart. The microprocessor
requires accurate measurements of the cardiac electrical activity by the sense amplifier of
the pacemaker in the presence of noise and external interference.
5.2 Unipolar and Bipolar Sensing
In unipolar pacing, the lead tip acts as the cathode and the pulse generator acts as anode.
Whereas, in the bipolar sensing the lead tip acts as cathode and the lead ring acts as
anode. Fig 5.2 shows the unipolar and bipolar sensing. Unipolar leads have simpler
design and smaller external diameter as compared to the bipolar leads. Bipolar leads can
function in the unipolar mode if programmed as required.
Fig.5.2: Unipolar and Bipolar Sensing [15]
4.3 Switched Capacitor Circuits
Before we discuss the operation of switched-capacitor circuits, it is important to
understand the motivation behind using these circuits. Switched-capacitor circuits are
used in order to allow both the analog and digital functions to be implemented on the
52
same silicon chip. Since the VLSI circuits use the MOS transistors and rely on the picofarad range of the MOS capacitors, switched capacitor circuits have to be used if the
analog circuits are implemented on the same chip. A switched capacitor is an electronic
circuitry that works by moving charges into and out of capacitors when switches are
opened and closed, respectively. Generally, non-overlapping signals are used which
control the switches. This is done so that not all switches are closed at the same
time. Filters implemented with these circuit elements are called switched-capacitor filters.
A Switched capacitor network offers an alternative to the RC active and passive circuits
and has significant advantages for implantable biomedical device applications:

Critical frequencies in the switched-capacitor circuit are functions of the ratios of
capacitors and not the absolute values of capacitors and resistors.

Critical frequencies are determined by an external clock in the switched-capacitor
circuit. A sufficiently low clock frequency can be used to determine frequencyresponse characteristics which are suitable for processing signals of biomedical
origin without large values of resistance or capacitance.
The simplest switched capacitor (SC) circuit consists of a capacitor of capacitance C is
connected to a matrix of four switches activated by a two-phase clock whose phases are
φ1 and φ2. With each switching cycle charge q is transferred from the input to the output
at the switching frequency f. Charge q on a capacitor C with a voltage V between the
plates is given by the equation (5.1):
53
q=CV
(5.1)
The two nonoverlapping clock signals φ1 and φ2 are never both high and low at the same
time. If Vi (Input Voltage) and Vo (Output Voltage) may vary at rates much less than the
clock frequency, capacitor C charges to (Vi – Vo ) when clock φ2 is active and gets
discharged when clock phase φ1 is active. Since both clock phases φ1 and φ2 will be
active once during one clock cycle, the capacitor passes a charge of C (Vi – Vo ) with
each clock cycle. The charge transferred per second is f C (Vi – Vo), where f is the
frequency of the clock signals. The switched capacitor appears to be an effective
resistance whose value is given by the equation (5.2):
Reff =
=
=
(5.2)
The effective resistance of the switched-capacitor circuit is therefore inversely
proportional to both the capacitance and the switching frequency.
Fig.5.3: Switched-capacitor circuit. [15].
54
Chapter 6:
Design of Low Power Hybrid CMOS Nano-Electro-Mechanical
(NEM) Switches for Implantable Pacemakers
6.1 Introduction
Low power consumption is a primary goal in biomedical pacemaker electronic designs
where it is crucial to increase the battery life of the device. Implantable pacemaker
(Fig.6.1) is a real time embedded system which is surgically placed in the body of the
patient and is used to treat bradyarrhythmia (a heart rate that is too slow). To address the
power consumption, we present a low power hybrid CMOS-NEMS implementation of a
bandpass filter used within the sense system of the implantable pacemaker and the
pacemaker microcontroller. The approach is based on replacing the CMOS switches
with the NEMS switches. The innovative NEMS structures enable the implementation
of a switch and the universal logic gates such as XOR, AND, NAND, NOT, etc. and
help in the more reduction in power consumption as compared to the CMOS. The
NEMS offers unique characteristics in terms of turn on voltage (≈ 1.5V), switching time
(≈ 1ns), virtually zero leakage current, infinite ON current, and a small footprint size
which enable low-power designs. Our experimental results reveal significant power
reduction for the hybrid CMOS-NEMS implementation of bandpass filter circuit and the
pacemaker microcontroller.
55
Fig.6.1: Human Heart and Implantable Pacemaker [17]
6.2 Design of Switched-Capacitor Bandpass Filters for Implantable Pacemaker
Designing mixed-signal integrated circuits for implantable cardiac pacemaker is
challenged by the low power, low frequency and low noise requirements. Power
consumed by such medical device ICs is a single most important design factor.
Implantable medical devices are usually powered by a long-lasting battery which remains
inside the body of the patient for several years. When the battery voltage comes to end of
life which is a certain prescribed value, the entire implantable device must be replaced
through surgery. Therefore, mixed signal ICs must be very low current and low voltage
circuits for the biomedical devices. While all other functions in a pacemaker chip
including the microprocessor, pacing system turn on periodically only on the need basis
to save every bit of battery, the heart sensing circuit, on the contrary, remains alert
continuously throughout the lifetime of the device. Power consumption and supply
voltage operation of this functional block, therefore remains the most critical design
performance.
56
The sensing system of the implantable pacemaker monitors the intra-cardiac activities.
After signal sensing, the signal is fed to the microprocessor which decides upon the
appropriate pacing therapy to be delivered by the stimulator. This sensing circuit is
usually a dedicated bandpass filter that attenuates spurious signals such as internal muscle
miopotential and noise from external sources and amplifies the desirable continuous
signals such as the electrocardiogram (ECG) signals shown in Fig.6.2.
Fig. 6.2 ECG (Electrocardiogram) waveform [12]
6.2.1 Filter Characteristics
The frequency spectrum of the intracardiac signal is categorized into four bands. First,
the ventricular QRS signal has frequency between the ranges of 20-60Hz and amplitude
between the ranges of 1mV-10mV peak-to-peak. Second, the atrial P-wave signal has
57
frequency between the ranges of 40-100Hz and amplitude between the ranges of 50uV1mV peak-to-peak. Frequencies lower than 10Hz are occupied by the repolarization
signals called the T-waves. Frequencies greater than 120Hz are occupied by the muscle
potential noise [16]. The objective of the bandpass filter within the sensing system is to
reject the low frequency T-wave and the high frequency muscle noise and environmental
disturbances. The filter must amplify and condition the small amplitude signals of the
QRS and P-wave to the larger amplitude so that they are fully digitized by on-chip analog
to digital converter.
The designed bandpass filter has two main objectives: (1) to reject T-wave and
repolarization wave at low frequencies (<10Hz), (2) to reject muscles and environmental
noise at high frequencies (>120Hz). Therefore, the implemented second order bandpass
transfer function should have two poles approximately located at 20Hz and at 120Hz,
respectively. This second order bandpass filter has a peak value at filter's center
frequency (FO) which is the geometric mean of lower frequency (FL) and Upper
frequency (FU) of the filter as shown in equation 6.1 below.
√
= 48.98Hz
(6.1)
The quality factor of a bandpass filter with two poles on real-axis is shown is equation
6.2.
⁄
(6.2)
The continuous desired function of the implemented filter is described in equation 6.3
below. HO is the mid-band gain and
is the filter natural frequency.
58
(
(
)
(6.3)
)
6.2.2 The Pacemaker Filter
In our research work, we use a fully differential micro-power op-amp with a class AB
output stage. The output stage as shown in the Fig 6.4 produces a rail-to-rail output
signals which eliminates the need for a nulling zero compensation resistor. The total opamp bias current is 14xIB. For the bias current of 5nA, the unity gain bandwidth is 11.5
KHz when the output load capacitance is 2pF. The filter has a switched-capacitor
common-mode feedback circuit as shown in Fig 6.3.
59
Fig. 6.3 Fully-Differential Double Sample Rate Two Op-Amp Bandpass Filter [16]
60
Fig. 6.4 Fully-Differential Operational Amplifier [16]
To demonstrate the power efficiency of switch when used in the bandpass filter circuit
within the sensing system of an implantable pacemaker, we have designed circuits in both
CMOS and NEMS and compared them in term of power consumptions. For CMOS we
used HSPICE simulator to compute the power. To evaluate the power of NEMS circuits,
we used a NEMS circuit simulation model and a corresponding NEMS circuit simulator
[3]. To insure the accuracy of the NEMS circuit simulator, the NEMS circuit simulation
model is calibrated with the NEMS physical device model. Our experiment showed that
the energy and thus power dissipation using NEMS technology is much lower than
CMOS technology.
It is important for the pacemaker sensing circuit to exclude the noise signals. The ECG
input signals were tested in the designed bandpass filter circuit. After the signal is passed
61
through the bandpass filter circuit it rejects the T-wave and repolarization wave at low
frequencies and muscles and environmental noise at high frequencies.
6.2.3 Results
Fully-Differential Double Sample Rate Two Op-Amp Bandpass Filter shown in Fig.8 is
implemented in the pacemaker sensing circuitry. This pacemaker sensing filter is realized
by cascading two identical Op-Amps shown in Fig.6.4. The filter is implemented with
tsmc018 (0.18um) technology. The experimental power requirement results shown in
Fig.6.5 reveal significant power dissipation reduction for the Hybrid CMOS-NEMS
implementation (225uW) over the counterpart CMOS circuit (364uW) using 1024Hz
system clock with the CMOS Op-Amp requiring 180uW.
Table 6.1: Cardiac Filter Characteristics
PARAMETERS
VALUE
Technology
0.18μm
Supply Voltage
1.3 V
Clock Frequency Rate
1024 Hz
Average Power Dissipation (CMOS Implementation)
364 μW
Average Power Dissipation (Hybrid CMOS-NEMS)
225 μW
Lower Band-edge Frequency
20 Hz
Upper Band-edge Frequency
120 Hz
62
Fig 6.5: Power Advantages of Hybrid CMOS-NEM Switches for Bandpass Filter
6.3 Design of Microcontroller based Pacemaker system
An implantable pacemaker is real time embedded system with hardware/software codesign strategy with a dedicated microcontroller. As it is a battery operated device, low
power design methodology plays a crucial role in the design. Embedded computing
devices are power critical and therefore power constraints form an important part of the
design specification. The pacemaker microcontroller is an important computing element
in a battery operated real time system and consumes most of the battery energy. Thus,
an optimized design and analysis is very important for such device.
Basic building blocks of an implantable pacemaker are ECG front-end circuitry, battery,
microcontroller and the output circuitry to trigger the normal heart rhythm. The frontend circuitry senses the voltage generated due to the pumping action of the heart which
63
is a small signal with noise components. This front-end circuitry consists of a
differential amplifier, bandpass filter, level shifter and the synchronizing circuit. The
heart signal is sensed and amplified by a low noise pre-amplifier, gain amplifier. It is
then filtered by the second order low pass bandpass filter to remove the noise signals
and get the appropriate ECG. This signal is then applied to the comparator, which is a
threshold detector and generates a pulse depending on the threshold voltage level. The
output from the comparator is connected to the microcontroller. The output circuitry
consists of a charge pump which is a voltage multiplier/ pulse generator to stimulate the
heart. The amplitude and the pulse width are customized for each patient. Supply
Voltage Supervisor (SVS) monitors the battery voltage.
An arrhythmia is a problem which causes the heart to beat too fast, too slow, or with an
irregular rhythm. When the heart rate is too fast (>180bpm, Tachycardia), too slow
(<60bpm, Bradycardia) or irregular, the heart may not be able to pump enough blood to
the body. Lack of blood flow may damage the heart, brain and other organs.
6.3.1 High Level Software Design:
A Pacemaker uses ultra-low-power microcontroller which is crucial for the battery
operated implantable devices. Microcontroller with optimized software is a basic
component in it. In our research work, we design a simple pacemaker system which will
receive the desired pulse rate (calculated from equation 5.8 below) from the programmer
and use it to pace the fetal heart.
64
Bpm= 60000/t (ms)
(6.7)
Since a pacemaker is a real time embedded system which consumes most of the battery
power, therefore it is important to conserve the battery life. The battery will be monitored
constantly by the circuit and the pacemaker will be in sleep mode between pulses. The
implemented pacemaker will continue to pace at the set rate until it detects another value
from the programmer.
The pacemaker software is written in Verilog Hardware Description Language to output
a 1.2ms pulse high pulse and a low pulse for the remainder of the pulse width. For
example, if the heart rate is set to 120bpm which gives the pulse rate of 500ms
(calculated from equation 6.7). Therefore the output will be high for 1.2ms and low for
498.8ms. The designed software will ask the user to input the desired heart rate and
calculate the pulse rate which will be converted to the binary value.
In general, a pacemaker is a timer which changes the state in response to the sensed
signals or elapsed intervals. This operation drives the processor to move from one state to
the next in response to time-out signals. Depending upon the present state of the
controller which has its own set of conditions, it goes to the next state based on the
inputs. Figure 6.8 shows a simple state diagram of an implantable pacemaker.
65
Fig 6.6: Flow Chart of Simple Pacemaker [18]
66
6.3.2 Schematic and Symbol for the Pacemaker Microcontroller
Fig 6.7: Schematic of Pacemaker Microcontroller
Fig 6.8: Symbol of Pacemaker Microcontroller
67
6.3.3 Results
The circuit successfully paces at the cardiac rate set by the programmer. When the heart
beat is set to 120bpm, the circuit pulses every 500ms (1.2ms high and 498.8ms low). The
pulse rate can be changed by the programmer by varying the heart beat but the pulse
width and amplitude of the high output is constant. A Verilog Netlist for the Pacemaker
microcontroller is derived by synthesis using Mentor Graphics ASIC design tools. The
CNEMS simulation was performed using the circuit simulation technique which shows
the reduction in the power consumption.
Fig 6.9: Output Waveform of Pacemaker Microcontroller
68
Fig 6.10: Output Waveform of Pacemaker Microcontroller (Magnified View)
Table 6.2: Pacemaker Microcontroller Characteristics
PARAMETERS
VALUE
Technology
0.18μm
Supply Voltage
1.3 V
Average Power Dissipation (CMOS Implementation)
1.0598 mW
Average Power Dissipation (NEMS Implementation)
0.38 μW
Pulse-High
1.2ms
Pulse-Low
498.8ms
69
Fig 6.11: Power Advantages of Hybrid CMOS-NEMS for Pacemaker Microcontroller
6.4 Summary
This research works aimed at addressing energy efficiency and idle power consumption
in implantable cardiac pacemaker design by proposing innovative hybrid design
containing both CNEMS (Complimentary Nano Electro Mechanical Switches) and the
CMOS. This novel design is based on using the CNEM switching device as a
replacement of CMOS devices in the circuit design of implantable pacemakers. NEM
Switches can be dropped in and hybridized with the CMOS at the metallization level or
device level which manages the leakage current and power dissipation greatly. NEM
Switches can be fabricated using same steps as of CMOS and offers a seamless
integration with CMOS logic style and design technologies. Our experiments showed that
70
the energy dissipated in NEMS technology is much lower than CMOS technology when
implemented in an implantable cardiac pacemaker design.
71
Chapter 7:
Conclusions
In this research work, the excessive quiescent power dissipation in CMOS technology
was addressed by investigating the properties of Nano-Electromechanical Switch
(NEMS). This device offer unique characteristics in terms of low turn on voltage (~1V),
less switching time (~1ns), virtually zero leakage current and footprint size. These
characteristics make this switch attractive and can be implemented in digital CMOS
circuits especially, portable embedded systems that have limited battery-life. The NEM
Switch can be fabricated easily by utilizing CMOS fabrication process and equipment.
NEM Switches can also be hybridized with the CMOS to manage leakage power.
Additionally, innovative design paradigms for the logic gates and memory design using
NEM Switches have been illustrated. We presented a low power hybrid CMOS-NEMS
implementation of a various blocks of an implantable pacemaker including bandpass
filter (used within the sense system) and the microcontroller. The approach was based on
replacing the CMOS switches with the NEMS switches.
Our experimental results reveal significant power reduction for the hybrid CMOS-NEMS
implementation. With the nature of results obtained because of superior characteristics of
NEM Switches, we can affirm that the usage of NEMS in implantable pacemaker possess
strong potential to lead innovation and technology breakthroughs.
72
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