RZ/G Series Document Errata
for RZ/G1 Series
Rev.1.10
2015.12.01
Renesas Electronics Corporation
OA Solution Department
R01TU0102EJ0110
List of RZ/G Series Errata (1/2)
No
Title
001
Usage Notes for RZ/G Series PFC SD/VIN Control Register Setting
002
RZ/G Series User‘s Manual: Hardware Corrections (Manual Errata)
003
RZ/G1M User's Manual: Hardware Corrections
004
RZ/G Series User‘s Manual: Hardware Corrections (Manual Errata 2)
005
Usage note for DMAC of RZ/G Series
006
RZ/G Series, User‘s Manual: Hardware Corrections (FDP1, VSP1, I2C)
007
MMC Specification Change for RZ/G1M and G1N
008
RZ/G Series, User‘s Manual: Hardware Corrections and Usage Notes
(Audio, SSIU, ADG, SCU)
009
CPG Specification Change and Usage Note for RZ/G1H,G1M and G1N
010
Limitation of SPI mode for MSIOF of RZ/G Series
011
RZ/G Series, User‘s Manual: Hardware Correction
(CPG, Module Standby and Software Reset, APMU, RST)
012
RZ/G Series User‘s Manual: Hardware Correction (DU)
013
Addendum for DBSC3 Pin States
014
Corrections of VSP1 for RZ/G Series
015
Usage Notes for DBSC3 of RZ/G Series
016
RZ/G Series User‘s Manual: Hardware Corrections (CAN interface)
017
Specification Change and Usage Notes for MSIOF of RZ/G Series
018
QSPI Specification Change and Manual Correction of RZ/G Series
019
RZ/G Series User‘s Manual: Hardware Corrections (RCLK Watchdog Timer)
020
RZ/G Series User‘s Manual: Hardware Corrections
(CPG, Module Standby and Software Reset, RST)
021
Usage Note for GPIO of RZ/G Series
022
Addendum for PFC Pin Function Settings of RZ/G1M and G1N
023
Usage Notes for DBSC3 of RZ/G Series
024
Usage Note for R-GP2D of RZ/G1H
025
DVFS and AVS Specification Change of RZ/G1H,G1M, and G1N
026
DBSC3 Specification Change of RZ/G Series
027
Limitation of Transfer Performance for MMC of RZ/G Series
028
RZ/G Series Electrical Characteristics Correction
029
Document Corrections for RZ/G Series
030
Specification Change for VSP1 of RZ/G Series
031
Specification Change for SSI of RZ/G Series
032
Usage Note for SCU of RZ/G Series
List of RZ/G Series Errata (2/2)
No
Title
033
Specification Change for FDP1 of RZ/G Series
034
RZ/G Series, User's Manual: Hardware Correction (DU)
035
Limitation of MDT Pin Monitor Registor for RST of RZ/G1H
036
Trademark Notation Correction of RZ/G Series
037
Corrections of No.031 and DU Register Suffixs for RZ/G Series
038
RZ/G1E Electrical Characteristics Correction
039
Correction of No.011 and RZ/G Series User's Manual:
Hardware (Module Standby and Software Reset)
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
No.
001
Title
Usage Notes for RZ/G Series PFC SD/VIN Control Register Setting
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B001A/E
2 Page
[Summary]
RZ/G1H, G1M, G1N, and G1E each User's manual: hardware usage notes for SD/VIN IO voltage settings.
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
There is no specification change (document correction only).
[Correction]
PFC (table 1 each reference document section 5)
1) RZ/G1H: Section 5.3.40 POC（SD） Control Register 6 (IOCTRL6)
2) RZ/G1M and G1N: Section 5.3.43 SD Control Register 6 (IOCTRL6)
3) RZ/G1E: Section 5.3.36 POC Control Register 3 (IOCTRL3)
(Red part (abcd) is newly added)
Current (from): Correction (to):
Notes1. Any pin belongs to the same SD/VIN channel must be set the same IO voltage. Event
though setting different voltage for each pin, it is impossible to change each pin voltage
from the power supply voltage of the VCCQ(_MMC)_SD/VDDQ_VIN pin.
2. When the VCCQ(_MMC)_SDn/VDDQ_VINm power supply voltage is 1.8-V to use the SDHI
interface as SDR50/SDR104 mode, the VIN or the GPIO (multiplexed with SDHI channel
n/VIN channel m pin) as 1.8-V IO, specify 1.8-V for related IOCTRL, then IO voltage of the
SDHI channel n/VIN channel m pins and multiplexed other function pins is all 1.8-V. In this
condition, never input 3.3-V signal to these pins; if input 3.3-V signal, the LSI may be
permanently damaged even though specifying the pin voltage to 3.3-V individually,
furthermore, pull-up voltage of the unused pin which belongs to the same SD/VIN
channel must be 1.8-V.
3. When the VCCQ(_MMC)_SDn/VDDQ_VINm power supply voltage is 3.3-V, to use the SDHI
interface as default mode, high-speed mode/VIN or other module function, specify 3.3-V
for related IOCTRL, then IO voltage of the SDHI channel n/VIN channel m and multiplexed
other function pins is all 3.3-V. In this condition, output level of the pin is 3.3-V and if the
external device can only operate with1.8-V, the external device may be permanently
damaged even though specifying the pin voltage to 1.8-V individually.
4. For details of SDn/VINm related pin function settings, refer to following section for each
product reference document.
RZ/G1H:
Section 5.3.5 GPSR 3, 5.3.16 IPSR 8 through 5.3.19 IPSR11, 5.3.25 MOD_SEL, 5.3.26
MOD_SEL2, 5.3.27 MOD_SEL3.
RZ/G1M,G1N:
Section 5.3.8 GPSR 6, 5.3.23 IPSR13, 5.3.24 IPSR14, 5.3.28 MOD_SEL2, 5.3.29 MOD_SEL3.
RZ/G1E:
Section 5.3.8 GPSR 6, 5.3.9 IPSR0, 5.3.24 MOD_SEL2.
Page 1 of 1
[Reference Document]
table 1 Reference Document for each RZ/G series
Products
Document title
RZ/G1H
RZ/G1H User’s Manual : Hardware
RZ/G1M
RZ/G1M User’s Manual : Hardware
RZ/G1N
RZ/G1N User’s Manual : Hardware
RZ/G1E
RZ/G1E User’s Manual : Hardware
Revision
0.50
0.50
0.50
0.50
Date
Oct 2015
Oct 2015
Oct 2015
Oct 2015
Document No.
R01UH0627EJ0050
R01UH0626EJ0050
R01UH0628EJ0050
R01UH0544EJ0050
No.
002
Title
RZ/G Series User‘s Manual: Hardware Corrections (Manual Errata)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B011A/E
8 Pages
/ TN-RCS-B023A/E
[Summary]
RZ/G Series, User's manual: hardware corrections (manual errata).
[Products]
RZ/G1H, G1M, G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change in this Technical Update (document correction only).
[Corrections]
1. Section 6. GPIO for RZ/G1H, G1M, G1N, and G1E
Table 6.3 Register Configuration, Table columns (pages 6-26 to 6-30):
Current (from): Manual Reset column is applicable.
Correction (to): This column is removed because the manual reset is not supported.
2. Section 7. CPG for RZ/G1H, G1M, G1N, and G1E
Section 7.5.9, MMC0CKCR Bit 8 table description for RZ/G1H, G1M, G1N, and G1E (page 7-26):
(Red part (abcd) is newly added)
Current (from): Clock Stop
0: Supplies MMC0 clock
1: Stops MMC0 clock
Correction (to): Clock Stop
0: Supplies MMC0 clock
1: Stops MMC0 clock
Note. When the QSPI module is enabled, do not stop MMC0 clock.
3. Section 7A. Module Standby and Software Reset for RZ/G1H, G1M, G1N, and G1E
Table 7A.2 Register States in Response to a Reset, Table header for RZ/G1H, G1M, G1N, and G1E (page
7A-3):
Current (from): Power-On Reset/WDT Reset
Correction (to): Power-On Reset
4. Section 11. INTC-SYS for RZ/G1M and G1N
1)Table 11.1 AP-System core (INTC-SYS) Interrupt Mapping (7/11), SPI# 235 source for RZ/G1M and
G1N (page 11-7):
Current (from): SPD
Correction (to): Reserved
2)Table 11.1 AP-System core (INTC-SYS) Interrupt Mapping (7/11), SPI# 238 source for RZ/G1M and
G1N (page 11-8):
Current (from): 12-bitADIF
Correction (to): Reserved
5. Section 16. LBSC within Bus Bridge for RZ/G1H, G1M, G1N, and G1E
Usage Note as new section 16.7.4 (page 16-78):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): 16.7.4 Usage Note
When using QSPI or HSCIF booting by mode pins setting (MD[3:1]), the area 0 beginning 256-kByte
space (H'00 0000 0000 to H'00 0003 FFFF) cannot be accessed from the LBSC even after booting.
Page 1 of 8
6. Section17. DBSC3 for RZ/G1H, G1M, G1N, and G1E
1) Figure 17.1b Block Diagram of the DBSC3 [RZ/G1N and G1E], Pin configuration for RZ/G1E (page 175):
(Red part (abcd) is newly added)
Current (from): M0VREFDQ0, M0VREFDQ1, M0BKPRST#, M0ZQ
Correction (to): M0VREFCA (RZ/G1E), M0VREFDQ0, M0VREFDQ1, M0BKPRST#, M0ZQ
2) Section 17.3.18 DBTR9 Table Notes. 3 for RZ/G1H, G1M, G1N, and G1E (page 17-32):
Current (from): TRDPR = BL/2 + max {2, ceil(tRTP / tCK)} - 2
Correction (to): TRDPR = max {4, ceil(tRTP / tCK)}
3) Section 17.3.33 DBRFCNF1 Description (1) (a) for RZ/G1H, G1M, G1N, and G1E (page 17-52):
Current (from): (a) To minimize variation of the Refresh Interval
Set REFPMAX to 0. In this case, the time between one round of....to the DBRFEN register during this
period.
Correction (to): Description (a) is all deleted.
4) Section 17.3.33 DBRFCNF1Description (1) (b) for RZ/G1H, G1M, G1N, and G1E (page 17-52):
(Red part (abcd) is corrected)
Current (from): (1st-line) Set REFPMAX to a value greater than or equal to 1.
Correction (to): (1st-line) Set REFPMAX to a value greater than or equal to 2.
5) Section 17.4.3.1 (1)(d) DBSC setting 2 after 6th bullet items order for RZ/G1H, G1M, G1N, and G1E
(page 17-82):
(Red parts (abcd) are moved)
Current (from):
• Set the ARFEN bit to 1 in the auto-refresh enable register (DBRFEN).
• Set the ACCEN bit to 1 (access enabled) in the SDRAM access enable register (DBACEN).
• Write H'00000000 to the PHY unit lock register (DBPDLCK).
• Write H'00000010 to the PHY unit address register (DBPDRGA).
• Write H'F00464DB to the PHY unit access register (DBPDRGD).
This locks the access to the PHY unit registers.
Correction (to):
• Set the ARFEN bit to 1 in the auto-refresh enable register (DBRFEN).
• Write H'00000010 to the PHY unit address register (DBPDRGA).
• Write H'F00464DB to the PHY unit access register (DBPDRGD).
• Set the ACCEN bit to 1 (access enabled) in the SDRAM access enable register (DBACEN).
• Write H'00000000 to the PHY unit lock register (DBPDLCK).
This locks the access to the PHY unit registers.
6) Section 17.4.11 (3) DDR3-SDRAM (64-bit External Bus) [RZ/G1H and G1M] Table Note for RZ/G1H and
G1M (page17-113):
Current (from): (3rd-line) Setting sy_phyportnum = 1 for the DBSC3 pin sets 64-bit external bus mode.
Correction (to): This description is removed because this setting is not necessary for using the DBSC3.
7) Section 17.4.14 (2) Recovery from SDRAM Power-Supply Backup Mode Case 1 description for
RZ/G1M and G1E (page 17-103):
Current (from): Case 1 is available.
Correction (to): Case 1 is not available, and related description and figure are deleted.
8) Section 17.4.14 (2) Recovery from SDRAM Power-Supply Backup Mode Case 2, sequence 3 for
RZ/G1H, G1M, G1N, and G1E (page 17-103):
(Red parts (abcd) are corrected)
Current (from): Write H'40000000 to the PHY unit address register (DBPDRGA).
Correction (to): Write H'40000000 to the PHY unit access register (DBPDRGD).
Page 2 of 8
7. Section 20. LBSC-DMAC HPB for RZ/G1H, G1M, G1N, and RZ/G1E
1) Figure 20.3 DMA Transfer Flowchart (2), Bus names in flow (6) for RZ/G1H, G1M, G1N, and G1E (page
20-45):
Current (from): HPB
Correction (to): APB
2) Section 20.5.3 Packing Data Read from Peripheral or External Module 1st-paragraph bus names in 9th
and 10th lines for RZ/G1H, G1M, G1N, and G1E (page 20-50):
Current (from): HPB
Correction (to): APB
8. Section 24. DU for RZ/G1H, G1M, G1N, and RZ/G1E
1) Table 24.3, 24.5, 24.7, 24.9, 24.11, 24.13, 24.15, 24.17, 24.19, 24.21, 24.23, Sleep column for RZ/G1M
and G1E (pages 24-21, 24-22, 24-25, 24-26 24-28, 24-39 to 24-48, 24-51, 24-52, 24-54, 24-56, 24-57, 2458, 24-60, 24-61)
Current (from): Sleep columns are applicable.
Correction (to): These columns are removed because they are not applicable.
2) Section 24.3.1.3 (DSMRn) description for RZ/G1H, G1M, and G1N (page 24-71):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): For the RZ/G1H, G1M, and G1N, this register setting is also available for the display
data output via the LVDS.
3) Section 24.4.18 2nd-paragraph “Data formats” description for RZ/G1M, G1N, and G1E (page 24-264):
(Red part (abcd) is newly added)
Current (from): Refer to table 24.31, Output Data Format. In the case of ARGB1555, the A value is
determined by the setting of DCPCRm*.
Correction (to): Refer to table 24.31, Output Data Format. In the case of ARGB1555, the A value is
determined by the setting of DCPCRm*. In the case of ARGB8888, the A value is determined by the
setting of DCnMRm*.
9. Section 25. LVDS for RZ/G1H, G1M, and G1N
1) Table 25.4 Register States in the Various Processing Modes, Sleep column for RZ/G1H, G1M, and
G1N(page 25-5):
Current (from): Sleep column is applicable.
Correction (to): This column is removed because this is not applicable.
2) Section 25.3.4 3rd paragraph, Clock source selection for RZ/G1H, G1M, and G1N (page 25-19):
(Red parts (abcd) are corrected)
Current (from): DU_COTCLKIN0, DU_COTCLKIN1 or DU_COTCLKIN2*
Correction (to): DU_DOTCLKIN0, DU_DOTCLKIN1 or DU_DOTCLKIN2*
10. Section 30A. VPC for RZ/G1H,G1M, G1N, and G1E
1) Table 30A.2 States of Registers in Each Processing Mode, Manual Reset and Sleep column for
RZ/G1H,G1M, G1N, and G1E (Page 30A-2):
Current (from): These columns are applicable.
Correction (to): These columns are removed because they are not applicable.
Page 3 of 8
11. Section 39. SSIU for RZ/G1H,G1M, G1N, and G1E
Table 39.1 Pin Configuration, Name, Pin Name and Function (page 39-4):
(Red parts (abcd) are newly added)
SSI_SCK0129(SSI_SCK01239)
RZ/G1H, G1M, G1N, G1E
SSI_WS0129(SSI_WS01239)
SSI_SCK34(SSI_SCK349)
SSI_WS34(SSI_WS349)
RZ/G1H, G1M, G1N, G1E
12. Section 46. CAN interface for RZ/G1H,G1M, G1N, and G1E
Table 46.3 Register Configuration, Table header (pages 46-4 to 46-7)
Current (from): P4 Address
Correction (to): Address
13. Section 51. SCIF for RZ/G1H,G1M, G1N, and G1E
1) Section 51.2.8 SCBRR and 51.2.9 SCFCR 2nd-paragraph for RZ/G1H,G1M, G1N, and G1E (pages 51-20
and 51-21):
(Red part (abcd) is newly added)
Current (from): SCBRR/SCFCR can always be read from and written to by the CPU.
Correction (to): SCBRR/SCFCR can always be read from and written to by the CPU except for during
transfer.
2) Figure 51.8 Sample Flow Chart for Initializing the SCIF, and Figure 51.17 Sample Flow Chart for SCIF
Initialization, Figure note for RZ/G1H,G1M, G1N, and G1E (pages 51-33 and 51-40):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): Note. SCBRR and SCFCR registers can only be set while both TE and RE bits of SCSCR are
cleared.
3) Figure 51.25 BRG Block Diagram, Sub-block name for RZ/G1H,G1M, G1N, and G1E (page 51-50):
(Red part (abcd) is corrected)
Current (from): HPB IF
Correction (to): APB IF
14. Section 52. SCIFA* for RZ/G1H,G1M, G1N, and G1E
Table 52.2 Register Configuration, Table header for RZ/G1H,G1M, G1N, and G1E (page 52-4):
Current (from): CPU Access
Correction (to): This indication is deleted.
*：This correction is needed in the next-version of RZ/G series User's manual.
Page 4 of 8
15. Section 53. SCIFB* for RZ/G1H, G1M, G1N, and G1E
Table 53.2 Register Configuration, Table header for RZ/G1H, G1M, G1N, and G1E (page 53-4):
Current (from): CPU Access
Correction (to): This indication is deleted.
*：This correction is needed in the next-version of RZ/G series User's manual.
16. Section 54. HSCIF for RZ/G1H, G1M, G1N, and G1E
1) Section 54.2.8 HSBRR and 54.2.9 HSFCR 2nd-paragraph (pages 54-18 and 54-19):
(Red part (abcd) is newly added)
Current (from): HSBRR/HSFCR can always be read from and written to by the CPU.
Correction (to): HSBRR/HSFCR can always be read from and written to by the CPU except for during
transfer.
2) Figure 54.3 Sample Flowchart for Initializing the HSCIF, Figure note (page 54-32):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): Note. HSBRR and HSFCR registers can only be set while both TE and RE bits of HSSCR
are cleared.
3) Figure 54.16 BRG Block Diagram, Sub-block name for RZ/G1H,G1M, G1N, and G1E (page 54-44):
(Red part (abcd) is corrected)
Current (from): HPB IF
Correction (to): APB IF
17. Section 55. I2C for RZ/G1H,G1M, G1N, and G1E
1) Table 55.2 Register Configuration (1), Table note (page 55-3):
Current (from): (4th-line) ... (the number "2" of ICCCR2 is not channel number)
Correction (to): This sentence is removed because ICCCR2 is not available.
2) Table 55.2 Register Configuration (2), Table header (page 55-4):
Current (from): Power-On Reset By PRESET# Pin/WDT/H-UDI
Correction (to): Power-On Reset
3) Table 55.2 Register Configuration (2), Table columns (page 55-4):
Current (from): Manual Reset and Sleep columns are applicable.
Correction (to): These two columns are removed because they are not applicable.
4) Section 55.5.1 (3) 3 description (page 55-26):
(Red part (abcd) is newly added)
Current (from): Reset the MAT bit.
Correction (to): Reset the MAT and MDE bits.
5) Section 55.5.2 (3) 3 description (page 55-27):
(Red part (abcd) is newly added)
Current (from): Reset the MAT bit.
Correction (to): Reset the MAT and MDR bits.
6) Section 55.5.3 (5) 3 description (page 55-28):
(Red part (abcd) is corrected)
Current (from): Reset the MAT and MDE bits.
Correction (to): Reset the MAT and MDR bits.
18. Section 57. MSIOF for R RZ/G1H,G1M, G1N, and G1E
Section 57.3.1 SITMDR1 bits 22 to 20 and 18 to 16 Table descriptions (page 57-7):
Current (from): In case of SPI mode, only 000 is allowed to set to this field.
Correction (to): This description for each field is deleted.
Page 5 of 8
19. Section 59. SDHI for RZ/G1H,G1M, G1N, and G1E
1) Section 59.1.1 2nd-bullet item SDR104 clock frequency (page 59-1):
(Red part (abcd) is corrected)
Current (from): SD clock frequency ≤ 156 MHz
Correction (to): SD clock frequency ≤ 195 MHz
2) Figure 59.2 Block Diagram of SDHI [RZ/G1M, G1N, G1E], RZ/G1M and G1N channel number (page 593):
(Red parts (abcd) are corrected)
Current (from):
Block name: SDHI 1, SDHI 2
Pin name: SD1_xxx, SD2_xxx
Correction (to):
Block name: SDHI 2, SDHI 3
Pin name: SD2_xxx, SD3_xxx
3) Table 59.1 Pin Configuration, Table note for RZ/G1M and G1N (page 59-4):
(Red part (abcd) is corrected)
Current (from):
n=0 to 2 [RZ/G1M, RZ/G1N, G1E]
Correction (to):
n=0, 2, 3 [RZ/G1M, RZ/G1N], n=0 to 2 [RZ/G1E]
Page 6 of 8
20. Section 63. HS-USB for RZ/G1H,G1M, G1N, and G1E
1) Table 63.2 Register Configuration (3/3), UGSTS register address for RZ/G1H,G1M, G1N, and G1E (page
63-5):
Current (from): H'E659 0190
Correction (to): H'E659 0188
2) Section 63.2.1 SYSCFG Description for RZ/G1H,G1M, G1N, and G1E (pages 63-8 and 63-9):
Current (from): (1st-line) ... , selects the host controller function or the function controller function,
Correction (to): This sentence and host related descriptions in table are removed because the HS-USB
does not support host controller function.
3) Section 63.2.4 DVSTCTR description for RZ/G1H,G1M, G1N, and G1E (page 63-12):
Current (from): Host related description is applicable (bit 8).
Correction (to): Host related description is removed because the HS-USB does not support host
controller function.
4) Section 63.2.14 INTSTS0 description for RZ/G1H,G1M, G1N, and G1E (pages 63-34 to 63-36):
Current (from): Host related description is applicable (bits 14 to 11 and 6 to 0).
Correction (to): Host related description is removed because the HS-USB does not support host
controller function.
5) Section 63.2.32 (2) description for RZ/G1H,G1M, G1N, and G1E (page 63-66):
Current (from): Host related description is applicable (bit 8).
Correction (to): Host related description is removed because the HS-USB does not support host
controller function.
6) Section 63.2.36 Bits 4 to 1 descriptions for RZ/G1H,G1M, G1N, and G1E (pages 63-72, 63-73):
Current (from): Notes (bits 4 to 1) and Host mode descriptions (bits 4 and 3) are applicable.
Correction (to): These notes and descriptions are removed because the DRPD bit is not available and
the HS-USB does not support host controller function.
7) Section 63.2.39 UGSTS Lock bit location and description for RZ/G1H,G1M, G1N, and G1E (page 6376):
Current (from): Bits 1 and 0 (initial value: 00); Description 11: Embedded USB PHY PLL Lock completed,
Others: Embedded USB PHY PLL clock halted.
Correction (to): Bit 8 (initial value: 0); Description 1: Embedded USB PHY PLL Lock completed, 0:
Embedded USB PHY PLL clock halted.
8) Section 63.3.1 (1) Power control and Initialization sequence 6 for RZ/G1H,G1M, G1N, and G1E (page
63-77):
(Red part (abcd) is corrected)
Current (from): HS-USB module
Correction (to): HS-USB and EHCI modules
9) Section 63.3.1 (2) Setting Selection of Controller Functions for RZ/G1H,G1M, G1N, and G1E (page 6377):
Current (from): This setting is applicable.
Correction (to): This setting is removed because this is not applicable.
10) Section 63.3.1 (3) Enabling High-Speed Operation for RZ/G1H,G1M, G1N, and G1E (page 63-77):
Current (from): Host controller is applicable in this section.
Correction (to): Host controller related descriptions are removed because the HS-USB does not
support host controller function.
11) Section 63.3.2 (8) Resume Interrupt 2nd paragraph for RZ/G1H,G1M, G1N, and G1E (page 63-88):
Current (from): Host controller is applicable.
Correction (to): Host controller related descriptions are removed because the HS-USB does not
support host controller function.
12) Table 63.14 Pipe Settings, PIPEPERI remarks for RZ/G1H,G1M, G1N, and G1E (page 63-89):
Current (from): Pipes 6 to 8 Setting allowed only when the host control function is selected
Correction (to): This sentence is deleted.
Page 7 of 8
21. Section 65. USB3.0 Host Controller for RZ/G1H, G1M, and G1N
1) Figure 65.4 xHCI Register Map (2/3), Offset H‘590 and H’594 register abbreviation for RZ/G1H, G1M,
and G1N (page 65-10):
(Red parts (abcd) are corrected)
Current (from): DDCP0 and DDCP1
Correction (to): DCCP0 and DCCP1
2) Figure 65.4 xHCI Register Map (2/3), Offset H‘598 and H’59C description for RZ/G1H, G1M, and G1N
(page 65-10):
Current (from): DCDDI1 and DCDDI2 assigned
Correction (to): Reserved; because they are not supported.
3) Section 65.3.2.7 No.14 and 15 in table, Offset H'38 and H'3C description for RZ/G1H, G1M, and G1N
(page 65-74,65-82):
Current (from): Table items No.14 and 15, and following (j) and (k) DCDDIn (n=0, 1) descriptions are
available.
Correction (to): These DCDDIn related descriptions are all removed because they are not supported.
22. Section 68 TPU for RZ/G1H, G1M, G1N, and G1E
Table 68.3 Register Configuration (3/3), Address H'E70F xxxx (pages 68-5 to 68-7) and Table note (page
68-7):
Current (from): Addresses H'E70F xxxx are available for DMAC address.
Correction (to): Addresses H‘E70F xxxx are removed from table description and table note is removed
because these addresses are reserved.
23. Section 69B. CMT1 for RZ/G1H, G1M, G1N, and G1E
Section 69B.2.6 CMCNTHn description for reading of 48-bit counter (page 69B-21):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): When reading the value of 48-bit counter, upper 16-bit can be read out by reading bits
15 to 0 of this register.
At the same time of the reading, the value of 48-bit counter is stored to the readbuffer. After reading CMCNTHn, lower 32-bit can be read out by reading CMCNTn.
Note. If CMCNTn is read out before reading CMCNTHn, the read out value of 48-bit
counter may not be correct.
24. Section 70. TMU for RZ/G1H, G1M, G1N, and G1E
1) Table 70.2 Register Configuration (1), Table header for RZ/G1H, G1M, G1N, and G1E (pages 70-4 and
70-5):
Current (from): P4 Address
Correction (to): Address
2) Table 70.3 Register Configuration (2), Table header for RZ/G1H, G1M, G1N, and G1E (pages 70-6 and
70-7):
Current (from): By PRESET# Pin/WDT/H-UDI (Power-On Reset)
Correction (to): This indication is deleted.
3) Table 70.3 Register Configuration (2), Sleep column for RZ/G1H, G1M, G1N, and G1E (pages 70-6 and
70-7):
Current (from): Sleep column is applicable.
Correction (to): Sleep column is removed because this is not applicable.
25. Section 73. PWM Timer for RZ/G1H, G1M, G1N, and G1E
Table 73.3 Register States in Each Operating Mode, Manual Reset and Sleep columns (page 73-3):
Current (from): These columns are applicable.
Correction (to): These columns are removed because they are not applicable.
Page 8 of 8
No.
003
Title
RZ/G1M User's Manual: Hardware Corrections
Applicable Product
RZ/G1M
Note for RENESAS
TN-RCS-B012A/E
2 Pages
[Summary]
RZ/G1M User's manual: hardware corrections (manual errata).
[Products]
RZ/G1M only
[Note]
There is no specification change (document correction only).
[Corrections]
1. Section 1. Overview
1) Figure 1.1 RZ/G1M System Configuration, Sub-system bus connection (page 1-2):
(Red parts (abcd) are corrected in figure 1.1)
Current (from): SDHI, MMCIF and TSIF modules are connected to the AXI-bus.
Correction (to): SDHI, MMCIF and TSIF modules are connected to the APB.
2) Section1.4 Power Supply Voltage and Temperature Range, MMC, STAT, PCI Express, USB3.0 power
supply voltage (typ.)(page 1-22):
Current (from): MMC, SATA, PCI Express, USB3.0 are all in 1.8 V.
Correction (to): MMC is removed from 1.8 V because MMC is only supported at 3.3 V, and SATA, PCI
Express, USB3.0 are moved to 1.03V.
3) Section1.4 Power Supply Voltage and Temperature Range, DDR3_GPIO power supply voltage (typ.)
(page 1-22):
Current (from): - (missing)
Correction (to): DDR3_GPIO is added to 1.8 V.
2. Section 3. Pin Assignment
Section 3.1 Top View (Left) and 3.2 Top View (Right), Pins name (pages 3-1 and 3-2):
(Gray parts (abcd) are corrected or newly added)
Page 1 of 2
3. Section 4. Pin Multiplexing
Table 4.1 through 4.3, Pins name (pages 4-15 to 4-51):
(Gray parts (abcd) are newly added).
Page 2 of 2
No.
004
Title
RZ/G Series User‘s Manual: Hardware Corrections (Manual Errata 2)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B013A/E
4 Pages
[Summary]
RZ/G Series, User's manual: hardware corrections (manual errata 2).
[Products]
RZ/G1H, G1M, G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change in this Technical Update (document correction only).
[Corrections]
1. Section 26 VIN for RZ/G1H, G1M, G1N, and G1E
26.2.23 VnDMR2, Bit 23 Table description (page 26-49):
(Red part (abcd) is newly added)
Current (from): Correction (to): Note. When using ITU-R BT.601, BT.709, BT.1358 interface, and the VIn_CLKENB pin is
unused, the CHS bit must be set to 1.
2. Section 63 USB High-Speed Module (HS-USB) for RZ/G1H, G1M, G1N, and G1E
Number of pipes and DMAC channels are corrected.
1) Section 63 general description 2nd-paragraph (page 63-1):
(Red parts (abcd) are corrected)
Current (from): This module can use up to twelve pipes when the function controller is selected.
Correction (to): This module can use up to 16 pipes.
2) Section 63.1 Features, (4) (page 63-1):
(Red parts (abcd) are corrected)
Current (from): On-chip 2-channel DMA interface
Correction (to): On-chip 4-channel DMA interface
3) Section 63.1 Features, (5) 1st-bullet item (page 63-1):
(Red parts (abcd) are corrected)
Current (from): Up to twelve pipes are selectable (including the default control pipe)
Correction (to): Up to 16 pipes are selectable (including the default control pipe)
4) Section 63.1 Features, (5) 4th-bullet item (page 63-1):
Pipes 3 to 5 and 9 to F
(Red parts (abcd) are corrected)
Current (from): Pipes 3 to 5 and 9 to F: Bulk transfer, continuous transfer mode, programmable buffer
size (up to 2-Kbytes: double buffer can be specified)
Correction (to): Pipes 3 to 5 and B to F: Bulk transfer, continuous transfer mode, programmable buffer
size (up to 2-Kbytes: double buffer can be specified)
Page 1 of 4
5) Section 63.2.6, 2nd-paragraph (page 63-15):
(Red parts (abcd) are newly added)
Current (from): Each FIFO port consists of this register (CFIFO) for data read/write from/to the FIFO
buffer memory, the select registers(CFIFOSEL, D0FIFOSEL and D1FIFOSEL) to select
pipes to be allocated to a FIFO port, and the control registers (CFIFOCTR, D0FIFOCTR
and D1FIFOCTR).
Correction (to): Each FIFO port consists of this register (CFIFO) for data read/write from/to the FIFO
buffer memory, the select registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL, D2FIFOSEL and
D3FIFOSEL) to select pipes to be allocated to a FIFO port, and the control registers
(CFIFOCTR, D0FIFOCTR, D1FIFOCTR, D2FIFOCTR and D3FIFOCTR).
6) Section 63.2.6, table description of bit name “FIFOPORT [31:0]” (page 63-15):
(Red parts (abcd) are newly added)
Current (from): Access to this register is enabled only when the FRDY bit in each control register
(CFIFOCTR, D0FIFOCTR and D1FIFOCTR) is set to 1.
Correction (to): Access to this register is enabled only when the FRDY bit in each control register
(CFIFOCTR, D0FIFOCTR, D1FIFOCTR, D2FIFOCTR and D3FIFOCTR) is set to 1.
7) Section 63.2.28, Bits 15 and 14 (TYPE[1:0]) table description (page 63-53):
Pipes 3 to 5, 9 to F
(Red parts (abcd) are corrected)
Current (from): Pipes 3 to 5, 9 to F
Correction (to): Pipes 3 to 5, B to F
Pipes 9 to A
(Red parts (abcd) are newly added)
Current (from): - (included pipes 9 to F)
Correction (to): Pipes 9 to A
00: No pipe is used.
01: Bulk transfer
10: Interrupt transfer
11: Setting prohibited
8) Table 63.14, Pipe Settings (page 63-89):
(Cancelation line parts (abcd) are deleted (not correct) and gray parts (efgh) are newly added (correct))
9) Section 63.3.3 (2), Transfer Type 3rd-bullet item (page 63-90):
(Red parts (abcd) are corrected and newly added)
Current (from): Pipes 3 to 5, 9 to F: Set bulk transfer.
Correction (to): Pipes 3 to 5, B to F: Set bulk transfer.
Pipes 9 to A: Set bulk transfer or interrupt transfer.
Page 2 of 4
10) Section 63.3.3 (4), Maximum Packet Size (page 63-91):
Pipe 9 to A
Current (from): - (included pipes 9 to F)
Correction (to): Pipes 9 to A: Set a value from 1 to 64 for interrupt transfer.
11) Section 63.3.4 (3) (c), DnFIFO Auto-Clear Mode (D0FIFO and D1FIFO Port Read Direction) (page 6399):
(Red parts (abcd) are newly added)
Current (from): (c) DnFIFO Auto-Clear Mode (D0FIFO and D1FIFO Port Read Direction)
Correction (to): (c) DnFIFO Auto-Clear Mode (D0FIFO, D1FIFO, D2FIFO and D3FIFO Port Read Direction)
12) Section 63.3.7 is corrected as follows: (page 63-102)
(Red parts (abcd) are corrected)
Current (from): 63.3.7 Interrupt Transfer (Pipes 6 to 8)
Correction (to): 63.3.7 Interrupt Transfer (Pipes 6 to A)
3. Section 81 SYSC for RZ/G1E
1) 81.1 Overview for RZ/G1E (page 81-1):
(Red part (abcd) is newly added)
Current (from):
The SYSC module controls the supply of power to CPUs (CA15*1, CA7*2), SGX, with the aim of low
leakage power. When a module is not in use, shutting off power to the module further lowers
leakage power than just stopping supply of the clock signal.
Correction (to):
The SYSC module controls the supply of power to CPUs (CA15*1, CA7*2), SGX, with the aim of low
leakage power. When a module is not in use, shutting off power to the module further lowers
leakage power than just stopping supply of the clock signal.
For the RZ/G1E, only pseudo power off is supported. In pseudo power off mode, clock distribution
for target modules are stopped with reset assert, but shutting off power-line for reducing leakage
current is not supported. In this section, ‘power off' means pseudo power off for the RZ/G1E.
Page 3 of 4
2) Figure 81.3, Block Diagram for RZ/G1E (page 81-4):
(gray-encircled part ( ) is deleted)
Current (from):
Correction (to):
Page 4 of 4
No.
005
Title
Usage note for DMAC of RZ/G Series
Applicable Product
RZ/G1H, G1M, G1N and G1E
Note for Renesas
TN-RCS-B020A/E
1 Pages
[Summary]
An illegal DMA transfer may occur before descriptor transfer.
[Products]
RZ/G1H, G1M, G1N and G1E (for details, refer to each correction)
[Modules]
SYS-DMAC and Audio-DMAC
(reference document section 18 and 43)
[Note]
There is no specification change (additional usage note only).
[Description]
When using descriptor transfer with both condition 1) and 2), an illegal DMA transfer occurs before the
descriptor transfer starts.
・ Conditions
1) Descriptor start timing is specified after descriptor information is loaded, i.e. DPB=1.
SYS-DMAC: DMACHCR_n.DPB=1 (refer to section 18.3.17, bit 22 description)
Audio-DMAC: DMACHCR_n.DPB=1 (refer to section 43.3.17, bit 22 description)
2) Address translation by the uTLB is enabled.
・ Problem
In condition 1) and 2), an illegal DMA read transfer occurs to the former stored DAR address after
DMA enable (DE=1). If the address is undefined in the IPMMU, the DMA transfer may be stopped
and hang-upped without any error indication.
[Workarounds]
1. Use the descriptor transfer with DPB=0.
2. Use the descriptor transfer with DPB=1 and the uTLB address translation is disabled.
3. When use the descriptor transfer with DBP=1 and the uTLB address translation is enabled, write the
same destination address with the 1st descriptor memory address to the corresponding DAR before
DMA enable (DE=1). However an illegal DMA read transfer occurs, the descriptor transfer is
executed correctly if the writing address to the corresponding DAR is not undefined address.
Page 1 of 1
No.
006
Title
RZ/G Series, User‘s Manual: Hardware Corrections (FDP1, VSP1, I2C)
Applicable Product
RZ/G1H, G1M , G1N, and G1E
Note for Renesas
TN-RCS-B021A/E
4 Pages
[Summary]
RZ/G Series, User's manual: hardware corrections (manual errata).
[Products]
RZ/G1H, G1M , G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change in this Technical Update (document correction only).
[Corrections]
1. Section 31. Fine Display Processor (FDP1) for RZ/G1H, G1M , G1N, and G1E (refer to Red highlighted)
1) Section 31.1.1 Overview (page 31-1)
Current (from): 2. Full HD video processing performance
Correction (to): 2. Full HD video processing performance
Can process maximum Full-HD 60i to 60p at 266 MHz operating frequency.
2) Section 31.1.1 Overview (page 31-1)
Current (from): 3. High image-quality de-interlacing algorithm
Correction (to): 3. High image-quality de-interlacing algorithm (basing on luma component only)
3) Section 31.1.2 FDP1 Architecture (page 31-1)
Current (from): Figure 31.1 shows the block diagram of the FDP1.
Correction (to): Figure 31.1 shows the block diagram of the FDP1. In this figure, “Previous field image”
and “Next field Image” are luma image only.
4) Section 31.1.2 FDP1 Architecture (page 31-2)
Current (from): (3) IPC (Interlace to Progressive Converter)
Correction (to): Add Note.
Note: the motion adaptive algorithm is applied to only luma component. conventional
2D de-interlacing is applied to Chroma component.
5) Section 31.2 Function List (page 31-3)
Current (from): Table 31.1 Input
Correction (to): Table 31.1 Input*3
6) Section 31.2 Function List (page 31-4)
Current (from): Table 31.1 Interpolation
Correction (to): Table 31.1 Interpolation (luma)
7) Section 31.2 Function List (page 31-4)
Current (from): - (missing)
Correction (to): Interpolation (chroma) / 2D fixed
8) Section 31.2 Function List (page 31-4)
Current (from): Motion adaptive
Correction (to): Motion adaptive (luma only)
9) Section 31.2 Function List (page 31-4)
Current (from): Supported
Correction (to): Supported (luma only)
Page 1 of 4
10) Section 31.2 Function List (page 31-4)
Current (from) : - (missing)
Correction (to): Notes 3.Chroma component (Cb, Cr or U,V) of RPF0, RPF2 is not read from bus in case
of planar or semi-planar format and discarded after reading in package with luma
component in case of interleaved format because it is processed in fixed 2D deinterlacing.
11) Section 31.3.3 National Conventions for Registers and Bit Fields (page 31-6)
Current (from) :5. A wildcard (*) indicates any characters in a name and represents all registers or bits
that match the specified first part of a name. For example, when there are three
registers FD1_RPF0_ADDR_Y, FD1_RPF0_ADDR_C0 and FD1_RPF0_ADDR_C1,
FD1_RPF0_ADDR_* indicates three registers.
Correction (to): 5. A wildcard (*) indicates any characters in a name and represents all registers or bits
that match the specified first part of a name. For example, when there are three
registers FD1_RPF0_ADDR_Y, FD1_RPF1_ADDR_C0 and FD1_RPF1_ADDR_C1,
FD1_RPF1_ADDR_* indicates three registers.
12) Section 31.3.7 Memory Map (page 31-10)
Current (from) : FD1_RPF0_ADDR_Y
Correction (to): FD1_RPFn_ADDR_Y
13) Section 31.3.7 Memory Map (page 31-10)
Current (from) : RPFn Source Component-C0 Address Register (n=0,1,2)
Correction (to): RPF1 Source Component-C0 Address Register
14) Section 31.3.7 Memory Map (page 31-10)
Current (from) : FD1_RPF0_ADDR_C0
Correction (to): FD1_RPF1_ADDR_C0
15) Section 31.3.7 Memory Map (page 31-10)
Current (from) : H'0070+ H'C×n
Correction (to): H'007C
16) Section 31.3.7 Memory Map (page 31-10)
Current (from) : RPFn Source Component-C1 Address Register (n=0,1,2)
Correction (to): RPF1 Source Component-C1 Address Register
17) Section 31.3.7 Memory Map (page 31-10)
Current (from) : FD1_RPF0_ADDR_C1
Correction (to): FD1_RPF1_ADDR_C1
18) Section 31.3.7 Memory Map (page 31-10)
Current (from) : H'0074+ H'C×n
Correction (to): H'0080
19) Section 31.3.9.2 Table 31.7 YCbCr Formats for RPF Input and WPF Output*4 (page 31-31)
Current (from): Table 31.7 YCbCr Formats for RPF Input and WPF Output*4
Correction (to): Table 31.7 YCbCr Formats for RPF Input*5 and WPF Output*4
20) Section 31.3.9.2 Table 31.7 YCbCr Formats for RPF Input*5 and WPF Output*4 (page 31-31)
Current (from): - (missing)
Correction (to): Notes 5. Chroma component (Cb, Cr or U,V) of RPF0, RPF2 is not read from bus in case
of YCbCr planar, YCbCr semi-planar formats, and discarded after reading in package
with luma component in case YCbCr interleaved formats because it is processed in
fixed 2D de-interlacing.
21) Section 31.3.9.3 Source Picture Stride Register (FD1_RPF_PSTRIDE) [Bit 15 to 0 : Description] (page
31-34):
Current (from): These bits specify in 1-byte units the memory stride of the source picture C plane read
by the RPFn(n=0,1,2)
Correction (to): These bits specify in 1-byte units the memory stride of the source picture C plane read
by the RPF1.
Page 2 of 4
22) Section 31.3.9.4 RPFn Source Component-m Address Register. / Title (page 31-35):
Current (from): RPFn Source Component-m Address Register
(FD1_RPFn_ADDR_m: n = 0, 1, 2; m = Y, C0, C1)
Correction (to): RPFn Source Component-m Address Register
(FD1_RPFn_ADDR_m :{n,m} is one of {0,Y},{1,Y},{1,C0},{1,C1},{2,Y})
23) Section 31.3.9.4 RPFn Source Component-m Address Register. / Description (page 31-35):
Current (from): RPFn Source Field Address for Component-m(n = 0, 1, 2; m = Y, C0, C1)
Correction (to): RPFn Source Field Address for Component-m({n,m} is one of
{0,Y},{1,Y},{1,C0},{1,C1},{2,Y})
24) Section 31.3.11 IPC Control Registers, register categorization table (page 31-46)
Current (from): - (missing)
Correction (to): Table shows registers categorized in function of IPC.
25) Section 31.3.11.1 IPC Mode Register (FD1_IPC_MODE) (page 31-46)
Current (from): These bits specify the de-interlacing mode.
Correction (to): These bits specify the de-interlacing mode of luma component as following. The deinterlacing process of chroma component is fixed 2D de-interlacing regardless of these bits.
2. Section 32. VSP1 for RZ/G1H, G1M, G1N, and G1E
1) Section 32.2.7.6 RPFn α Plane Selection Control Registers (VI6_RPFn_ALPH_SEL) (page 32-81)
Current (from): Bit: 15 to 8, Description
8-Bit α Value Output when 1-Bit α Value is 0
These bits specify the 8-bit α value to be output when 1-bit α data is input and the α
value input to the 8-bit transparent α generator shown in figure 32.25 is 0
Correction (to): Bit: 15 to 8, Description
8-Bit α Value Output when 1-Bit α Value is 1
These bits specify the 8-bit α value to be output when 1-bit α data is input and the α
value input to the 8-bit transparent α generator shown in figure 32.25 is 1
Page 3 of 4
2) Section 32.2.7.6 RPFn α Plane Selection Control Registers (VI6_RPFn_ALPH_SEL) (page 32-81)
Current (from): Bit: 7 to 0, Description
8-Bit α Value Output when 1-Bit α Value is 1
These bits specify the 8-bit α value to be output when 1-bit α data is input and the α
value input to the 8-bit transparent α generator shown in figure 32.25 is 1.
Correction (to): Bit: 7 to 0, Description
8-Bit α Value Output when 1-Bit α Value is 0
These bits specify the 8-bit α value to be output when 1-bit α data is input and the α
value input to the 8-bit transparent α generator shown in figure 32.25 is 0.
3) Section 32.2.8.9 WPFn Destination Y/RGB Address Registers (VI6_WPFn_DSTM_ADDR_Y) (page 32119)
Current (from): - (missing)
Correction (to): Add Table 32.26a and Table 32.26b
4) Section 32.2.19.1 LIF Control Register (VI6_LIF_CTRL) (page 32-200)
Current (from): - (missing)
Correction (to): Bit: 26 to 16, Description
Recommendation value of OBTH is 128.
5) Section 32.2.19.2 LIF Clock Stop Buffer Control Register (VI6_LIF_CSBTH) (page 32-202)
Current (from): - (missing)
Correction (to): Bit: 26 to 16, Description
Recommendation value of HBTH is 1536.
6) Section 32.2.19.2 LIF Clock Stop Buffer Control Register (VI6_LIF_CSBTH) (page 32-202)
Current (from): - (missing)
Correction (to): Bit: 10 to 0, Description
Recommendation value of LBTH is 1520.
3. Section 55, I2C for RZ/G1H, G1M , G1N, and G1E
(Red parts (abcd) are corrected)
Section 55.3.6, ICMSR Bit3 (MDE) table description, 2nd-line from the bottom (page 55-12):
Current (from): ... clear the MDT and MAT bits ...
Correction (to): ... clear the MDE and MAT bits ...
Note. If the MDE bit is not cleared, the data transmission does not progress.
Page 4 of 4
No.
007
Title
MMC Specification Change for RZ/G1M and G1N
Applicable Product
RZ/G1M and G1N
Note for RENESAS
TN-RCS-B022A/E
1 Pages
[Summary]
MMC_D output data delay times are changed
[Products]
RZ/G1M and G1N
[Note]
This is a specification change of MMC.
[Specification Change]
MMC_D output delay time, tMMCDADD1 and tMMCDADD2 max value (table 84.25):
(red parts (abcd) are changed)
Current (from): tMMCDADD1 (max.) = tMMCCYC x 3/4 + 1
tMMCDADD2 (max.) = tMMCCYC x 1/2 + 1
Change (to): tMMCDADD1 (max.) = tMMCCYC x 3/4 + 1 for other than MMC_D[7:6] pins
tMMCDADD1 (max.) = tMMCCYC x 3/4 + 3 for MMC_D[7:6] pins
tMMCDADD2 (max.) = tMMCCYC x 1/2 + 1 for other than MMC_D[7:6] pins
tMMCDADD2 (max.) = tMMCCYC x 1/2 + 3 for MMC_D[7:6] pins
[Description]
This specification change is caused by the lack of timing margin of MMC_D[7:6] pins.
The MMC_D[7:6]_B pins specification are not changed. When using MMC_D[7:6] pins for high speed
mode, specify tMMCDADD2 by setting CE_ODATSEL.ODTS to 1.
However the MMC can operate with under 26 MHz, some of the card interface timing specification
are not supported. When
using the MMC as backward compatible system, its system operation by using card interface must be
tested and evaluated thoroughly by the user.
Page 1 of 5
No.
008
Title
RZ/G Series, User‘s Manual: Hardware Corrections and Usage Notes (Audio, SSIU, ADG, SCU)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B025A/E
5 Pages
[Summary]
Correction and usage note for Audio, SSIU, ADG and SCU manual
[Products]
RZ/G1H, G1M, G1N, and G1E (for details, refer to each correction)
[Note]
This correction includes usage note for Audio.
[Corrections]
1. Section 38. Audio for RZ/G1H, G1M, G1N, and G1E
1) Figure 38.3 Data Format, Note 4 (page 38-6):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): Notes 4 : In Data Format of “16-bit stereo data or multichannel data” and “9- to 15bitstereo data or multichannel data”, set SSIU.SSI_MODE0.ind_word_swap*(*=0-9) in
the setup of independent SSI transmission(SSIU.SSI_MODE0.ind*(*=0-9)=1).
2) 38.2 Usage Notes (page 38-14):
(Red part (abcd) is newly added)
Current (from): - (missing)
Correction (to): The following Usage notes are added.
38.2.7 Note on Usage of the SCU Module
Before starting data transfer, the SCU module needs certain “input data timing” and
“output data timing”.
When “input data timing” and “output data timing” are not inputted before the
transmission start, it does not operate correctly.
Page 1 of 5
2. Section 39. Serial Sound Interface Unit (SSIU) for RZ/G1H, G1M, G1N, and G1E
1) Figure 39.1 Block Diagram of SSIU (SSI0, SSI1, SSI2, SSI3, SSI4, and SSI9) [RZ/G1H, G1M, G1N, and
G1E] (page 39-2):
Current (from):
[1] (missing)
[2] (missing)
Correction (to):
[1] Add symbol for the description
[2] Adding the route descriptions
Page 2 of 5
2) Figure39.2 Block Diagram of SSIU (SSI5, SSI6, SSI7, and SSI8) [RZ/G1H, G1M, G1N, and G1E] (page 393):
Current (from):
[1] (missing)
[2] (missing)
Correction (to):
[1] Add symbol for the description
[2] Adding the route descriptions
3. Section 40. Audio Clock Generator (ADG) for RZ/G1H, G1M, G1N, and G1E
1) 40.2.13 SRC Output Timing Select Register 0 (SRCOUT_TIMSEL0) (page 40-38):
(Red part (abcd) is corrected)
Current (from): 0000: Setting prohibited
Correction (to): 1111: Setting prohibited
Page 3 of 5
2) Figure 40.1 Block Diagram [for RZ/G1H, G1M, G1N, and G1E] (page 40-2):
Current (from):
[1] 21
[2] (missing)
[3] (missing)
Correction (to):
[1] 22
[2] Control registers are added.
[3] Control register name is added.
4. Section 42. SCU for RZ/G1H, G1M, G1N, and G1E
1) 42.2.5 SRCm Control Register (SRCm_CONTROL) (page 42-23):
(Red part (abcd) is corrected)
Current (from): When CMD is used and the sync_out bit in the SRCm_MODE register is set for
synchronous mode,
Correction (to): When CMD is used and the sync_in bit in the SRCm_MODE register is set for
synchronous mode,
2) Table note (page 42-158):
(Red part (abcd) is corrected)
Current (from): Table 42.8 shows the INITFS setting examples in the SRC block.
Correction (to): Table 42.8 shows the INTIFS setting examples in the SRC block.
Page 4 of 5
3) Table 42.8 INTIFS Values in SRCm_IFSVR Register for Some Specific Cases (page 42-158):
(Red part (abcd) is corrected)
Current (from): INITFS[27:0]
Correction (to): INTIFS[27:0]
Page 5 of 5
No.
009
Title
CPG Specification Change and Usage Note for RZ/G1M
Applicable Product
RZ/G1H, G1M, and G1N
Note for RENESAS
TN-RCS-B026A/E
2 Pages
[Summary]
GPU clock control register is newly added and note for setting
[Products]
RZ/G1H, G1M, and G1N
[Note]
This is a specification change of CPG.
[Specification Change]
RGX Control Register (RGXCR) is newly added for the RZ/G1M.
(initial value: H'0000 0000)
[Usage Note]
Bit 16 in RGXCR should be set to 1 before enabling the GPU (3DG/3DGE) of the RZ/G1H, G1M, and G1N.
Refer to section 7A, Module Standby and Software Reset, too.
RZ/G1H
RZ/G1M
RZ/G1N
RZ/G1E
RZ/G1H
RZ/G1M
RZ/G1N
RZ/G1E
[Document Correction]
(gray parts (abcd) are changed)
1) Table 7.10, Register Configurations (page 7-12):
Current (from):
Change (to):
Page 1 of 2
2) Section 7.5.5, RGX Control Register (RGXCR) (page 7-21):
Current (from):
- Products indication:
- Bit 16 (SGXEX) Table description (initial value: 0) :
Disable external logic for SGX Series5
0: Enable external logic for SGX Series5
1: Disable external logic for SGX Series5
Change (to):
- Products indication
- Bit 16 (SGXEX) Table description (initial value: 0) for RZ/G1H, G1M, and G1N :
Disable external logic for SGX Series5
0: Enable external logic for SGX Series5
1: Disable external logic for SGX Series5
Note. When using the GPU, set this bit to 1 before enabling the GPU.
[Others]
Above SGX Series5 indicates following 3D Graphics Engine (3DGE) in section 23:
RZ/G1H: PowerVR G6400
RZ/G1M and G1N: SGX544-MP2
Page 2 of 2
No.
010
Title
Limitation of SPI mode for MSIOF of RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B027A/E
1 Page
[Summary]
SPI slave mode cannot start transmission with a certain condition
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
This limitation will not be fixed.
[Limitation]
When the MSIOF operates with all of the following condition 1 to 3, the MSIOF in SPI slave mode cannot
start the next transmission. The MSIOF cannot support SPI mode under following condition.
・ Condition
1) MSIOF is in SPI slave mode (SITMDR1.TRMD=0, SITMDR1.SYNCMD[1:0]=10)
2) SYNC (CS) signal is being asserted from master
3) TXE or RXE in SICTR is set to 1 during SYNC (CS) is asserted
[Description]
This limitation means the MSIOF cannot respond to the SYNC (CS).
It is necessary to control the MSIOF enabling timing by the master and system.
[Workaround]
Use master mode for SPI.
If use slave mode for SPI, consider following alternative.
[Alternative]
If the master device can support handshaking, use the handshaking transmission.
For the MSIOF in SPI slave mode, use with the GPIO output for SPI handshaking; the system operation
must be tested and evaluated thoroughly by user.
Page 1 of 1
No.
011
Title
RZ/G Series, User‘s Manual: Hardware Correction
(CPG, Module Standby and Software Reset, APMU, RST)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B028A/E
5 Page
[Summary]
RZ/G Series, User's Manual correction (manual errata)
[Products]
RZ/G1H, G1M, G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change (manual correction only).
[Corrections]
1. Section 7, CPG for RZ/G1H, G1M, G1N, and G1E
1) Section 7.1, ACPɸ in Figure 7.1c for RZ/G1E (page 7-4):
Current (from): ACPɸ, 15MHz, Common Peripheral
Correction (to): - (Removed)
(because ACPɸ is unused in RZ/G1E)
2) Section 7.3, Table 7.2a,7.2b and 7.2c for RZ/G1H, G1M, G1N, and G1E (pages 7-7, 7-8, 7-9, 7-10)
Table note for USB clock (Note. 5 for G1H and G1E, Note. 4 for G1M and G1N)
Current (from): For choosing the external crystal resonator for USB_EXTAL, the acceptable variation
from 48 MHz (accuracy of frequency) is defined in section 84, Electrical Characteristics.
The maximum frequency of RCANϕ (= 8MHz) doesn’t have to be considered when
deciding the frequency of USB_EXTAL. That is, the frequency of RCANϕ is tolerant
about the variation derived from one of USB_EXTAL.
Correction (to): The maximum value of the RCAN clock frequency is defined by calculating from the
frequency of divided-by-8 of the USB clock. Note that external clock input from
USB_EXTAL pin is not supported; use the crystal resonator for the USB clock.
3) Section 7.3, Table 7.2b List of Clocks [RZ/G1M and G1N] (page 7-9):
Note (*) number in table is not correct
Current (from): *2 through *6 in table (beginning from *2)
Numbering for Notes: 1 through 5
Correction (to): *1 through *5 in table (beginning from *1)
Numbering for Notes: 1 through 5
4) Section 7.3, Table 7.2c ACPɸ for RZ/G1E (page 7-10):
Current (from): ACPɸ is defined
Correction (to): - (Removed)
(because ACPɸ is unused in RZ/G1E)
5) Section 7.3, Table 7.2b List of Clocks [RZ/G1M,G1N], ZGɸ, Maximum and Initial (page 7-9):
Current (from): 520 MHz
Correction (to): 520/312 MHz
(520 MHz for G1M, 312 MHz for G1N)
Page 1 of 2
6) Section 7.4, Table 7.5b PLL Multiplication Ratio [RZ/G1E] (page 7-11):
(gray parts (abcd) MDn settings are not supported for RZ/G1E; setting prohibited)
Current (from):
7) Section 7.5.11, Bit 15 (ZGCKSEL) of GPUCKCR for RZ/G1N (page 7-28):
Current (from):
For RZ/G1M and RZ/G1N
Initial value: 0
0: (PLL1/VCO × 1/2) × 1/3
1: (PLL1/VCO × 1/2) × 1/5
Correction (to):
For RZ/G1M, above current description is correct.
For RZ/G1N, Bit 15 description is corrected as follows.
Initial value: 1
0: Setting prohibited
1: (PLL1/VCO × 1/2) × 1/5
Page 2 of 2
2. Section 7A, Module standby and Software Reset
1) Section 7A.3.1.1, Bit 11 in figure and Table 7A.3, MSTPSR0 for RZ/G1H,G1M,G1N, and G1E (page 7A5):
Section 7A.3.2.1, Bit 11 in figure and Table 7A.14, RMSTPCR0/SMSTPCR0 for RZ/G1H,G1M,G1N, and G1E
(page 7A-28):
Current (from): MSTPST011, ARMREG assigned
Correction (to): - (reserved)
(value of the bit 11 of MSTPSR0 must not be changed from the initial value)
2) Section 7A.3.1.4, Bit 10 in figure and Table 7A.6, MSTPSR3 for RZ/G1H (page 7A-11):
Section 7A.3.2.4, Bit 10 in figure and Table 7A.17, RMSTPCR3/SMSTPCR3 for RZ/G1H (page 7A-34):
Section 7A.3.3.4, Bit 10 in figure and Table 7A.28, SRCR3 for RZ/G1H (page 7A-57):
Section 7A.3.4, Bit 10 in figure and Table 7A.38, SRSTCLR3 for RZ/G1H (page 7A-77):
Current (from): - (Reserved)
Correction (to): SCIF2
(SCIF2 bit assignment for RZ/G1H is missing in each register)
3) Section 7A.3.1.6, Table 7A.8, Bit 22 of MSTPSR5 for RZ/G1E (pages 7A-15):
Section 7A.3.2.6, table 7A.19 Bit 22 of RMSTPCR5/SMSTPCR5 for RZ/G1E (pages 7A-38):
Current (from): Thermal Sensor
Correction (to): (R-Car E2 does not support Thermal Sensor)
4) Section 7A.3.1.7, Bit 23 in figure and Table 7A.9, MSTPSR7 for RZ/G1E (page 7A-17):
Section 7A.3.2.7, Bit 23 in figure and Table 7A.20, RMSTPCR7/SMSTPCR7 for RZ/G1E (page 7A-40):
Section 7A.3.3.7, Bit 23 in figure and Table 7A.31, SRCR7 for RZ/G1E (page 7A-63):
Section 7A.3.4, Bit 23 in figure and Table 7A.41, SRSTCLR7 for RZ/G1E (page 7A-80):
Current (from): - (Reserved)
Correction (to): DU1
(DU1 bit assignment for RZ/G1E is missing in each register)
3. Section 7B, APMU for RZ/G1H, G1M, G1N, and G1E
1) Section 7B.3.4, The initial value of bits 1 and 0 of CA7PSTR/CA15PSTR (page 7B-7):
2) Section 7B.3.4, The initial value of bits 1, 0 of CA7PSTR/CA15PSTR (page 7B-8):
Note *: RZ/G1H /CA7PSTR: Initial value is equal to 00 when (MD7,MD6) = (L,H) : CA7 booting
Initial value is equal to 11 when (MD7,MD6) = (L,L): CA15 booting
RZ/G1H /CA15PSTR: Initial value is equal to 00 when (MD7,MD6) = (L,L) : CA15 booting
Initial value is equal to 11 when (MD7,MD6) = (L,H) CA7 booting
RZ/G1M /CA15PSTR: Initial value is equal to 00 when (MD7,MD6) = (L,L) : CA15 booting
RZ/G1N /CA15PSTR: Initial value is equal to 00 when (MD7,MD6) = (L,L) : CA15 booting
RZ/G1E /CA7PSTR: Initial value is equal to 00 when (MD7,MD6) = (L,H) : CA7 booting
Other than above MD[7:6] mode settings are prohibited.
No.
012
Title
RZ/G Series User‘s Manual: Hardware Correction (DU)
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B031A/E
4 Pages
[Summary]
RZ/G Series, User's Manual: Hardware Correction (manual errata)
[Products]
RZ/G1H, G1M G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change (document correction only).
[Corrections]
1) Section 24.1.1, Features (13) VSP1 Connection for RZ/G1H, G1M G1N, and G1E (page 24-3):
Current (from): Connection with the VSP1 allows the image data processed by the VSP1 to be output
directly to the display unit without an external memory. Plane 1 for the DU0 or DU1 has
been connected with the VSP1. To connect with another plane, select either plane 2 for
the DU0/DU1. Plane 1 and Plane 2 for the DU0 or DU1 has been connected with the
VSP1*1. Plane 1 for the DU0 or DU1 has been connected with the VSP1*2.
Correction (to): Connection with the VSP1 allows the image data processed by the VSP1 to be output
directly to the display unit without an external memory. VSP1-ch0 has been connected
with plane1 for the DU0 or DU1, VSP1-ch1 has been connected with either plane2 for
DU0 or DU1. VSP1-ch0 has been connected with plane1 for the DU0 or DU1, VSP1-ch1
has been connected with plane2 for the DU0 or DU1*1. VSP1-ch0 has been connected
with plane1 for the DU0 or DU1*2.
2) Section 24.3.1.3 Display Unit Mode Register n (DSMRn) for RZ/G1H, G1M G1N, and G1E:
(Red parts (abcd) are newly added or corrected)
- Bit 28 (VSPM) table description (page 24-71):
Current (from): "VSYNC pin" refers to the DU_VSYNC/DU_EXVSYNC pin indicated in table 24.1a*1.
"VSYNC pin" refers to the DU0_VSYNC/DU0_EXVSYNC pin indicated in table 24.1b or the
DU1_VSYNC/DU1_EXVSYNC pin indicated in table24.1c*2.
Correction (to): "VSYNC pin" refers to the DU_VSYNC/DU_EXVSYNC pin indicated in table 24.1a*1.
"VSYNC pin" refers to the DU1_VSYNC/DU1_EXVSYNC pin indicated in table 24.1a*3.
"VSYNC pin" refers to the DU0_VSYNC/DU0_EXVSYNC pin indicated in table 24.1b or the
DU1_VSYNC/DU1_EXVSYNC pin indicated in table24.1c*2.
- Bit 27 (ODPM) table description (page 24-71):
Current (from): "ODDF pin" refers to the DU_ODDF/DU_EXODDF pin indicated in table 24.1a*1.
"ODDF pin" refers to the DU0_ODDF/DU0_EXODDF pin indicated in table 24.1b or the
DU1_ODDF/DU1_EXODDF pin indicated in table 24.1c*2.
Correction (to): "ODDF pin" refers to the DU_ODDF/DU_EXODDF pin indicated in table 24.1a*1.
"ODDF pin" refers to the DU1_ODDF/DU1_EXODDF pin indicated in table 24.1a*3.
"ODDF pin" refers to the DU0_ODDF/DU0_EXODDF pin indicated in table 24.1b or the
DU1_ODDF/DU1_EXODDF pin indicated in table 24.1c*2.
Page 1 of 4
- Bits 26 and 25 (DIPM) table description (page 24-72):
Current (from): "DISP pin" refers to the DU_DISP pin indicated in table 24.1a*1.
"DISP pin" refers to the DU0_ DISP pin indicated in table 24.1b or the DU1_ DISP pin
indicated in table 24.1c*2.
Correction (to): "DISP pin" refers to the DU_DISP pin indicated in table 24.1a*1.
"DISP pin" refers to the DU1_DISP pin indicated in table 24.1a*3.
"DISP pin" refers to the DU0_ DISP pin indicated in table 24.1b or the DU1_ DISP pin
indicated in table 24.1c*2.
- Bit 24 (CSPM) table description (page 24-72):
Current (from): "CSYNC pin" refers to the DU_HSYNC/DU_EXHSYNC pin indicated in table 24.1a*1.
"CSYNC pin" refers to the DU0_HSYNC/DU0_EXHSYNC pin indicated in table 24.1b or
the DU1_HSYNC/DU1_EXHSYNC pin indicated in table 24.1c*2.
Correction (to): "CSYNC pin" refers to the DU_HSYNC/DU_EXHSYNC pin indicated in table 24.1a*1.
"CSYNC pin" refers to the DU1_HSYNC/DU1_EXHSYNC pin indicated in table 24.1a*3.
"CSYNC pin" refers to the DU0_HSYNC/DU0_EXHSYNC pin indicated in table 24.1b or
the DU1_HSYNC/DU1_EXHSYNC pin indicated in table 24.1c*2.
- DSMRn Table note (page 24-70):
Current (from): Notes 1. For RZ/G1M and G1M
2. For RZ/G1E
3. n = 0 and 1 [RZ/G1M, G1N, and G1E]
Correction (to): Notes 1. －
2. For RZ/G1E
3. For RZ/G1M and G1N
3) Section 24.3.1.34 Display Unit Extensional Function Control 6 Register m (DEF6Rm,m = 0 and 2):
(Red parts (abcd) are corrected or newly added)
- Bits 11 and 10 (ODPM12) table description (page 24-130):
Current (from):
"ODDF pin" refers to the DU_EXODDF/DU_ODDF pin indicated in table 24.1a*1.
"ODDF pin" refers to the DU1_ODDF/DU1_EXODDF pin indicated in table 24.1c*2.
Correction (to):
"ODDF pin" refers to the DU_EXODDF/DU_ODDF pin indicated in table 24.1a*3.
"ODDF pin" refers to the DU1_ODDF/DU1_EXODDF pin indicated in table 24.1a*7.
"ODDF pin" refers to the DU1_ODDF/DU1_EXODDF pin indicated in table 24.1c*2.
- Bits 9 and 8 (ODPM02) table description (page 24-131):
Current (from):
"ODDF pin" refers to the DU_EXODDF/DU_ODDF pin indicated in table 24.1a*1.
"ODDF pin" refers to the DU0_ODDF/DU0_EXODDF pin indicated in table 24.1b*2.
Correction (to):
"ODDF pin" refers to the DU_EXODDF/DU_ODDF pin indicated in table 24.1a*3.
"ODDF pin" refers to the DU1_ODDF/DU1_EXODDF pin indicated in table 24.1a*7.
"ODDF pin" refers to the DU0_ODDF/DU0_EXODDF pin indicated in table 24.1b*2.
Page 2 of 4
- DEF6Rm Table note (page 24-132):
Current (from): Notes: 1. For RZ/G1H, G1M, and G1N
:
6. m = 0 and 2 for RZ/G1H, m = 0 for G1M, G1N, and G1E.
Correction (to): Notes: 1. For RZ/G1H, G1M, and G1N
:
6. m = for RZ/G1H, m = 0 for G1M, G1N, and G1E.
7. For R-Car RZ/G1M and G1N
4) Section 24.3.1.36 Display Unit Extensional Function Control 8 Register m (DEF8R) (page 24-134):
Bit 6 (VSCS) table description:
Current (from): 0: VSP1 is connected with the DU1/DU0 plane 2.
1: VSP1 is connected with the DU2 plane 1.
To display the VSP1 image data, make the setting in the plane n display data control 4
register m(PnDDC4Rm*2).
This bit is not provided in the display unit extensional function control 8 register 2
(DEF8R2).
Correction (to): 0: VSP1-ch1 is connected with the DU0/DU1 plane 2.
1: VSP1-ch1 is connected with the DU2 plane 1.
To display the VSP1 image data, make the setting in the plane n display data control 4
register m(PnDDC4Rm*2).
VSP1-ch0 is always connected with the DU1/DU0 plane 1. VSP1-ch1 cannot be used at
the same time in the DU0/DU1 and DU2.
This bit is not provided in the display unit extensional function control 8 register 2
(DEF8R2).
5) Section 24.3.4.18 Plane n Transparent Color 3 Register m (PnTC3Rm, m = 0 and 2),
Table 24.24, Data Comparison by Plane n Transparent Color 3 Register m (PnTC3Rm) bit allocation (page
24-190):
Current (from):
Correction (to):
Page 3 of 4
6) Section 24.3.8.6 Display Superimpose 1 Priority Register (DS1PR) (page 24-230):
Current (from): Address: DU0: H'FEB11024
Correction (to): Address: DU1: H'FEB11024
7) Section 24.3.9.4 Cb Normalization Offset Register m (CBNOR) (page 24-238):
Bits 23 to 16 (CBNO1) table description
Current (from): The offset is an integer. Its default value is 128.
Correction (to): The offset is an unsigned 8-bit integer. Its default value is 128.
8) Section 24.4.19 Dual Display Output:
- (2) Display of Different Images on Monitors of the Same Size
Figure 24.17 Display of Different Images on Monitors of the Same Size, bottom right port description
(page 24-283):
Current (from): LVDS1 pins or DU pins*1
DU pins*2
DU1 pins*3 *4
Correction (to): DU pins*1
DU pins*2
DU1 pins*3 *4
(3) Display of the Same Image on Monitors of the Same Size
Figure 24.18 Display of the Same Image on Monitors of the Same Size, center row port description
(page 24-283):
Current (from): LVDS0 pins or DU pins*1
LVDS pins or DU pins*2
DU0 pins*3
Correction (to): DU pins*1
DU pins*2
DU0 pins*3
Page 4 of 4
No.
013
Title
Addendum for DBSC3 Pin States
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B032A/E
1 Page
[Summary]
DQS/DQS# pin states during power-on reset and default state
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (addendum only).
[Addendum]
Section 4, Pin Multiplexing: MnDQSx and MnDQSx# pins of DBSC3 (n=0, 1; 1 is available for RZ/G1H and
G1M):
Pin states during power-on reset and default state
(Red parts (abcd) are newly added)
Current (from): Z
Addendum (to): Z*
Note. *: The drivers output states are both high-impedance (Z), and the internal
circuit controls pin levels as low-level for the MnDQSx pin and high-level for the
MnDQSx# pin respectively.
Page 1 of 1
No.
014
Title
Corrections of VSP1 for RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B034A/E
1 Page
[Summary]
VSP1 VI6_WPFn_DSTM_ADDR_Y description in No.006 is corrected
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (document correction only).
[Corrections]
1. No.006 : Item 2, "2. Section 32. VSP1 forRZ/G1H, G1M, G1N and G1E"
Table number and table title in "Correction (to)" are not correct:
(gray parts (abcd) are corrected from No.006)
3) Section 32.2.8.9 WPFn Destination Y/RGB Address Registers (VI6_WPFn_DSTM_ADDR_Y) (page 32121)
Table number and table title are not corrected
Current (from): - (missing)
Correction (to): Add Table 32.26a and Table 32.26b
Page 1 of 1
No.
015
Title
Usage Notes for DBSC3 of RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B036A/E
1 Page
[Summary]
Usage notes for DBSC3 initialization sequence
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (usage note only).
[Description]
1. Section 17.4.3.1 (1) (b), DBSC3 Setting 1, bullet-sequences for RZ/G1H and RZ/G1M (page 17-73):
• SDRAM type setting register (DBKIND)
• SDRAM configuration setting register 0 (DBCONF0)
• PHY type setting register (DBPHYTYPE)
• SDRAM operation setting register (DBBL)
• SDRAM timing registers 0 to 19 (DBTR0 to DBTR19)
• ODT operation setting register 0 (DBRNK0)
• DBSC3 operation adjustment registers 0 and 2 (DBADJ0, DBADJ2)
• AXI port setting registers 0 and 4 (DBWT0CNF0, DBWT0CNF4)
- Usage Note: However there is no number of order for these sequences, they must be executed in
above order from top-bullet to bottom-bullet.
2. Section 17.4.3.1 (1) (d), DBSC3 Setting 2, bullet-sequences for RZ/G1H and RZ/G1M (pages 17-75 and
17-76):
• Bus control unit 0 control register 1 (DBBS0CNT1)
• DDR3-SDRAM calibration configuration register (DBCALCNF)
• DDR3-SDRAM calibration timing register (DBCALTR)
• Refresh configuration registers 0 to 2 (DBRFCNF0 to DBRFCNF2)
• Write H'00000004 to the PHY unit address register (DBPDRGA).
Read the PHY unit access register (DBPDRGD) and wait until 1 is read from bit 0.
• Set the ARFEN bit to 1 in the auto-refresh enable register (DBRFEN).
• Write H'00000010 to the PHY unit address register (DBPDRGA).
• Write H'F00464DB to the PHY unit access register (DBPDRGD).
• Set the ACCEN bit to 1 (access enabled) in the SDRAM access enable register (DBACEN).
• Write H'00000000 to the PHY unit lock register (DBPDLCK).
This locks the access to the PHY unit registers.
- Usage Note: However there is no number of order for these sequences, they must be executed in
above order from top-bullet to bottom-bullet.
[Document Correction]
Regarding these usage notes, each bullet-sequence items in section 17.4.3.1 (1) (b) and (d) are
numbered from 1 for top-bullet to n for bottom-bullet inclusively; n=8 for sequence (b) and n=10 for
sequence (d), in section 17.4.3.1 (1).
Page 1 of 1
No.
016
Title
RZ/G Series User‘s Manual: Hardware Corrections (CAN interface)
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B037A/E
1 Page
[Summary]
RZ/G Series, User's manual: hardware corrections (manual errata)
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (document correction only).
[Corrections]
(Red highlighted parts (abcd) are corrected)
1. Section 46.3.9, CANi Message Control Register j (CiMCTLj) (i = 0, 1; j = 0 to 63) for RZ/G1H, G1M G1N,
and G1E
(page 46-27):
Registers CiMCTL32 to CiMCTL63, 2nd-bullet item:
Current (from): Receive mailbox setting enabled (When the TRMREQ bit is "1" and the RECREQ bit is "0")
Correction (to): Receive mailbox setting enabled (When the TRMREQ bit is "0" and the RECREQ bit is
"1")
2. Section 46.5.3, Bit-rate for RZ/G1H, G1M G1N, and G1E (page 46-70):
Equation (denominator)
Current (from):
Correction (to):
Page 1 of 1
No.
017
Title
Specification Change and Usage Notes for MSIOF of RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B038A/E
1 Page
[Summary]
Specification change and usage note for MSIOF transmit clock select register (SITSCR)
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
This document includes specification change.
[Description]
Section 57.3.8, MSIOF Transmit Clock Select Register (SITSCR) for RZ/G1H, G1M G1N, and G1E (page 5718):
1. MSIMM (bit 13) table descriptions:
Master Clock Direct Select
0: Selects the clock output from the baud rate generator as the serial clock.
1: Selects the master clock itself as the serial clock.
- Specification change:
Current (from): "1" setting is available
Change (to): "1" setting is not available because this setting is not supported for the RZ/G Series.
2. BRPS[4:0] (bits 12 to 8) table description:
Prescalar Setting
These bits specify the master clock division ratio in the count value of the prescalar in the baud rate
generator.
- Usage Note:
“Master clock” means internal clock source, i.e. MPɸ (52 MHz), this clock is indicated as “Module
clock” in figure 57.1 (page 57-2). For details of MPɸ, refer to section 7, Clock Pulse Generator (CPG).
[Document Correction]
Regarding these specification change and usage note, SITSCR descriptions in reference document is
corrected as follows:
(cancelation line parts (abcd) are deleted and Red highlighted parts (efgh) are newly added)
1. MSIMM (bit 13) table descriptions:
When setting MSIMM = 1, the master clock source should be set to 26 MHz or lower.
Set 0 when MSSEL = B'00.
0: Selects the clock output from the baud rate generator as the serial clock.
1: Selects the master clock itself as the serial clock Setting prohibited.
2. BRPS[4:0] (bits 12 to 8) table descriptions:
These bits specify the master clock (MPɸ) division ratio in the count value of the prescalar in the
baud rate generator.
Page 1 of 1
No.
018
Title
QSPI Specification Change and Manual Correction of RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B040A/E
1 Page
[Summary]
LEAD/LAG signal timing is changed
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
This is a specification change and user's manual correction of the QSPI.
[Document Correction]
(cancelation line parts (abcd) are deleted (before correction) and Red highlighted parts (efgh) are newly
added (after correction))
1. Section 58.4.10, Clock Delay Register (SPCKD) (page 58-17):
SCKDL[2:0] (bits 2 to 0) setting values in table description
000: 1.5 1 SPCLK cycles
001: 2.5 2 SPCLK cycles
010: 3.5 3 SPCLK cycles
011: 4.5 4 SPCLK cycles
100: 5.5 5 SPCLK cycles
101: 6.5 6 SPCLK cycles
110: 7.5 7 SPCLK cycles
111: 8.5 8 SPCLK cycles
(LEAD time is shortened by 0.5 SPCLK cycles for each setting value.)
2. Section 58.4.11, Slave Select Negation Delay Register (SSLND) (page 58-18):
SLNDL[2:0] (bits 2 to 0) setting values in table description
000: 1 0.5 SPCLK cycles
001: 2 1.5 SPCLK cycles
010: 3 2.5 SPCLK cycles
011: 4 3.5 SPCLK cycles
100: 5 4.5 SPCLK cycles
101: 6 5.5 SPCLK cycles
110: 7 6.5 SPCLK cycles
111: 8 7.5 SPCLK cycles
(LAG time is shortened by 0.5 SPCLK cycles for each setting value.)
[Other Correction]
(Red highlighted parts (abcd) are corrected)
- QSPI clock indications in this section
Current (from): QSPICLK
Correction (to): QSPIɸ
- Table 58.3, Relationship between SPBR and BRDV[1:0] Settings, left end column of table header (page
58-15):
Current (from): SPBR[7:0] (N)
Correction (to): SPBR[7:0] (n)
Page 1 of 1
No.
019
Title
RZ/G Series User‘s Manual: Hardware Corrections (RCLK Watchdog Timer)
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B041A/E
3 Pages
[Summary]
RCLK clock frequency and overflow period are corrected
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (document correction only).
[Corrections]
(Red highlighted parts (abcd) are corrected or newly added)
1. Section 66.2.2, RCLK Watchdog Timer Control/Status Register A (RWTCSRA), Bits 2 to 0 (CKS0[2:0])
table description for RZ/G1H, G1M G1N, and G1E (page 66-4):
1) Description of 5th-line
Current (from): when the RCLK is 32.768 kHz
Correction (to): when the RCLK is 31.7 kHz*
Note. *: 1560MHz / (1024 * 48) = 31.73828125 kHz
2) Overflow periods of each setting value are corrected as follows;
Current (from):
000: Rɸ (2.0 s (RWTCNT: H'FF00 = 7.8 ms))
001: Rɸ/4 (8.0 s (RWTCNT: H'FF00 = 31.3 ms))
010: Rɸ/16 (32.0 s (RWTCNT: H'FF00 = 125.0 ms))
011: Rɸ/32 (64.0 s (RWTCNT: H'FF00 = 250.0 ms))
100: Rɸ/64 (128.0 s (RWTCNT: H'FF00 = 500.0 ms))
101: Rɸ/128 (256.0 s (RWTCNT: H'FF00 = 1.0 s))
110: Rɸ/1024 (2048.0 s (RWTCNT: H'FF00 = 8.0 s))
111: RCLK select expanded mode
The clock cycle varies depending on the CKS1 bit in RWTCSRB. Its initial value is Rɸ/4096 (8192.0 s
(RWTCNT: H'FF00 = 32.0 s)).
Correction (to):
000: Rɸ (2.1 s (RWTCNT: H'FF00 = 8.06 ms))
001: Rɸ/4 (8.2 s (RWTCNT: H'FF00 = 32.2 ms))
010: Rɸ/16 (33.0 s (RWTCNT: H'FF00 = 129.0 ms))
011: Rɸ/32 (66.0 s (RWTCNT: H'FF00 = 258.0 ms))
100: Rɸ/64 (132.0 s (RWTCNT: H'FF00 = 516.0 ms))
101: Rɸ/128 (264.0 s (RWTCNT: H'FF00 = 1.03 s))
110: Rɸ/1024 (2112.0 s (RWTCNT: H'FF00 = 8.25 s))
111: RCLK select expanded mode
The clock cycle varies depending on the CKS1 bit in RWTCSRB. Its initial value is Rɸ/4096 (8438.0 s
(RWTCNT: H'FF00 = 33.0 s)).
Note. These overflow periods are calculated from the rounded value of Rɸ=31.7 kHz.
Page 1 of 3
2. Section 66.2.3, RCLK Watchdog Timer Control/Status Register B (RWTCSRB), Bits 5 to 0 (CKS1[5:0])
table description for RZ/G1H, G1M G1N, and G1E (page 66-5):
1) Description of 5th and 6th lines
Current (from): ... H‘FF00). Assuming that Rϕ/128 = 256 s (1 s), the overflow cycle in the table is
calculated for the case when the RCLK is 32.768 kHz.
Correction (to): ... H‘FF00). Assuming that Rϕ/128 = 264 s (1.01 s), the overflow cycle in the table is
calculated for the case when the RCLK is 31.7 kHz.
2) Overflow periods of each setting value are corrected as follows;
Current (from):
Page 2 of 3
Correction (to)
Note. - (-): Reserved, - (xxx): Not recommendable
These overflow periods are calculated from the rounded value of Rɸ=31.7 kHz.
Page 3 of 3
No.
020
Title
RZ/G Series User‘s Manual: Hardware Corrections
(CPG, Module Standby and Software Reset, RST)
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B042A/E
2 Pages
[Summary]
RZ/G Series, User's Manual correction (manual errata)
[Products]
RZ/G1H, G1M G1N, and G1E (for details, refer to each correction)
[Note]
There is no specification change (document correction only).
[Corrections]
1. Section 7, CPG for RZ/G1E
1) Section 7.1, CPEXɸ in Figure 7.1c for RZ/G1E (page 7-4):
Current (from): CPEXɸ is not defined
Correction (to): CPEXɸ, 15MHz for CMT1 is newly defined
2) Section 7.3, Table 7.2c for RZ/G1E (page 7-10):
(gray highlighted parts (abcd) are newly added)
Current (from): CPEXɸ is not listed (CPɸ is different from CPEXɸ for RZ/G1E)
Correction (to): CPEXɸ is newly listed for CMT1
3) Table 7.2c, Note 3 for RZ/G1E (page 7-10):
(Red highlighted parts (abcd) are corrected)
Current (from): The frequency of CPɸ is equal to EXTAL×1/2. For example, when the frequency of
EXTAL is equal to 20 MHz, the frequency of CPCLK is equal to 10 MHz.
Correction (to): The frequency of CPEXɸ is equal to EXTAL×1/2. For example, when the frequency of
EXTAL is equal to 20 MHz, the frequency of CPEXɸ is equal to 10 MHz.
2. Section 7A, Module standby and Software Reset
(Red highlighted parts (abcd) are corrected)
1) Section 7A.3.3.6, SRCR5 Bit 8 in Table 7A.30 for RZ/G1H, G1M G1N, and G1E (page 7A-61),
Section 7A.3.4, SRSTCLR5 Bit 8 in Table 7A.40 for RZ/G1H, G1M G1N, and G1E (page 7A-79):
Current (from): SCUW
Correction (to): SCU
Page 1 of 3
3. Section 8.4.1, MODEMR Bits 17 and 16 for RZ/G1E (page 8-6):
(gray highlighted parts (abcd) are corrected)
Current (from): initial value is 0
Correction (to): initial value is 1
Page 3 of 3
No.
021
Title
Usage Note for GPIO of RZ/G Series
Applicable Product
RZ/G1H, G1M G1N, and G1E
Note for RENESAS
TN-RCS-B043A/E
1 Page
[Summary]
GPIO input is still enabled even if selecting other than GPIO function
[Products]
RZ/G1H, G1M G1N, and G1E
[Note]
There is no specification change (usage note only).
[Description]
This usage note is for the GPIO related registers; section 6.4.4, INDTn and section 6.4.5, INTDTn.
- Usage Note: The GPIO input function is still enabled even if after the pin function has been set for any
modules other than the GPIO; if the module pin setting is input, the input signal is also
propagated to the GPIO block and the GPIO input related registers are updated by the
latest input of the corresponding pin. It may occur an unexpected GPIO interrupt unless
the GPIO interrupt is not masked.
The GPIO interrupt should be masked when the multiplexed pin is used for input of other than the
GPIO function. Refer to section 6.4.7, INTMSKn for the GPIO interrupt mask.
When all GPIOn pin is not in use as the GPIO, the clock signal supply to the GPIOn block can be stopped.
Then GPIOn related registers are not updated.
Page 1 of 1
No.
022
Title
Addendum for PFC Pin Function Settings of RZ/G1M and G1N
Applicable Product
RZ/G1M and G1N
Note for RENESAS
TN-RCS-B045A/E
1 Page
[Summary]
Addendum for PFC IPSR3 and IPSR6 HSCIF functions
[Products]
RZ/G1M and G1N
[Note]
There is no specification change (addendum only).
[Description]
The following HSCIF pin functions of IPSR3 and IPSR6 registers are double assigned in one function
number on the PFC.
These bit allocations are correct and they can be specified by MOD_SEL and MOD_SEL3 registers. For
details, refer to section 5.3.11, IPSR3, 5.3.16, IPSR6, 5.3.27 MOD_SEl and 5.3.29, MOD_SEL3.
IPSR3: IP3[11:9] Function 2, HRX2_B/HRX2_D* (RD/WR# pin)
IPSR6: IP6[18:16] Function 2, HRX1_C/HRX1_E* (IRQ4 pin)
IPSR6: IP6[20:19] Function 2, HTX1_C/HTX1_E* (IRQ5 pin)
- Addendum: Note. *: These pin functions can be specified by MOD_SEL and MOD_SEL3 registers.
Page 1 of 1
No.
023
Title
Usage Notes for DBSC3 of RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B046A/E
1 Page
[Summary]
The processing order of request command may be changed by DBSC3
[Products]
RZ/G1H,G1M,G1N, and G1E
[Note]
There is no specification change (usage note only).
[Usage Note]
Following usage note is for the 1st-paragraph of (1) Basic Access in section 17.4.2, SDRAM Command
Issue
- Usage Note:
In a command processing, the DBSC3 may change the order of the command execution after
acceptance of the command request to improve the memory efficiency. This change is done by the
DBSC3 automatically within the allowance of the AXI-bus protocol, so they cannot be explicitly issued
by software.
[Description]
Example 1 (change)
Request order: (1) Read-1(ID: A) - (2) Write (ID: B) - (3) Read-2(ID: C)
DBSC3 may change execution order to improve the memory efficiency;
Execution order (1) Read-1(ID: A) - (2) Read-2(ID: C) - (3) Write (ID: B)
Example 2 (no change)
Request order: (1) Read-1(ID: A) - (2) Write (ID: B) - (3) Read-2(ID: B)
DBSC3 does not change execution order because the AXI protocol does not allow changing order
between same ID requests;
Execution order (1) Read-1(ID: A) - (2) Write (ID: B) - (3) Read-2(ID: B)
[Document Correction]
Regarding this usage note, there is following document correction;
(There is mismatched document between AXI QoS function and DBSC3 Basic Access description about
complete order.)
Section 17.4.2, SDRAM Command Issue for RZ/G1H,G1M,G1N, and G1E (page 17-71):
(Red highlighted parts (abcd) are corrected)
Current (from):
(1) Basic Access, 1st-paragraph
The DBSC3 stores in a queue the requests received via the AXI. The order for the start of request
processing changes according to whether or not this is preceded by processing for precharging or
activation, but processing is completed in the same order as the reception of requests for the queue.
Correction (to):
(1) Basic Access, 1st-paragraph
The DBSC3 stores in a queue the requests received via the AXI. The order for the start of request
processing changes according to whether or not this is preceded by processing for precharging or
activation, but processing is executed in the order allowed in AXI protocol to improve the memory
efficiency.
Page 1 of 1
No.
024
Title
Usage Note for R-GP2D of RZ/G1H
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B048A/E
1 Page
[Summary]
Register read out value is illegal in some conditions
[Products]
RZ/G1H only
[Note]
There is no specification change (usage note only).
[Usage Note]
Following usage note is for "Legend for Register Description" in section 22.2, Register Description (page
22-11).
- Usage Note:
When reading the R-GP2D registers under one of the following conditions, the first reading out value
may be illegal.
Conditions:
1) After power-on reset (PTESET#=L to H)
2) After exiting the module stop state (MSTPSR8.MSTPST807=1 to 0)
3) After drawing states; i.e., one of the following states (when using interrupt);
Rendering break (SR.BRK=1)
Command error (SR.CER=1)
Interrupt (SR.INT=1)
Trap (SR.TRA=1)
Workaround:
One dummy read should be executed after power-on reset, exiting module stop state and in the
beginning of the interrupt handling routine for the R-GP2D respectively.
Note:
When using polling to the flags of SR, this usage note and workaround are not necessary because a
read operation maybe executed in the polling.
Page 1 of 1
No.
025
Title
DVFS and AVS Specification Change of RZ/G1H,G1M, and G1N
Applicable Product
RZ/G1H,G1M, and G1N
Note for RENESAS
TN-RCS-B050A/E
3 Pages
[Summary]
DVFS and AVS function are not available
[Products]
RZ/G1H,G1M, and G1N
[Note]
This is a specification change of the DVFS and AVS functions.
[Specification Change]
- The DVFS function of the RZ/G1H,G1M, and G1N :
Current (from): Available (recommendable)
Change (to): Not available (not recommendable)
- The AVS function of the RZ/G1H,G1M, and G1N :
Current (from): Available
Change (to): Not available
[Description]
These functions may have a little effect for current products for control of the power.
[Document Correction]
Regarding this change, AVS pin description in Section 4, Pin Multiplexing is corrected as follows:
1) RZ/G1M and G1N
- Table 4.1, No.204 and 205, and Table Note 1 (page 4-9 for RZ/G1M , page 4-5 for RZ/G1N):
(cancelation line parts (abcd) are deleted and gray highlighted parts (efgh) are newly added)
Notes: 1. (No.204 and 205): Output value of the AVS[2:1] pins depends on each product.
2. (No.212): ASEBRK#/ACK pin is available for pull-down function.
- Table 4.2, No.205 and 206 (page 4-32 for RZ/G1M, page 4-29 for RZ/G1N):
Page 1 of 2
- Table Note 3 for table 4.2 (page 4-41 for RZ/G1M):
Notes:
1. No.94, 95, 98 to 106 and 108 to 129: Default Pin Function
MD[28:27],[22] = 111: DBSC3 channel 1 32-bit operation
MD[28:27],[22] = 011 or 110: GP_DDRn (n = 1 to 29) operation
2. No.134 to 187: Default Pin Function
MD[28:27],[22] = 111: DBSC3 channel 1 32-bit operation
MD[28:27],[22] = 011: DBSC channel 0 64-bit (M0DQ[63:32] enable) operation
MD[28:27],[22] = 110: Reserved except for power supply pins.
3. No.204 and 205: AVS Default State
The output is high or low, depending on product.
4. No.213 to 254: Default Pin Function
[Other Correction]
The DVFS description in RZ/G Series, User's Manual: Hardware will be removed.
2) RZ/G1H
- Table 4.1, No.205 and 206, and Table Note 2 (page 4-9):
Notes: 1. (No.191): Must be fixed to VSS.
2. (No.205 and 206): Output value of the AVS[2:1] pins depends on each product.
Page 2 of 2
- Table 4.2, No.205 and 206 (page 4-34):
- Table Note 4 for table 4.2 (page 4-40):
Notes: 1. No.94, 95, 98 to 106 and 108 to 129: Default pin function
MD[28:27], [22] = 111: DBSC3 channel 1 32-bit operation
MD[28:27], [22] = 011 or 110: GP_DDRn (n = 1 to 29) operation
2. No.134 to 187: Default pin function
MD[28:27], [22] = 111: DBSC3 channel 1 32-bit operation
MD[28:27], [22] = 011: DBSC channel 0 64-bit (M0DQ[63:32] enable) operation
MD[28:27], [22] = 110: Reserved except for power supply pins.
3. No.191: EXREFIN
Must be fixed to VSS (; not user application).
4. No.205 and 206: AVS default state
The output is high or low, depending on product.
5. No.208 to 249, 251, 252, 259, 260, and 262 to 264: Default pin function
[Other Correction]
The DVFS description in RZ/G Series, User's Manual: Hardware will be removed.
No.
026
Title
DBSC3 Specification Change of RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B052A/E
2 Pages
[Summary]
DBSC3 initialization sequence is changed
[Products]
RZ/G1H,G1M,G1N, and G1E
[Note]
This is a specification change of the DBSC3.
[Description]
The initialization sequence of the DBSC3 must be changed because the DBSC3 may enter a deadlock
state and it is necessary to execute the hardware reset again to exit from the state.
The DBSC3 has the AXI bus control brock (AXI), DDR control block including registers (DBSC3_n) and PHY
block (DDR3-PHY). The AXI bus control block and DDR control block are operating by different clocks
respectively.
Because of a hazard generated by a register write cycle during DBSC3 initialization sequence, a request
que control block of the AXI bus control block may become an unusual state (que full).
Once the DBSC3 becomes this state during initialization sequence, the DBSC3 cannot accept a request
from the AXI anymore and it causes a dead lock state of the DBSC3.
[Specification Change]
The internal hazard for this problem can be rejected by setting initialization sequence as follow.
17.4.3.1 Starting the System
(1) 64 Bits × 1-ch Mode [RZ/G1H] and [RZ/G1M]
- Both sequences (a) and (d) must be changed:
(a): Execute Setting-A of following document correction, before sequence 2.
(d): Execute Setting-B of following document correction, before bullet sequence "Set the ACCEN bit
to 1 (access enabled)
(2) 32 Bits 2-ch Mode [RZ/G1H] and [RZ/G1M], (3) and (4) 32 Bits × 1-ch Mode, [RZ/G1N,G1E] and
[RZ/G1H, RZ/G1M]
- Both sequences (a) and (d) must be changed for corresponding (1) 64 Bits × 1-ch Mode (a) and (d):
(a): Execute Setting-A of following document correction, before sequence 2.
(d): Execute Setting-B of following document correction, before bullet sequence "Set the ACCEN bit
to 1 (access enabled)
Page 1 of 2
[Document Correction]
Following and Setting-B (under-lined and encircled with red-line) are newly added for each initialization
sequence.
1. Section 17.4.3.1 Starting the System, (1) 64 Bits × 1-ch Mode [RZ/G1H,G1M]:
(a) After power is turned on, apply a power-on reset and wait until the DBSC3 is released from the reset
state.
1. After release from the reset state, set the registers as follows (page 17-73):
- Write H'0000A55A to the PHY unit lock register (DBPDLCK).
This allows the access to the PHY unit registers.
Setting-A
Write H'0000A55A to DB_ADDR + H’4000.
Write H'00000001 to DB_ADDR + H’4008.
2. Here, the setting on the M0/1RESET# signals should be executed (The following 3 lines correspond to
this setting):
:
(b) DBSC3 Setting 1
:
(c) PHY Setting 1
:
(d) DBSC3 Setting 2, bullet-sequences for RZ/G1H and G1M (pages 17-75 and 17-76):
:
• Write H'F00464DB to the PHY unit access register (DBPDRGD).
• Write H'00000000 to DB_ADDR + H’4008.
Setting-B
• Write H'00000000 to DB_ADDR + H’4000.
• Set the ACCEN bit to 1 (access enabled) in the SDRAM access enable register (DBACEN).
• Write H'00000000 to the PHY unit lock register (DBPDLCK).
:
2. Section 17.4.3.1 (2) 32 Bits 2-ch Mode [RZ/G1H,G1M], bullet-sequences for RZ/G1H and G1M (page
17-107),
(3) 32 Bits × 1-ch Mode [RZ/G1N, G1E] and (4) 32 Bits × 1-ch Mode [RZ/G1H, G1M] (page 17-76):
Following Setting-A must be executed before corresponding sequence 2 of (a), in No.1.
Write H'0000A55A to DB_ADDR + H’4000.
Setting-A
Write H'00000001 to DB_ADDR + H’4008.
In the section "(1) 64 Bits 1-ch Mode", the DBSC3_1 setting should also be executed in the flowing each
subsection;
(b) DBSC3 Setting 1
(c) PHY Setting 1
(d) DBSC Setting 2 (refer to above 64 Bits × 1-ch Mode):
Following Setting-B must be executed before corresponding sequence (d), in No.1.
:
• Write H'F00464DB to the PHY unit access register (DBPDRGD).
• Write H'00000000 to DB_ADDR + H’4008.
Setting-B
• Write H'00000000 to DB_ADDR + H’4000.
• Set the ACCEN bit to 1 (access enabled) in the SDRAM access enable register (DBACEN).
• Write H'00000000 to the PHY unit lock register (DBPDLCK).
:
Note. Initial value of area DB_ADDR + H'4000 and DB_ADDR + H'4008 is H'0000 0000.
Page 2 of 2
No.
027
Title
Limitation of Transfer Performance for MMC of RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B054A/E
2 Pages
[Summary]
MMC transfer performance is limited by internal latency and MMC_CLK stops
[Products]
RZ/G1H,G1M,G1N, and G1E
[Note]
This limitation will not be fixed.
[Limitation]
When the MMC module of the RZ/G series products operates with all of the following condition 1 to 3,
the transfer performance of the MMC interface is limited up to 35 MB/s at MMC_CLK=48.75MHz by the
internal latency.
・ Condition
1) MMC transfer data size is over 1024 bytes.
2) MMC dedicated RAM (1024 bytes) all data has been transferred.
3) MMC continues data transfer after 1024 bytes of dedicated RAM data transferred.
[Description]
The MMC has two 512 bytes (total 1024 bytes) dedicated RAMs as the transfer buffer which operates
alternately. When MMC_CLK=48.75 MHz (20.5128 ns for cycle time), it needs 512 x 20.5128 = 10,502 ns
to transfer 512 bytes data via MMC_D[7:0] pins. In this case, the transfer rate is 48.75MB/s. Otherwise,
after condition 3), the internal transfer time for 512 bytes of the dedicated RAM is calculated as follows;
512 / 4 x 11 x 10.2564 = 14,441 ns (11: internal latency of 4-byte transfer, 10.2564:internal operation
clock cycle)
This means MMC transfer is stopped for 14,441 - 10,502 = 3,939 ns and the MMC_CLK stops by each
512 bytes transfer. If this clock signal stopping is a problem for the external device, the MMC_CLK must
be set up to 14,441 / 512 = 28.2051 ns for cycle time; i.e., MMC_CLK=35.45 MHz or less. The transfer
rate is limited up to 35.45 MB/s.
[Workaround]
1. Transfer performance
There is no workaround to keep the transfer performance at 48.75 MB/s with above conditions.
Page 1 of 2
2. MMC_CLK Stopping
If MMC_CLK stopping is a problem for the external device, set the MMC_CLK frequency less than 35.45
MHz (i.e., 35.45 MB/s) by CE_CLK_CTRL.CLKDIV[3:0]. For details of CE_CLK_CTRL, refer to section 60.2.6,
CE_CLK_CTRL.
CE_CLK_CTRL setting value for less than 35.45 MHz as the MMC_CLK can be calculated as follows;
Default: CLKDIV[3:0]=B‘0000, then MMC_CLK = 97.5MHz / 2 = 48.75 MHz: not available
When CLKDIV[3:0]=B‘0001, then MMC_CLK = 97.5MHz / 4 = 24.375 MHz: available
When CLKDIV[3:0]=B‘0010, then MMC_CLK = 97.5MHz / 8 = 12.1875 MHz: available
:
:
When CLKDIV[3:0]=B‘1001, then MMC_CLK = 97.5MHz / 1024 = 0.0952 MHz: available
Other then adove: setting prohibited
(MMCnφ = 97.5MHz, MMCnCKCR.DIV[5:0]=B'000011)
Note that this calculation is not included internal bus traffic load of the SoC.
Actually, the internal latency for the MMC depends on the bus traffic, the available MMC_CLK
estimation and the system operation must be tested and evaluated thoroughly by user.
Page 2 of 2
No.
028
Title
RZ/G Series Electrical Characteristics Correction
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B056A/E
1 Page
[Summary]
Electrical characteristics corrections for RZ/G series
[Product]
RZ/G1H,G1M,G1N, and G1E
[Note]
There is no specification change (document correction only).
[Description]
1. Table 84.1, Item: Input/output voltage (pages 84-1,84-2): For RZ/G1E only
Current (from): VCCQ_SD
Correction (to): VCCQ_SD/VCCQ_MMC_SD
2. Table 84.2, Symbol: SDHI (page 84-3): For RZ/G1E only
Current (from): VCCQ_MMC_SD
Correction (to): VCCQ_MMC_SD2
3. Power Sequence (Details): Power off condition from VCCQ_LVDS to VCCQ_ISO (page 84-6): For
RZ/G1H , G1M, and G1M
Current (from): - (missing)
Correction (to): Spec.=0 (min.)
4. Power Sequence (Details): Power supply pin name of LVDS (page 84-6)
Current (from): VCCQ_LVDS
Correction (to): VDDQ_LVDS
5. Table 84.3, Symbol: 3.3-V I/O [SDHI] (page 84-12): For RZ/G1E only
Current (from): ICCQ_SD0, ICCQ_SD2, ICCQ_SD3
Correction (to): ICCQ_SD0, ICCQ_SD2/ICCQ_SD1, ICCQ_SD3/ICCQ_MMC_SD2
6. Table 84.3, Remarks: 3.3-V I/O [SDHI] (page 84-12): For RZ/G1E only
Current (from): VCCQ_SD=3.6V ([N])
Correction (to): VCCQ_SD=VCCQ_MMC_SD=3.6V ([G1N/G1E])
7. Table 84.3, Remarks of IDD_CPGPLL (page 84-13): For RZ/G1N and G1E
Current (from): (n=0, 2, 3)
Correction (to): (n=0, 1, 3)
Page 1 of 1
No.
Title
029
Document Corrections for RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B057A/E
4 Pages
[Summary]
User‘s manual for document corrections for RZ/G series
[Product]
RZ/G1H,G1M,G1N, and G1E
[Note]
There is no specification change (document correction only).
[Description]
1. Document Corrections for RZ/G Series User's Manual
1.1 Section 45, Ether
Table 45.3, Initial values of CXR15 and CXR16 for RZ/G1M and G1E (page 45-6)
Current (from): H'0007 0007 (CXR15), H'0000 0000 (CXR16)
Correction (to): H'0000 0000 (CXR15), H'0007 0007 (CXR16)
1.2 Section 45A, EtherAVB
45A.2.3, DLR 1st-line of description for RZ/G1M and G1E (page 45A-10)
Current (from): ... from the count descriptor ...
Correction (to): ... from the current descriptor ...
1.3 Section 58, Quad Serial Peripheral Interface
58.2 Features, 1st-line of 3rd-bullet; Bit rate description for RZ/G1M and RZ/G1E (page 58-1)
Current (from): SPCLK can be divided by 1 to 4080 in master mode.
Correction (to): SPCLK is generated by the on-chip baud rate generator, by dividing QSPIɸ with division
rate 1 to 4080 in master mode.
1.4 Section 63, HS-USB
Table 63.1, Reference resistance: Pin Name for RZ/G1M and G1E (page 63-2)
Current (from): REFR
Correction (to): RREF
Page 1 of 2
2. Document corrections for RZ/G Series, Electrical Characteristics
1) 84.6, LBSC Figure 84.6.3, DRACK0 signal for RZ/G1M and G1E (page 84-28)
Current (from): tDDRQ
Correction (to): tDDRK
2) 84.7, DBSC3 Figure 84.7.4, Address signal for RZ/G1M and G1E (page 84-39)
Current (from): - (missing)
Correction (to): M*A[15:0] for 2nd-signal group
3) 84.7, DBSC3 Figure 84.7.7, Address signal for RZ/G1M and G1E (page 84-40)
Current (from): - (missing)
Correction (to): M*A[15:0] for 2nd-signal group
4) 84.7, DBSC3 Figure 84.7.8, DQS signal for RZ/G1M and G1E (page 84-40)
Current (from): tRDQSH, tRDQSL
Correction (to): tRQSH, tRQSL
5) 84.19, SCIFA/B Table 84.19.1 and 84.19.2, Symbol of SCK clock for RZ/G1M and G1E (page 84-64)
Current (from): tSCWHO, tSCWLO
Correction (to): tSCWH, tSCWL
6) 84.22, IIC Table 84.22.2, Symbol for RZ/G1M and G1E (page 84-69)
Current (from): Rp (Cb<100pF)
Correction (to): Rp (Cb=100pF)
7) 84.22, IIC Figure 84.22.2, Symbol of spike suppression for RZ/G1M and G1E (page 84-69)
Current (from): VSP
Correction (to): tSP
Note. Figure number will be corrected as 84.22.1.
Page 2 of 2
No.
030
Title
Specification Change for VSP1 of RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for Renesas
TN-RCS-B059A/E
1 Page
[Summary]
YCbCr422 format cannot be used to DU input
[Products]
RZ/G1H,G1M,G1N, and G1E
[Note]
This is a specification change for the VSP1.
[Specification Change]
YCbCr422 format from the VSP1 cannot be used for DU input format.
[Description]
However the VSP1 can output both YCbCr444 and YCbCr422 formats, the DU can handle only YCbCr444
format.
[Document Correction]
Regarding this change, reference document is corrected as follows:
Red-highlighted parts (abcd) are corrected.
- Section 32.2.19.1, VI6_LIF_CTRL for RZ/G1H,G1M,G1N, and G1E (page 32-200):
Bit 4 (CFMT) Description
Current (from): Chroma Format
0: YCbCr444 or RGB Format
1: YCbCr422 Format
Correction (to): Chroma Format
0: YCbCr444 or RGB Format
1: Reserved
Note. ARBG8888 or RGB888 can be used for DU input format.
[Other Corrections]
Red-highlighted parts (abcd) are corrected (document correction only).
- Section 32.2.16.1, VI6_BRU_INCTRL, Bits 14 to 12 (DITH3 [2:0]) Table description for RZ/G1H,G1M,G1N,
and G1E(page 32-158):
Current (from): 010: Dithering of BRUin3 input image at 12 bpp
(RGB666: 4,096 colors)
101: Dithering of BRUin3 input image at 8 bpp
(RGB666: 256 colors)
Correction (to): 100: Dithering of BRUin3 input image at 12 bpp
(RGB444: 4,096 colors)
101: Dithering of BRUin3 input image at 8 bpp
(RGB332: 256 colors)
Page 1 of 1
No.
031
Title
Specification Change for SSI of RZ/G Series
Applicable Product
RZ/G1H,G1M,G1N, and G1E
Note for RENESAS
TN-RCS-B060A/E
1 Page
[Summary]
SSI input and output clock cycle times are changed
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
This is a specification change for the SSI.
[Specification Change]
Table 84.12.1, SSI Interface Signal Timing: Max values of tO and tI are changed (page 84-52) for all
products
Gray highlighted parts (abcd) are changed.
Current (from):
Change (to):
Page 1 of 1
No.
032
Title
Usage Note for SCU of RZ/G Series
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B061A/E
1 Page
[Summary]
Additional usage note for SCU in No007; 2) of Correction 1
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
However this is a usage note for the SCU, that specification is not changed.
[Usage Note]
In addition, if the SSI module operates in master mode, and if the WS signal is used as "input/output
timing signal for the SRC",set SSIWSRn.CONT to 1.
(The WS signal inputted into the ADG module is the same signal as the SSI_WS terminal.)
[Description]
No008 describes usage note as follows;
38.2.6 Note on Usage of the SCU Module (page 38-14)
Before starting data transfer, the SCU module needs certain “input data timing” and
“output data timing”.
When “input data timing” and “output data timing” are not inputted before
the transmission start, it does not operate correctly.
The additional usage note follows above 38.2.7, in section 38, AUDIO for RZ/G1H,G1M,G1N and G1E.
Unless SSIWSRn.CONT is set to 1, the SCU may not operate correctly. For details of SSIWSRn, refer to
section 39A.2.5.
Page 1 of 1
No.
033
Title
Specification Change for FDP1 of RZ/G Series
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B062A/E
1 Page
[Summary]
Channel Activation Register (FD1_CTL_CHACT) settings are changed in active 2D/3D and fixed 3D modes
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
This is a specification change for the FDP1.
[Specification Change]
Values in table 31.5, FD1_CTL_CHACT Setting for FD1_IPC_MODE.DIM Parameter are changed as follows
(page 31-16):
Gray highlighted parts (abcd) are changed.
Page 1 of 1
No.
034
Title
RZ/G Series, User's Manual: Hardware Correction (DU)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B063A/E
2 Pages
[Summary]
RZ/G Series User's Manual: Hardware Correction (manual errata)
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
There is no specification change (document correction only).
[Correction]
Red parts (abcd) are newly added or corrected.
1. Tables 24.10 and 24.11 in section 24.2 (3), (e) Alpha Plane Register Configuration
Current (from): - (missing)
Correction (to): following two registers are newly added respectively
Offset
Address
Access
Size
Alpha-ratio plane n
display
data control 4
register m
APnDDC4Rm
R/W
H'A490
32bits
All bits
Alpha-ratio plane n
display
data control 4
register
APnDDC4R
 -
-
RZ/G1E
R/W
RZ/G1N
Abbr.
RZ/G1H
Register name
Bit with
Internal
Update
Function
RZ/G1M
Table 24.10 Alpha Plane Register Configuration (1): pages 24-52 to 24-53
-
-
 

RZ/G1E
-
-
 

Abbr.
Power-on Reset
Alpha-ratio plane n
display data control 4
register m
APnDDC4Rm
H'**** ****
 -
Alpha-ratio plane n
display data control 4
register
APnDDC4R
-
RZ/G1E
Register name
RZ/G1M
RZ/G1M
Table 24.11 Alpha Plane Register Configuration (2): pages 24-54 to 24-55
Page 1 of 2
2. Section 24.3.1.3, DSMRn: General description (page 24-71, and refer to ,No002 item 2 of correction 8)
Current (from): For the RZ/G1H, G1M, and G1N this register setting is also available for the
display data output via the LVDS.
Correction (to): For the RZ/G1H, G1M, and G1N all bit in this register setting is also available
for the display data output via the LVDS.
3. Section 24.3.4.23, PnDDC4R Address notation (page 24-198)
Current (from): DU0: H'FEB00#90, DU2: H'FEB40#90 (unused for the alpha-ratio planes)
Correction (to): DU0: H'FEB00#90, DU2: H'FEB40#90 (Alpha ratio plane address: DU0: H'FEB0A#90,)
4. Section 24.4.5 (4), YC: YUV422 Formula of G (page 24-261)
Current (from): G = YNC × (Y − YNO) + GCRCR × (Cr − CRNO) − GCBC × (Cb − CBNO)
Correction (to): G = YNC × (Y − YNO) − GCRCR × (Cr − CRNO) − GCBC × (Cb − CBNO)
Page 2 of 2
No.
035
Title
Limitation of MDT Pin Monitor Registor for RST of RZ/G1H
Applicable Product
RZ/G1H
Note for RENESAS
TN-RCS-B064A/E
2 Page
[Summary]
RZ/G1H Mode Monitoring Register (MODEMR) value for MDT[1:0] is illegal
[Products]
RZ/G1H only
[Note]
This limitation will not be fixed.
Other than RZ/G1H, this limitation is not corresponding.
[Limitation]
When reading the MODEMR in the RST module of the RZ/G1H, the read values from the 30th bit (MDT1)
and 29th bit (MDT0) are always 0 respectively.
[Description]
Section 8.4.1, Mode Monitoring Register (MODEMR) for RZ/G1H (page 8-5)
Although the values of 30th bit (MDT1) and 29th bit (MDT0) of MODEMR depend on the mode setting
of them in the following specification, they are always read as 0 in the RZ/G1H. Note that the internal
mode signals of MDT1 and MDT0 are correct.
[Specification Change]
Values in table 31.5, FD1_CTL_CHACT Setting for FD1_IPC_MODE.DIM Parameter are changed as follows
(page 31-16):
Gray highlighted parts (abcd) are changed.
MODEMR of RZ/G1H
Page 1 of 1
[Workaround]
There is no workaround.
It is impossible to confirm the settings of MDT1 and MDT0 by MODEMR for RZ/G1H, confirm it by
external pins setting by users.
[Document Correction]
Regarding this limitation, description of MODEMR is corrected as follows (page 8-5).
Section 8.4.1, Mode Monitoring Register (MODEMR): Bits 30 and 29 table description for RZ/G1H
Current (from): Refer to above "Description"
Correction (to):
Following gray highlighted parts (abcd) are corrected.
No.
036
Title
Trademark Notation Correction of RZ/G Series
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B065A/E
1 Page
[Summary]
Notation for ARM Cortex-A series CPU cores and AMBA are not correct in related documents of RZ/G
Series
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
There is no specification change (notation correction only).
Cortex and AMBA are registered trademarks of ARM Limited.
All trademarks and registered trademarks are the property of their respective owners.
In this technical update, notation about trademarks or registered trademarks are omitted. Refer to
reference documents for these notations.
[Correction]
Cortex-A series notations as the CPU cores and AMBA notations in each document listed in table 1 are
corrected as follows.
Current (from): CA15, CA7, CortexTM, and AMBA4®
Correction (to): Cortex-A15, Cortex-A7, Cortex®, and AMBA® 4 respectively
Table 1 Reference Document
Product
Document Title or Category
Revision
Document No.
RZ/G1H
RZ/G1H User’s Manual; Hardware
0.50
R01UH0627EJ0050
RZ/G1M
RZ/G1M User’s Manual; Hardware
0.50
R01UH0626EJ0050
RZ/G1N
RZ/G1N User’s Manual; Hardware
0.50
R01UH0628EJ0050
RZ/G1E
RZ/G1E User’s Manual; Hardware
0.50
R01UH0544EJ0050
All
RZ/G Series User’s Manual; Hardware
0.50
R01UH0543EJ0050
All
RZ/G Series Document Errata
for RZ/G Series
1.00
ICTS1-IMB-15-0XXX
[Description]
In the documents about the RZ/G Series listed in table 1, the notation that means the Cortex-A15 CPU
and Cortex-A7 CPU are corrected from CA15 and CA7 to Cortex-A15 and Cortex-A7 except for the index
of related registers, bits/flags, signals, and sub-systems other than CPU cores.
Furthermore, trademark notation for ARM Cortex is corrected from TM (trademark) to ® (registered
trademark), and for AMBA
the ® position is corrected from AMBA4® to AMBA® 4 for corresponding descriptions.
These notation in the newly published documents will be corrected from now on.
Page 1 of 1
No.
037
Title
Corrections of No.031 and DU Register Suffixs for RZ/G Series
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B066A/E
1 Page
Following Red parts (abcd) are corrected.
[Summary]
Alpha-plane register offset address in technical update and register suffix in user's manual: hardware are
corrected
[Products]
RZ/G1H, G1M, G1N, and G1E
[Note]
There is no specification change (document correction only).
[Corrections]
1. No.031: Item 1, newly added APnDDC4Rm and APnDDC4R offset address (n=1, 2, 3)
Current (from): H'A490
Correction (to): H'A#90
(for Table 24.10 Alpha Plane Register Configuration (1): pages 24-52 to 24-53 in user's
manual: hardware)
Note. #: Replaces n (in hexadecimal) in addresses.
n = 1, 2 for RZ/G1H, G1M, G1N, and G1E
2. Section 24.3.1.18, DEFRm, suffix m for this register
Current (from): m
Correction (to): m/n
Note. However, there are two notation for this register as DEFRm and DEFRn, they are
same register.
For DEFRm and DEFRn,
m/n = 0 and 2 for RZ/G1H,DU2 only for RZ/G1H.
m/n = 0 for RZ/G1M, G1N and G1E.
For m/n = 1 (DEFR1), refer to section 24.3.1.19, DEFR1.
Page 1 of 1
No.
038
Title
RZ/G1E Electrical Characteristics Correction
Applicable Product
RZ/G1E
Note for RENESAS
TN-RCS-B067A/E
1 Page
Following Red parts (abcd) are corrected.
[Summary]
Electrical Characteristics has irrelevant contents and RZ/G1E power name suffix is not correct in AC
timing condition (MMC)
[Products]
RZ/G1E only
[Note]
There is no specification change (document correction only).
[Corrections]
1. Table 84.25.1, MMC Signal Timing: Table conditions (page 84-79)
Current (from): VCCQ_SDn
Correction (to): VCCQ_SDn/VCCQ_MMC_SD2 ([E] only)
Page 1 of 1
No.
039
Title
Correction of No.011 and RZ/G Series User's Manual:
Hardware (Module Standby and Software Reset)
Applicable Product
RZ/G1H, G1M, G1N, and G1E
Note for RENESAS
TN-RCS-B068A/E
5 Pages
Following Red parts (abcd) are corrected
.
[Summary]
No.011 and RZ/G Series User's Manual: Hardware correction (manual errata)
[Products]
RZ/G1H, G1M, G1N and G1E (for details, refer to each correction)
[Note]
There is no specification change (document correction only).
[Corrections]
1. No.011 Corrections
1) Item 2) of correction 1, Section 7, CPG for RZ/G1H, G1M, G1N, and G1E
Section 7.3, Table 7.2b and 7.2d for RZ/G1H, G1M, G1N, and G1E (pages 7-6, 7-7)
Correction is described as follows (for RZ/G1H, G1M, G1N, and G1E):
Correction (to): The maximum value of the RCAN clock frequency is defined by calculating from the
frequency of divided-by-8 of the USB clock. Note that external clock input from
USB_EXTAL pin is not supported; use the crystal resonator for the USB clock.
2nd-line in above correction is corrected as follows.
Current (from): divided-by-8 of...
Correction (to): divided-by-6 of...
Note. RCAN clock frequency is calculated as follows;
48 MHz / 6 = 8 MHz
Here, frequency of USB_EXTAL/USB_XTAL is using 48 MHz resonator.
2) Item 2) of correction 2, Section 7A, Module standby and Software Reset;
Section 7A.3.3.7, Bit 23 in figure and Table 7A.31, SRCR7 for RZ/G1E (page 7A-63)
Section 7A.3.4, Bit 23 in figure and Table 7A.41, SRSTCLR7 for RZ/G1E (page 7A-80)
However, No.010 correction is described as follows for these two registers;
Correction (to): DU1
Correctly bits 23 of SRCR7 and SRSTCLR7 are not available for the RZ/G1E; bits 23 of these two registers
are still reserved as described in reference document.
This means DU software reset control is available only for all DU channels at the same time.
Refer to following 3) and 4) of 2, User's Manual: Hardware Corrections, too.
(This correction is equivalent to following 3) and 4) of 2 for User's Manual: hardware)
Note that each bit 23 of MSTPSR7 and RMSTPCR7/SMSTPCR7 is available for DU1 control of the RZ/G1E
as described in No.011.
Page 1 of 5
2. User's Manual: Hardware Corrections
1) Section 7A.3.1.10, MSTPSR10: Table 7A.12, Bits 31 and 24 to 22 (page 7A-23)
SRC0 and SCR7-9 are not available for RZ/G1E
Current (from):
Assignment of Modules to Bits in MSTPSR10
Bit
RZ/G1M
RZ/G1E
31
SCU(SRC0)
SCU(SRC0)
30
SCU(SRC1)
SCU(SRC1)
:
:
:
25
SCU(SRC6)
SCU(SRC6)
24
SCU(SRC7)
SCU(SRC7)
23
SCU(SRC8)
SCU(SRC8)
22
SCU(SRC9)
SCU(SRC9)
:
:
:
Current (to):
Assignment of Modules to Bits in MSTPSR10
Bit
RZ/G1M
RZ/G1E
31
SCU(SRC0)
-
30
SCU(SRC1)
SCU(SRC1)
:
:
:
25
SCU(SRC6)
SCU(SRC6)
24
SCU(SRC7)
-
23
SCU(SRC8)
-
22
SCU(SRC9)
-
:
:
:
Page 2 of 5
2) Section 7A.3.2.10, RMSTPCR10/SMSTPCR10: Table 7A.23, Bits 31 and 24 to 22 (page 7A-46)
SRC0 and SCR7-9 are not available for RZ/G1E
Current (from):
Assignment of Modules to Bits in RMSTPCR10 and SMSTPCR10
Bit
RZ/G1M
RZ/G1E
31
SCU(SRC0)
SCU(SRC0)
30
SCU(SRC1)
SCU(SRC1)
:
:
:
25
SCU(SRC6)
SCU(SRC6)
24
SCU(SRC7)
SCU(SRC7)
23
SCU(SRC8)
SCU(SRC8)
22
SCU(SRC9)
SCU(SRC9)
:
:
:
Current (to):
Assignment of Modules to Bits in RMSTPCR10 and SMSTPCR10
Bit
RZ/G1M
RZ/G1E
31
SCU(SRC0)
-
30
SCU(SRC1)
SCU(SRC1)
:
:
:
25
SCU(SRC6)
SCU(SRC6)
24
SCU(SRC7)
-
23
SCU(SRC8)
-
22
SCU(SRC9)
-
:
:
:
Page 3 of 5
3) Section 7A.3.3.7, SRCR7: Bit configuration and Table 7A.31, Bits 24 to 22 (page 7A-63)
DU software reset control is available only for all DU channels at the same time for RZ/G1H, G1M, G1N,
and G1E.
Current (from):
Assignment of Modules to Bits in SRCR7
Bit
RZ/G1H
RZ/G1M G1N
RZ/G1E
24
DU0
DU0
DU0
23
DU1
DU1
DU11)
22
DU2
-
-
:
:
:
:
Current (to):
Assignment of Modules to Bits in SRCR7
Bit
RZ/G1H
RZ/G1M G1N
RZ/G1E
24
DU0,DU1,DU2
DU0,DU1
DU0,DU1
23
-
-
-1)
22
-
-
-
:
:
:
:
Note. 1) Bit 23 for RZ/G1E is corrected again because it has been corrected by No.010, item 2) of
correction 2.
Page 4 of 5
4) Section 7A.3.4, SRSTCLR7, Table 7A.41, Bits 24 to 22 (page 7A-73~74)
DU software reset control is available only for all DU channels at the same time for RZ/G1H, G1M, G1N,
and G1E.
Current (from):
Assignment of Modules to Bits in SRSTCLR7
Bit
RZ/G1H
RZ/G1M G1N
RZ/G1E
24
DU0
DU0
DU0
23
DU1
DU1
DU11)
22
DU2
-
-
:
:
:
:
Current (to):
Assignment of Modules to Bits in SRSTCLR7
Bit
RZ/G1H
RZ/G1M G1N
RZ/G1E
24
DU0,DU1,DU2
DU0,DU1
DU0,DU1
23
-
-
-1)
22
-
-
-
:
:
:
:
Note. 1) Bit 23 for RZ/G1E is corrected again because it has been corrected by No.010, item 2) of
correction 2.
Page 5 of 5