Copyright © 2010 IEEE
Reprinted from
European Microwave Conference (EuMC), 28-30 Sept. 2010, Paris, pp 69-72
This material is posted here with permission of the IEEE. Such permission
of the IEEE does not in any way imply IEEE endorsement of any of Universität Ulm's
products or services. Internal or personal use of this material is
permitted. However, permission to reprint/republish this material for
advertising or promotional purposes or for creating new collective works
for resale or redistribution must be obtained from the IEEE by writing to
pubs-permissions@ieee.org.
By choosing to view this document, you agree to all provisions of the
copyright laws protecting it.
Proceedings of the 40th European Microwave Conference
A PLL with Ultra Low Phase Noise for Millimeter
Wave Applications
Xiaolei Gai, Gang Liu, Sébastien Chartier ∗ , Andreas Trasser and Hermann Schumacher
Institute of Electron Device and Circuits, University of Ulm
Albert-Einstein-Allee 45, 89081 Ulm Germany
∗
EADS Defense & Security T/R Modules and MMICs
Wörthstrasse 85, 89077 Ulm, Germany
xiaolei.gai@uni-ulm.de
Abstract— An ultra low noise phase locked loop (PLL) for
millimeter wave applications is presented. The complete design
includes a mixer type phase detector, a divide-by-32 frequency
divider, a VCO and an off-chip active low pass filter. A method
for the phase noise optimization of the PLL is described. The
chip was designed using a 0.8 µm SiGe HBT technology. The
frequency can be tuned from 29.9 GHz to 33.1 GHz. The output
phase noise is around -112 dBc/Hz at 1 MHz offset.
II. C IRCUIT T OPOLOGY
A 3 order linear type PLL was designed in this work as
shown in Fig. 1, which included a mixer type phase detector,
a divide-by-32 frequency divider, a VCO and an active low
pass loop filter. The phase detector, divider, and VCO were
integrated on chip; the loop filter was designed off chip due
to the technology limitation to achieve sufficient output voltage
swing for tuning the VCO frequency. The complete circuit was
designed in differential structures using a 0.8 µm SiGe HBT
technology. The SIC-npn transistor (with selectively implanted
collector) improves the fT from 50 GHz (for non-SIC npn
transistor) to 80 GHz, at the price of a lowered collectoremitter breakdown voltage (BVCEO ) of 2.4 V (4.3 V for nonSIC npn transistor).
rd
I. I NTRODUCTION
In wireless communication systems, when the operating
frequency increases up to the millimeter wave range, the noise
performance becomes more and more a critical factor that
limits the overall performance of the systems. The spectrum
purity of the local oscillator can directly influence the noise
level of the transceiver. For example, in Synthetic Aperture
Radar (SAR) applications, the phase noise will consequently
degrade the SAR imaging [1]. Therefore, frequency synthesis
of local oscillator signals requires a well behaved PLL with
low phase noise.
Phase noise, spur level and lock time are 3 main parameters in PLLs designs, which all highly depend on the
loop bandwidth ωn . For the phase noise at offset frequencies
lower than ωn , the noise of the phase detector, the low pass
loop filter and the divider dominates the overall phase noise,
while for the noise at offset frequencies higher than ωn , the
phase noise of the VCO dominates the overall phase noise.
As a rule of thumb, the loop bandwidth is in the range of
0.1 to 0.01 of the comparison frequency [2]. The lock time
is inversely proportional to the loop bandwidth. Therefore,
a higher comparison frequency is required to achieve fast
locking. A more conventional PLL topology for frequency
synthesis in modern communication systems is using a 3state phase frequency detector (PFD) for phase error detection
[3][4][5]. However, this type of phase detector has certain
limitations in terms of noise performance and operating speed.
When the comparison frequency increases, the noise of the
PFD becomes critical for the phase noise of the PLL at the
offset frequencies lower than the loop bandwidth. In this work,
a mixer type phase detector was chosen to achieve better noise
performance.
978-2-87487-016-3 © 2010 EuMA
Low pass
filter
Ref 1 GHz
VCO
32GHz
Mixer
divide
by 32
Fig. 1.
32 GHz
Block diagram of the 3rd order linear PLL
A. Phase detector
Instead of the 3-state PFD, a mixer type phase detector was
used for this design as its noise is relatively lower and quasi
independent on the comparison frequency. However, it has a
very poor phase detecting range, which is limited to 180o .
For practical applications in wide locking range PLLs, a phase
frequency detector can be used as assistant to enlarge the phase
detecting range in the phase locking process [6].
Fig. 2 shows the topology of the mixer type phase detector,
which combines a Gilbert mixer core and an output buffer.
The low frequency noise, here especially the 1/f noise, around
the DC component will influence the overall phase noise
performance. Since the 1/f noise in the transconductance will
be up converted to the high comparison frequency, the low
frequency noise at the phase detector output will mainly
69
28-30 September 2010, Paris, France
VCC
VCC
Output
VCO+
*L
*u
Vb2
VCORef+
Ref-
Vb1
TFMSL
Vtune
Fig. 2.
Simplified schematic of the mixer type phase detector
depend on the mixer switching pairs [7]. 1/f noise in HBT
is proportional to the current density of the collector [8].
However, a too low collector current density will limit the
speed of the transistors, which will degrade the phase detecting
range. Trade-off was made between the noise performance
and the phase detecting range. Two capacitors were added in
parallel with the load resistors to attenuate the up converted
components at the detector output.
Fig. 3.
Schematic of VCO core with output buffer
in the PLLs design, the advantage of this type of loop filter
is that it has an infinite hold-in range as long as the output
voltage swing of the op-amps is sufficient [11].
B. Frequency dividers
Two types of frequency dividers are suitable for millimeter
wave and microwave signals dividing: dynamic frequency
divider and static frequency divider. Dynamic frequency
dividers are well known for their high operating frequency,
while static frequency dividers have relatively large input
dynamic range and better output signal waveforms. Here,
a divide-by-32 divider was designed using 5 stages. The
first two stages were dynamic dividers with additional
transimpedance amplifiers, and the remaining 3 stages were
static frequency dividers. More details were discussed in [9].
Vin+
_
Vin-
+
Fig. 4.
Vout
Active PI low pass filter
III. P HASE N OISE S IMULATION
C. VCO
The overall phase noise of this PLL can be estimated from
[2], as shown in Eq. 1:
A differential negative resistance VCO was used as shown
in Fig. 3. The VCO is a modified design from the one in
[10] with smaller tuning range. Diode varactors were used
for frequency tuning. The inductors were realized using Thin
Film Microstrip Lines (TFMSL). Compared with the spiral
inductors, the inductance of microstrip lines is easier to adjust.
The TFMSLs were simulated using EM simulation tools
(Momentum and Sonnet). Capacitive degeneration was used
to generate a negative resistance looking into the base node,
and the base inductor was used to complete the resonance
circuits. A common-base stage was cascaded to the VCO core
as an output buffer to increase the output power and isolate
the VCO core from the load. The VCO has two differential
output branches, which can feed the mixer and the frequency
divider respectively.
1
1
+ P NF lt ·
Kφ
Kφ Z(s)
(1)
G
1
+ P NV CO ·
+ P NDiv ) ·
1 + GH
1 + GH
where P NRef , P NDiv and P NV CO are the phase noise of
the reference signal, frequency divider and VCO; P NP D and
P NF lt are the intrisic voltage noise of the phase detector and
the low pass filter; G is the loop gain and H represents the
feedback factor as in Eq. 2 and Eq. 3:
P NP LL = (P NRef + P NP D ·
G = Kφ Z(s)
KV CO
s
(2)
1
(3)
N
where Kφ is the phase error gain of the phase detector , KV CO
is the gain of the VCO, and Z(s) is the transfer function of the
loop filter and N is the divider ratio of the frequency divider.
The simulated phase error gain of the phase detector Kφ is
H=
D. Low pass loop filter
An active PI low pass filter was designed off chip which is
shown in Fig. 4. The operational amplifier is a 350 MHz low
noise high speed amplifier THS4021 from Texas Instruments.
As compared with the passive and other types of active filters
70
1 V/rad; the gain of the VCO KV CO is 1.2 GHz/V at 32 GHz
center frequency.
To simulate the overall phase noise, the noise parameter
of each block of the PLL should be known. The noise
performances of the phase detector and frequency divider were
achieved from the simulation results, due to measurement
difficulties; the phase noise of the VCO was assessed directly
from the measurement results of the free running VCO; the
low frequency noise of the active filter was modeled following
the data sheet of the noise performance of the operational
amplifier; and the phase noise of the 1 GHz reference was
taken from the data sheet of a SAW crystal oscillator CCSO914X3-1000 from CRYSTEK. Fig. 5(a) shows the noise
performance of each individual block of the PLL.
−20
PD
Ref
Divider
Filter
VCO
No VCO*
−40
Phase noise, dBc/Hz
Fig. 5(a). Then, assume the loop bandwidth is zero, which
means GH << 1, the phase noise is contributed only by the
VCO; as for this design, the phase noise of the PLL will be
the phase noise of the free running VCO. Now, the optimum
loop bandwidth will be the offset frequency where the VCO
has the phase noise of -120 dBc/Hz, which is around 20 MHz.
However, the reference spur level is also dependent on the loop
bandwidth; a high loop bandwidth implies a high spur level.
The simulated spur attenuation value at 2 GHz offset for the
20 MHz loop bandwidth is around 130 dB. Therefore, the spur
noise can be neglected in this design.
Fig. 5(b) shows the noise contribution of each block to the
overall output noise: for low offset frequencies up to around
300 KHz inside the loop bandwidth, the reference dominated
the output noise; for medium offset frequencies from around
300 KHz to 15 MHz inside the loop bandwidth, the noise
was dominated by the divider and the phase detector; and the
VCO dominates the phase noise at offset frequencies outside
the loop bandwidth.
−60
−80
IV. L AYOUT AND M EASUREMENT
The layout of the phase detector, frequency divider and
VCO is shown in Fig. 6(a), which has chip area of 1.2 mm2 .
Transmission lines were folded to save chip area. The chip
size and shape were not optimized for this evaluation version.
The off-chip active loop filter was mounted on a PCB as
shown in Fig. 6(b). The useful frequency range of the active
low pass filter has an upper limit of approximate tens of MHz;
widths of the signal lines on board were optimized to reduce
the parasitic effect as much as possible.
−100
−120
−140
−160
10
2
10
3
10
4
(a)
5
6
10
10
Frequency,Hz
10
7
10
8
10
9
−80
Phase noise, dBc/Hz
−100
−120
−140
−160
−180
−200
−220
−240
102
(b)
Total
PD
Ref
Divider
Filter
VCO
103
(a)
104
105
106
Frequency,Hz
107
108
109
Fig. 5. (a) Phase noise or equivalent phase noise of each block of the PLL
*Noise of the PLL with an infinitely large loop bandwidth (b) Phase noise
contribution of each block to the overall phase noise of the PLL
(b)
The loop bandwidth needs to be designed properly to
achieve good phase noise performance, the following method
can be simply used: First, assume the loop bandwidth is
infinitely large, which means GH >> 1, the overall phase
noise is contributed by the other blocks of the PLL but the
VCO; as for this design, according to Eq. 1, the phase noise
of the reference, the phase detector and the frequency divider
will be summed and multiplied by the divide ratio 32, which
now has a noise floor of around -120 dBc/Hz, as shown in
Fig. 6. (a) Layout of the phase detector, divider and VCO using SiGe HBT
technology (b) Test board of the PLL with off chip active loop filter
On wafer measurement was done using an Agilent 8565 EC
spectrum analyzer to measure the output spectrum of the PLL.
The reference signal generator was an Agilent 8254A. While
sweeping the reference signal from 934 MHz to 1.03 GHz,
the PLL maintains the locked state, resulting in the output
71
TABLE I
frequency between 29.9 GHz and 33.1 GHz, which covers
the complete tuning range of the free running VCO. The
differential output power of the PLL at 32 GHz is around
0.3 dBm by taking into account of the cable and probe losses.
The output spectrum at 32 GHz is shown in Fig. 7 with a span
of 100 MHz . The bandwidth of the PLL is around 15 MHz.
It has a slight variation during the frequency sweep due to the
non-constant gain of the VCO for different tuning voltages.
M EASURED PERFORMANCE COMPARED WITH PRIOR PUBLISHED WORKS
Frequency
(GHz)
Tuning Range
(GHz)
Phase Noise
(dBc/Hz)
1 MHz offset
Power
(mW)
−10
RBW: 1MHz
−20
Technology
VBW: 1MHz
SWP: 0.05s
Power, dBm
−30
[5]
This Work
32
18
20
32
3.5
1.4
1.8
3.2
-81
-110
-101.2
-112
287.5
-
480
684
0.25 µm
BiCOMS
0.25 µm
BiCMOS
0.13 µm
CMOS
0.8 µm
HBT
V. C ONCLUSIONS
An ultra low phase noise PLL was realized for millimeter
wave applications using a SiGe HBT technology. Methods for
the loop bandwidth design and the phase noise simulation of
the PLL were discussed. Measurement results showed that
this PLL had achieved very good phase noise performance
of around -112 dBc/Hz at 1 MHz offset at 32 GHz oscillation
frequency; it has a tuning range of around 3 GHz.
−50
−60
−70
−80
−90
31.95 31.96 31.97 31.98 31.99
32
32.01 32.02 32.03 32.04 32.05
Frequency,GHz
−60
−80
−100
−120
−140
103
104
105
106
Offset frequency, Hz
107
R EFERENCES
[1] G. Krieger and M. Younis, “Impact of Oscillator Noise in Bistatic
and Multistatic SAR,” IEEE GEOSCIENCE AND REMOTE SENSING
LETTERS, vol. 3, no. 3, pp. 424–428, July 2006.
[2] D. Banerjee, PLL Performance, Simulation, and Design, Fourth Edition.
Dog Ear Publishing, 2006.
[3] J. Lee, S. Lee, H. Kim, and H. Yu, “A 28.5 - 32-GHz Fast Settling
Multichannel PLL Synthesizer for 60-GHz WPAN Radio,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, pp. 1234–1246,
May 2008.
[4] F. Herzel, S. Osmany, K. Schmalz, W. Winkler, J. Scheytt, J.C., and
T. Podrebersek, “An Integrated 18 GHz fractional-N PLL in SiGe
BiCMOS technology for satellite communications,” Radio Frequency
Integrated Circuits Symposium, 2009. RFIC 2009. IEEE.
[5] W. Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Namhoon Kim;
Deog-Kyoon Jeong; Kim, “A 20-GHz phase-locked loop for 40-gb/s
serializing transmitter in 0.13-m CMOS,” IEEE Journal of Solid-State
Circuits, vol. 41, pp. 899–908, 2006.
[6] D. Messerschmitt, “Frequency Detectors for PLL Acquisition in Timing
and Carrier Recovery,” IEEE Transactions on Communications, vol. 27,
pp. 1288–1295, Sept. 1979.
[7] H. Darabi and A. Abidi, “Noise in RF-CMOS mixers: a simple physical
model,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 12–25, Jan.
2000.
[8] M. Das, “On the Current Dependence of Low-Frequency Noise in
Bipolar Transistors,” IEEE Transactions on Electron Devices, vol. 22,
pp. 1092–1098, Dec. 1975.
[9] S. Chartier, E. Sönmez, J. Dederer, B. Schleicher, and H. Schumacher,
“Millimeter-Wave Si/SiGe HBT Frequency Divider Using Dynamic and
Static Division Stages,” Microwave Conference, 2007. APMC 2007.
Asia-Pacific, pp. 1–4, Dec. 2007.
[10] G. Liu, S. Chartier, A.Trasser, and H.Schumacher, “Fully Integrated
Millimeter-Wave VCO with 32% Tuning Range,” Silicon Monolithic
Integrated Circuits in RF Systems, 2009. SiRF ’09. IEEE Topical
Meeting, pp. 1–4, Jan. 2009.
[11] R. E. Best, Phase Locked Loops. Reading, MA: McGraw-Hill Professional Publishing, 06/1999.
Spectrum of the PLL output in the lock state with a span of 100
The phase noise was also measured using the Agilent
8565 EC, as shown in Fig. 8, with the offset frequency varying
from 1 KHz to 100 MHz at a center frequency of 32 GHz.
The phase noise at 1 MHz offset is -112 dBc/Hz, which is 8
dB higher than the simulation result. This is mainly caused
by the poor noise performance of the signal generator. The
power consumption of the chip is around 628 mW at 4 V
supply, and 56 mW at 8 V supply for the active filter. The
measured performance is summarized in Table I and compared
with some prior published works.
Phase noise, dBc/Hz
[4]
Attenuation:10 dB
−40
Fig. 7.
MHz
[3]
108
Fig. 8. Measured phase noise of the PLL output at 32 GHz center frequency
72