Broadband Amplier Design and Test
T. J. W. Clarke, v1.00
Second Year Electronics Lab, Department of Electrical & Electronic Engineering, Imperial College
February 18, 2013
Contents
ˆ Components
ˆ (optional) Spice simulation software
1 Introduction
1.1 Timetable . . . . . . . . . . . . . . . . . . .
1
1
2 Design
2.1 Specication . . . . . . . . . . . . . . . . . .
2.2 Top-Level Design . . . . . . . . . . . . . . .
2.3 Approximation . . . . . . . . . . . . . . . . .
2
2
2
3
3 Build and Test
3.1 Circuit Characterisation . . . . . . . . . . . .
3
3
4 Circuit Stability
4.1 Single Stage Stability
4.2 Power Supply Noise .
4.2.1 Rules . . . .
4.3 Ground Noise . . . .
4.3.1 Rules . . . .
4.4 Capacitive Coupling .
4.4.1 Rules . . . .
4.5 Inductive Coupling . .
4.5.1 Rules . . . .
ˆ Appreciate trade-os and pitfalls in high gain low noise
3
amplier design.
4
4
5
5
5 1 Introduction
5
6
6 Although this problem is in principle open-ended, the design
6 specication constrains the possible design space. The solution will be a cascaded set of op-amp stages (inverting or
6 non-inverting). The experiment provides an extended application of non-ideal op-amp theory, as taught in the second year
6 Analog course, but also explores some additional issues: noise
7 (Section 6)and parasitic feedback (Section 4).
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5 Nonlinear eects
6 Noise
6.1 Noise in a Multi-Stage Amplier . . . . . . .
A Non-ideal Op-Amp Theory
B Op-amp Data
Equipment
ˆ Oscilloscope with two probes
ˆ Function generator
ˆ dual bench PSU
ˆ Soldering iron
ˆ Set of tools
EEE & ISE Second Year Electronics Laboratory
Aims
ˆ Understand the uses and limitations of op-amp ampliers
ˆ Design ampliers using non-ideal op-amp models
7 Credit will be given for design which is driven by analysis, and
testing which identies and corrects errors in the analysis, as
8 well as the deliverable: a well performing design.
1.1 Timetable
1. Session 1 - Background reading, complete initial design
2. Session 2 - Build and test rst two stages
3. Session 3 - Build and test remaining stages
4. Session 4 - Further testing
1
2 Design
2.1 Specication
Design Specication
+15v, -15v
Power
Gain
2 104
Input impedance 1k
Load resistance 470
3dB Bandwidth 1kHz - 100kHz (as at as
possible over passband,
-3dB at given frequencies, as low as possible at
500Hz/200kHz)
Op-amps
4 MC33078 (2 ICs)
and/or 6 TL072 (3 ICs)
Capacitors
0:22F
Noise
As low as possible
Circuit must be free of oscillation
2.2 Top-Level Design
RF
CF
-
RI
Vi
CI
A
Vo
+
Inverting stage
RI
RF
CF
Vi
A
Vo
+
CI
RIN
Non-inverting stage
Figure 1: Top-level stages
EEE & ISE Second Year Electronics Laboratory
The circuit will consist of a number of cascaded op-amp stages
as in Figure 1. Note that capacitors CI and CF create respectively low and high pass lters and both are optional in any
specic stage.
The more stages, the lower the gain needed in each. Each
stage can be made from either MC33078 or TL072 op-amps,
however op-amp ICs are dual. Using one IC for two stages
which are not adjacent would lead to very problematic feedback issues between the two halves of the IC because of the
high total gain.
It may be practically dicult to use DC coupling (no CI )
through too many stages because small op-amp oset errors
in the rst such stage will be amplied by subsequent stages
and lead to a saturated DC output voltage larger than the
available linear range.
The feedback capacitor CF will provide phase advance in the
feedback loop at high frequencies, so may be useful to stabilise
a given stage as well as to provide the required frequency
response.
See Section 4 for information on input node
impedance.
For each stage, independently, the design choices are therefore:
ˆ op-amp type
ˆ closed loop gain
ˆ Inverting input node impedance
ˆ stage type (inverting or non-inverting)
ˆ AC or DC coupling between stages
ˆ Supply decoupling (yes or no).
Further work in the design would be to use a more complex RC
network to dene op-amp gain of one or more stages. This
could allow gain shaping to make the passband gain atter
and counteract gain errors caused by op-amp gain reduction
at higher frequencies.
To make sure you understand the use of these stages answer
the following questions:
ˆ What are the Bode plots of these two stages, with both
CI and CF non-zero?
ˆ Why does non-zero CF in the inverting stage make oscillation less likely? (Section 4)
ˆ Why is the inverting stage with non-zero CF less likely to
oscillate than the non-inverting stage with non-zero CF ?
Section 4
ˆ What is the input impedance (within the passband) of
these two stages?
ˆ The op-amps have nite output resistance (see Appendix B) and should not drive total loads of less than
double this. The large signal response of the op-amps is
2
current limited so the total resistance loading of the last
stage op-amp (where voltages may be large) should be
higher than this. What is the minimum load resistance
for each stage, and what therefore the minimum values
of RF ; RI ? Note that the last stage must also drive the
specied load, and that output voltage of 8V peak to
zero must be possible.
2.3 Approximation
ˆ
ˆ
iron will short-circuit anything it touches. Use appropriate current limits on the PSU to reduce damage from
accidental shorting.
When testing, ALWAYS connect oscilloscope GND and
signal generator GND to the circuit GND, not to the
circuit V- supply.
When testing use a suitable potential divider to scale
down the signal generator output to an appropriate level.
A ratio of roughly 100:1 (e.g. 22k / 220) is suggested.
The potential divider must be implemented on the circuit
ground plane so as to minimise capacitive or inductive
pickup onto the (low level) divider output. Note that the
circuit input impedance will be in parallel with the bottom
divider resistor and therefore aect the division ratio.
Note that adding the specied load to the nal stage will
increase output currents and therefore may make the circuit unstable. Do this only when the circuit is otherwise
stable and working
Note that instability (oscillation) will not always appear
to be a sine wave. It may look like high amplitude noise.
Oscillation can be distinguished from noise because small
changes to the physical location of components - even
putting a hand near the circuit - will aect oscillation but
not noise. Also the expected noise from your circuit can
be calculated: signicantly higher level output than this
will be oscillation.
The remaining sections in this document detail the various
design issues that will inform the above choice. You can see
that there are many possibly conicting requirements. The
key to making progress in the design is approximation. Initially, use a simple analytic model for the performance of each
ˆ
stage to get a rough feel for what is required. Follow this by
more detailed analysis. Only when the analysis is complete
should you consider SPICE simulation. In fact such simulation will be of limited benet because it will not model the
ˆ
issues (PSRR, parasitic feedback) which are more dicult to
determine, and other issues can be calculated explicitly from
theory and datasheet information.
ˆ From the non-ideal op-amp equations consider only the
eect of op-amp gain.
ˆ Assume that op-amp gain is determined only by the dominant (lowest frequency) pole
ˆ From the above, for an inverting stage with CF = 0 opamp dominant pole fP , low-frequency closed loop gain 3.1 Circuit Characterisation
G, op-amp open loop gain A, the frequency response is
equivalent to gain G, pole at fP A=G . Otherwise the high You should test your circuit as follows, comparing measurefrequency pole is determined by CF RF . The low fre- ments with values calculated from theory:
quency breakpoint is determine by RI CI if CI is present.
ˆ Gain versus frequency over range 100Hz - 1MHz.
ˆ A non-inverting stage
ˆ Large signal response: clipping and slew rate.
ˆ Noise: overall amplitude and (using oscilloscope FFT
This model will allow you to work through an initial rough
function) variation with frequency. Measuring noise is a
design. You can then determine, and compensate for, the
specialised topic, some notes are posted on the handout
eects of non-ideal components.
web page.
ˆ Output impedance and change in large signal response
under load.
3 Build and Test
The circuit must be built and tested as follows. Failure to
understand and follow these rules, most of which apply to all
build and test exercises, will lead to problems.
ˆ Use copper-plane (un-etched PCB) as a ground plane
connected to GND, or use Veroboard. From Section 4
you will realise that ground plane has certain advantages.
ˆ Build and test one stage at a time.
ˆ Use bench power supplies for the power, always switch
this o before soldering the circuit, because the soldering
EEE & ISE Second Year Electronics Laboratory
4 Circuit Stability
This section is unique in this document because it describes
practical design issues which, with the exception of supply
noise, cannot be calculated theoretically.
High gain ampliers are practically dicult to implement because unintended feedback from parasitic capacitance and inductance can make the system unstable. There are a number
of problems:
3
ˆ Single stage instability
ˆ Power supply noise
ˆ Ground loop noise
ˆ Parasitic capacitive coupling
ˆ Parasitic inductive coupling
Each of these problems is dicult to quantify, but can be understood and avoided through careful design and construction.
The sections below explain the problem and provide rules of
thumb which if followed will make the chance of a successful
design much more likely.
4.1 Single Stage Stability
Op-amps are internally compensated and have a single lowfrequency pole designed to reduce open-loop gain to less than
unity before phase lag gets to 180 . They are thus, in theory,
unconditionally stable. However additional phase lag in the
feedback path can make single stages unstable. Also unintended positive feedback can do the same. Phase lag in the
feedback path will be more likely to aect low gain stages,
since a stage gain of G implies a feedback gain of 1=G , and
therefore total loop gain of A=G . If the dominant pole is at f0
we can approximate the frequency at which gain margin drops
to 1, and therefore above which stability is guaranteed, as
f0 A=G . At higher frequencies unintended phase lag becomes
more problematic because:
ˆ Higher poles inside the op-amp contribute some phase
lag. This eect can be quantied by looking at the opamp Bode plot from the datasheets, for example Figure 2.
ˆ At higher frequencies parasitic impedances become more
signicant and therefore unintended external phase lags
are higher.
The problem with unintended positive feedback is opposite.
Here the op-amp stage itself is stable, but the input and output couple together with some gain > 1=G . This always apply to single stages where the proximity of inputs and outputs
makes some coupling inevitable. A good rule of thumb is
therefore to limit the maximum gain in any one stage to less
than 50, but there is no precise rule therefore designing, as far
as other constraints make possible, for constant gain in each
stage is desirable.
4.2 Power Supply Noise
Supply currents in output stages will result in noise on supply
rails. This is coupled back to input stages and depending on
the power supply noise rejection of these stages will create a
feedback path with loop gain > 1. Op-amps are designed to
have high PSRR (power supply rejection ratio) and so suer
less from this problem than other circuits. Figure 3 shows the
XS
V+
IS
Stage 1
Stage 2
IL
Stage 3
RL
VXS
Figure 3: Power supply noise
Figure 2: MC33078 Bode plots
EEE & ISE Second Year Electronics Laboratory
problem. The supply voltage change due to current through
output load RL from input Vi is Vi G XRSL where G is the total
closed loop gain and XS is the supply impedance. The multiplier G XRSL is the unwanted coupling from Vi to the power
supply. This divided by the input stage PSRR gives the loop
gain from supply feedback, and must be 1 to ensure stability. The solution is to decouple the supply of each stage
with an RC lter, as in Figure 4. This greatly reduces the
coupling between supply current in one stage and supply voltage in another. It also has the benet of reducing the area
of output stage current loops, and therefore the mutual inductance coupling such loops to inputs. The attenuation in
power supply noise from each RC lter is 1=!RC . Between
two stages the eect is (!RC ) 2 . Using op-amp data the
eect of nite PSRR at any frequency can be computed and
if needed appropriate supply decoupling inserted to make the
loop gain from supply feedback between last and rst stage
1.
4
V+
C
C
C
Stage 3
Stage 2
Stage 1
C
C
C
4.4 Capacitive Coupling
R
R
R
Only one rule: keep output and input ground connections
separate. This can be accomplished in general by single-point
ground connection or on a ground plane PCB by ensuring
that input ground, output ground and supply ground are all
separately connected to the PCB with the input separated
physically from output or supply.
R
R
R
4.3.1 Rules
V-
In a multiple stage system the high gain from input to output
makes even very small parasitic feedback paths problematic.
Generally if the overall gain between input of one stage and
Figure 4: Power supply decoupling
output of another is G we must ensure any feedback path
between these stages has attenuation GF 1=G .
4.2.1 Rules
To see why this is dicult, consider the specication of your
amplier. A parasitic capacitance Cp from output Vo to inˆ If possible design for high PSRR at input stages.
put Vi will form a potential divider with the amplier input
ˆ Calculate magnitude of problem using PSRR of input impedance Ri :
stage.
Vo ! Cp ! Vi ! Ri ! GND
ˆ If problematic add supply decoupling to output stage
(rst) or output and input stages. Note that output stage Given the 1k input impedance, this will make a potential divider with gain > 1=20; 000, and hence unwanted feedback
supply decoupling also reduces inductive parasitics.
loop gain > 1, if:
2f Cp 1k > 1=20000 ! C > 1=(60f )
4.3 Ground Noise
Note units of f is in MHz and Cp in pF. Thus very small
Ground noise is closely related to power supply noise. The parasitic capacitances between output and input can result in
current from output stages must travel through the supply instability. Figure 6 shows some typical parasitic capacitances
ground connection as shown in Figure 3. If this overlaps with on a board layout. These gures assume that the wires are
input signal path, as in Figure 5, the noise voltage adds directly
to the input voltage. Although this is a serious problem it can
Component leads 0.075pF
relatively easily be prevented by ensuring that output current
1cm long sepaloops and input signal paths do not overlap. Also, it can be
rated by 1cm
reduced by using a low impedance ground plane instead of
Adjacent pins of a 2pF
ground wires.
DIL IC
Opposite side pins 0.1pF
of a DIL IC
XS
V+
IS
Stage 1
XG
IL
Stage 2
RL
GND
VXS
Voltage
source
Figure 5: Ground loop
EEE & ISE Second Year Electronics Laboratory
Figure 6: Approximate parasitic capacitances
isolated. When wires are close to a ground plane, as will be
the case with good construction, parasitics are much smaller
because the proximity of the ground plane reduces the capacitance between two nodes by partially shielding the electric
eld. The shielding eect is roughly
max(h; d )
b
where h is the height above ground, b the wire separation and
d the wire diameter as shown in the cross-section Figure 7.
5
b
d
h
Figure 7: Cross-section of wires above ground plane
4.4.1 Rules
ˆ Separate signal inputs and outputs of high gain stages,
ˆ
or multiple stages.
Use shielded wire for input and output signals.
Keep leads short.
Use a ground plane.
Place components susceptible to parasitic coupling close
to ground plane.
Where possible use lower impedances in input ampliers.
Both eects are documented in the op-amp datasheets and
so can be calculated.
One experimental problem to beware is measuring linear response at too large an amplitude, and therefore observing nonlinear eects. Any measurement can be tested for linearity by
the test of halves. Reduce input amplitude to half its original
value and check that output similarly changes.
6 Noise
This section provides a simple, adequate for design work,
treatment of noise analysis in electronic design. Noise perˆ
formance of op-amp circuits is well understood theoretically
and can be predicted with some accuracy from datasheet inˆ
formation.
Noise is inevitable in electronic circuits above absolute zero.
ˆ
At frequency T K the Johnson-Nyquist noise power in a resistor is:
Pn = 4k f T
4.5 Inductive Coupling
Where k is Boltzmann's constant and f is the circuit bandThe problem here is that currents in output stages or sup- width. At room temperature this therefore represents an abplies create magnetic elds that couple with wire loops in solute limit for the noise performance of an op-amp amplier
input stages. The coupling magnitude depends on the cross- with input resistor RI :
sectional area of output current loops and input signal loops.
p
Vn = RI 4kT f = RI
As always a ground plane is helpful by providing current or
signal return paths close to the wires so reducing this area.
Inductive coupling becomes more signicant with low circuit Note the dependence on f which means that noise voltage
increases as does circuit bandwidth. The square root is an
resistances, and hence higher currents.
inevitable consequence of the fact that noise powers add, and
voltage is the square root of power. At room temperature,
4.5.1 Rules
1kHz bandwidth, and 1k
this is approximately 400nV.
ˆ
As for minimising capacitive coupling except that lower
impedances do not help.
5 Nonlinear eects
There are two nonlinear eects in op-amps which cause deviations from the response expected from linear analysis:
ˆ Clipping. Maximum positive or negative output voltage
relative to supplies.
ˆ Slew Rate. Maximum positive or negative rate of change
of output voltage.
Clipping can be observed, and will be roughly constant, at
any frequency. Slew rate can be observed at high frequencies.
Both eects are visible only for large enough output amplitudes, though in the case of slew rate the amplitude will be
frequency dependent, since for a sine wave V0 sin !t :
dV
dt
= !V0
EEE & ISE Second Year Electronics Laboratory
Figure 8: MC33078 noise characteristics
Added to this noise is the noise from the op-amp semiconductors, typically much larger than this limit. Figure 8 extracted
6
from the MC33078 datasheet species noise voltage VN and For an op-amp which is ideal but has nite gain A(!), the
current IN . Note that both parameters refer to noise at the op-amp inverting amplier with ideal closed loop gain G has
input pins of the op-amp. To obtain output noise voltage we actual closed loop gain and phase G :
must use the op-amp closed loop voltage gain G and input
1
impedance RI :
G = G
(2)
G
1 + A(!)
√
VNout = G (VN + RI IN ) (f )
To determine overall gain the magnitude of this complex num√
Notepthat VN and IN are typically specied in nA= (Hz ) and ber is usually taken. If the op-amp also has nite output
nV= Hz , and are uniform across a wide frequency range with
however a substantial increase at low frequencies.
RF
We can dene the input referred noise of the stage to be the
output noise VN divided by the gain G .
V
V
V
I
RI
A
X
+
6.1 Noise in a Multi-Stage Amplier
O
RO
op-amp equivalent
RL
Consider an amplier with M stages, stage j has input ∏
referred
noise Vj . The noise from stage j will be multiplied by M
Figure 10: Op-amp with non-zero RO
i =1 Gi
leading to an expression for the total noise at the amplier
output referred back to the input of the rst stage.
impedance RO things become more complex. As Figure 10
shows the eect of the nite output impedance can be mod[
]
1=2
( )2 (
)2
V
V
2
3
eled as a reduction in the open loop gain A(!) caused by
VN = V12 +
+ G G + :::
G1
the potential divider made from RO and the op-amp load re1 2
sistance. This load resistance is the parallel combination of
∏
external load RL resistance and and the feedback resistor RF .
G
to
obtain
the
output
Multiply this expression by M
i
i =1
The feedback resistor terminates in the op-amp virtual earth
noise.
From this we see that the noise is dominated by that of the and is equivalent to a smaller resistor RF to ground using a
rst stage, or possibly rst two stages, and that high gain in derivation similar to that for the Miller eect:
the rst stage is desirable to minimise the noise contribution
A (! )
RF = RF
(3)
of subsequent stages.
1 + A(!)
RF k RL
Further information can be found on the handout web
A (!) = A(!)
(4)
page.
RO + (RF k RL )
A Non-ideal Op-Amp Theory
RF
Vi
RI
-
A
Vo
+
Figure 9: Ideal op-amp
Substituting Equation 4 into Equation 2 with A = A gives
the overall closed loop gain.
Note that although the overall equation for G is not very intuitive1 , theG , A and RF equations here, each of which
normally makes only a small change to the corresponding parameter, are easy to understand. Depending on the accuracy
required, the approximate or more precise value can be used
as shown below:
Approximation
Error
Error in G
G G
G
A
RO
RL kRF
G
A
G RO
A RL kRF
G RO 1
A RL kRF A
A A
The ideal op-amp inverting amplier circuit as shown in Fig1
RF RF
ure 9 has gain:
A
RF
G=
(1) The approximations are listed in order of importance, since for
RI
example an error in A will correspond to a smaller error in G
Note that in Equation 1 the feedback and input resistors can by the given factor of G=A.
be replaced by more complex RC circuits, with the resulting
1 See Analog II notes
complex impedance used to determine G .
EEE & ISE Second Year Electronics Laboratory
7
B Op-amp Data
Op-amp
GBP
Full datasheet
MC33078
16
see handout page
TL072
3
see handout page
EEE & ISE Second Year Electronics Laboratory
8