Imperial Journal of Interdisciplinary Research (IJIR)
Vol-2, Issue-8, 2016
ISSN: 2454-1362, http://www.onlinejournal.in
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Abstract: In this paper 5.0v, 14 bit charge scaling
DAC uses two split arrays is designed and applied in three specific approaches, i.e., Binaryweighted, unary-weighted, and segmented capacitive simulated. The concept of two split array is employed to reduce the total area of capacitor required for high resolution DACs. Design of charge scaling architecture is implemented in
CMOS 250nm technology. Further Successive approximation register (SAR) ADC is designed using the binary weighted capacitor array as its charge redistribution purpose. A design of 14 bit
SAR ADC is implemented using tanner 13.0v at 250 nm CMOS process, which consumes power of
0.0142mw.
Keywords: T-SPICE, Dynamic latched comparator, multiplexer circuit, SAR Logic, Double differential amplifier, two split capacitor DAC array
I.
INTRODUCTION
Applications which include Wi-Fi communications and digital audio and video have created the need for price-effective data converters, a good way to achieve higher velocity and decision[1]. The needs require with the aid of virtual sign processor constantly challenge analog designers to enhance and develop new ADC and
DAC architectures. Essentially ,the successive approximation check in A/D converter, which is understood for its superb power performance, it includes 3 essential additives an analog comparator, a DAC and a successive-approximation register
(SAR) [1],[4] .The operation of SA-ADC is likewise follows, the input voltage (Vin) is sampled by using the sample and maintain circuit throughout the sampling segment and bring an output V
H
,this voltage does not trade during the conversion phase
[2],[5].during the conversion segment the output of
DAC (VDAC) is compared to VH and the result of comparisons is fed to successive approximation register ADC [5].
In an SA-ADC structure one of the most vital building blocks is the virtual to analog converter .The capacitive- array DAC utilized in SA-ADC can be array.[4],[6]. The Binary-weighted capacitive DAC has exceptional structures, e.g., conventional capacitive array, split capacitive array with attenuation capacitor,
C-2C capacitive arrays-ADC with twin capacitive array and price redistribution DAC with step-smart charging.
For a Binary-weighted capacitor array, because the resolution will increase. A problem comes up: the entire range of capacitors in CDAC will have an exponential boom. This could lead to an increasing chip region, electricity dissipation as well as lowers the pace because of a huge charging time-constant. To mitigate this problem, break up capacitor array is used, which could lessen total number of capacitors[4],[6].The vicinity discount impact may be more tremendous with the growing resolution of the
ADC.It can be used broadly in high-pace and mediumto-high decision SAR ADC [7]. In this paper, section II deals the 7bit conventional flash ADC and 6 level pipelined ADC the usage of shifting sampling method.
Section III offers with the 14 bit rate scaling DAC uses two-break up the array. Segment IV offers the design of 14 bit SAR ADC. In phase V gives the simulation consequences are reviewed. Earlier or later, the realization of this paper is drawn in segment VI.
II.
BASIC SHIFTED SAMPLING ADC
ARCHITECTURE
Commonly Analog to digital Converters (ADC) is classified in: soaring rapidity and excessive choice.
Converters via pace (or sampling rate) advanced than
10MHz are measured excessive pace ADCs. One of the issues of the high velocity ADCs is their most affordable/right showing judgment, decision, in other phrases low energetic series [9]. In software along with ultrasound, high speed and excessive selection
ADCs are cautiously notion about necessary. Among a combination of ADC architectures have their person income in adding to increase the field of excessive speed and resolution.
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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-2, Issue-8, 2016
ISSN: 2454-1362, http://www.onlinejournal.in
A.
Flash-type/ equal ADC,
B.
Successive approximation ADC
C.
Oversampled / Sigma-Delta ADC and
D.
Pipeline ADC
DESIGN OF 7-BIT CONVENTIONAL FLASH
ADC
In a conventional flash ADC, the enter sign is coupled to the every comparator, phase comparator dividing lines/factors where matters start or exchange is absolutely spaced by way of 1 LSB. The linear input is then connected at once to the igniter of all of the comparators.[8], Those associated with what holds the something together and make it a strong layout depends on the powerful voltage reference, and then the input signal variety is amazingly minute, so very small comparators are certainly desired. truth at an excessive conversion charge with low complex issue and energy use with the motive of such software bring about sampling rate of about
100MS/s or above. For its miles very extra ordinarily crucial to cut back electricity use beside with maintaining a high velocity of operation. Pipeline
ADC combines the praise of the complete talk approximately ADCs closer to constructing a higher visible sharpness output via the pleasant upkeep velocity, pleasant of being very near the reality or proper variety. On the other hand, their electricity and vicinity waste very little while working or producing something values are collecting of their most accurate resolution consistent with a degree. In advance degrees, stages operate on the residue in that way allow for high-velocity converting from one nation of thoughts to any other state [3], [9]. At the equal time as, the filtrate of the first stage is creature operate on via the second one degree, the first level is free to function scheduled after that samples.
After, a conversion the comparator output may be guessed to the thermometric code [8], [10]. This kind of comparator points where something begins or modifications are monotonically growing by means of layout, reducing the sign volume/length lower the
SNR through decrease the signal strength even as the noise electricity stays pressed.
Fig 2: Idea based totally block Diagram of 6- stage pipelined ADC
A sinusoidal input is applied at 0.5V deliver voltage and this kind of ADC accomplishes a strength of 0.25mW at a sampling fee of 14MS/s, and it occupies an area of 0.031mm² and higher decision may be acquired and the conversion put off is decreased. Fig 1: Conventional 7-bit flash ADC uses a single reference level
This sort of ADC destroys a complete energy of 0.056mW of decreased supply voltage and increasing the put off of one sample to subsequent pattern length conversion.
DESIGN OF 6-STAGE PIPELINED ADC
The Pipelined ADC be converted into the maximum famous ADC structure for sampling quotas as of a small range of mega-samples for each instantaneous (MS/s) as much as a 100+MS/s [9],
This ADC has the good-looking attribute of preserving excessive first-rate of being very near the
Imperial Journal of Interdisciplinary Research (IJIR)
III. 14 BIT RATE SCALING DAC USING
SPLIT ARRAY
The 14-bit DAC is based on the price scaling split array method. The block diagram of a 14-bit rate scaling DAC the usage of the spilt array method is shown in figure 3. Numerous constructing blocks of discerning three are operational amplifier, capacitive network and multiplexer switches, to which the digital word is given[4]. To start with the enter digital phrase is given to a multiplexer circuitry. Relying on the good judgment fee of each bit of the word, the multiplexer chooses the specific voltage to which the capacitor is to be charged. If the
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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-2, Issue-8, 2016
ISSN: 2454-1362, http://www.onlinejournal.in input bit inside the digital phrase is common sense '0' then the multiplexer chooses to enter that's connected to the 'GND' and the capacitor is charged to 0V. If the entire bit inside the virtual word is common sense
'1' then the capacitor is charged to5.0 V, that's 5.0 V.
The output is taken off a distinctive node and an extra attenuation capacitor is used to separate the array right into an LSB array and an MSB array [4],
[6].The price of
C = Sum of LSB Array Capacitors/Sum of MSB
Array Capacitors
B. Double Differential Amplifier
The differential amplifier is most customarily used with a cutting-edge supply load as shown in
Figure 5. If the gate voltage of M1 is extra than the gate voltage of M2, then drain present day of M1 increases with recognizing to an empty current of
M2. This boom in drain current of M1 implies a growth in drain currents of M3 and M4. Therefore, the best manner to set up circuit equilibrium is for output current to grow to be advantageous and output voltage V
OUT
to growth[7],[11] If the gate voltage of M1 is less than the gate voltage of M2 then output contemporary become terrible and V
OUT decreases. Biasing is also used for the second shape, with a complementary MOS transistor, which is likewise driven intently to the corresponding threshold voltage. The more function that is delivered to the schematic shown in discerning 4, to improve the overall performance of the differential amplifier is the current reflect on the biasing circuit of the differential amplifier.
Fig 3: The T-SC Array capacitor DAC
The capacitor at the give up of the network is used as a 'terminating capacitor'. Depending at the capacitors, which might be charged to different voltages based totally at the center digital word, the effective resultant analog voltage is calculated from the respective digital combination[7]. The analog voltage is passed through the op-am and appears as an analog voltage [1].
A. Switch Design
A 2:1 multiplexer is very simple to implement in CMOS era, as most effective two transmission gates and one inverter are wanted. The choice signal (V
IN
) is used to enable one or the alternative of the transmission gate switches[4],[7].
When is V
IN
excessive, V
HIGH is hooked up to the output V
OUT
. When V
IN
is LOW, V
LOW
is hooked up to the output. Figure 4 shows the schematic of 2:1 multiplexer.
Fig 4: Schematic of 2:1 Multiplexer
Fig 5: Schematic view of double differential amplifier
IV.
DESIGN OF 14 BIT SAR ADC
The SAR ADC is extensively used in many communiqué systems, along with ultra-wideband and Wi-Fi sensor networks which require low-tomedium-resolution converters, with low energy consumption. Analog input voltage, V
IN
is held on a pattern/preserve device. [7]The SAR ADC structure is shown in figure 6. To put in force the binary search, N-bit code sign in the SAR common sense block is first set to midscale: N’b100…00, wherein
MSB is good judgment 1. This forces the DAC output (VDAC) to be 1/2 of the reference voltage
(V
REF
). Then comparator plays a contrast among
V
IN
and VDAC: if the V
IN
is extra than VDAC, the comparator output is a good judgment, excessive and the MSB of the N-bit code sign in remains at logic 1, if Vin is much less than Vdac, the comparator output is a common sense LOW and the
MSB of the check in cleared to logic 0.[9]The SAR
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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-2, Issue-8, 2016
ISSN: 2454-1362, http://www.onlinejournal.in common sense then actions to the subsequent bit down, forces that bit excessive, and does any other evaluation. The collection keeps all the way down to the LSB. As soon as that is executed, the conversion is whole and the N-bit virtual phrase is to be had within the SAR’s code sign in. the interface intermediate stage, which consists of all of the transistors besides two cross coupled inverters. The second degree is the regenerative stage that is blanketed of the 2 move, coupled inverters, wherein at every stage input is connected to the output of the alternative[9],[10]. It operates in two phases I)
Interface section and II) Regeneration phase. It has a single NMOS tail transistor linked to the ground. When the clock is low tail transistor is turned off and depending on vice chairman and Vn output reaches to
VDD or the ground, if vice president>Vn output of vice chairman discharge faster than the output of Vn. Whilst clock is high (clk = Vdd) tail transistor is activated and each the outputs discharge to the floor.
Fig 6: SAR ADC ARCHITECTURE
A.
Sample and Hold Circuit
Sample and hold circuit is used to pattern an analog sign and to shop its fee for length of time.
The inputs to a sample and maintain circuit is a sine wave with top of height voltage and a clock sign respectively[7],[12]. During ON duration of a clock, sampling of enter takes region and at some stage in
OFF length of clock, capacitor holds the sampled price and it is carried out to the comparator enter.
And also for the duration of OFF period of clock, conversion from analog to virtual takes place. The capacitance of 5pF with preliminary voltage 0V is taken.
B.
Dynamic Latched Comparator
Fig 7: Schematic view of dynamic latched comparator
The dynamic latched comparator is composed of two levels as proven in figure 7. The first degree is
C.
Synchronous SAR Control Logic
The schematic of the SAR good judgment includes shift register and code shift register using Dturn flop as proven in figure7. Initially the reset line is going low. This line controls set line of FF1 and reset lines of all other sequencer turn flops. The identical reset sign additionally controls the reset line of code register turn flops. Q and Qb of FF1 are set to one and
0respectively. Qb additionally controls the set line of
CF1. For this reason the CF1 output is forced to at least one[6].This is the MSB bit and the burden for VFSR/2.
It should be mentioned that since series check in is reset to begin with, the set input of all of the code registers turns flops besides CF1 is logic 1.
Consequently, all of the different code sign up output states is logic0 0. We get a chain MSB=1 and all different set to zero.
The analog equal of this weight will be generated with the aid of the DAC. When reset goes excessive and the clock is brought about, Q turns into a zero and FF2 outs logic excessive[12],[7],[6].
Triggers or clocks the code register flip flop CF1 to shop control bus cost to its output. Whilst clock runs further, the code sign in turn flop retains the set fee as
FF2 output is going to 0. This method is repeated for each of the flip flops until after N clock cycles a high nation comes out of sequencer flip flop controlling the code check in LSB flip flop [6].
Fig 7: Schematic of SAR LOGIC
V.
SIMULATION RESULT OF 14 BIT
SAR ADC
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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-2, Issue-8, 2016
ISSN: 2454-1362, http://www.onlinejournal.in
All simulations are performed using
TANNER EDA 250nm CMOS process technology files in S-edit environment. To design and simulate the 14bit SAR ADC, tanner schematic S-editor is used and functionality is verified through simulations using tanner EDA 13.0V tool. Delay and
Power consumption of the overall system is measured. The comparisons of ADCs power consumption is shown in Figure 8. Table 1 details the simulation results of SAR ADC.
A 0.5V, 14-bit SAR ADC and simulated in
TANNER EDA environment. It is observed that, this SAR ADC consumes
0.0142mWpower.
Fig 8: Comparison of ADCs power consumpt ion.
.
.Table 1: Performance comparison. Of the 7-bit conventional flash ADC, 6-stage pipelined ADC and 14 bit
Successive Approximation Register ADC.
Architecture Flash ADC with shifted sampling
Technique
(PREVIOUSWORK)
Pipelined ADC with shifted sampling
Technique
(PREVIOUSWORK)
14-bit Successive Approximation
Register ADC using two split capacitor array method
(PROPOSED WORK)
Resolution(bit) 9 15 17
Supply Voltage(V)
Power(mW)
ENOB(bit)
SNR(dB)
Delay(ns)
Speed(ps)
Area(mm²)
0.5V
0.058
3.74
24.78
31.92
31.32
0.083
0.5V
0.25
3.46
23.46
21.84
45.78
0.031
0.5V
0.014
14
104.1
19.38
51.54
0.101
FoM(µJ/conv.step) 10.85 22.71 37.47
Technology(nm) 250 250 250
The proposed 14 bit Successive Approximation
Register ADC is designed in 250 nm technology to operate at 0.5v supply voltage. The total power use of the
14bit Successive Approximation Register ADC accomplishes a 0.01424mw. 14 bit Successive
Approximation Register ADC design can reduce a lot of the energy use and delay by using the proposed 14 bit
Two split capacitor DAC Array technique of doing things; the speed will be increased and compared with other type of ADC’S.
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Imperial Journal of Interdisciplinary Research (IJIR)
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