RESUME, NOVEMBER 2007
1
A 10b 100MS/s Time-Interleaved SAR ADC
Abstract— Analog-to-Digital Converters (ADC) are electronic
circuits which translate analog signals to its binary representation
(digital). Since the signal processing is easier in digital domain,
this type of circuits is extremely important in several areas, for
example in the communications sector. This dissertation proposes
a new implementation for an Analog-to-Digital Converter (ADC)
with 100 MS/s of sampling frequency and 10 bits of resolution.
This proposal consists in an 11-channel time-interleaved ADC,
each sub-converter with a SAR (Successive Approximation Register) topology. The first part of this work presents the subconverter SAR project. To optimize the sub-converter hardware
it is implemented using a segmented topology; it combines
different DAC architectures and different bit decoding methods
(unary/binary). Moreover, it is provided a performance limitations analysis of the time-interleaved structure. The second part
of the thesis describes in more detail the design of the SAR blocks.
Firstly the comparator, which consists in a pre-amplifier and a
latched comparator. Secondly some digital blocks used to control
the converter, namely: (i) a state machine; (ii) a successive approximation register; (iii) a row/column decoder for the capacitor
matrix; and (iv) an output register. Finally, some simulations were
performed in order to evaluate the proposed architecture. The
presented results show that the proposed architecture achieves
the initial requirements. Besides, the implementation proposed
yield good power performance results as shown by the Factor of
Merit (FOM) obtained.
Index Terms— Analog-to-Digital Converter (ADC), Successive
Approximation Register (SAR), Segmented Topology, TimeInterleaved, Sub-Converter.
I. I NTRODUCTION
T
HE quick development of the wireless communications
sector have been demanding for improvements. Wireless
communications often require the use of analog signals, since
signal processing is easier in the digital domain, circuits
capable of convert signals between the two domains are
essential. Analog-to-Digital Converters (ADC), produce the
binary representation of an analog signal, while Digital-toAnalog Converters (DAC) have the opposite function.
The 2 parameters used to characterize any signal converter
are: sampling frequency (fS ) and resolution (N ). The fS
parameter give the number of results per second and the N
parameter corresponds to the number of bits for each sample,
thus it determines the minimum amplitude of the signal that
can be distinguished. In practice, is hard to improve both
parameters at the same time, so a trade-off is needed between
them.
Nowadays, for wireless applications, it is common to utilize
ADCs with a sampling frequency around 80 MHz and 10
bit of resolution. Typically this is obtained with a Pipelined
architecture, but it is becoming harder to satisfy the linearity
requirements. Therefore, is important to explore other possible
implementations.
This work proposes a solution for a 10 bit ADC with a
fS of 100 MHz. In order to avoid the linearity issues, the
new solution is based in a Successive Approximation Register
vIN
S/H
SAR
b N-1
vDAC
Fig. 1.
...
b1
b0
DAC
SAR ADC block diagram.
(SAR). However this type of converter tends to be slower.
Therefore a parallel architecture with an 11-channel timeinterleaved ADC is used to achieve the above requirements.
Besides the performance limitations of this parallel architecture will be discussed.
The rest of this article is organized as follows: Section II
reviews two different SAR ADC topologies. this topologies
were merged and optimized to achieve better performance.
This section also provides an analysis of a parallel structure.
Section III presents the design of the analog blocks. Section
IV presents the digital blocks needed to control the ADC.
Section V shows some simulation results. Finally, we conclude
in Section VI.
Luı́s Simões
November 2007
II. T OPOLOGY
The proposed converter is based on a successive approximation topology comprising four parts (see Fig. 1): a comparator,
a S/H mechanism, a DAC and a register. The comparator
determines if the sampled voltage (by the S/H) is higher/lower
than the DAC generated voltage, which is given according to
the SAR value.
The successive approximation algorithm has the following
steps: (i) the comparator verify if vIN is higher than 12 Vref 1 ,
to determine MSB; (ii) if the decision of the most significant
bit (MSB) is ”1”, the DAC voltage to compare with vIN is
3
1
4 Vref ; (iii) otherwise the DAC will generate 4 Vref ; and so
on and so forth. So this algorithm needs N cycles to determine
the complete binary word.
There are several ways to implement the DAC unit, e.g.
with a resistive ladder, or a capacitor array utilizing charge
redistribution. The following sections are dedicated to explain
the DAC design.
1V
ref
is the maximum scale voltage.
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DAC
2
QX = −2N CvIN .
N
vIN
N
2 -1
(1)
2) Charge-Redistribuition: This stage is divided in N steps,
where N is the resolution (number of bits to determine). Firstly,
to find the value of MSB, it is forced at ”high” in the SAR,
this ensure that half of the capacitors switch to VREF P and
the other half to VREF N (VREF N = 0).
Now the charge of X node is given by,
S/H
N
2 -2
...
vDAC
3
2
1
QX = 2N −1 C(vX − VREF P ) + 2N −1 C(vX − VREF N ), (2)
the charge in X node is constant, so we have
SAR
−2N CvIN = 2N −1 C(vX −VREF P )+2N −1 C(vX −VREF N ), (3)
simplifying its possible to obtain,
Fig. 2.
SAR ADC block diagram.
1
VREF P − vIN .
(4)
2
Clearly the comparator has conditions to verify if vIN is
higher than the middle of the scale ( 21 VREF P ).
Secondly, if the previous decision was ”1”, vX will be,
vX =
Array de Condensadores
vX
2
N-1
C
N-2
2
C
...
2C
C
C
VREFP
vIN
VREFN
3
VREF P − vIN .
4
and the opposite case (MSB=0), vX is given by,
vX =
Interruptores
SAR
Fig. 3.
SAR ADC block diagram.
A. DAC with Resistive Ladder
In this case the DAC is implemented with a resistive ladder
and a group of switches. The switches permit to access the
voltages generated in the ladder, as shown in Fig. 2. The ladder
has 2N resistors and the same number of switches, i.e. 1024
resistors and 1024 switches, becoming impracticable.
B. DAC with Capacitor Array
Another possible DAC architecture uses a capacitor array as
represented in Fig. 3. In this method, power consumption is
reduced and the input signal is sampled and holded directly in
the capacitor array, so it does not need a dedicated S/H block.
As in the previous design (section II-A) the great disadvantage here is the number of components used, because
the capacitor array needs 2N capacitors. This architecture
also needs switches to control the capacitors. Two different
methods can be used, unary and binary. In the first one
each capacitor is controlled by one switch, so it requires 2N
switches, besides the capacitors. In the binary method it needs
just N switches, since the number of capacitors to commute
depends on the weight.
Bellow are described the sample and charge-redistribuiton
functionalities, to simplify we consider binary decoding.
1) Sample: First the input signal is sampled, to do so vX
goes to ground (vX = 0), then all capacitors are switched to
vIN . This makes the total charge of X:
(5)
1
VREF P − vIN .
(6)
4
One can easily verify that the comparator is deciding if
the input voltage is higher than 43 VREF P or than 14 VREF P ,
according to the previous decision. This continues untill all N
bits are determined. Finally vX is given by
"N #
X bN −i vX = VREF P
− vIN ,
(7)
2i
i=1
vX =
each bit-weight contributes to make DAC generate the nearest
voltage to vIN .
C. Segmented Topology
Taking into account the previous hardware limitations, this
work adopts a segmented topology. This alternative permits
to use a reasonable number of components without modifying
the paradigm of the previous methods.
The segmented topology uses a resistive ladder to decode
4 bits and a capacitor array to decode the remaining 6 bits.
Therefore only 16 resistors and 16 switches are used in the
ladder. Concerning the capacitor array, only 64 capacitors are
required; and another segmentation is performed (unary/binary
decoding) to reduce the number of switches.
There is no straightforward decision for the number of bits
used for each segment (unary/binary), thus a Matlab model
was used to simulate the influence of different segmentations
on the DNL results. The simulations results are shown in
Fig. 4.
Cases (c) and (d) have missing codes, because the minimum
DNL value reaches -1, so, it is only possible to choose
between (a) and (b). The first case is clearly better, but its
implementation uses more hardware, for this reason the (b)
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Vreflsb
Array de Condensadores
Array de Condensadores
(dummy)
Escada de
Resistências
SAR
Fig. 6.
Block diagram of the adopted topology.
VCM is a DC voltage and an unwanted charge injection can
have a significant impact in the result of expression (9). To
avoid this, a dummy capacitor array is used to sample VCM
all the time, and both nodes suffer similar charge injections;
the blocks diagram is shown in Fig. 6.
Fig. 4. DNL histograms to decide the segmentation (unary/binary): (a) - 5+1
(b) - 4+2 (c) - 3+3 (d) - 2+4.
Array de Condensadores
60C
Descodificação
Unária
Descodificação
Binária
Vx
b9
...
4C
b6
...
4C
2C
C
C
Descodificador
b5
Escada de
Resistências
b5
b4
b4
vrefp
Vin
vrefn
16
15
14
...
Interruptores
Descodificador
b3
...
b0
3
2
Vreflsb
1
Fig. 5. Connection between resistive ladder and capacitor array and, the
different segmentations.
segmentation was adopted (i.e. 4 bits unary and 2 binary
decoding). Such implementation only requires 18 switches in
the capacitor array instead of 64.
The final topology is presented in Fig. 5 where the SAR
bits b0 to b3 control the resistive ladder switches through a
decoder; b4 and b5 directly control the binary switches from
capacitor array; and b6 to b9 control the unary switches from
the capacitor array through another decoder. The variation of
vX is calculated according to the scheme in Fig. 5, the total
charge of X node:
QX = 2Nc C(VCM − vIN ),
(8)
where Nc is the number of bits determined by the capacitor
array. Following the procedure used in section II-B.2 to
determine (7), vX is:
#
" 10 X b10−i vX = VCM + VREF P
− vIN .
(9)
2i
i=1
Thus vX has a known evolution and the comparator can
determine if the tested bit should be ”1” or ”0”.
D. Time-Interleaved
In order to obtain the sampling frequency of 100 MHz, a
parallel structure with 11-channel time-interleaved is used to
get one sample per clock cycle, as can be seen in Fig. ??.
This architecture permits to use some common blocks, saving
power and circuit area. Although, time-interleaving ADCs
bring some issues that can limit the overall performance. Thus,
some considerations are discussed in the sections below.
1) Channel Offset Mismatches: This type of mismatch
can be modeled as a voltage source serially connected with
each ideal channel. This means that ADC has a pattern of
mismatches along the time with a period of M/fS , this is
manifested in the frequency domain as tones at multiples
of fS /M . With the Discrete Fourier Transform (DFT), the
Fourier coefficients are [1, 2, 3]:
Vk =
M
−1
X
Vosi e−j ( M )ki .
2π
(10)
i=0
This error is independent from the input signal frequency and
level.
There are two ways to solve this potential problem; an
analog method, which consists in a comparator with a lower
offset, using more area and power; and a digital method, which
generates an offset correction. The latter needs a mechanism
to determine the offset in each channel and digitally correct
them.
2) Channel Gain Mismatches: Channel gain mismatch
can be modeled as the previous mismatch, but with a gain
stage instead of the voltage source. Each fixed gain factor
is multiplied to the input signal in time domain, obtaining
a periodical pattern. The multiplication in the time domain
corresponds to the convolution of the gain pattern with the
input signal in the frequency domain. The convolution results
in side bands centered around multiples of fS /M . Assuming
this mismatches are time invariant, the output spectrum Y (jω)
is [1, 3]:
∞
1 X
2πk
Gk X j ω −
,
Y (jω) =
T
MT
k=−∞
(11)
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where X(jω) is the input spectrum and the Fourier coefficients
Gk are
M
−1
X
2π
(12)
Gk =
gi e−j ( M )ki .
VDD
M 5a
latch
M 4a
M 3b
M 3a
M 4b
latch
M 5b
i=0
vON
The effect of this error only depends on the input level. Since
this issue is caused by mismatches in the reference voltages, all
channels need to share the same reference voltages generators.
3) Timing Mismatches: Finally, the timing mismatches consists in different sampling times between the channels, this
is caused by non-idealities of multi-phases. The fixed timing
deviations lead to fixed side bands around fS /M in frequency
domain.
Considering ideal instants, each clock signal has a ∆Ti
delay, the output spectrum is [1, 2, 3]:
∞
2πk
1 X
Φk (ω)X j ω −
,
Y (jω) =
T
MT
(13)
vOP
M 2a
M 2b
vDP
vDN
vIP
M 1a
latch
Fig. 7.
vIN
M 1b
M6
Dynamic Latched comparator.
k=−∞
VDD
where X(jω) is the input spectrum and the Fourier coefficients Φk (ω) are given by
Φk (ω) =
M
−1
X
M 4a
e
2πi
2π
j (ω− M
T )∆Ti −j ( M )ki
e
.
M 3a
M 3b
M 4b
(14)
i=0
q
In order to avoid the timing mismatches, all channels need
to share a S/H block, this strategy allows to control all the
samples with the same phase signal.
qz
r
s
M 2a
M 2b
III. A NALOG B LOCKS
In this section is discussed the comparator design. This
block is responsible for determining if the input voltage is
higher/lower than the voltage generated in the DAC. In order
to implement it, a latched comparator is used, as well as a
pre-amplifier to reduce the offset contribution.
M 1a
Fig. 8.
M 1b
Latched SR.
A. Dynamic Latched Comparator
This work adopted a latched comparator with a topology of
the Fig. 7, based on [4, 5].
When latch is ”0”, the transistors M4a /M4b and M5a /M5b
reset the output nodes (q and qz ) and the drains of differential
pair (M1a /M1b ) to VDD . M6 is off and no supply current
exists. When latch rise, M4a /M4b and M5a /M5b are switched
off, and current starts flowing through M6 and through the
differential pair, discharging the M1a /M1b drains, this leads to
a vDN and vDP reduction. When this voltages become smaller
thsn VDD −Vt , M2a /M2b switch on and cause an output nodes
voltage reduction. When this voltages reach smaller values
than VDD − Vt , transistors M3a /M3b turn on. In this moment,
considering a positive input voltage, M2a current is higher
than M2b , so vON decrease faster than vOP . This in turn,
makes the vGS2a increase faster than vGS2b , which causes a
further increase of the difference between the currents in this
transistors - there is a positive feedback mechanism.
Analyzing the incremental model of the circuit, is possible
to get an expression for vod evolution
t
vod (t) = ∆Vi e τreg ,
(15)
where τreg is
τreg =
CL + CDBp + CGSp + 2CGDp + CDBn + CGSn + 2CGDn
.
gmp + gmn
(16)
Considering the total capacitance of 20 fF and a total gm
of 200 µS, it is possible to obtain τreg ,
20 f
= 0.1 ns,
(17)
200
to achieve a voltage level vodf inal = 2 V, with ∆Vi = 1 mV,
we can get a regeneration time estimation:
vodf inal
t = τreg ln
= 0.76 ns.
(18)
∆Vi
τreg =
Since the latch impulse is very short, it is needed a circuit
to save the decision for the rest of the cycle, so it is used
a latch SR (see Fig. 8), this permits SAR to update the new
iteration value.
When s signal is high and r is low, M1a and M4b turn on,
M4b drain current charge qz node that goes to VDD , this in
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VDD
M 2a
M 3a
M 3b
vON
vIP
M 2b
vOP
M 1a
M 1b
vID
vIN
Fig. 10.
I SS
Fig. 9.
Pre-amplifier simulation with a vid = 1 mV.
Considering expression (21), the 95% voltage level is
achieved when
t = 3τ,
(25)
Dynamic pre-amplifier.
to reach the targeted voltage level in 8 ns,
turn, switch on M2a , putting ground at q output node. When
the latch goes zero (reset phase of the comparator), s and r
signals go high, this way M4a /M4b turn off and M1a /M1b
switch on, this leads to M2a /M2b and M3a /M3b connected
as a back-to-back inverters, saving the compared result.
With a simulation the worst case was when the input
changed from vindif f = 2 mV to vindif f = −2 mV and
the regeneration time is 646 ps, that is accordingly with the
expected.
8 ns
.
(26)
3
To obtain a first iteration, some parameters were assumed,
τ<
as
CLtot = 100 fF
(27)
gm3 = 0.6gm2 .
(28)
and a gm relation,
The differential gain was assumed to be
Avd > 5.
B. Pre-Amplifier
To reduce the offset error, the comparator is enhanced with
a pre-amplifier as the one presented in the Fig. 9.
Analyzing the small signal model of the circuit it is possible
to obtain the gain expression, which is given by:
vod
Avd =
= gm1 Req ,
(19)
vid
where Req is
Req =
1
.
gm2 − gm3
(20)
The goal of the pre-amplifier is to achieve 95% of VF IN AL
in 8 ns, considering the parasitic capacitances, it is possible
to write the vod (t) expression:
t
gm1
vod (t) = Vid
1 − e− τ ,
(21)
gm2 − gm3
where τ is
τ=
Ca + 2Cb
,
gm2 − gm3
(22)
with,
Ca = CL + CDB1 + CGD1 + CGS2 + CDB2 + CGS3 , (23)
and
Cb = 2CGD3 .
(24)
(29)
Based on [6] for the strong inversion, it is considered Vod =
200 mV.
Assuming this values allowed to achieve a first shot and
after some iterations to obtain the results presented in Fig.10.
The final W/L relations are shown in Table I.
TABLE I
F INAL W/L RELATIONS .
Transistor
M1
M2
M3
W/L
10
10.56
5.56
Finally the simulation results show a pre-amplifier gain of
Avd = 5.186 and an amplification time tamp95% = 6.35 ns.
IV. D IGITAL C ONTROL
A. Global State Machine
In order to control the sub-converter states, it was created
one global state machine, this measure allowed to reduce circuit area and power consumption. Since we have 11 channels
and each one has 11 states, the state machine has 11 flip-flops
organized as a shift register. This way, each sub-converter only
need to see a different state machine output, i.e. each subconverter is working in a different state.
RESUME, NOVEMBER 2007
Fig. 11.
Output spectrum without random deviations.
6
Fig. 12.
Output spectrum with Monte Carlo parameters.
Fig. 13.
sation.
Output spectrum with Monte Carlo parameters and offset compen-
B. Successive Approximation Register
This block goal is to save the successive approximations
and consequently the final result of each channel. It is implemented by a register with 10 flip-flops, each flip-flop is single
controlled by a state signal to know when it needs to save a
result coming from the comparator block.
C. Row/Collumn Decoding
The unary decoding mechanism needs a complex control
system for the capacitors, to implement it, the capacitors are
placed with a matrix format, and the SAR’s bits connected to
row/column decoder. This permits to switch only the required
capacitors, avoiding the binary procedure.
D. Output Register
Intuitively, to obtain a converter with a single output, the
ADC requires an output register.
The 11 channels are connected to a multiplexer to correctly
handle the several results.
V. S IMULATION R ESULTS
In order to evaluate the proposed architecture some simulations were performed. The simulations allowed to verify the
performance of the complete converter. Since this siluations
take lots of time it was used HSIM, which permits some
calculus simplifications.
A. Output Spectrum Without Monte Carlo Distributions
The first simulation has a sinusoid with fi = 10449219
MHz as input signal. The simulation results have been analyzed by a Matlab script in order to obtain the output spectrum.
As can be seen in Fig. 11 the tones coincide with the input
frequency multiples, as expected and the ENOB is 8.9 bit.
Only an ideal converter could reach 10 bit.
B. Output Spectrum With Monte Carlo Distributions
In this simulation, the input wave used is the same of the
previous simulation (section V). The output spectrum was
obtained with the same Matlab script and can be seen in
Fig. 12.
Analyzing the results, they clearly are lower than expected,
since the ENOB is only 6.55 bit. This can result from random
deviations, but also from the simplifications taken by HSIM.
As indicated in Fig. 12, the higher tones coincide with
fS /11 multiples, which correspond to channel offset mismatches. However, other tones result from timing mismatches.
In order to solve the offset problem, a calibration can be implemented. To comfirm this an offset calibrations was performed
with Matlab, resulting in the output spectrum of Fig. 13, as
can be seen the ENOB increased from 6.55 to 8.07. Fig. 14
presents both spectrums (Fig. 12 and Fig. 13) becoming easier
to verify that the offset’s tones had a significant reduction and
the timing mismatches tones did not suffered any changes.
C. Factor of Merit
In order to compare the several performances of many ADC
types, it is possible to calculate the Factor of Merit (FOM),
RESUME, NOVEMBER 2007
7
Fig. 14. Output spectrum with Monte Carlo parameters, with and without
offset calibration.
to obtain a better converter without significant disadvantages.
An overview of the steps performed in this project is
presented below:
• In order to design an ADC sub-converter, this work
studied some possible topologies and adopted the one
with less circuit area and most power efficient.
• This work analyzed some issues of a parallel structure,
namely, the influences of offset, gain and timing mismatches.
• To implement this project some analog parts needed a
more careful design, namely the latch comparator and
the pre-amplifier. In the end the expected results were
achieved.
• To control the entire converter some blocks were designed, e.g. a global state machine and a SAR (register
to contain the intermediate iterations and the final result).
This work always intended to save circuit area and
power consumption, so when possible, the channels share
blocks, as well as reference voltages generators.
• Finally, combining all converter parts, some simulations
were effectuated to verify its performance. The results
were a little below expectations, mainly because of the
used simulator, due to some calculus simplifications.
Some improvements can be considered, as shown in section
V-B an offset calibration is important to improve the overall
performance.
R EFERENCES
Fig. 15. FOM comparison between this project and some projects presented
in ISSCC’07.
its value is given by the following expression [7]:
Ptotal
[pJ/conv],
FOM =
ENOB
2
fS
(30)
where ENOB is the effective number of bits. It is noticeable
that lower FOM values correspond to better performances.
Applying to the obtained simulation results, with 2.6 mA
in the analog voltage source, 490 µA in the digital voltage
source and considering 9 effective bits, we have:
FOM =
(2.6 mA)2.5 V + (490 µA)1.2 V
= 0.138 pJ/conv (31)
29 100 MHz
In the Fig.15 is represented some FOM values in order to the
frequency from ADC projects presented in ISSCC’07.
As can be seen the obtained FOM is better than the
published results.
VI. C ONCLUSION
This work consists in an ADC project, with a parallel
structure, it was verified that with this topology it is possible
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