A 1.5V, 1.5GHz CMOS Low Noise Amplifier
Derek K. Shaeffer and Thomas H. Lee
Stanford University
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Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
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Simple CMOS Noise Model
vg2
Cgd
Rg
Channel
Thermal Noise
+
Cgs
_
vgs
gmvgs
id2
ro
• Channel thermal noise is dominant.
i = 4 kTBγg d 0
2
d
• Gate resistance minimized by good layout.
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Channel Thermal Noise
• Current HSPICE Implementation:
8
i = kTBg m
3
2
d
(NLEV < 3)
(
)
2
8
1
+
+
a
a
id2 = kTB ⋅ K ' V gs − VT
GDSNOI
3
1+ a
• BSIM-3 Implementation:
i =
2
d
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4 kT µeff
2
eff
L
Q inv
(NLEV = 3)
Vds
a = 1−
Vdsat
How To Get 50Ω
Rf1
Zin
Zin
Zin
Zin
RL
Rf2
Dual Feedback
Zin =
Rt
Resistive Termination
R f 1Rf 2
Need high gain.
Stability problems.
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Ls
1/gm Termination
1
gm
Z in = Rt
Zin =
Poor NF.
NF > 3dB
(γ>1)
Inductive Degeneration
Re[Z in ] =
gm
L
C gs s
Narrowband.
LNA Input Stage
 gm 
1
 Ls ≈ ωT Ls
+ 
Zin = s Ls + Lg +
sCgs  Cgs 
(
G m ,eff
)
g m1
= g m1Qin =
ω C gs ( Rs + ωT Ls )
ωT
ωT
=
=
 ωT Ls  2ω Rs
ω Rs 1 +

Rs 

Note: Gm,eff is independent of gm1!
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Zin
Lg
Vbias
M2
M1
Ls
Noise Factor
A common form
A better form
γ g d 0 Rsω 2 C gs2
Rl
+
+
F =1+
Rs Rs
g m2
Rg
ω 
Rl Rg
+
+ γg d 0 Rs  
F = 1+
Rs Rs
 ωT 
• Reducing gd0, Increasing Qin lowers F!
• Achieving low F involves linearity tradeoff.
V gs = Qin V s
• Technology Scaling is Key.
• Problem : The Free Lunch Principle
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2
Induced Gate Effects
Vgs
Ig
G
S
D
• Gate Noise Current
• Real Component of Zg
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Vds
Equivalent Gate Circuit
_
+
+
Vgs
_
+
ig2
gg
Cgs
-OR-
Vgs
_
vg2
rg
Cgs
2 2
ω
Cgs
1
1
2
2
gg =
rg =
v g = 4 kTB δ rg
ig = 4 kTB δ g g
5 gd 0
5 gd 0
“Blue” Noise
“White” Noise
• δ (∼ 4/3) modified by hot electron effects
• ig2 partially correlated with id2 (c = 0.395j)
• ig2 and gg not modeled in HSPICE
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Revised Noise Factor
Lg
vl2
Rl
v g2
Rg
2
iout
2
g
i
Rs
vs2
gg
Additional
Noise Source
ω
Rl
+
+ γg d 0 Rs  
F = 1+
Rs Rs
 ωT 
Rg
gmvgs
id2
Ls
2


δα 2
δα 2
2 
1 + QL ]
QL c +
[
1 + 2
5γ
5γ


(At Resonance)
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Cgs
+
vgs
_
Noise Factor Terms
ω
Rl
+
+ γg d 0 Rs  
F = 1+
Rs Rs
 ωT 
Rg
QL =
(
ω Ls + L g
Rs
)=
1
≈ 2 * Qin
ω Rs C gs
gm
α =
≤1
gd 0
c=
i g id*
ig2 id2
2
= 0.395 j
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

δα 2
δα 2
2 
1 + QL ]
QL c +
[
1 + 2
5γ
5γ


Q of the Input Circuit
Decreases with shorter channels
Gate / Drain Correlation Factor
Minimum Noise Factor
∂F
Take
= 0 to find the condition for minimum F:
∂WM1
QL ,opt
Fmin = 1 +
4
δγ
5
5γ
.
= 1+
2 ≥ 187
δα
 ω  
δα 2
 c + 1+
5γ
 ωT  
Long Channel
Values

ω
.  
 ≥ 1 + 133
 ωT 

Note: Worst-Case Fmin = 4 (6dB) when gm= gg.
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Architecture / Noise Summary
• MOS Device has gate current noise in addition to
drain current noise.
Optimum Zs exists.
Power savings
• Optimum Qin relatively large.
and lower F by reducing WM1 for Qin < Qopt.
• HSPICE models of MOS noise are inadequate.
• Induced gate effects are not modeled at all.
• Hot Electron effects influence the noise power spectral
density of channel-related noise sources.
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Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
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Complete LNA Schematic
Vdd
Lvdd
Lb2
Input Bias Tee
Vbias
Lb1
Rs
Output
Bias Tee
Vdd
Cb2
M4
Ld
Off Chip Matching
Cb1
Tm
Lg
M2
Lout
M3
M1
Vs
Cm
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Ls
Lgnd
To Spectrum
Analyzer
Die Photo
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S21
Marker 2
Peak S21 22dB
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S11
VSWR 1.38
Marker 2
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S12
Marker 2
Null @ 1.5GHz
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Reverse Isolation
Ld
Lg
1
M2
Cgd3
Lout
M3
3
M1
Cg1+Cpad
Cg2
Ls
Cd
Cpad
Substrate Node
Lgnd
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2
• Substrate tied to lowest
inductance signal ground.
• Parasitic capacitances from
spiral inductors and pads
degrade reverse isolation.
• Simulation with parasitics
shows null in S12 as seen in
experimental data.
Noise Figure / S21 vs. Vdd
30.00
NF / S21 (dB)
25.00
20.00
3.5dB NF / 22dB S21
15.00
10.00
5.00
Vdd (V)
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2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.00
Linearity - IP3
30.00
1dB Comp. = -22dBm (Input)
Output Power (dBm)
20.00
10.00
0.00
-10.00
-20.00
-30.00
-40.00
IP3 = -9.3dBm (Input)
-50.00
-60.00
Source Power (dBm)
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-6.00
-8.00
-10.00
-12.00
-14.00
-16.00
-18.00
-20.00
-22.00
-24.00
-26.00
-28.00
-30.00
-32.00
-34.00
-36.00
-70.00
Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
Stanford University
Performance Summary
Frequency
Noise Figure
S21
IP3 (Input)
1dB Compression (Input)
1.5GHz
3.5dB
22dB
-9.3dBm
-22dBm
Supply Voltage
Power Dissipation
First Stage
1.5V
30mW
7.5mW
Technology
Die Area
0.6µm CMOS
0.12 mm2
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Conclusions
•
•
•
•
CMOS is suitable for low noise above 1GHz.
3.5dB NF is lowest to date for CMOS above 1GHz.
1dB NF can be expected with current generation.
Current CMOS noise models, as in HSPICE, are
inadequate for accurate simulation of RF noise.
• Significant noise contributors are absent from the models.
• Short channel effects have not been properly accounted for.
• More research is required.
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Acknowledgments
Stanford Center for Integrated Systems
Air Force Office of Scientific Research
Howard Swain of Hewlett Packard
for many helpful discussions on CMOS noise
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