A 0.6V HIGH REVERSE-ISOLATION HIGH GAIN SINGLE-STAGE
NON-CASCODE DIFFERENTIAL CMOS LNA
T.T.N. Tran, C.C. Boon, M.A. Do, and K.S. Yeo
Department of Electrical and Electronic Engineering
Nanyang Technological University, Singapore
ABSTRACT
II. LOW VOLTAGE CCC-LNA
In many designs, low supply voltage allows for efficient
use of power. However, it often leads to low reverse isolation
which is critical to the RF front-end component and
particularly to the low-noise amplifier (LNA). In this paper, a
fully integrated differential low-voltage CMOS LNA with
high reverse isolation is presented. This LNA makes use of
the single-stage non-cascode structure and the capacitive
cross coupling (CCC) technique. The CCC technique has
been utilized in many LNA designs. However, in all of the
reported works using CCC, the CCC technique was mainly
used to improve the noise figure (NF), not the reverse
isolation. The poor reverse isolation problem in single-stage
non-cascode structure has never been analyzed in the
CCCLNA. This work shows a novel analysis on the feedback
self-cancellation mechanism to improve the reverse isolation.
Other analysis on input matching, gain and NF was also
performed to show the feasibility of employing CCC
technique for low-voltage LNA as well as the advantages of
CCCLNA over the conventional common-source (CS) and
common-gate (CG) LNA. The LNA consumes only 0.5 mW
from 0.6V supply voltage. It achieves a gain of 14dB and a
NF of 3.5 dB.
The schematic of the CCCLNA is shown in Fig. 1(a). Two
large capacitors Cc are used to cross couple the input devices
M1 and M2. The design in [5] also used the CCC technique to
realize a low-voltage LNA. However, the problem with poor
reverse isolation was left untouched and there were many offchip components required in the design. In [5-10], the CCC
technique is only used to improve the LNA’s NF. This paper
presents a novel analysis on the feedback self-cancellation
using CCC technique and emphasizes on analyzing the
feasibility of using CCC technique for low supply voltage
LNA as well as the advantages of using this technique in
LNA design when compared to the conventional CS and CG
topology.
I. INTRODUCTION
In response to the ultra low power requirement of wireless
transceiver, maximum supply voltages have been steadily
decreasing. A supply voltage of 0.5-0.7V is expected for low
power devices [1]. LNAs are key building blocks in many
modern receiver systems [2-4]. In order to operate at low
supply voltage without degrading the linearity and dynamic
range, the number of transistors stacked in series must be
reduced. In addition, to lower the supply voltage and reduce
the power dissipation simultaneously, a circuit without folded
structure is preferred. In this paper, a fully integrated ultralow power LNA operating at 0.6V for 2.4GHz ISM band is
presented. It has a differential single-stage non-cascode
structure. The poor reverse isolation problem in this structure
is improved by employing the capacitive cross-coupling
(CCC) across the two sides of a differential input stage.
The paper is organized as follows. Details of the design
and circuit implementations are presented in Section II and III
respectively. Design’s performance and comparisons with
state-of-the-art low-power low-voltage LNAs are discussed in
Section IV. Finally, the paper is concluded in Section V.
A. Reverse isolation
Fig. 2 shows the CMOS transistor small signal model with
its parasitic capacitances ,
,
,
and
. A
single-stage non-cascade LNA has very poor reverse isolation
due to the direct feedback paths from output to input through
the parasitic capacitors as shown in Fig.3. Since there are two
feedback paths in the CSLNA and the feedback is normally
dominated by the Cgd path, the CSLNA usually has worse
reverse isolation than the CGLNA. In the CCCLNA, there
exists feedback self-cancellation. The simplified half circuits
as shown in Fig.4 will be used to explain this mechanism.
Since capacitor
is much larger than the parasitic
capacitors, it is considered as short circuit in this analysis.
Fig.1 (a) CCCLNA (b) CCCLNA with added capacitors for extra feedback
cancellation
voltages from Vout+ and Vout- are 180o out of phase which
results in a feedback self-cancellation at the input and an
improvement in the reverse isolation. The same cancellation
mechanism can be applied for Vin-. To analyze the feedback
from the outputs, let us define the equivalent drain-source,
,
drain-gate and gate-source parasitic impedances as
and
respectively. The total impedance at each input node
is defined as which is equal to /2 at matching condition.
,
and
are much larger than .
S12 (dB)
Fig. 2 CMOS transistor small signal model
Fig.5
Fig.3 (a) Output – input feedback paths in common source (CS) LNA (b)
Output – input feedback path in common gate (CG) LNA
of different topologies
The feedback factor from Vout- to Vin+ is:
.
(1)
The feedback factor from Vout+ to Vin+ is:
.
Fig.4 Feedback paths from (a) Vout- to Vin+ (b) Vout+ to Vin+
At each input node, there are feedback voltages from both
Vout+ and Vout- . Vout- is fed back to Vin+ through paths 1 and 2
as shown in Fig. 4(a). These two paths are the same as the
feedback paths in the CSLNA. Vout+ is fed back to Vin+
through paths 3 and 4 as shown in Fig. 4(b). The feedback
(2)
To maximize the feedback cancellation, the feedback
factors from Vout+ and Vout- to Vin+ should be matched.
Equalizing equation (1) with (2) results in a condition
. Impedance is mainly contributed by the
of . Impedance is formed by the
parasitic capacitance output resistance ro and parasitic capacitances
and
in most of the cases. Therefore, to
which are smaller than
maximize the feedback cancellation, the designer can add an
additional capacitor, Ca, across the drain-source terminal as
shown in Fig. 1(b) or an inductor across the drain-gate
terminal. The former method is preferred since on-chip
capacitor normally occupies less area than on-chip inductor.
is as closed to
The size of Ca should be designed so that as possible. To verify the theory, we simulated the
circuits in Fig. 1(a), 1(b), 3(a) and 3(b). The CSLNA and
CGLNA are single sides of the CCCLNA without the cross
coupling capacitor . The four LNAs draw the same amount
of drain current. The transistor sizes used in the four LNAs
are also the same. As shown in Fig.5, the CSLNA has poor
reverse isolation due to the large parasitic capacitor . At
2.4GHz, the CCCLNA shows an improvement of 8dB in term
of reverse isolation when compared to the CSLNA. With the
added capacitor, Ca, the improvement increases to 12dB. The
value of capacitor Ca is varied from 8fF to 17fF. As Ca
approaches which results in
increases, the value of a better reverse isolation as seen in Fig.5. When Ca increases
to 17fF, the reverse isolation starts to drop. The optimum
value of Ca is 15fF in our simulation. The presented
CCCLNA has superior reverse isolation than the CSLNA,
especially at high frequency. At 6GHz, the CCCLNA shows a
reverse isolation improvement of 10dB. With an added
capacitor Ca equals to 15fF, the CCCLNA introduces an extra
26dB of reverse isolation compared to the CSLNA.
Practically, it is hard to achieve a complete cancelation
since matching of parasitic components is a difficult task.
Luckily, in most of the applications, the reverse isolation
requirement is not very strict. A value of better than -30 dB is
parameter. Therefore, a complete feedback
acceptable for
cancellation is not required. Over-designing the reverse
isolation of the LNA may result in trade-offs with other
performance parameters such as gain, NF and chip area. In
non-cascode CS structure, high reverse isolation is hardly
achievable due to the direct feedback paths from output to
input through the parasitic capacitors. By reducing the
transistor’s size of the CSLNA, the parasitic capacitors
become smaller, resulting in a better
but smaller gain and
higher NF. In the CCCLNA, the feedback self-cancellation at
the input makes the -30 dB target more achievable. In our
simulation, the CCCLNA achieves a reverse isolation better
than -30 dB even without the added capacitors Ca. The high
reverse isolation in the CCCLNA is achieved by the feedback
self-cancellation mechanism.
C. Gain and input matching
The voltage gain is:
,
(5)
2
,
is the load impedance. While drawing the same
where
current consumption, the CCCLNA provides double gain
when compared to the conventional CGLNA.
The input impedance of the CCCLNA can be found using
the small signal analysis as shown in Fig.6. Capacitors are
very large so they were considered as short circuit in this
analysis. The single input impedance is found to be:
2
4
1/
(7)
1/ 2
The resonance frequency is:
,
1/√4
It has been proven in [5] that the transconductance of the
CCCLNA is effectively boosted to:
(3)
2
where
is the transconductance of the input device. The NF
of the CCCLNA therefore can be expressed as:
1
1
(4)
2 2
When the input is matched, the CCCLNA’s NF is
1
/ 2
[5]. This NF is lower than of the CGLNA
which is 1
/
. In addition, to achieve the same
matching condition with the CCCLNA, the CGLNA requires
double amount of power consumption.
2
At resonance frequency,
, simply becomes
,
1/ 2
. Therefore, the matching condition for the
CCCLNA is:
B. Noise Factor
,
(6)
1
,
Fig. 6 CCCLNA’s small signal input impedance analysis
(8)
value or the same power
of input matching. At the same
consumption, the CCCLNA achieves a much better match to
the 50Ω source impedance than the CGLNA.
II. CIRCUIT IMPLEMENTATION
A. Output buffer
The main purpose of an output buffer is to match the
output port to the 50Ω load of the measuring equipment. To
avoid the need of de-embedding the LNA’s linearity, a highly
linear buffer is favored. The conventional source follower as
shown in Fig. 9(a) is commonly used due to its high linearity.
Its output impedance is:
Fig.7 NF of CG and CCCLNA
1/
,
(11)
//
is the transconductance of the transistor
.
where
For 50Ω output matching,
is normally chosen to be very
is designed to be 50 Ω.
large and 1/
Vin
Vin
Ms
Vout
Fig.8 Input impedance of CG and CCCLNA
In the case of the CGLNA, the matching condition and the
resonance frequency are, respectively:
RL2
Rout,sf2
Rout,sf1
RL
RL1
(9)
1/
and
(a)
,
Ms
1/√
(10)
(b)
Fig. 9 (a) Conventional source follower output buffer (b) Improved output
buffer
As we can see from equations (5) and (7)-(10), the
or double current
CGLNA requires double value of
consumption and four times larger source inductor, , to
achieve the same matching condition and same voltage gain
with the CCCLNA.
Plotting of NFs and input impedances of the CCCLNA
,
and CGLNA versus the input device’s transconductance,
at the resonance frequency are shown in Fig. 7 and Fig. 8.
The dotted lines represent the simulation data and the solid
lines represent the analysis data. The simulation results agree
well with the analysis. As shown in Fig. 7, the NF of the
CCCLNA is much lower than of the CGLNA. Even when we
increase the drain current of the CGLNA to make the CG’s
, the NF of the CGLNA is still
g equal to the CCC’s
,
higher than of the CCCLNA. The CCCLNA shows a superior
performance in term of NF over that of the CGLNA. Fig. 8
illustrates the advantage of CCCLNA over CGLNA in term
Fig. 10 Output matching of conventional source follower
,
Fig. 11 Output matching of improved buffer and the low-voltage CCCLNA
(with output buffer)
When the source follower’s input is connected to our
LNA, its output matching is greatly degraded. Fig. 10
demonstrates this problem. When the source follower in Fig.
, is better than
9(a) is simulated alone, its output matching,
-20dB. However, when it is integrated with our LNA, the
output matching of the whole circuit is degraded, especially
near the resonance frequency. In this simulation, the
resonance frequency is around 2.65GHz. The degradation of
the output matching can be explained as follows. If two twoport networks A and B are connected in series, the scattering
matrix
of the equivalent circuit is:
(12)
1
1
1
//
1/
When
is much larger than ,
can be
,
approximated to
and the effect of 1/
on total
output impedance is neglected. The output is matched when
/
R equals to 50Ω. The buffer’s gain equals to which is much smaller than one. This helps to lower the
effect of the second term in the
equation to the total
value. The total
will be dominated by the of the
buffer. Fig. 11 shows the output matching of the improved
buffer and of the low-voltage CCCLNA integrated with this
buffer. As expected, the output matching in the two cases are
not very different. The simulation results agree well with the
analysis.
B. Full circuit implementation
Fig. 12 shows a low-voltage CCCLNA designed to operate
at 2.4GHz in a 0.18µm RF CMOS technology with 0.6V
act as output impedance
supply voltage. On-chip inductors
and have quality factor of 8.3. Capacitors are used to cross
couple
and . Capacitors
and
are bypass
capacitors. On-chip inductors are used to tune out the total
capacitances at the source nodes including pad capacitances.
To facilitate accurate measurement, two separate
differential output pads are implemented. Output 1 is placed
before the buffer and Output 2 is placed after the buffer.
Voltage gain, output and input matching will be measured
from Output 2. The other parameters like NF, reverse
isolation and IIP3 will be measured from Output 1. When one
output is measured, the other is open circuit. The gain of the
LNA equals to the gain measured from Output 2 subtracting
the loss from the output buffer.
1
and
are the S-parameters of A and B
where
respectively . In our case, network A represents the LNA and
network B represents the output buffer. Ideally, we want
to be dominated by
. It can be realized by designing
and
to be much smaller than one so that the contribution
of to the total
/ 1
is neglected.
However, the source follower’s gain normally equals to one
and at resonance frequency, the output impedance of the
LNA is very large which results in a
value of
approximately to one. Therefore, the
equals to:
/ 1
(13)
contributes a
is small, the term
/ 1
As
significant amount to the total . The value can’t be
approximated to and the total output matching is therefore
degraded. To solve this problem, a buffer as shown in Fig.
9(b) was designed. The output impedance of the improved
buffer is:
(14)
Fig. 12 The low-voltage CCCLNA with improved output buffer
1.2 mm
Output 2
NF (dB)
Input
Output 1
Fig.13 Chip micrograph of the presented low-voltage CCCLNA
S11 and S22 (dB)
Voltage gain (dB)
Fig.16 Simulated and measured NF of the presented low-voltage CCCLNA
Fig. 14 Simulated and measured voltage gain of the presented low-voltage
CCCLNA
Fig.17 Simulated and measured S11 and S22 of the presented low-voltage
CCCLNA
25.0
Fundamental tone
0
IM3 tone
Pout (dBm)
-25.0
-50.0
-75.0
-100.0
IIP3 = -6.8dBm
@2.4 GHz
Freq (GHz)
-125.0
-40
-30
Fig.15 Simulated IIP3 at 2.4GHz
-20
Pin (dBm)
-10
0
Fig.18 Simulated and measured S12 of the presented low-voltage CCCLNA
TABLE I.
PERFORMANCE COMPARISONS
Tech
(nm)
Vdd
(V)
Power
(mW)
Freq
(GHz)
Gain
(dB)
NF
(dB)
S11
(dB)
IIP3
(dBm)
Differen
tial?
This
work
180
0.6
0.5
2.4
14
3.5
<-22
-6.8
Yes
[11]*
90
0.6
3
2.4
15
3
<-10
-7
No
[12]*
90
0.75
3.75
1.95
23
1.6
<-37
0
Yes
0.9
0.5
0.7
0.6
3.9
1.0
7.76
0.4
2.44
4.7
2-2.5
3
15.3
16.8
16.7
9.1
3.34
2.7
3.53
4.7
<-16
<-18
<-15
<-20
-10
-18.5
-0.5
-11
No
No
No
No
[13]
0.13
[14]
90
[15]*
180
[16]
130
*: simulation results
IV. MEASUREMENT RESULTS
The prototype of the CCCLNA is fabricated in a six-metal
0.18 µm CMOS technology for the 2.4 GHz ISM band. The
die micrograph is shown in Fig. 13. The total die area
including the output buffer and pads is 1.2x1.0mm2.Inductors
and are on chip. Inductors
are used to tune out the
total capacitances at the source nodes including pad
act as output impedance. The LNA
capacitances. Inductors
was purposely designed with a positive frequency offset in
order to account for un-modeled parasitic capacitances and
inductances. The simulated and measured voltage gain is
plotted in Fig.14. The LNA’s voltage gain is 14dB at 2.4GHz.
Fig. 15 plots an IIP3 of -6.8 dBm at 2.4GHz. The simulated
and measured NF is shown in Fig. 16. Several dies were
measured and mean value of the NF is plotted. The difference
between the measured and simulated NF is owed to the
process variations. The LNA achieves a NF of 3.5dB at
2.4GHz. The comparison between the measured and simulated
and
is plotted in Fig. 17. The LNA has good
value is better than -22dB and
input/output matching. The
value is better than -15dB at 2.4GHz. The simulated
the
is shown in Fig.18. The LNA has good
and measured
reverse isolation of -37dB. The core LNA draws 0.83mA from
a 0.6V voltage supply. Total power consumption is 0.5mW.
The comparisons of this LNA with published literatures are
summarized in Table II. The LNAs in [11]-[16] operate at
supply voltages of 0.5-0.9V. Among the designs, the
presented LNA consumes the least power. The power
consumption of [16] is quite comparable to the presented
LNA, but the NF is 4.7dB which is quite high. In the
presented LNA, there is a tradeoff between NF and power.
For lower NF, higher power is required. However, LNA’s NF
is not a critical performance parameter for the ISM band
standard [18]. A NF of 3.5 dB is acceptable for such low
power consumption. The design in [12] and [15] have good
linearity but more power is consumed when compared to the
rest. The figure of merits (FOM1 and FOM2) defined in [19]
are used to compare the performance of the LNAs.
Topology
Single-stage non-cascode
CCC
Inductive source degeneration
with forward body biasing
Inductive source degeneration
with off-chip gate inductors
Inductive source degeneration
Transformer – folded cascode
Folded cascode
Sub-threshold CS
FOM1
FOM2
12.88
6.08
6.55
-0.4
12.17
12.17
4.98
15.76
2.45
10.4
-5
-2.74
2
-0.6
The FOM1 is a function of the operating frequency, gain,
noise factor, and power consumption. It is given by:
1
(15)
.
10
1
.
FOM2 includes IIP3 and is given by:
2
10
.
1
.
.
3
(16)
Based on the FOM calculated in Table I, the presented
work shows comparable performances to the other designs.
V. CONCLUSION
An ultra-low voltage single-stage non-cascode LNA was
presented. With the same structure, the conventional CSLNA
normally has better noise figure but lower reverse isolation.
The basic CGLNA on the other hand has better reverse
isolation but much higher NF. The CCC technique introduces
the self-cancellation of output-to-input feedback, therefore
solves the reverse isolation problem in CSLNA. The LNA
using this technique can also achieve NF much lower than of
the CGLNA. Novel analysis on the reverse isolation and input
matching of the low-voltage CCCLNA was performed. Other
analysis on gain and NF was also presented to show the
advantages over the conventional CS and CGLNA. The
design is very suitable for low supply voltage such as 0.6V. At
2.4GHz, it has good reverse isolation of -37dB and good input
matching of -22dB. The total voltage gain is 14dB. It draws
only 0.83mA from 0.6V supply voltage and produces only
3.5dB NF. The total power consumption is only 0.5mW
VI. ACKNOWLEDGMENT
The authors would like to thank Global Foundries
Singapore for chip implementation. They would also like to
thank Lim Wei Ming, for his help in the measurement.
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Thi Thu Nga Tran received the B.E. degree (Hons.)
in electronics from Nanyang Technological
University (NTU), Singapore, in 2008. Currently, she
is working toward the Ph.D. degree in NTU,
Singapore.
Her research interests include ultra-low power
RF front-end IC design and mixed-signal circuits for
high speed applications.
Chirn Chye Boon received the B.E. (Hons) (Elect) in
2000 and Ph.D. (Elect. Eng.) in 2004 from the
Nanyang Technological University, Singapore.
In 2005, he joined NTU as a Research Fellow and
became an Assistant Professor in the same year. Before
that, he was with Advanced RFIC, where he worked as
a Senior Engineer. He specializes in the RFIC design
for bio-medical and communication applications.
Professor Boon is a reviewer for IEEE
Transactions of Circuits and Systems–I, IEEE Microwave and Wireless
Components Letters and IEEE Transactions on Microwave Theory and
Techniques. He provides consultation to multinational companies and serves
as a program committee member in several international conferences.
Manh Anh Do obtained his B.E. (Hons) (Elect) in 1973,
and Ph.D. (Elect. Eng.) in 1977 both from University of
Canterbury, New Zealand.
Between 1977 and 1989, he held various positions
including: R & D engineer and production manager at
Radio Engineering Ltd., research scientist at Fisheries
Research Centre, New Zealand, and senior lecturer at
National University of Singapore. He joined the School of
Electrical and Electronic Engineering, Nanyang
Technological University (NTU), Singapore as a senior
lecturer in 1989, and obtained the Associate Professorship in 1996 and the
Professorship in 2001. He has been a consultant for many projects in the
Singapore electronic industry, and was the principal consultant for the design,
testing and implementation of the $200 million Electronic Road Pricing (ERP)
island-wide project in Singapore, from 1990 to 2001. His current research is on
digital and mobile communications, RF IC design, mixed-signal circuits and
intelligent transport systems. Before that, he specialsed in sonar designing,
biomedical engineering and signal processing. Since 1995, he has been Head of
Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE,
UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).
Prof. Do is a Chartered Engineer. He is a Fellow of the Institution of
Engineering Technology (IET). He was a Council Member of IET, U.K.,
from 2001to 2004 and an Associate Editor for the IEEE TRANSACTIONS
ON MICROWAVE THEORY AND TECHNIQUES in 2005 and 2006.
Kiat Seng Yeo received his B.E. (Hons) (Elect) in 1993,
and Ph.D. (Elect. Eng.) in 1996 both from Nanyang
Technological University, Singapore.
He is currently the Head of the Division of
Circuitsand Systems and a Professor of electrical and
electronic engineering with NTU. He is a recognized
expert in CMOS technology and low-power CMOS IC
design. He gives consulting to multinational corporations.
He is the holder of 15 patents. He has published four
books (International editions) and more than 250 papers in his areas of
expertise. His research interests include device modeling, low-power circuit
design, and RFIC design.
Prof. Yeo serves in the organizing and program committee of several
international conferences as the General Chair, a Cochair, the Technical Chair,
etc.