ARQ-HFADC001
ARQ-HFADC001
RAD-HARD, 15b 100 MSPS ADC
FEATURES




Up to 15 bit resolution
Up to 100MSPS sampling
Up to 50MHz analog input
THD=74dB @ 5MHz
DESCRIPTION
ARQUIMEA’s ARQ-HFADC001 is a radiation hardened
15b 100MSPS ADC available in a TBD-pin Ceramic
Quad Flat Package.
The ARQ-HFADC001 design uses specific circuit
topology and layout methods to mitigate total
ionizing dose effects and single event latch-up.
These characteristics make the ARQ-HFADC001
especially suited for the harsh environment
encountered in Space missions. It is guaranteed
o
o
operational from -55 C to +125 C and space
qualified.
APPLICATIONS






Aerospace instrumentation
Space data acquisition systems
High speed data acquisition systems
CCD signal processor
Radiation detector
Radiation spectrometer
GENERAL KEY SPECIFICATION





The ARQ-HFADC001 is especially designed to
optimize power consumption and dissipates less
than TBC W in normal operation, while maintaining a
proper performance.
Nominal Power supply operation: 3.3V (I/O)
Analog Input Frequency: 100k to 50MHz
Analog input range: 2Vpp
o
o
Operational from -55 C to +125 C
Space qualified
RADIATION HARDENING
PARAMETER
Value
UNIT
COMMENTS
TID
300
Krad
TBC
2
SEL
60
MeVcm /mg
TBC
SEE performance 1E-10
Err/Bit/day
For GEO orbit TBC
More information about radiation hardening features and radiation test conditions is available under request.
AVAILABLE OPTIONS
PRODUCT
Quality Level
PACKAGE (*)
OPERATING
TEMPERATURE
RANGE
ORDERING
NUMBER
ARQARQ-HFADC001 So
o
S (Space)
Die
-55 C to 125 C
HFADC001
DIE
ARQARQ-HFADC001
Bo
o
SCC B (Space)
xxx-pin LQFP
-55 C to 125 C
HFADC001
CQFPXXX
(*) other packaging options, including raw die format, are also available under request.
Description
Die
Package
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This
documentation is not contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no
obligation towards third parties, liability or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
1
ARQ-HFADC001
Index
FEATURES ................................................................................... 1
Glossary
APPLICATIONS ............................................................................ 1
ADC
ASIC
Bin.
Dec.
IC
LSB
MSB
POR
QA
S&H
SEE
SEL
SPI
TID
GENERAL KEY SPECIFICATION ..................................................... 1
DESCRIPTION .............................................................................. 1
RADIATION HARDENING ............................................................. 1
AVAILABLE OPTIONS ................................................................... 1
ABSOLUTE MAXIMUM RATING ................................................... 3
ELECTRICAL CHARACTERISTICS (at room temperature) .............. 4
DIE & PACKAGE PINOUT ............................................................. 5
IO pins Description ..................................................................... 5
Analog-to-Digital Converter
Application-Specific Integrated Circuit
Binary
Decimal
Integrated Circuit
Less Significant Bit
Most Significant Bit
Power-On Reset
Charge Amplifier
Sample and Hold
Single Event Effect
Single Event Latch-up
Serial Port Interface
Total Ionising Dose
ADC BLOCK DESCRIPTION ........................................................... 5
ESD CAUTION............................................................................ 13
QUALITY STANDARDS ............................................................... 13
IMPORTANT NOTICE ................................................................. 13
Revision History ..................................................................... 15
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
2
ARQ-HFADC001
ABSOLUTE MAXIMUM RATING
Description
Symbol
Maximum rating
Units
Peripheral I/O Supply
Voltage
VDDD
VDDA
4.5
V
Input Voltage
Vin
-0.5 to VDD + 0.5
V
Top
-55 to 125ºC
ºC
TSTG
-65 to 150
ºC
TSOL
300
°C
Operational
temperature range
Storage Temperature
(non-operating temp.)
Soldering lead
temperature (10 s)
Recommended max
operating range
Operating from
2.97V to 3.63V
Nominal Values 0V, 3.3V
VDD rating should not be
exceeded
Table 1: Absolute Maximum Ratings
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
3
ARQ-HFADC001
ELECTRICAL CHARACTERISTICS (at room temperature)
Nominal Supply Voltage unless otherwise specified
ADC Parameters
Parameter
ADC_OE
Offset Error
ADC_FSE
Full Scale
Error
ADC_Gf
Gain Flatness
ADC_Gs
Gain Stability
ADC_THD
Total
Harmonic
Distortion
Spurious Free
Dynamic
Range
ADC_IVCC1
Operating
Current
consumption
ADC_PSRR
Power Suply
Rejection
Ratio
ADC_Fqc
Sample rate
ADC_Func.
Functional
verification
Power Supply
ADC_SFDR
Timing
ADC_ENOB
Effective
Number of
Bits
Func
Dynamic
Static
Symbol
Description
Limites HF
typ
Max
Unit
Without correction. Zero
value in input and check the
output.
TBD
LSB
Without correction
TBD
%FSR
Fin= 5MHz, 25MHz, 50MHz
0.4
dB
Fin= 5MHz at operational
temperature range
0.1
dB
Test Conditions
Offset error is the difference between
the measured and ideal voltage at the
analog input that produces the first
code or middle code (differential input
case) at the output.
Gain Error or Full scale Error is the
difference between the measured full
scale and ideal full scale. This is usually
expressed as a percentage of full scale.
Gain Flatness is the measure of the
variation of gain over a specified
frequency range
Gain Stability is the measure of the
variation of gain over the temperature
range
THD is the ratio of the rms sum of the
first five harmonic components to the
rms value of a full-scale input signal.
(Note)
ENOB is a measurement of the
resolution with a sine wave input. It is
related to SINAD and is expressed in
bits by ENOB = [(SINADdB − 1.76)/6.02]
(Note)
SFDR is the difference, in decibels (dB),
between the rms amplitude of the
input signal and the peak spurious
signal. (Note)
IVCC1 is the consumption current at
VCC when the converter is Converting
at 10MHz frequency.
Power supply rejection ratio (PSRR) is
the ratio of the change in power supply
voltage to the resulting change in the
converter’s gain or offset.
Maximum operating frequency
expressed in MSamples Per Second
(MSPS).
Test that all Registers, different mode
are configurable and working properly.
Min
Fin= 5MkHz
74
Fin= 25MHz
64
Fin= 50MHz
-
dB
Resolution
15
Fin= 5MkHz
Fin= 25MHz
12
10
Fin= 50MHz
Fin= 5MkHz
74
Fin= 25MHz
64
Fin= 50MHz
-
n
dB
Fin=25MHz, Fs= 100 MSPS
250
mA
VCC=Min to Max Voltage
TBD
LSB/
V
100
MSP
S
20
Functional Modes if testable.
(mode / cal, etc)
Note: Dynamic tests are typically made with the analog coherent signal (sinus waveform) at the rated frequency with a signal power of 0.1 dB,
0.5 dB, or 1 dB below full scale (dBFS).
Table 2: ADC Electrical Parameters
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
4
ARQ-HFADC001
DIE & PACKAGE PINOUT
TBD
IO pins Description
TBD
ADC BLOCK DESCRIPTION
The ARQ-HFADC001 analog-to-digital converter (ADC) is used for digitizing high frequency, wide dynamic
range signals with input frequencies of up to 50 MHz and sampling up to 100 MSPS.
ADC Equivalent Circuits:
CMO_ADC,
CMO!_ADC,
CMI_ADC,
REF_ADC,
BIAS_ADC
IN_ADC,
IN_CDS
from REGs
A1a, A1b, A1c, A2, A3
from
BG
ADC
from DIG ADC,
DIG ADC & DAC
CLK_ADC
TEST_ADC,
pc1_ADC,
p1_ADC,
p2_ADC,
pc2_ADC
Figure 1: ADC equivalent circuit
ADC Architecture
Figure 2: ADC Architecture
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
5
ARQ-HFADC001
Four different constitutive sub-blocks, which correspond to the analog, digital, bias, and clock conditioning
sections, can be identified. They are denoted as PipeADC_ANALOG, PipeADC_DIGITAL, PipeADC_BIAS and
MASTER_ CLOCK, respectively. In what follows, a brief introduction of their main features and properties is
presented.
The MASTER_CLOCK part reconstructs the clock master providing a square output signal with 50% duty
cycle, 100ps rising and falling time and maximum jitter of 0.15ps. A differential implementation based on a
low-jitter LVDS receiver is recommended.
The Pipeline ADC_DIGITAL part’s functions:
- Provides, via SPI, the configuration signals for both the analog and digital cores,
- Allows loading and monitoring the calibration error codes from an external FPGA or PC.
- Performs the time alignment of unsynchronized sub-codes, given by precode[20:0].
- Performs the digital correction task eliminating redundancy after synchronization.
- Controls the signals to be provided at the output bus outcode[20:0]. Its functionality is specified by the
external signal modeADC[2:0].
- Reconfigures the analog section for calibration, provides the digital stimulus for the error measurements
and generate the calibration codes.
The Pipeline ADC analogue part is formed by a front-end Sample&Hold followed by seven stages (STG) with
2.5-bit resolution. Calibration facilities are included in stages from STG1 to STG4, herein denoted as SUC1 to
SUC4 (SUC, stage under calibration). By default the two most significant stages are calibrated. Two extra
SUCs are considered for greater calibration flexibility:
Figure 3: Pipeline ADC analogue part
The PipeADC_BIAS part generates the voltage
references and power supplies for the HFADC.
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
6
ARQ-HFADC001
ADC analog Input/Output Consideration
The master clock output (ckin) is considered an analog signal, since its properties (shape, duty cycle and
jitter) has a great impact on the behavior of switched-capacitor circuits.
Name
INp_ADC, INm_ADC
INp_CDS, INm_CDS
Function
Diff. Inputs
Diff. Inputs
BIAS_ADC
REFp_ADC,
REFm_ADC
CMI_ADC
CMO1_ADC
CMO
Current Ref.
Voltage Ref.
Voltage Ref.
Voltage Ref.
Voltage Ref.
Description
Differential input. Ain= 1V (2Vpp) around cmo ≈1.05V, fin=50MHz, Zin<0.6KOhms
Correlated doubled sampled differential input signals. In typical conditions:
INp_CDS = INm_CDS = 1.05V
External current generation. Ibias = 100uA, flowing throughout the pin to ground.
ADC References: cmo + Ain/2, cmo - Ain/2 Ain is the maximum ADC input
amplitude (1V) Referenced to the output common mode cmo = 1.05*(vdda/1.8).
Input common-mode. In typical conditions: cmi_ADC = 0.95V
OTA common mode (1 STG). In typical conditions: cmo1_ADC = 0.92V
OTA common mode (2 STG). In typical conditions: cmo_ADC = 1.05V
CLK_ADC
Input
Master clock: 100MHz (Down to 20 MHz is admissible, but not specified)
p1_ADC, p2_ADC,
pc1_ADC, pc2_ADC
TESTp_ADC,
TESTm_ADC
Output
Clock signals internally generated for the trimming of the clock phase generator.
Maximum fan-out: 50fF. They must be buffered.
ADC Differential intput test signals – Do not care
Output
Table 3: ADC analog Input/Output
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
7
ARQ-HFADC001
Analog Input signals (INp_ADC, INm_ADC)/ (INp_CDS, INm_CDS)
The primary differential input (INp_ADC,INm_ADC) must satisfy 15 effective bits at nominal 100MHz
sampling frequency to take advantage of ADC performances.
Maximum Peak current of 30mA are stated.
The correlated double-sampled pair (INp_CDS,INm_CDS), are biased externally and depend of Vdda Power
Supply value.
INp_CDS=INm_CDS=1.05*(vdda/1.8)
ADC Voltage Reference (REFp_ADC, REFm_ADC)
Similarly than for the primary differential input, the converter references (REFp_ADC, REFm_ADC) must
satisfy 15 effective bits at the nominal 100MHz sampling frequency to assure no limitation in the ADC
performance.
Particular care should be considered on inductive parasitic that can reduce consequently the ADC
performances. Indeed maximum Peak current of 30mA and stationary current of 2mA are stated.
ADC Bias Current Reference (BIAS_ADC)
The ADC Bias Current Reference of the internal current bias generator should be trimmed as depicted in
the
ADC Recommended Procedure section in order to source 100uA.
Pull down through Ribias=9.56kΩ is recommended.
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
8
ARQ-HFADC001
Common Mode Voltages (CMI_ADC, CMO1_ADC, CMO):
The Common bias Voltages are biased externally with 1% tolerance and depend of Vdda Power Supply
value.
- CMI_ADC= 0.95*(vdda/1.8)
-
-
CMO1_ADC= 0.92*(vdda/1.8)
CMO= 1.05*(vdda/1.8)
Clock (CLK_ADC, p1_ADC, p2_ADC, pc1_ADC, pc2_ADC)
Table 4 summarizes the main specifications of the required clock input.
Table 4: Specifications of the Master Clock
The clock phase generator should be trimmed by adjusting p1_ADC, p2_ADC, pc1_ADC, pc2_ADC signals as
depicted in
ADC Recommended Procedure section.
ADC digital Input/Output Consideration
Name
Bit range
STARTCAL_ADC
1
D[0..20]
<20:0>
READY_ADC
1
OR_ADC
1
ENDCAL_ADC
1
Direction
Description and comments
DEFINITION: Start calibration measurements. The number of stages
under measurements is defined by word stgMeas in CONFIG_CAL
Input (synchronous)
register.
GENERATION: dataready rising edge can be trigger external circuit.
INTERNALLY SAMPLED BY: p1 rising edge.
DEFINITION: ADC output code.
Output (synchronous)
TIMING: it changes with p1 rising edge.
CODIFICATION: shifted binary
DEFINITION: data ready.
Output
TIMING: The rising edge of p2 determines the best point for outcode
(synchronous)
sampling. P1 Falling edge is used.
Output
DEFINITION: Over-ranging detector.
(synchronous)
TIMING: it changes with p1 rising edge
DEFINITION: This signal indicates when any calibration codes are
available:
endCal takes the logical value ‘1’ just when the calibration codes are
available after measurements finish or the calibration codes have been
Output
loaded via SPI.
(synchronous)
endCal takes the logical value ‘0’ just when the calibration
measurement phase starts, the writing operation of the calibration
register via SPI starts or when the calibration logic is reset.
DEFAULT VALUE ON PoR: 0.
Table 5: ADC digital Input/Output
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
9
ARQ-HFADC001
Timing chronogram
Figure 4: ADC Chronogram in normal operation
ADC Recommended Procedure
A. Registers Configuration
In order to configure the ADC in its nominal performances, the following SPI sequence applies (See
p¡Error! Marcador no definido. for ¡Error! No se encuentra el origen de la referencia. in ¡Error! No
se encuentra el origen de la referencia.):
SPI Address
(hex)
406h
Data_In
(Hex)
0x3B74
405h
0xF500
404h
0x00FF
403h
402h
0xFFFF
0xFFFF
401h
0xFFFF
Description
ADC activation
Nominal configuration
Disable Output stages test
CALDAC current generator tuning
Disable Input stages test
Comp IBias Tuning in stages
Comp IBias Tuning in stages
Comp IBias Tuning in stages
OTA IBias Tuning in stages
OTA IBias Tuning in stages
B. Bias Current Trimming
The Bias Current trimming is performed through the following SPI sequence in order to source
100uA through BIAS_ADC pin loaded with a 9.56kΩ resistor:
SPI Address
(hex)
400h
Data_In
(Hex)
0x80FC
405h
0xFX00
Description
Ibias Internal (+current monitoring)
ADC Mode disable, no s/h gain
Nominal Latch Phase Control
Tune the value Xh in order to have 100µA
sourcing from BIAS_ADC pin
By default Xh=5h
(See effect of this register during test)
Once the Bias current is trimmed, send the following command through SPI for power saving:
SPI Address
Data_In
Description
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
10
ARQ-HFADC001
(hex)
400h
(Hex)
0x80F4
Ibias Internal (without current monitoring)
C. Clock synchronization (phase generator trimming)
The clock synchronization is performed trough SPI as follow in order to reach the clock
performances depicted in p9:
SPI Address
(hex)
400h
Data_In
(Hex)
0xXXF4
Description
Tune the value XXh in order to have
timing diagram of Figure 5.
By default XXh=80h
Nominal XXh=C6h (per design)
(See effect of this register during test)
Figure 5: ADC timing diagram
Note: At the nominal sampling frequency (100Msps), the clock phase’s pc1 and pc2 must be
synchronized with falling edge of p1 and p2, respectively. Their duty cycle can be adjusted through
SPI in order to have a pulse width of 1.4ns.
D. Operation Mode with Calibration option
To initiate an operation Mode with standard calibration option, the following SPI command should
apply
SPI Address
(hex)
400h
Data_In
(Hex)
0xXX14
Description
SUC1 to SUC2 calibrated
Note: The code XXh has been defined in C
E. Calibration (TBC)
In order to begin internal calibration:
- Apply pulse Voltage of 200ns on STARTCAL_ADC pin.
- Check that the output pin ENDCAL_ADC goes from ‘0’ to ‘1’ when the calibration finish.
F. ADC operation
The data bus is shared between the ADC and the DAC.
In order to enable these parallel signals for the ADC operation, the following SPI command apply:
SPI Address
(hex)
500h
Data_In
(Bin)
001x xxxx xxxx xxxxb
Description
SUC1 to SUC2
calibrated
Note:
- The code x xxxx xxxx xxxxb corresponds to the DAC Configuration (e.g. Keep this code to ‘0 1110 1110 0001b’
will reinitiate DAC configuration to its nominal mode without taking into account tuning performed in
¡Error! No se encuentra el origen de la referencia. section p¡Error! Marcador no definido.)
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
11
ARQ-HFADC001
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
12
ARQ-HFADC001
ESD CAUTION
ESD (electrostatic discharge) sensitive device - Electrostatic charges as high as TBC V readily accumulates on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
QUALITY STANDARDS
ARQUIMEA INGENIERÍA S.L.U. develops its activities under the premises of quality and sustainability, offering
efficient, liable and innovative technologies and solutions to its customers.
ARQUIMEA’s Quality Management System meets the requirements of ISO 9100:2010 Aerospace Series, and has
been audited and certified by the Spanish Association for Standardization and Certification, AENOR.
In order to meet the highest quality and reliability, ARQUIMEA designs and develops its aerospace product line
according to military and space standards.
Our space microelectronic devices are available in one or more of the following processes:
• Equivalent to QML 38535 LEVEL Q or Level V*
• Equivalent to ESCC 9000 Level C or level B*
For procurement in die form
• In accordance with ECSS-Q-ST-60-05C
• Equivalent to QML 38534 LEVEL H or Level K*
*With Radiation Qualification
IMPORTANT NOTICE
ARQUIMEA INGENIERÍA S.L.U. and its subsidiaries (ARQUIMEA) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue any
product or service without notice. Customers must obtain the latest relevant information before placing orders and
must verify that such information is current and complete. All products are sold subject to ARQUIMEA’s terms and
conditions of sale supplied at the time of order acknowledgment.
ARQUIMEA warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with ARQUIMEA’s standard warranty. Testing and other quality control techniques are used to the
extent ARQUIMEA deems necessary to support this warranty. Except where mandated by legal requirements,
testing of all parameters of each product is not necessarily performed.
ARQUIMEA assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using ARQUIMEA components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This documentation is not
contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no obligation towards third parties, liability
or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
13
ARQ-HFADC001
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the ARQUIMEA product would reasonably be expected to cause severe personal injury or death, unless officers of
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Buyers acknowledge and agree that any such use of ARQUIMEA products which ARQUIMEA has not designated as
military-grade or space-grade is solely at the Buyer's risk and that they are solely responsible for compliance with all
legal and regulatory requirements in connection with such use.
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This
documentation is not contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no
obligation towards third parties, liability or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
14
ARQ-HFADC001
Revision History
Date
Released
23-07-2014
Issue
Section
Changes
Draft A
All
Initial Release
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This
documentation is not contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no
obligation towards third parties, liability or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
15
ARQ-HFADC001
ARQ-HFADC001 Draft A, Date: 25-07-2014
The information contained herein is as of publication issue. Production processing does not necessarily include testing of all parameters. This
documentation is not contractual and content delivery cannot be considered as an offer or contract. Under this document, the Company assumes no
obligation towards third parties, liability or guarantee whatsoever.
© Arquimea Ingeniería, S.L.U.
www.arquimea.com
16