AT572D940-EB DIOPSIS 940HF
Evaluation Board
....................................................................................................................
User Guide
7014A–DSP–03/09
1-2
7014A–DSP–03/09
DIOPSIS 940HF Evaluation Board User Guide
Table of Contents
Section 1
Introduction................................................................................................................. 1-1
1.1
Deliverables ....................................................................................................................... 1-1
1.2
Electrostatic Warning ......................................................................................................... 1-1
1.3
Before Powering Up........................................................................................................... 1-1
Section 2
Functional Description................................................................................................ 2-1
2.1
DCM Resources................................................................................................................. 2-1
2.2
DBM Resources................................................................................................................. 2-1
2.3
DEB Block Diagram ........................................................................................................... 2-2
Section 3
Mechanical Description .............................................................................................. 3-1
3.1
Layout of the two Boards ................................................................................................... 3-1
3.2
Mechanical Dimensions ..................................................................................................... 3-3
3.3
DCM and DBM Component References............................................................................ 3-5
Section 4
Hardware Configuration ............................................................................................. 4-1
4.1
DCM Hardware Configuration............................................................................................ 4-1
4.2
DBM Hardware Configuration ............................................................................................ 4-5
Section 5
Functional Blocks ....................................................................................................... 5-1
5.1
Description ......................................................................................................................... 5-1
5.2
DCM Blocks ....................................................................................................................... 5-1
5.2.1
D940HF ............................................................................................................... 5-1
5.2.2
Power Supply Logic ............................................................................................. 5-1
5.2.3
Power Measurement............................................................................................ 5-2
5.2.4
Reset Logic.......................................................................................................... 5-2
5.2.5
Clock Logic .......................................................................................................... 5-3
5.2.6
SDRAM................................................................................................................ 5-4
5.2.7
NAND Flash......................................................................................................... 5-4
5.2.8
Parallel Flash ....................................................................................................... 5-4
5.2.9
Ethernet PHY....................................................................................................... 5-5
5.2.10 PIO Selectors ...................................................................................................... 5-5
5.2.11 ICE Interface Switch ............................................................................................ 5-6
DIOPSIS 940HF Evaluation Board User Guide
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Table of Contents (Continued)
5.2.12 Module Connectors.............................................................................................. 5-7
5.3
DBM Blocks ....................................................................................................................... 5-9
5.3.1
Power Supply Logic ............................................................................................. 5-9
5.3.2
Reset Logic........................................................................................................ 5-11
5.3.3
Clock Circuitry for CODECs............................................................................... 5-11
5.3.4
Audio Interface .................................................................................................. 5-11
5.3.5
JTAG ICE Interface............................................................................................ 5-14
5.3.6
CAN Interface .................................................................................................... 5-15
5.3.7
Secure Digital .................................................................................................... 5-16
5.3.8
Real Time Clock ................................................................................................ 5-16
5.3.9
DBGU, USART0 and MIDI-IN............................................................................ 5-17
5.3.10 USB Host and Device ........................................................................................ 5-18
5.3.11 Ethernet Interface .............................................................................................. 5-19
5.3.12 External Interrupt ............................................................................................... 5-20
5.3.13 Header Connectors............................................................................................ 5-21
5.3.14 DBM LEDs ......................................................................................................... 5-23
5.3.15 Module Connectors............................................................................................ 5-23
Section 6
Schematics................................................................................................................. 6-1
6.1
DCM Board Schematics..................................................................................................... 6-1
6.2
DBM Board Schematics..................................................................................................... 6-7
Section 7
Parts Lists................................................................................................................... 7-1
7.1
DCM Parts List................................................................................................................... 7-1
7.2
DBM Parts List ................................................................................................................... 7-2
Section 8
Revision History ......................................................................................................... 8-1
8.1
Revision History ................................................................................................................. 8-1
DIOPSIS 940HF Evaluation Board User Guide
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7014A–DSP–03/09
Section 1
Introduction
DIOPSIS® 940 HF Evaluation Board (part no. AT572D940-EB), DEB in short, is an effective platform for
evaluating chip performance and developing code for applications based on the DIOPSIS 940 HF.
From now on DIOPSIS 940 HF will be referred to as D940HF.
This manual is a description of the hardware included in the D940HF Evaluation Board (DEB).
The DEB is a system composed of two boards: the D940HF CPU Module (DCM) and the D940HF Back
Module (DBM). The DCM is plugged into the DBM by using SMD board connectors.
The DEB board will be described both at top level (see Section 2) and at single block level (see Section
5).
The complete collection of the DEB schematics is described in Section 6.
The main part lists are reported in Section 7.
For a detailed description of the DEB devices refer to the producer’s data sheet.
1.1
Deliverables
The AT572D940-EB is included in a package whose main items are:
1.2
!
DEB Board (DCM plus DBM)
!
Peripheral cables used to connect internal resourceso to D940HF
!
A universal input AC/DC power supply without plug adapter, for more details see “Before Powering
Up”
!
A DVD-ROM containing summary and full datasheets with electrical and mechanical characteristics,
application notes and getting started documentation. The D940HF software package is provided as
well. All the documentation included will allow the user to quickly evaluate the chip.
Electrostatic Warning
The AT572D940-EB evaluation board is shipped in a protective anti-static package. The boards must not
be exposed to high electrostatic potentials. A grounding strap or a similar protective equipment should
be worn when handling the boards. Please avoid touching the component pins or any other metallic
element.
1.3
Before Powering Up
Before powering up the board platform, we suggest to read this manual carefully in order to choose the
correct system configuration and connect the required external resources.
DIOPSIS 940HF Evaluation Board User Guide
1-1
7014A–DSP–03/09
Introduction
Most of the platform jumpers are already set in order to provide the minimal resources to bootstrap the
D940HF chip. A brief description of the default configuration will follow in the next chapters.
The AT572D940-EB requires a 5 Volt DC (5%) switching power supply (included in the package) with
the following characteristics:
!
Input: 100-240VAC 50/60Hz 0.5A (IEC 320 Plug)
!
Output: 5VDC 2.4A 12W max
These values have been obtained taking into account the maximum power consumption of the DEB. See
Table 1-1 for details:
Table 1-1. DEB Power Consumption
Board
Component
Q.ty
mA (Unit)
mA (Total)
D940HF Core
1
400
400
D940HF I/O
1
120
120
SDRAM (refresh)
2
180
360
Flash
2
30
60
Eth PHY
1
88
88
50MHz Oscillator
1
25
25
CODEC (Analog part)
2
95
190
CODEC (Digital part)
2
74
148
OP. Amplifier
6
1.5
9
CAN
2
17
34
SD Card Slot
1
70
70
USB Host Port
2
100
200
mA (Board)
DCM
1053
DBM
DEB Total
651
1704
The total power consumption of the DEB is: 1704 mA.
The power is supplied to the board via a coaxial cable with positive center pin polarity. The platform can
be switched on by simply plugging the power supply cable into the DBM female power connector J1
which has a maximum current rating of about 5A.
The user has the possibility to plug a battery (3 Volt Lithium Battery BR1225) in order to maintain time
and calendar resources permanently.
Note:
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7014A–DSP–03/09
The operating voltage of some 3 Volt Lithium Batteries can be sometimes, when used for
the first time, above the nominal voltage declared by the manufacturer, and this can cause
malfunctioning of the RTC device on the board. The problem can be solved by plugging the
battery in its board socket for about 24 hours before using the RTC device, in order to discharge the battery and reduce the operating voltage level to the nominal value.
DIOPSIS 940HF Evaluation Board User Guide
Introduction
Figure 1-1 shows the D940HF Development Board (with the DCM plugged into the DBM):
Figure 1-1.
D940HF Development Board (DEB)
DIOPSIS 940HF Evaluation Board User Guide
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Introduction
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DIOPSIS 940HF Evaluation Board User Guide
Section 2
Functional Description
The DEB is a low-cost, stand-alone, general-purpose platform that provides appropriate resources to
evaluate D940HF performance in a wide range of applications. The DEB is composed of two boards:
2.1
!
DCM: D940HF CPU Module
!
DBM: D940HF Back Module
DCM Resources
The following resources are supplied to D940HF by the DCM board:
!
Parallel Flash: 16 MByte (4Mx32)
!
SDRAM: 64 MByte (16Mx32)
!
NAND Flash: 256 MByte (256Mx8)
!
Ethernet PHY
!
Power Measurement Circuitry
!
Voltage Regulator 3.3V/1.2V
!
Configuration Jumpers and DIP SWITCH
!
Clock\PLL Circuitry
!
Module Connectors
For a detailed description of the DCM functional blocks see Section 5.2 ”DCM Blocks” on page 5-1
2.2
DBM Resources
The following resources are supplied to D940HF by the DBM board:
!
2 CODECs (total of 8 ADCs and 8 DACs)
!
2 USB Host Ports
!
1 USB Device Port
!
1 RS232 serial I/O Port
!
2 LVTTL asynchronous/synchronous serial I/O Ports
!
1 Debug Unit RS232 serial I/O Port
!
2 SPI serial I/O Ports
!
3 SSC serial I/O Ports
!
2 CAN Ports with transceivers
!
1 Secure Digital Slot
!
2 JTAG Ports (mAgic DSP® and ARM®)
DIOPSIS 940HF Evaluation Board User Guide
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Functional Description
!
1 Real Time Clock Controller with Back-Up Battery
!
1 Ethernet 10/100 Port
!
1 MIDI IN Input Port
!
Reset Logic (Push Button, Remote Reset IN)
!
Clock Circuitry for the CODECs
!
Configuration Jumpers & Status LEDs
!
Voltage Regulators: 5V/3.3V (Digital) and 5V/4.5V (Analog)
!
Module Connectors
!
Connectors for USART, SPI, USB, SSC, AUDIO, JTAG, PSU, CAN and ETH
For a detailed description of the DBM functional blocks see Section 5.3 ”DBM Blocks” on page 5-9.
2.3
DEB Block Diagram
Figure 2-1shows the platform resources:
Figure 2-1.
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7014A–DSP–03/09
D940HF Evaluation Board Block Diagram
DIOPSIS 940HF Evaluation Board User Guide
Section 3
Mechanical Description
The PCB has been constructed by using Multi-Layer technology with controlled impedance paths, buried, blind and through holes. The PCB is also composed of twelve layers (with power planes). The DEB
is equipped with SMT components on both sides (top and bottom) with a minimum of through-hole components. The DCM board is plugged into the DBM board through two 120-pin connectors (60x2) whose
references are X1 and X3.
There is only one way to plug the DCM into the DBM: the DIP-Switch (SW1) and the Atmel logo of the
DCM must be on the same side of the DBM audio jack connectors.
Four holes at each corner of both the DBM and the DCM are provided on the PCBs in order to fit the four
supports for desk placement. The holes of the two boards are aligned and mechanical supports can be
added to the boards in order to place the complete system on both sides according to the resources to
be accessed.
The layouts of the two boards and of the mechanical dimensions are shown in the next paragraphs.
3.1
Layout of the two Boards
Figure 3-1 shows the DCM Top Layout:
Figure 3-1.
DCM Top Layout
DIOPSIS 940HF Evaluation Board User Guide
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Mechanical Description
Figure 3-2 shows the DCM Bottom Layout:
Figure 3-2.
DCM Bottom Layout
Figure 3-3 shows the DBM Top Layout:
Figure 3-3.
DBM Top Layout
The main resources of the DBM are outside the area occupied by the DCM when plugged in.
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7014A–DSP–03/09
DIOPSIS 940HF Evaluation Board User Guide
Mechanical Description
Figure 3-4 shows the DBM Bottom Layout:
Figure 3-4.
3.2
DBM Bottom Layout
Mechanical Dimensions
The DCM mechanical dimensions are 70 x 80 mm. The longest side is the side with only one module
connector (X3).
DIOPSIS 940HF Evaluation Board User Guide
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Mechanical Description
Figure 3-5.
DCM Mechanical Dimensions (Transparent Top View)
The DBM mechanical dimensions are 100 x 100 mm.
Figure 3-6.
3-4
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DBM Mechanical Dimensions (Top View)
DIOPSIS 940HF Evaluation Board User Guide
Mechanical Description
3.3
DCM and DBM Component References
Electronic components are usually marked with a reference assigned by the schematic capture tool used
for designing the boards.
The reference number can help the user find the components placed on the boards.
The main schematic references of the DCM and DBM electronic components are described in the following pictures.
For more details on component references and part numbersrefer to Section 7.
Figure 3-7.
DCM Top Layer Component References
DIOPSIS 940HF Evaluation Board User Guide
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Mechanical Description
Figure 3-8.
DCM Bottom Layer Component References
Figure 3-9.
DBM Top Layer Component References
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DIOPSIS 940HF Evaluation Board User Guide
Mechanical Description
Figure 3-10. DBM Bottom Layer Component References
DIOPSIS 940HF Evaluation Board User Guide
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Mechanical Description
3-8
7014A–DSP–03/09
DIOPSIS 940HF Evaluation Board User Guide
Section 4
Hardware Configuration
The DEB provides a set of possible configurations in order to adapt its functionality to the requirements
of the relevant application.
The user can program the configurations either by hardware, jumpers, resistors or a dip-switch.
The following tables summarize all the hardware configurations, define default states and indicate the
paragraph in the current document where the corresponding function is detailed. Some photos have
been added in order to help the user locate the jumper position.
Take note that the possible setting options of a 2-pin jumper are:
!
Open (jumper not soldered)
!
Closed (jumper soldered)
The setting options of a 3-pin jumper are:
4.1
!
Pins 1-3 Closed (jumper pins 1 and 3 soldered)
!
Pins 2-3 Closed (jumper pins 2 and 3 soldered)
!
Open (no jumpers soldered, no choice taken)
DCM Hardware Configuration
The DCM jumpers and the configuration devices allow the user to select the needed resources.
The main functionalities of each configuration device are described in the following tables:
Table 4-1. DCM Configuration Jumpers
Ref.
Default
Setting
S1
2-3
S2
Closed
S3
Function
Details
PC14 Jumper
1-3: SD_WP (Secure Digital Write Protect)
2-3: RXD2 (USART2 RX Signal)
Section 5.2.10
Enables the RTCK <-> TCK Local Loop
Section 5.2.11
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
S4
Open
Disables TCK <-> RTCK local loop. If S4 is
closed S2 must be open
Section 5.2.11
S5
2-3
PC15 Jumper
1-3: SD_DET (Secure Digital Detection)
2-3: TXD2 (USART2 TX Signal)
Section 5.2.10
DIOPSIS 940HF Evaluation Board User Guide
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Hardware Configuration
Table 4-1. DCM Configuration Jumpers
4-2
7014A–DSP–03/09
Ref.
Default
Setting
Function
S6
Open
Disables BIAS use on some Voltage Regulators
Section 5.2.2
S7
2-3
PC18 Jumper
1-3: CFCD1 (Compact Flash Control)
2-3: SCLK2 (USART2 Clock Signal)
Section 5.2.10
S8
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
S9
1-3
EN Jumper
1-3: 3.3V (Voltage Regulator Enabled)
2-3: GND (Voltage Regulator Disabled)
Section 5.2.2
S10
2-3
PC16 Jumper
1-3: RDYBSY (NAND Flash Ready/Busy)
2-3: CTS2 (USART2 CTS Signal)
Section 5.2.7
Section 5.2.10
S11
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
S12
2-3
PC17 Jumper
1-3: CFIRQ1 (Compact Flash Interrupt)
2-3: RTS2 (USART2 RTS Signal)
Section 5.2.10
S13
Closed
Disables the JTAG switch between ARM and
mAgic
Section 5.2.11
S14
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
S15
2-3
PB26 Jumper
1-3: LINKSTS (ETH Link Status)
2-3: CANRX0 (CAN0 RX Signal)
Section 5.2.9
Section 5.2.10
S16
2-3
PC13 Jumper
1-3: CFCD2 (Compact Flash Control)
2-3: SCLK1 (USART1 Clock Signal)
Section 5.2.10
S17
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
S18
Open
Enables the JTAG switch between ARM and
mAgic
Section 5.2.11
PC11 Jumper
1-3: CFRST2 (Compact Flash Control)
2-3: CTS1 (USART1 CTS Signal)
Section 5.2.10
Disables the JTAG switch between ARM and
mAgic
Section 5.2.11
Details
S19
2-3
S20
Closed
S21
2-3
PC12 Jumper
1-3: CFIRQ2 (Compact Flash Control)
2-3: RTS1 (USART1 RTS Signal)
Section 5.2.10
S22
1-3
PC5CTRL Jumper
1-3: GND (Parallel Flash Write Enabled by HW)
2-3: PC5 (Parallel Flash Write Protect by SW)
Section 5.2.8
DIOPSIS 940HF Evaluation Board User Guide
Hardware Configuration
Table 4-1. DCM Configuration Jumpers
Ref.
Default
Setting
S23
1-3
JTAGSEL Jumper
1-3: GND (JTAG Boundary Scan Disabled)
2-3: 3.3V (JTAG Boundary Scan Enabled)
Section 5.2.1
S24
Open
External Connector to Main Clock Disabled
Section 5.2.5
TST Jumper
1-3: GND (Test Mode Disabled)
2-3: 3.3V (Test Mode Enabled)
Section 5.2.5
Function
Details
S25
1-3
S26
Open
External Connector or Oscillator to Main Clock
Disabled
Section 5.2.5
S27
Open
External Connector to Slow Clock Disabled
Section 5.2.5
S28
Open
External Connector or Oscillator to Slow Clock
Disabled
Section 5.2.5
S29
Open
Slow Clock Internal Source Enabled
Section 5.2.5
S30
1-3
EXT96MEN Jumper
1-3: GND (External 96MHz Clock Disabled)
2-3: 3.3V (External 96MHz Clock Enabled)
Section 5.2.5
S31
Open
12 MHz External Oscillator Enabled
-
S32
Open
32.768 KHz External Oscillator Enabled
-
S33
1-3
PORMSK Jumper
1-3: GND (Internal Power On Reset Enabled)
2-3: 3.3V (Internal Power On Reset Disabled)
Section 5.2.4
S34
Open
96 MHz External Oscillator Enabled
-
S35
Closed
SDRAM Memory Enabled
Section 5.2.6
Table 4-2. DCM Configuration Devices
Ref.
Default
Setting
R1
10 KOHm
NCP565D2TG Voltage Regulator Setting
Section 5.2.2
R2
30.1 KOHm
NCP565D2TG Voltage Regulator Setting
Section 5.2.2
C4
5.6 pF
NCP565D2TG Voltage Regulator Setting
Section 5.2.2
C5
Not Mounted
NCP565D2TG Voltage Regulator Setting
Section 5.2.2
C6
Not Mounted
NCP565D2TG Voltage Regulator Setting
Section 5.2.2
Function
Details
Table 4-3. DCM Configuration DIP Switch
Ref.
Switch
SW1
1
DIOPSIS 940HF Evaluation Board User Guide
Function
External Boot Mode
Default
OFF
Details
Section 5.2.10
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Hardware Configuration
Table 4-3. DCM Configuration DIP Switch
Ref.
Switch
Function
Default
Details
SW1
2
NAND Flash Write Protect
OFF
Section 5.2.7
SW1
3
Parallel Flash Write Protect
OFF
Section 5.2.8
SW1
4
Ethernet Clock Selector
OFF
Section 5.2.5
Figure 4-1shows the position of the DCM jumpers on the board top layer:
Figure 4-1.
DCM Jumper Position
The DCM jumpers are placed only on the board top layer.
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DIOPSIS 940HF Evaluation Board User Guide
Hardware Configuration
4.2
DBM Hardware Configuration
The main functionalities of each DBM configuration device are described in the following tables:
Table 4-4. DBM Configuration Jumpers
Ref.
Default
Setting
S1
Open
S2
1-3
S3
Open
S4
1-3
S5
Closed
S6
1-3
S7
Open
S8
2-3
S9
S10
Function
Details
Disables BIAS use on some Voltage Regulators
(U1)
Section 5.3.1
EN U1 Jumper
1-3: 5V (Voltage Regulator Enabled)
2-3: GND (Voltage Regulator Disabled)
Section 5.3.1
Disables BIAS use on some Voltage Regulators
(U3)
Section 5.3.1
EN U3 Jumper
1-3: 5V (Voltage Regulator Enabled)
2-3: GND (Voltage Regulator Disabled)
Section 5.3.1
Enables SPI0 Control on U5 Codec
Section 5.3.4
MCLKI Jumper
1-3: OSC OUT (Y1 Oscillator Output)
2-3: TF1 (D940 Clock Source for CODECs)
Section 5.3.3
Enables Y1 Oscillator
Section 5.3.3
VDRIVE Jumper
1-3: VDRIVES (Output Voltage Disabled)
2-3: GND (Output Voltage Enabled)
Section 5.3.1
Closed
Enables SPI0 Control on U6 Codec
Section 5.3.4
2-3
VSUPPLY Jumper
1-3: 5V (Supply Voltage Disabled)
2-3: GND (Supply Voltage Enabled)
Section 5.3.1
S11
2-3
VSENSE Jumper
1-3: 3.3V (Voltage Sense Disabled)
2-3: GND (Voltage Sense Enabled)
Section 5.3.1
S12
Open
Disables ARM JTAG NTRST
Section 5.3.5
S13
Open
Disables mAgic JTAG NTRST
Section 5.3.5
S14
Closed
Enables ARM JTAG RTCK
Section 5.3.5
S15
Closed
Enables ARM JTAG NSRST
Section 5.3.2
Section 5.3.5
S16
Open
Disables RTCK <-> TCK ARM JTAG Local Loop
Section 5.3.5
S17
Closed
CAN0 Termination Resistor Enabled
Section 5.3.6
S18
Closed
CAN0 Transceiver Output Enabled
Section 5.3.6
S19
Closed
CAN1 Termination Resistor Enabled
Section 5.3.6
S20
Closed
CAN1 Transceiver Output Enabled
Section 5.3.6
DIOPSIS 940HF Evaluation Board User Guide
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Hardware Configuration
Table 4-4. DBM Configuration Jumpers
Ref.
Default
Setting
S21
Closed
D940HF SPI0 Control Enabled
Section 5.3.8
S22
Closed
1 Hz Real Time Clock Enabled
Section 5.3.8
S23
Closed
VBUS Voltage from Power Jack Enabled
Section 5.3.1
S24
1-3
Opto Power Supply Jumper
1-3: 5V (Opto Power Supply)
2-3: 3.3V (Opto Power Supply Alternative)
Section 5.3.1
Section 5.3.9
S25
Open
RXD1 Jumper
1-3: Opto Output Enabled
2-3: HRDX1 (Header Output Enabled)
Section 5.3.9
S26
Open
Enables mAgic JTAG NSRST
Section 5.3.5
Function
Details
Table 4-5. DBM Configuration Devices
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Ref.
Default
Setting
Function
R4
51 KOHm
RF Resistor: 80.6 KOHm value to generate 3.3V
Section 5.3.1
R5
30.1 KOHm
Partition Resistor: (30.1 KOHm) value working
with R4
Section 5.3.1
R8
80.6 KOHm
RF Resistor: 80.6 KOHm value to generate 4.5V,
51 KOHm to generate 3.3V
Section 5.3.1
R9
30.1 KOHm
Partition Resistor (30.1 KOHm value) working
with R8
Section 5.3.1
R169
Mounted
Connect UART Chassis Ground to GND
Section 5.3.9
R180
Mounted
Connect USB Chassis Ground to GND
Section 5.3.10
C8
Not Mounted
Capacitor Mounted only for U1 VREGs filtering
Section 5.3.1
C9
Not Mounted
Capacitor Mounted only for U1 VREGs with Bias
Control
Section 5.3.1
C10
Not Mounted
Capacitor Mounted only for U1 VREGs with Soft
Start Control
Section 5.3.1
C14
Not Mounted
Capacitor Mounted only for U2 VREGs filtering
Section 5.3.1
C18
Not Mounted
Capacitor Mounted only for U2 VREGs with Bias
Control
Section 5.3.1
C20
Not Mounted
Capacitor Mounted only for U2 VREGs with Soft
Start Control
Section 5.3.1
FB1
Not Mounted
3.3V Power Supply for CODEC OP AMPs (with
S8, S10, S11 1-3 connected)
Section 5.3.1
FB2
Mounted
4.5V Power Supply for CODEC OP AMPs (with
S8, S10, S11 2-3 connected
Section 5.3.1
Details
DIOPSIS 940HF Evaluation Board User Guide
Hardware Configuration
Figure 4-2 shows the position of the DBM jumpers on the board top layer:
Figure 4-2.
DBM Top Layer Jumper Position
Figure 4-3 shows the position of the DBM jumpers on the board bottom layer:
Figure 4-3.
DBM Bottom Layer Jumper Position
DIOPSIS 940HF Evaluation Board User Guide
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Hardware Configuration
4-8
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DIOPSIS 940HF Evaluation Board User Guide
Section 5
Functional Blocks
5.1
Description
This section contains the description of each functional block of both the DCM and the DBM boards.
5.2
DCM Blocks
The DCM blocks are listed below:
5.2.1
!
D940HF
!
Power Supply Logic
!
D940HF Vdd Core Power Measurement Block
!
Reset Logic
!
Clock Logic
!
SDRAM Memories
!
NAND Flash Memory
!
Parallel Flash Memories
!
Ethernet PHY
!
PIO Selectors
!
ICE Interface Switch
!
Module Connectors
D940HF
The D940HF is a Dual Core System integrating an ARM926EJ-S™ ARM® Thumb® Processor Core and a
VLIW mAgic DSP™ optimized for audio, communication and beam-forming applications. The VLIW
mAgic DSP performs 1 GFlops - 1.6 GOps at 100 MHz. With its 1.7 MBits of On-chip SRAM, 32-bit integer and IEEE® 40-bit extended precision floating point numeric format, single cycle FFT butterfly, code
compression, SW pipelining, DMA engine and AHB master and slave ports, the DSP provides a very
powerful support to ARM and its rich set of peripherals. From now on, we refer to ARMSYSTEM as the
complete set of ARM core memories and its peripherals.
The D940HF can operate in two different modes: standard operational mode and test mode. Test mode
is only enabled for test purposes and it must not be enabled on the DCM board. The standard operational mode is selected by default with the S23 (JTAGSEL) and S25 (TST) jumper pins 1-3 closed.
5.2.2
Power Supply Logic
The DCM works with 3.3 Volt and 1.2 Volt power supplies. The 3.3 Volt power is supplied to the DCM by
the DBM through the Module Connectors. The DCM receives two separate 3.3 Volt power supplies for
DIOPSIS 940HF Evaluation Board User Guide
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Functional Blocks
the Ethernet PHY, that is already filtered on the DBM, and all the other devices. The other voltages, 2.5
Volt as the reference voltage level for the power measurement block and 1.2 Volt for the D940HF core,
are generated on board. The 1.2 Volt voltage is generated by the Power Supply Block that can host different types of voltage regulators (with or without Bias, with soft start reset capability or not, etc.). The
component reference is U1. The board now hosts the NCP565D2TG voltage regulator from ON-Semi.
This device works properly by setting the following configuration:
Table 5-1. Device Configuration with NCP565D2TG
Ref
Status or Value
R1
10 KOHm (partition resistor on the feed-back path)
R2
30.1 KOHm (partition resistor)
C4
5.6 pF (filter)
C5
Not Mounted (Bias not used, disabled)
C6
Not Mounted (Soft Start not used, disabled)
S6
Open (2-pin jumper, Bias not used, disabled)
S9
Pins 1-3 Closed (3-pin jumper, NCP565D2TG enabled)
This configuration generates 1.2 Volt voltage level.
5.2.3
Power Measurement
The D940HF core power consumption can be measured and monitored by the Power Measurement
Block. This block, powered by an on board filtered 3.3 Volt power supply, is composed of a 0.25 Ohm
(1% precision) resistor (R25), a precision current sense amplifier with voltage output (U2), a pseudo differential 12-bit A/D converter (reference U3) controlled by the D940HF with the 2.5 Volt reference
voltage provided by an external precision LDO Voltage Reference (U5). The results of the measurements are received by the SPI1 Port (Chip Select 3).
The 2.5 Volt voltage level comes from a precision, micropower LDO Voltage Reference Generator (U5)
and it is needed by the Power Measurement Block.
Some reference values that can help the user translate the numbers coming from the A/D converter to
voltage and current values are reported in the table below:
Table 5-2. A/D converter numbers to voltage and current values
5.2.4
Current
Values on
R25 (mA)
Voltage
Values on R25
(mV)
Value after
Amplifier (x20)
(V)
A/D Converter
Output Values
100
25
0.5
800
200
50
1
1600
400
100
2
3200
Reset Logic
The D940HF incorporates a power on reset cell that generates the reset signal for all the internal and
external devices through the NRST pin J17.
Another internal source for the reset is the Watch Dog that is enabled at power up. The internal boot
ROM code disables it.
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DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
The DCM can also receive an active low pulse on the same NRST line from the DBM reset logic block
through the module connectors generated by a push-button device or by the NSRST pin of the ARM
Hardware JTAG if enabled on the DBM board.
The power on the reset cell of the D940HF is enabled by the external 3-pin jumper S33 (1-3 closed).
The DCM devices that receive the reset signal are the Parallel Flash memories (U11 and U12) and the
Ethernet PHY (U13).
5.2.5
Clock Logic
The 32.768 KHz quartz (Y2) provides the source for the D940HF embedded oscillator for the internal
slow clock that is enabled by the 2-pin jumpers S28 and S29 when open.
The 12 MHz quartz (Y1) provides the source for the D940HF embedded oscillator for the main clock
when the 2-pin jumper S26 is open.
The 3-pin jumper S30 (1-3 closed) disables the internal by-pass clock circuitry.
Table 5-3. D940HF Default Source Clock Configuration
Ref
Status or Value
Y1
32.768 KHz Quartz Mounted
Y2
12 MHz Quartz Mounted
S26
Open (2-pin jumper)
S28
Open (2-pin jumper)
S29
Open (2-pin jumper)
S30
Pins 1-3 Closed (3-pin jumper)
The J1 clock connector can be used as an alternative source clock either to provide the clock to the slow
clock input pin V2 (Y2 quartz must be not mounted and the 2-pin jumpers S28 and S27 closed, S24 and
S26 open) or to provide the clock to the main clock input pin U5 (Y1 quartz must be not mounted and the
2-pin jumpers S24 and S26 closed, S27 and S28 open).
The test points TP1 and TP2 can be used to monitor mAgic internal clock and ARM core internal clock
respectively.
The 3-pin S25 jumper (1-3 closed) enables the normal functional mode of the internal clock circuitry.
The Ethernet PHY device (U13) can receive the working clock either by the 50 MHz oscillator (Y6) that is
enabled by the DIP-Switch SW1-4 pin when OFF (default) or by the T15 pin of the D940HF (SW1-4 in
ON position).
Table 5-4. Ethernet PHY Source Clock Configuration
SW1-4 Status
Clock Source
ON
D940HF Pin T15
OFF
Y6 Oscillator (50MHz)
Clock sources coming from the embedded peripherals of the D940HF through the PIO lines and going to
the external peripheral devices are serially terminated with 33 Ohm resistors.
The terminated PIO lines are: PA2, PA11, PB3, PB5, PB9, PB11, PB15, PB17, PB21, PB23, PC2, PC8,
PC13, PC18, PC21 and PC22.
DIOPSIS 940HF Evaluation Board User Guide
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Functional Blocks
5.2.6
SDRAM
The SDRAM Block is composed of two SDRAM chips with 16-bit bus size for a total of 32-bit bus size.
The U8 device is connected to the lower 16 bits of the external data bus while U9 is connected to the
higher 16-bit of the same bus.
The external data bus is shared among all the external memories (SDRAM, Parallel Flash and NAND
Flash) and the module connectors.
The DCM can host SDRAM memory chips up to 512 MBit density (size 32Mx16) for a total of 128 MByte
(two chips of 64 MByte each). The memory clock and the control signals come directly from the D940HF.
The SDRAM block can be disabled by hardware by opening the S35 jumper. The Chip Select signal is
controlled by the CS1 address space signal.
5.2.7
NAND Flash
The NAND Flash block is composed of only one chip that shares the least significant 8 bits of the external data bus. The DCM can host memory chips up to 4 GBit density (512Mx8). Write access operations
can be protected only by hardware. The DIP Switch SW1-2 pin enables the write operations when OFF
(default), as shown in the table below:.
Table 5-5. NAND Flash Write Protect
SW1-2 Status
Status
ON
Write Protect Enabled
OFF
Write Protect Disabled
The RDYBSY signal (pin 7 of the NAND Flash) sends the Ready/NotBusy information about the state of
the NAND Flash to the D940HF when the 3-pin jumper S10 is 1-3 closed. The Chip Enable pin of the
chip is controlled by the PA15 signal (D940HF pin V16).
5.2.8
Parallel Flash
The Parallel Flash Block is composed of two chips with a 16-bit bus size for a total 32-bit bus size. The
U11 device is connected to the lower 16 bits of the external data bus while the U12 is connected to the
higher 16 bits of the same bus.
The DCM can host Parallel Flash chips up to 64 MBit density (size 4Mx16) for total 16 MByte (two 8
MByte each chips).
Write Protection of the code can be performed in two ways: by hardware with the DIP Switch SW1-3 pin
in ON position (the chips are write protected) or by software with the SW1-3 pin OFF (chips are writable,
default position) and the 3-pin jumper S22 with 2-3 closed (the NWR0 write signal is masked by the PC5
signal, the pin G12 of the D940HF) as shown in the table below:
Table 5-6. Parallel Flash Write Protect
SW1-3 Status
S22 Status
Status
ON
-
OFF
Pins 1-3 Closed
Write Signal Unmasked by HW
OFF
Pins 2-3 Closed
Write Signal Mask controlled by SW
Write Protect Enabled by HW
The Chip Select signal is controlled by the CS0 address space signal.
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DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
5.2.9
Ethernet PHY
The DCM hosts the Ethernet PHY DM9161 (U13) from Davicom that provides a Media Independent
Interface (MII) as defined in the IEEE 802.3u specifications. In particular the U13 component has been
configured in order to implement the Reduced Media Independent Interface (RMII) supported by the
D940HF Ethernet interface.
When in RMII mode the PHY receives the clock from the external source (either from Y6 oscillator,
default, or from D940HF) through pin 42 of U13.
An output interrupt line from the PHY (pin 32 of U13) is connected to PB25 (pin H15 of U6) internally
redirected to the Interrupt Controller (AIC) line EXTIRQ0.
The LINKSTS signal (pin 14 of U13) reflects the status of the network connection. The information can
be read by D940HF on the PB26 (pin B12 of U6) when the 3-pin jumper S15 is with pin 1-3 closed (see
Section 5.2.10 ”PIO Selectors” on page 5-5).
The status of the network connection can also be checked by the user by watching the three LEDs
located on the DBM and driven by the output signals of U13 LINK_ACT, SPEED and FDX_COL going
through the module connectors.
5.2.10
PIO Selectors
D940HF provides three groups of 32-bit PIO (Parallel Input/Output) lines: PA[31:0], PB[31:0] and
PC[31:0]. Each line can be dedicated to general purpose I/O or to the multiplexed signals from the
embedded peripherals according to the PIO internal register configuration.
The PIO Selector Block allows the user to connect the same PIO line to more than one external device at
a time depending on the implemented functionalities. In particular, the embedded peripheral and external device signals supported by the jumper block are: Compact Flash, Secure Digital, USART1,
USART2, CAN0, NAND Flash, Ethernet PHY.
The jumpers set an alternative between:
!
CAN0 and Ethernet Link Status
!
Secure Digital, Compact Flash, NAND Flash on one hand and USART2 on the other hand
!
Compact Flash and USART1
The possible choices are described in the following table (take note that only two pins can be closed at
the same time, for instance if pins 1-3 are closed, pins 2-3 will be open and viceversa):
Table 5-7. PIO Jumper Block Settings
Ref
Pins 1-3 Closed
Pins 2-3 Closed
PIO Line
S15
LINKSTS (Ethernet)
CANRX0 (CAN0)
PB26
S1
SD_WP (Secure Digital)
RXD2 (USART2)
PC14
S5
SD_DET (Secure Digital)
TXD2 (USART2)
PC15
S7
CFCD1 (Compact Flash Control)
SCLK2 (USART2)
PC18
S12
CFIRQ1 (Compact Flash Control)
RTS2 (USART2)
PC17
S10
RDYBSY (NAND Flash)
CTS2 (USART2)
PC16
S16
CFCD2 (Compact Flash Control)
SCLK1 (USART1)
PC13
S19
CFRST2 (Compact Flash Control)
CTS1 (USART1)
PC11
S21
CFIRQ2 (Compact Flash Control)
RTS1 (USART1)
PC12
DIOPSIS 940HF Evaluation Board User Guide
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Functional Blocks
The PIO Selector Block allows the user to choose the boot mode of the D940HF:
!
Boot from internal ROM
!
Boot from external memory device
The selection is possible by acting on the PA24 line (Pin H16 of U6) connected to the DIP Switch SW1-1
(position 1) as described in the table below:
Table 5-8. Boot Mode Selector
Ref
OFF
ON
PIO Line
SW1-1
Boot from internal ROM
Boot from external memory
PA24
The default position is OFF (boot from internal ROM).
5.2.11
ICE Interface Switch
The ICE Interface Switch Block allows the user to connect the hardware JTAG devices to the mAgic and
ARM JTAG ports both with two separate HW JTAGs or using only one HW JTAG with the two ICE ports chained.
There are three possible configurations:
!
Independent JTAG ports (mAgic and ARM ports not chained, default configuration)
!
mAgic to ARM chain (HW JTAG plugged into mAgic JTAG connector on the DBM)
!
ARM to mAgic chain (HW JTAG plugged into ARM JTAG connector on the DBM)
The configuration of the jumpers is described in the following tables:
Table 5-9. Independent JTAG Ports (default)
Ref
Pins 1-2
S3
Open
S8
Open
S11
Open
S14
Open
S17
Open
S18
Open
S13
Closed
S20
Closed
Table 5-10. mAgic to ARM JTAG Port Chain
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7014A–DSP–03/09
Ref
Pins 1-2
S3
Closed
S8
Closed
S11
Open
S14
Closed
S17
Closed
DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
Table 5-10. mAgic to ARM JTAG Port Chain
Ref
Pins 1-2
S18
Closed
S13
Closed
S20
Open
Table 5-11. ARM to mAgic JTAG Port Chain
Ref
Pins 1-2
S3
Closed
S8
Closed
S11
Closed
S14
Closed
S17
Closed
S18
Open
S13
Open
S20
Closed
It is also possible to enable the ARM TCK<->RTCK local loop by setting the S2 and S4 jumpers as
described in the following table:
Table 5-12. ARM TCK<->RTCK Local Loop
Local Loop State
S2
S4
Enabled
Open
Closed
Disabled
Closed
Open
By default the local loop is not enabled.
5.2.12
Module Connectors
The DCM is plugged into the DBM by using the module connectors.
The connectors are used to provide the power supply to the DCM and to exchange signals between
D940HF and the peripheral support devices mounted on the DBM.
The DCM module male connectors are X1, X2 and X3, but only the corresponding X1 and X3 female
connectors are mounted on the DBM.
The X2 connector is an extension to be used with other motherboards:
DIOPSIS 940HF Evaluation Board User Guide
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Functional Blocks
Figure 5-1.
P in
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
X1, X2 and X3 Connector Pinouts
X 1 C o nne c t o r
S igna l
P in
NC
2
NC
4
NC
6
NC
8
NC
10
NRST
12
X1_RTCK
14
TDI
16
TCK
18
GND
20
PA8
22
P A 11R
24
PA9
26
PA7
28
GND
30
P C10
32
SCLK1
34
CTS1
36
P C9
38
GND
40
P C31
42
SCLK2
44
CTS2
46
RXD2
48
GND
50
PA5
52
PB7
54
P C19
56
P A 10
58
GND
60
PA1
62
P A 2R
64
PA4
66
PA6
68
GND
70
PB1
72
P B 3R
74
PB2
76
P C8R
78
GND
80
HDP A
82
HDM A
84
HDP B
86
HDM B
88
GND
90
P C23
92
P C22R
94
P C25
96
NC
98
GND
100
NC
102
NC
104
NC
106
P B 30
108
NC
110
P B 27
112
CA NRX0
114
A GND_ETH
116
RXIp
118
RXIm
120
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7014A–DSP–03/09
S igna l
NC
NC
NC
NC
NC
NRST
TM S
X1_TDO
NTRST
NC
NC
NRST
P A 10
PA8
3V3
NC
NRST
RTS1
P C10
3V3
P C30
NC
RTS2
TXD2
3V3
P B 24
P A 26
PA6
PB1
3V3
PA0
PA3
PA5
P B 25
3V3
PB0
P B 5R
PB4
P C7
NC
NC
NC
DDP
DDM
SD_WP
P C24
P C27
P C26
SD_DET
3V3
NC
NC
NC
SP EED
NC
FDX_COL
LINK_A CT
A VDD_ETH
TXOp
TXOm
P in
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
S igna l
NC
NC
NC
NC
GND
NC
NC
NC
NC
GND
NC
NC
NC
NC
GND
NC
NC
NC
NC
GND
A0
A2
A4
A6
A8
A9
A 11
A 13
A 15
GND
A 17
A 19
A 21
P A 25
GND
D0
D2
D4
D6
GND
D8
D10
D12
D14
GND
NC
NC
P A 26
NCS2
GND
P A 30
NC
NWR1
NWR0
GND
P A 11
CFRST2
NC
NC
GND
X 2 C o nne c t o r
P in
S igna l
2
NC
4
NC
6
NC
8
NC
10
3V3
12
NC
14
NC
16
NC
18
NC
20
3V3
22
NC
24
NC
26
NC
28
NC
30
3V3
32
NC
34
NC
36
NC
38
NC
40
3V3
42
A1
44
A3
46
A5
48
A7
50
3V3
52
A 10
54
A 12
56
A 14
58
A 16
60
3V3
62
A 18
64
A 20
66
P B 28
68
NWR1
70
3V3
72
D1
74
D3
76
D5
78
D7
80
3V3
82
D9
84
D11
86
D13
88
D15
90
3V3
92
NWR0
94
CFOE_NOE_NRD
96
P A 27
98
SM CS_NCS3
100
3V3
102
CFOE_NOE_NRD
104
P A 31
106
NWR3
108
CFIRQ1
110
3V3
112
CFCD1
114
CFCD2
116
CFIRQ2
118
P B 31
120
NC
P in
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
X 3 C o nne c t o r
S igna l
P in
S igna l
NC
2
NC
NC
4
NC
NC
6
NC
NC
8
NC
NC
10
NC
P C29
12
NC
P C28
14
NC
NC
16
NC
NC
18
NC
GND
20
3V3
NC
22
NC
NC
24
NC
NC
26
NC
NC
28
NC
GND
30
3V3
NC
32
NC
NC
34
NC
NC
36
NC
NC
38
NC
GND
40
3V3
P C1
42
P C0
P C2R
44
P C3
P C4
46
P C5
P C6
48
P A 12
GND
50
3V3
PB7
52
PB6
P B 9R
54
P B 11R
PB8
56
P B 10
P C21R
58
P C20
GND
60
3V3
P B 13
62
P B 12
P B 15R
64
P B 17R
P B 14
66
P B 16
P C8R
68
P C7
GND
70
3V3
P B 19
72
P B 18
P B 21R
74
P B 23R
P B 20
76
P B 22
P C21R
78
P C20
GND
80
3V3
D16
82
D17
D18
84
D19
D20
86
D21
D22
88
D23
GND
90
3V3
D24
92
D25
D26
94
D27
D28
96
D29
D30
98
D31
GND
100
3V3
A1
102
NWR3
NC
104
M TM S
M TDI
106
X1_M TDO
M TCK
108
M NTRST
GND
110
3V3
NC
112
NC
NC
114
NC
NC
116
NC
NC
118
NC
GND
120
3V3
DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
5.3
DBM Blocks
The DBM blocks are listed below:
5.3.1
!
Power Supply Logic
!
Reset Logic
!
Clock Circuitry for CODECs
!
Audio Interface
!
JTAG ICE Interfaces
!
CAN Interface
!
Secure Digital
!
Real Time Clock
!
DBGU, USART Interfaces and MIDI-IN
!
USB Host and Device
!
Ethernet Interface
!
External Interrupt
!
Header Connectors
!
Module Connectors
Power Supply Logic
Power is supplied to the DBM by an external 5 Volt PSU connected via a standard coaxial cable to the J1
two-pole connector (with nominal current 5A) on the PCB.
The table below defines the PSU connector pin assignment:
Table 5-13. PSU Connector (J1) Pin Assignment
Pin
Name
Function
1
5V
External PSU Positive Pole (5V)
2
Shield
Not Connected
3
GND
Ground
The required polarity is shown in the figure below:
Figure 5-2.
Female Coaxial Power Connector Polarity
Two on-board voltage regulators, located in the bottom part of the DBM board, provide the needed internal supplies starting from the 5V external PSU: 3.3 Volt (U1) and 4.5/3.3 Volt (U3). 5 Volt power can be
used directly by the USB Host connector through the S23 jumper (when closed) and by the optoisolator
component U17 via the 3-pin jumper S24 (U17 power is 5 Volt when pins 1-3 are closed otherwise the
power is 3.3 Volt when pins 2-3 are closed).
!
U1 VREG provides 3.3 Volt power supply to the DCM, the filtered Ethernet power (by the L1 ferrite),
the CODECs digital VDD, and the DBM devices and ports such as JTAG, CAN transceiver, Real Time
DIOPSIS 940HF Evaluation Board User Guide
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Functional Blocks
Clock, Secure Digital, RS-232, opto-isolator and the user’s header connectors (USART, Timer, CAN,
SPI, SSC and TWI)
!
U3 VREG can be configured to supply either 4.5 Volt or 3.3 Volt power supply to the audio analog
operational amplifiers
A yellow LED (DS3) is connected to the 3.3 Volt power supply to show when the power is on.
The 3.3/4.5 Volt voltage power supplies are generated by a power supply block that can host different
types of voltage regulators (with or without Bias, with soft start reset capability or not, etc.). The board
now hosts two TPS75801 voltage regulators from Texas Instruments. U1 generates 3.3 Volt with the following settings:
Table 5-14. U1 VREG Configuration (TPS75801)
Ref
Status or Value
R4
51 KOHm (on feed-back path)
R5
30.1 KOHm (partition resistor)
C8
Not Mounted (filter not required with this model)
C9
Not Mounted (Bias not used, disabled)
C10
Not Mounted (Soft Start not used, disabled)
S1
Open (2-pin jumper, Bias not used, disabled)
S2
Pins 1-3 Closed (3-pin jumper, TPS75801 enabled)
U3 can generate 3.3 Volt by using U1 same settings and also with the FB1 ferrite mounted and FB2 not
mounted. The 3-pin jumpers S8, S10 and S11 must be with pins 1-3 closed (3.3 Volt power generation of
CODEC U5 disabled).
In order to generate 4.5 Volt the following settings are required for U3:
Table 5-15. U3 VREG Configuration (TPS75801)
Ref
Status or Value
R8
80.6 KOHm (on feed-back path)
R9
30.1 KOHm (partition resistor)
C14
Not Mounted (filter not required with this model)
C18
Not Mounted (Bias not used, disabled)
C20
Not Mounted (Soft Start not used, disabled)
S3
Open (2-pin jumper, Bias not used, disabled)
S4
Pins 1-3 Closed (3-pin jumper, TPS75801 enabled)
S8, S10, S11
Pins 2-3 Closed (3-pin jumpers, 3.3 Volt power for CODECs
generated by U5)
FB1
Not Mounted (Operational Amplifiers voltage is 4.5 Volt)
FB2
Mounted (Operational Amplifiers voltage is 4.5 Volt and 3.3
Volt for CODECs generated by U5)
In this case the 3.3 volt power for the digital VDD of both CODECs is internally generated by the U5 component with the external help of the U4 component (PNP high current transistor).
Another ferrite (L3) is used to filter the power for the audio operational amplifiers.
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DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
5.3.2
Reset Logic
The DBM can receive an active low pulse on the open-drain NRESET line from the DCM D940HF
through the module connectors. On the other hand the SW1 push-button device on the DBM can force
an active low level on the same line.
A 2-pin remote reset connector (J4) is available to send/receive the reset signal to/from a remote system
as well.
An active low pulse can also be forced by the NSRST pin of the ARM Hardware JTAG if enabled by closing the 2-pin S15 jumper (default configuration).
The NRESET signal acts on the following DBM devices: U5 and U6 CODECs, J4 connector, J22 and
J26 header connectors (USART1 and USART2).
5.3.3
Clock Circuitry for CODECs
The U5 and U6 CODECs can receive the source clock signal both from the D940HF PB8 PIO line
through the X3 connector or from the on board Y1 device (12.288 MHz oscillator). The selection can be
done by setting the 3-pin S6 and 2-pin S7 jumpers as follows:
Table 5-16. CODEC Clock Source Selection
Clock Source
5.3.4
S6
S7
On board oscillator Y1
1-3 closed
open
DCM through X3
2-3 closed
closed
Audio Interface
The DBM Audio Interface Block provides eight audio channels (four stereo inputs and four stereo outputs) connected to eight audio jack connectors. Each channel works with a 24-bit word, I2S format, with
sampling rate up to 192 KHz. D940HF can connect to analog I/O signals through two AD1939 CODECs
located in the bottom part of the DBM board.
The AD1939 is a single-chip CODEC that provides four analog-to-digital converters with differential input
and eight digital-to-analog converters with differential output. An SPI port is included in order to configure
the CODECs.
The two CODECs are connected to the SSC0 Port in a daisy-chain mode in which the U6 is the first
component and U5 is the second component of the chain.
The SPI0 Port is used to control and configure the two CODECs (SPI NPCS01 control signal is connected to U5 and SPI0 NPCS02 control signal is connected to U6), but the control must be enabled by
hardware by closing the 2-pin jumpers S5 and S9 (default configuration). These jumpers can be disabled
when the user needs to use the SPI0 Port with the J24 header connector.
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Functional Blocks
Figure 5-3.
D940HF Connections to AD1939 CODECs with SSC0 and SPI0
The U5 AD1939 outputs to audio jack connectors are low-pass filtered with an anti-image filter and converted from a differential voltage to a single-ended voltage by AD8608 quad op-amps. The quad opamps in U7 act on signals coming from the first two outputs (OUT1 and OUT2), while the ones in U8 on
the last two (3 and 4). The U5 CODEC outputs OUT1, OUT2, OUT3 and OUT4 (each one is a stereo
line) are connected to the corresponding audio jacks J5, J6, J7 and J8.
The table below summarizes the DAC paths:
Table 5-17. DAC Output Line Paths
Codec
Stereo Outputs
Codec
Reference
Quad Op-Amp
Reference
Stereo
Output Line
Output Jack
OL1, OR1
U5
U7
OUT1
J5
OL2, OR2
U5
U7
OUT2
J6
OL3, OR3
U5
U8
OUT3
J7
OL4, OR4
U5
U8
OUT4
J8
Component U5 is used for both DAC and ADC conversions.
Component U6 is only used for ADC conversion.
The four input channels IN1, IN2, IN3 and IN4 coming from audio jack connectors J9, J10, J11 and J12
are filtered and converted from a single-ended voltage to a differential voltage by the AD8608 quad opamp logic block. In particular, the stereo line coming from the audio connectors are redirected as
described in the table below:
Table 5-18. ADC Input Line Paths
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Input Jack
Stereo
Input Lines
Quad Op-Amp
Reference
Codec
Reference
Codec Stereo
Input
J9
IN1
U9
U5
ADC1L, ADC1R
J10
IN2
U10
U5
ADC2L, ADC2R
J11
IN3
U11
U6
ADC3L, ADC3R
J12
IN4
U12
U6
ADC4L, ADC4R
DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
A sketch of the CODECs connections with the I/O Stereo Lines are described in the figure below:
Figure 5-4.
CODECs Connections with I/O Stereo Lines
Standard stereo 3.5 mm male jack connectors must be plugged into the IN/OUT receptacles of the DBM:
Figure 5-5.
Standard Stereo 3.5 mm Jack
The U5 and U6 CODECs are connected to allow a daisy-chain configuration to expand the system to the
requested four stereo ADC lines.
The ADC port can be configured to work in Time Division Multiplexed (TDM) Mode.
At the end the working configuration is an ADC TDM Daisy-Chain Mode with 8 Channels I2S data format
and the bit-clock frequency 256 fs (sampling frequency).
The first slots of the ADC TDM data stream belong to the second AD1939 (U5) in the chain and the last
slots belong to the first one (U6).
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Functional Blocks
The only DAC output ports used are the ones of the second AD1939 (U5) that is connected to the
D940HF TDM port (SSC0) directly.
The working configuration for the DAC ports is a DAC TDM (no Daisy-Chain) Mode with 8 Channels I2S
data format and the bit-clock frequency 256 fs.
The figure below sums up the TDM Chain Modes implemented:
Figure 5-6.
5.3.5
ADC/DAC TDM Daisy-Chain Modes
JTAG ICE Interface
The JTAG-ICE Interface Block allows the user to connect the hardware JTAG devices to the mAgic and
ARM JTAG ports. The ARM JTAG connector is J13 while the mAgic DSP JTAG connector is J14 (both of
them are located on the top side of the board). J13 and J14 pin numbering are shown in the table below:
Table 5-19. JTAG-ICE Connector Pin Numbering
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
Pin 1 is at the bottom left-hand corner as indicated on the PCB.
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The JTAG-ICE connector is compatible with all 20-pin hardware JTAG devices. The table below defines
the JTAG-ICE connector pin assignment:
Table 5-20. JTAG-ICE Connector (J13 and J14) Pin Assignment
Pin
Name
Function
1
VCC
Target Reference Voltage
2
VCC
3.3 V Power Supply
3
NTRST
5
TDI
Test Data In signal from HW JTAG to the target JTAG port
7
TMS
Test Mode Select signal from HW JTAG to the target JTAG port
9
TCK
Test Clock signal from HW JTAG to the target JTAG port
11
RTCK
13
TDO
15
NSRST
17
NC
-
19
NC
-
4, 6, 8, 10, 11, 12,
14, 16, 18, 20
GND
Target JTAG port Reset from HW JTAG Probe to the target ICE logic
Return Test Clock signal from the target JTAG port for adaptive clocking
(not implemented in J14)
Test Data Out from the target JTAG port to HW JTAG
Open collector output from HW JTAG probe to the target system reset
(not implemented in J14)
Connection to Ground
NTRST (pin 3 of both connectors) can be left unconnected if the HW JTAG device does not use this signal. S12 is the 2-pin jumper for the J13 connector used in order to leave the ICE_ANTRST signal
unconnected (S12 open, default configuration) on the DBM, because D940HF internal logic provides
directly the reset to the TAP controller.
The S13 2-pin jumper connected to pin 3 of J14 with ICE_MNTRST signal is left open by default.
The open collector ICE_ANSRST signal from pin 15 of J13 is connected by default to the NRESET line
of the DBM board through the 2-pin jumper S15 (closed), while the open collector MNSRST signal from
pin 15 of J14 is not connected to the NRESET line by default (S26 open).
It is also possible to enable (disabled by the default configuration) the ARM TCK<->RTCK local loop by
setting S14 and S16 jumpers as described in the table below (the corresponding settings must be used
on the DCM):
Table 5-21. ARM TCK<->RTCK Local Loop
5.3.6
Local Loop State
S14
S16
Enabled
Open
Closed
Disabled
Closed
Open
CAN Interface
The CAN Interface Block allows the user to connect directly CAN0 and CAN1 Ports through the two CAN
transceivers U13 (CAN0) and U14 (CAN1) to either a terminated CAN Bus or a non-terminated one.
CAN0 and CAN1 signals are available on the J27 header connector without going through the
transceiver.
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Functional Blocks
The on board CAN Bus terminations can be enabled by closing the 2-pin jumper S17 for CAN0 Port and
the 2-pin jumper S19 for CAN1 Port (both of them are disabled by default).
Both CAN transceiver devices can be by-passed by opening the 2-pin jumpers S18 (CAN0) and S20
(CAN1). The table below summarizes all the possible options:
Table 5-22. CAN0 and CAN1 Port Termination and Transceiver Control
5.3.7
Ref
Pins 1-2
Function
S17, S19
Closed
CAN Bus termination enabled by hardware (the ports can be
attached to an external non-terminated bus)
S17, S19
Open
CAN Bus termination disabled by hardware (the ports can be
attached to an external already terminated bus)
S18, S20
Closed
On board CAN0 and CAN1 transceivers enabled
S18, S20
Open
On board CAN0 and CAN1 transceivers disabled
Secure Digital
The Secure Digital Block provides the user with a card connector slot, with a card detection and write
protect signals available. The card connector reference is J15. The J15 pinout is shown in the table
below:
Table 5-23. Secure Digital Card Slot Pinout
5.3.8
Signal
Pin
MCDA3
1
MCCDA
2
GND
3
3.3 Volt
4
MCCK
5
GND
6
MCDA0
7
MCDA1
8
MCDA2
9
SDDET
10
SDWP
11
GND
12
Real Time Clock
The Real Time Clock (RTC) Block provides a serial alarm real-time clock (RTC) (DS1306, reference
U15) with a battery connector (J16).
The RTC provides a full binary coded decimal (BCD) clock calendar that is accessed by the SPI0 Port
using NPCS03 signal.
The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end
of the month date is automatically adjusted for months with fewer than 31 days, including corrections for
leap year. The clock operates either in the 24-hour or in the 12-hour format with AM/PM indicator.
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Functional Blocks
The DS1306 offers dual-power supplies as well as a battery-input pin. The dual-power supplies support
a programmable trickle charge circuit that allows a rechargeable battery to be used for a backup supply.
Two programmable time-of-day alarms are provided by the DS1306. Each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day.
A 1Hz clock output is also available through the 2-pin jumper S22 (when closed, default condition) both
for the D940HF and the Timer header connector J23.
The RTC provides an open-drain interrupt line (active low) usually asserted by the internal programmable alarm block. The interrupt line is connected to the IRQ1 signal that is shared with both the on board
interrupt push button SW2 and the SPI1 header connector.
The access control of SPI0 Port must be enabled by closing the 2-pin jumper S21 (default configuration).
This jumper must be disabled (open) when the user needs to use the SPI0 Port (Chip Select 3) with the
J24 header connector.
Table 5-24. RTC Jumper Settings
Available Resources
S21
S22
Closed
Closed
Open
Closed
RTC, J23, J24
U15: Chip Select enabled, 1Hz signal unusable
J23: Pin 10 Timer Input 0 available
J24: Pin 10 not usable
Closed
Open
J23, J24
U15: Chip not accessible, 1Hz signal unusable
J23: Pin 10 Timer Input 0 available
J24: Pin 10 NPCS03 available
Open
Open
RTC, J23, J24
J23, J24
5.3.9
Resource Status
U15: Chip Select enabled, 1Hz signal available
J23: Pin 4 receives 1 Hz signal from RTC output
J24: Pin 10 not usable
U15: Chip not accessible, 1Hz available if already
programmed
J23: Pin 4 not usable
J24: Pin 10 NPCS03 available
DBGU, USART0 and MIDI-IN
The DBGU, USART0 and MIDI-IN Block provides an external interface to the Debug Unit (DBGU) and
USART0 Ports of D940HF using an RS-232 transceiver (U16) and two DB9 male connectors (J17 for the
DBGU and J19 for the USART0).
An opto-isolator circuit has been added in order to translate a MIDI signal level from an external remote
system (such as a MIDI sequencer) to the RS-232 Receive signal level of the USART1 Port.
The RS-232 transceiver is a MAX3387E device with three receivers and three transmitters. The block
supports the DBGU Port communication using only receive and transmit signals while the support for
CTS and RTS signals has been added to the USART0 Port in order to allow the user to enable the hardware handshaking feature for the automatic flow control.
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Functional Blocks
The DB9 connector for the DBGU signals is J17. The pinout of the J17 connector is described in Table 525:
Table 5-25. J17 DB9 Connector for DBGU
Pin
Name
Function
2
RSRXD
Receiving input data
3
RSTXD
Transmitting output data
5
GND
Reference
The pinout of the J19 connector is Table 5-26:
Table 5-26. J19 DB9 Connector for USART0 Pinout
Pin
Name
Function
2
RSRXD
Receiving input data
3
RSTXD
Transmitting output data
5
GND
Reference
7
RSRTS0
Request To Send output
8
RSCTS0
Clear To Send input
Both chassis connectors are connected to GND through R169 (0 Ohm) resistor.
The Optoisolator Block provides a MIDI-IN interface from an external system through the 4-pin header
connector (2x2) J31. The connector pinout is described in Table 5-27:
Table 5-27. J31 MIDI-IN Connector Pinout
Pin
Name
Function
1
VPlus
MIDI Positive Voltage Level
2
VMinus
MIDI Negative Voltage Level
3
GND
Connection to Ground
4
GND
Connection to Ground
The opto-isolator component U17 mounted on the DBM requires a 5 Volt power supply. The 3-pin
jumper S24 provides 5 Volt voltage level when pins 1-3 are closed (3.3 Volt voltage is provided when
pins 2-3 are closed).
The opto-isolator output is pin 6 of U17 and it is connected to the RXD1 signal to USART1 when pins 13 of the 3-pin jumper S25 are closed. This setting does not allow the use of the J22 USART1 header
connector (J22 can be used if S25 pins 2-3 are closed).
5.3.10
USB Host and Device
The USB Host and Device Interface Block provides two USB Host Ports V2.0 Full-speed Compliant, 12
MBits per second (UHP) and one USB Device Port V2.0 Full-speed Compliant, 12 MBits per second
(UDP). The USB Host connector (reference J18) is a type A double socket with A and B receptacles (A is
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DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
the upper receptacle and B is the lower one). The A receptacle is connected to the USB Host A Port with
the pinout shown in Table 5-28:
Table 5-28. USB Host A Receptacle Pinout
Pin
Name
Function
A1
VBus
VBus Power Supply Voltage
A2
HDMA
USB Host A Port Minus Data
A3
HDPA
USB Host A Port Plus Data
A4
GND
Ground
The B receptacle is connected to the USB Host B Port with the pinout shown in Table 5-29:
Table 5-29. USB Host B Receptacle Pinout
Pin
Name
Function
B1
VBus
VBus Power Supply Voltage
B2
HDMB
USB Host B Port Minus Data
B3
HDPB
USB Host B Port Plus Data
B4
GND
Ground
Pins 1, 2, 3 and 4 are connected to the USB chassis plane and are connected to the ground through the
R180 resistor.
The USB Device connector (reference J21) is a single socket with type B receptacle that is connected to
the USB Device Port with the pinout shown in Table 5-30:
Table 5-30. USB Device Receptacle Pinout
Pin
Name
Function
1
CAP
Pin to be connected to ground through a capacitor
2
DDM
USB Device Port Minus Data
3
DDP
USB Device Port Plus Data
4
GND
Ground
Pins 5 and 6 are connected to the USB chassis plane and are connected to the ground through the R180
resistor.
5.3.11
Ethernet Interface
The Ethernet Interface Block provides a 10/100 Base-TX RJ45 connector with integrated magnetics
(ICM) and LEDs, mounted to support fast Ethernet applications, such as LAN-on-Motherboard (LOM).
The connector is suitable for Cat. 5 cables. The connector reference is J20 and it integrates two LEDs for
Link Status (green) and Speed Status (yellow). An external red LED has been added (DS4) to report
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Network Full-Duplex and Collision Status. The J20 connector pinout is divided into two parts: the PCB
side to the PHY on the DCM and the cable side. The PCB side pinout is described in Table 5-31:
Table 5-31. PCB Side Ethernet Connector Pinout
Pin
Name
Function
1
TD+
Transmit Data Positive Level
2
TD-
Transmit Data Negative Level
3
CT
4
CHS GROUND
Chassis Ground
5
CHS GROUND
Chassis Ground
6
CT
7
RD+
Receive Data Positive Level
8
RD-
Receive Data Negative Level
9
Left LED PU
LED Connection to the External Pull-Up
10
Left LED Ctrl
Link Status LED Control (green LED)
11
Right LED PU
Speed Status LED Control (yellow LED)
12
Right LED Ctrl
LED Connection to the External Pull-Up
13
CHS GROUND
Chassis Ground
14
CHS GROUND
Chassis Ground
Take note that the left and right position of the Ethernet connector LEDs are referred to:
– The front view of the J20 connector
– The bottom layer of the DBM
The cable side pinout is shown in Table 5-32:
Table 5-32. Cable Side Ethernet Connector Pinout
5.3.12
Pin
Name
Function
1
TX+
Transmit Data Positive Level
2
TX-
Transmit Data Negative Level
3
RX+
Receive Data Positive Level
4
NC
-
5
NC
-
6
RX-
Receive Data Negative Level
7
NC
-
8
NC
-
External Interrupt
The External Interrupt Block provides a way to send an active low pulse on the open-drain IRQ1 interrupt
line connected to the PIOA12 of D940HF through the X3 module connector.
The reset pulse can be generated by pushing the SW2 push button mounted on the top side of the PCB.
The reset pulse lasts the whole time the push button is maintained under pressure.
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Functional Blocks
5.3.13
Header Connectors
The Header Connector Block provides an easy way to interface the D940HF ports to an external system.
The connectors are 12-pin vertical headers organized in two rows (6x2) located in the bottom part of the
DBM. The connector references start from J22 to J30.
The connectors can be used without any contention by configuring the DBM jumpers as reported in the
previous paragraphs and by checking the DCM Section 5.2.10 ”PIO Selectors” on page 5-5.
Take note that pull-up resistors have been added to the TWI lines TWD0, TWCK0, TWD1 and TWCK1
(J25, J29 and J30 connectors).
The connector pinout and functionalities are shown in the tables below:
Table 5-33. USART1 Port Connector (J22)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
NC
4
NC
5
SCLK1
6
NRESET
7
CTS1
8
RTS1
9
HRXD1
10
TXD1
11
GND
12
3.3 Volt
:
Table 5-34. USART2 Port Connector (J26)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
NC
4
NC
5
SCLK2
6
NRESET
7
CTS2
8
RTS2
9
RXD2
10
TXD2
11
GND
12
3.3 Volt
:
Table 5-35. TIMER Port Connector (J23)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
TIOA0
4
TII0
5
TIOA1
6
TIOA2
7
TIOB2
8
TIOB1
9
TII1
10
TIOB0
11
GND
12
3.3 Volt
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:
Table 5-36. CAN0/1 Port Connector (J27)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
CANL0
4
CANH0
5
CANRX0
6
CANTX0
7
CANRX1
8
CANTX1
9
CANL1
10
CANH1
11
GND
12
3.3 Volt
:
Table 5-37. SPI0 Port Connector (J24)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
MOSI0
4
MISO0
5
SCK0
6
NPCS00
7
IRQ0
8
NPCS01
9
NPCS02
10
NPCS03
11
GND
12
3.3 Volt
:
Table 5-38. SPI1 Port Connector (J28)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
MOSI1
4
MISO1
5
SCK1
6
NPCS10
7
IRQ1
8
NPCS11
9
NPCS12
10
NPCS13
11
GND
12
3.3 Volt
:
Table 5-39. SSC1/TWI1 Port Connector (J25)
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Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
TD1
4
RD1
5
TK1
6
RK1
7
TF1
8
RF1
9
TWCK1
10
TWD1
11
GND
12
3.3 Volt
DIOPSIS 940HF Evaluation Board User Guide
Functional Blocks
:
Table 5-40. SSC2/TWI0 Port Connector (J29)
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
TD2
4
RD2
5
TK2
6
RK2
7
TF2
8
RF2
9
TWCK0
10
TWD0
11
GND
12
3.3 Volt
:
Table 5-41. SSC3/TWI1 Port Connector (J30)
5.3.14
Pin
Signal
Pin
Signal
1
3.3 Volt
2
GND
3
TD3
4
RD3
5
TK3
6
RK3
7
TF3
8
RF3
9
TWCK1
10
TWD1
11
GND
12
3.3 Volt
DBM LEDs
A summary of the LEDs available on the DBM is reported in the table below:
Table 5-42. DBM LEDs Summary
5.3.15
Ref.
Signal
Color
Description
DS1
CPULED/PB30
Red
General purpose LED from CPU Module
DS2
SCLK0/PA11
Red
General purpose LED from CPU Module in common with
USART0 Clock
DS3
3.3 Volt
Red
Power LED
DS4
LEDCOL
Red
Full-Duplex/Collision Status LED from DCM Eth. PHY
J20 (Pin 10)
LEDLINK
Green
Link Status LED included in J20 (Eth. Connector)
J20 (Pin 11)
LEDSPEED
Yellow
Speed Status LED included in J20 (Eth. Connector)
Module Connectors
The DBM hosts the DCM by using only the two module connectors X1 and X3. The connectors are used
to provide the power supply to the DCM and to exchange signals between D940HF and the peripheral
support devices mounted on the DBM. The DBM module female connectors are X1 and X3 and provide
mechanical support to the DCM. But in order to improve the mechanical stability of the board when
plugged in, other supports are available as well.
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Functional Blocks
Figure 5-7.
X1 and X3 Female Connector Pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
5-24
7014A–DSP–03/09
X1 Connector
Signal
Pin
Signal
NC
2
NC
NC
4
NC
NC
6
NC
NC
8
NC
NC
10
NC
NRESET
12
NC
RTCK
14
ATMS
ATDI
16
ATDO
ATCK
18
ANTRST
GND
20
NC
NC
22
NC
SCLK0
24
NC
CTS0
26
RTS0
RXD0
28
TXD0
GND
30
3V3
NC
32
NC
SCLK1
34
NC
CTS1
36
RTS1
RXD1
38
TXD1
GND
40
3V3
DTXD
42
DRXD
SCLK2
44
NC
CTS2
46
RTS2
RXD2
48
TXD2
GND
50
3V3
TIOA0
52
TII0
TIOA1
54
TIOA2
TIOB2
56
TIOB1
TII1
58
TIOB0
GND
60
3V3
TIOA0
62
MISO0
SCK0
64
NPCS00
NPCS01
66
NPCS02
NPCS03
68
IRQ0
GND
70
3V3
TD0
72
RD0
TK0
74
RK0
TF0
76
RF0
TWCK0
78
TWD0
GND
80
NC
HDPA
82
NC
HDMA
84
NC
HDPB
86
DDP
HDMB
88
DDM
GND
90
SDWP
MCCDA
92
MCDA0
MCCK
94
MCDA3
MCDA1
96
MCDA2
NC
98
SDDET
GND
100
3V3
NC
102
NC
NC
104
NC
NC
106
NC
CPULED
108
LEDSPEED
NC
110
NC
CANTX0
112
LEDCOL
CANRX0
114
LEDLINK
AGND_ETH
116
AVDD_ETH
RXp
118
TXp
RXm
120
TXm
P in
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
X 3 C o nne c t o r
S igna l
P in
S igna l
NC
2
NC
NC
4
NC
NC
6
NC
NC
8
NC
NC
10
NC
CA NTX1
12
NC
CA NRX1
14
NC
NC
16
NC
NC
18
NC
GND
20
3V3
NC
22
NC
NC
24
NC
NC
26
NC
NC
28
NC
GND
30
3V3
NC
32
NC
NC
34
NC
NC
36
NC
NC
38
NC
GND
40
3V3
M OSI1
42
M ISO1
SCK1
44
NP CS10
NP CS11
46
NP CS12
NP CS13
48
IRQ1
GND
50
3V3
TD1
52
RD1
TK1
54
RK1
TF1
56
RF1
TWCK1
58
TWD1
GND
60
3V3
TD2
62
RD2
TK2
64
RK2
TF2
66
RF2
NC
68
NC
GND
70
3V3
TD3
72
RD3
TK3
74
RK3
TF3
76
RF3
NC
78
NC
GND
80
3V3
NC
82
NC
NC
84
NC
NC
86
NC
NC
88
NC
GND
90
3V3
NC
92
NC
NC
94
NC
NC
96
NC
NC
98
NC
GND
100
3V3
NC
102
NC
NC
104
M TM S
M TDI
106
M TDO
M TCK
108
M NTRST
GND
110
3V3
NC
112
NC
NC
114
NC
NC
116
NC
NC
118
NC
GND
120
3V3
DIOPSIS 940HF Evaluation Board User Guide
Section 6
Schematics
This sections shows the schematics of the DCM and DBM boards.
6.1
DCM Board Schematics
The DCM schematics are composed of the following five sheets:
!
Sheet 1: POWER AND SWITCHES
!
Sheet 2: D940HF
!
Sheet 3: EXTERNAL MEMORIES
!
Sheet 4: ETHERNET INTERFACE
!
Sheet 5: X CONNECTORS
DIOPSIS 940HF Evaluation Board User Guide
6-1
7014A–DSP–03/09
A
B
3V3
COPPER HEATSINK
AREA UNDERNEATH
THE VOLTAGE
REGULATOR
2 CM LENGHT
MOUNTED
ONLY FOR
BIAS USE
C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
C28
C27
C26
C25
C24
C23
C22
C21
100nF
8
C51
10µF
10V
C35
10µF
10V
C19
10µF
10V
C36
10µF
10V
C20
10µF
10V
1 CM WIDE
C2
+
DEFAULT
CONFIGURATION
FOR
NCP565D2TG:
R2= 30.1KOHm;
R1= 10KOHm;
C4= 5.6pF;
C5 AND C6 NOT
MOUNTED
100UF/16V
CE5MM
ESR 0.2
FEEDBACK
connection (PIN4 to
PIN5) as short as
possible
6
R5
0.25
1V2_CORE
1V2
7
1
4
5
VCC
MAX4372
(20x)
GND OUT
RS+
RS-
U2
2
3
6
1µF
C57
3V3_A
100nF
C52
PC[0..31]
PC[0..31]
PC[0..31]
PC[0..31]
S2,5 PC[0..31]
S5 CFIRQ2
VIN
NC
NC
NC
VOUT
ADR121AUJZR2
100nF
2 GND
3V3_A 3
C58
U5
C56 330nF
5
4
1
5
6
1
4
2
7
6
8
S10
S7
S5
S12
S15
S16
S19
S21
GND
2V5_Vref
1µF
1
3
5
100nF
C60
AD7457BRT-R2
C59
5
VDD
2
2
2
2
2
PC0
PC6
PC0
3V3_A
C53
10µF
10V
PC[0..31]
RTS1 S5
CTS1 S5
SCLK1 S5
CANRX0 S5
RTS2 S5
CTS2 S5
SCLK2 S5
2
2
TXD2 S5
RXD2 S5
2
2
SDATA
PC2R
CS
SCLK
VIN+
VINVREF
U3
PC12
1
PC11
1
PC13R
1
PB26
1
PC17
1
PC16
1
PC18R
1
PC15
1
PC14
S1
JP SELECTORS
S2,5 PC2R
PC[0..31]
PC[0..31]
PC6
PC2R
(COMP. FLASH)
S5 CFRST2
S2 PC13R
S5 CFCD2
S2,3,4,5 PB[0..31] PB[0..31]
(ETH PHY)
S4 LINKSTS
S2,5 PC[0..31]
S5 CFIRQ1
(NAND FLASH)
S3 RDYBSY
S2 PC18R
S5 CFCD1
S5 SD_DET
S5 SD_WP
D940HF Vdd CORE POWER MEASUREMENT BLOCK
C37 100nF
100nF
100nF
C38 100nF
100nF
100nF
C39 100nF
100nF
100nF
C40 100nF
100nF
100nF
C41 100nF
100nF
100nF
C42 100nF
100nF
100nF
C43 100nF
100nF
100nF
100nF
C44 100nF
100nF
100nF
C45 100nF
100nF
1V2_CORE
3V3
10K
5.6 pF
C5 1µF
C4
R1
3
4
1V2
CAPS CLOSED TO D940HF POWER PINS
VOLTAGE
REGULATOR
T0 - 263
PACKAGE
S6
C29
C46 100nF
100nF
100nF
C
CAP FOR
SOFT START
10 NF MAX
C6
1.0nF
3
30.1K
R2
GND
OUT
NCP565D2TG
EN
FB
IN
C30
C47 100nF
100nF
100nF
S9
3V3
CERAMIC CAP AS
CLOSE AS POSSIBLE
TO 3V3 INPUT PIN
1µF
C3
1
5
2
C31
C48 100nF
100nF
D
1
2
U1
C34
C1
10µF
10V
3V3
C32
C49 100nF
100nF
1
2
7
C33
C50 100nF
100nF
3
3
3
3
3
3
3
3
3
6-2
4
4
C54
100nF
Ferrite
S2,5 MTCK
S2,5 TCK
S2,5 MTMS
S2,5 TMS
S2,5 MNTRST
S2,5 NTRST
L1
3V3
S14
S8
S3
3
3
S5 X1_MTDO
S2,5 TDI
S5 X1_TDO
S2,5 MTDI
S5 X1_RTCK
S17
TCK
S20
S13
S4
S18
S11
X1_RTCK
MTDO
TDI
TDO
MTDI
S2
1
PC[0..31]
3V3
PC5CTRL
R3
10K
1
2
3
4
Y
VCC
4
5
3V3
D940HF CPU MODULE
Monday, November 05, 2007
B
DWG NO
Rev
Sheet
<Doc>
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
Date
PRJ
100nF
FLWRITE S3
C55
MTDO S2
TDI S2,5
TDO S2
MTDI S2,5
RTCK S2
Via G. V. Galati, 91 - 00155 Rome - ITALY
SN74lvc1g32
GND
A
B
U4
8
7
6
5
POWER AND SWITCHES
-
3
1
2
SW DIP-4
SW1
R4
10K
Atmel Roma
S2,5 NWR0
3
S22
PA24
AT572D940
Roma
PC5
S3 NWP
S3 FLVPP
S4 ETHEXTCKEN
3V3
DIP SWITCH BLOCK AND FLASH PROTECTION
MTCK S2,5
TCK S2,5
MTMS S2,5
TMS S2,5
MNTRST S2,5
NTRST S2,5
S2,3,4,5 PA[0..31] PA[0..31]
MTCK
TCK
MTMS
TMS
MNTRST
NTRST
2
ICE INTERFACE SWITCHES
2
7014A–DSP–03/09
1
8
5
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
S24
XINM_OSC
12MOUT
32KOUT
3V3
1V2_CORE
Ferrite
C71
Ferrite
PA2R S5
PA11R S5
PB3R S5
PB5R S5
PB9R S5
PB11R S5
PB15R S5
PB17R S5
PB21R S5
PB23R S5
PC2R S1,5
PC8R S5
PC13R S1
PC18R S1
PC21R S5
PC22R S5
PA22
PA21
8
7
6
5
L4
L3
L2
1%
1,5K
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
3V3
U7
C70
SN74AVCH2T45
1
2
3
4
100nF
XINM_OSC
XINS_OSC
1V2_CORE
3
S30
GNDOSCM_PLLB
VDDOSCM_PLLB
GNDOSCS
VDDOSCS
GNDPLLA
VDDPLLA
XENS
XINS
XOUTS
XINM
XOUTM
PLLRCA
PLLRCB
NTRST
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
PA0_MISO0_MSIRQ0
PA1_MOSI0_CFCE1
PA2_SPCK0_CFCE2
PA3_NPCS00_CDOUT1
PA4_NPCS01_MSIRQ2
PA5_NPCS02_TIOA0
PA6_NPCS03_TIOB1
PA7_URXD0_DTXD
PA8_UTXD0_CKOUT1
PA9_UCTS0_NPCS01
PA10_URTS0_TII1
PA11_USCK0_NPCS02
PA12_EXTIRQ1_URTS0
PA13_MDIO_MSIRQ1
PA14_MDC_EXTIRQ2
PA15_FCE100_TII2
PA16_EREFCK_CKOUT0
PA17_ECRSDV_NCS4
PA18_ERX0_NCS5
PA19_ERX1_NCS6
PA20_ERXER_NCS7
PA21_ETX0_MCK
PA22_ETX1_ACK
PA23_ETXEN_MSIRQ0
PA24_BMS_MSIRQ1
PA25_NWAIT_URTS2
PA26_NCS4_TIOA2
PA27_NCS5_CKOUT2
PA28_NCS6_SMOE
PA29_NCS7_SMWE
PA30_CFCE1_CKOUT3
PA31_CFCE2_MSIRQ3
U6
7
EXT96MIN
P7
100nF
C69
T5
R5
100nF
VDDOSCM
C68
VDDOSCS
U4
T3
100nF
U3
N7
VDDPLLA
S28
S29
V2
V3
U5
32.768 kHz
Y2
S26
C67
18PF
18PF
27PF
V5
U2
P6
M13
M14
N15
N17
M17
M16
N16
F11
C11
A11
B11
H10
G10
D10
B17
A17
B16
A16
C15
H17
V15
U15
V16
T15
V17
T16
T17
U18
T18
R15
R18
H16
B9
D9
G9
J9
A8
D8
B8
Y1
12.0000MHz
1.0nF PLLALFT
R22
VCCB VCCA
B1
A1
B2
A2
DIR
GND
8
TDI
TMS
TCK
RTCK
TDO
S1,5 NTRST
3
S1,5
S1,5
S1,5
S1
S1
27PF
C62
8.2nF
C64
C63
100nF
C66
S27
S23
C61
C65
3V3
Ferrite
XINS_OSC
SMB MALE
J1
1
2
3
4
5
3V3
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
A_CK
M_CK
TO BE PLACED NEAR D940HF
PA2
PA11
PB3
PB5
PB9
PB11
PB15
PB17
PB21
PB23
PC2
PC8
PC13
PC18
PC21
PC22
TP2
TP1
1
2
D
S1,3,4,5 PA[0..31]
S1,3,4,5 PB[0..31]
2
1
5
4
D940HF
3
S33
3V3
1V2_CORE
6
3V3
100nF
C72
S31
4
1
OUT
GND
12 MHz
VALPEY-FISHER
VDD
E/D
Y3
2
3
5
S32
100nF
C73
3V3
12MOUT
4
1
GND
OUT
32.768 KHz
VALPEY-FISHER
VDD
E/D
Y4
2
3
4
32KOUT
C74
3V3
S34
100nF
4
1
OUT
GND
96 MHz
VALPEY-FISHER
VDD
E/D
Y5
EXT96MEN
EXT96MIN
T6
R6
4
6
PORMSK
VEXTPOR
J11
T4
1
7
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
S1,5 PC[0..31]
2
1
U8
L9
P9
R9
V9
L10
N10
V10
T10
P10
M10
N11
M11
L11
U12
T12
R12
N12
V13
U13
T13
P13
V14
R14
J10
H15
B12
A12
F9
B10
A10
A9
NPCS03_SSRD0_PB0
TIOB0_SSTD0_PB1
CKOUT0_SSTF0_PB2
DOUT0_SSTK0_PB3
URTS0_SSRF0_PB4
MSIRQ1_SSRK0_PB5
DOUT0_SSRD1_PB6
TIOA1_SSTD1_PB7
CKOUT1_SSTF1_PB8
NPCS11_SSTK1_PB9
URTS1_SSRF1_PB10
A22_SSRK1_PB11
A23_SSRD2_PB12
MSIRQ2_SSTD2_PB13
A24_SSTF2_PB14
NPCS03_SSTK2_PB15
MDC_SSRF2_PB16
FCE100_SSRK2_PB17
A25_SSRD3_PB18
MSIRQ0_SSTD3_PB19
MDC_SSTF3_PB20
FCE100_SSTK3_PB21
URTS1_SSRF3_PB22
DTXD_SSRK3_PB23
MMODE_TII0_PB24
URTS2_EXTIRQ0_PB25
NPCS12_CDIN0_PB26
MSIRQ3_CDOUT0_PB27
NPCS01_A22_PB28
NPCS02_A23_PB29
CKOUT2_A24_PB30
CKOUT3_A25_PB31
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
D15
D14
C14
D13
C13
G12
F12
G13
F18
M18
L12
L13
L18
K12
H13
G17
G18
G14
F17
H14
F16
E18
K14
K16
K17
K15
K11
K10
E12
D12
P16
P17
F4
J4
L6
T2
M9
P11
T14
N13
L15
J13
H11
D16
E13
H9
E8
A2
2
3
2
3
3
EXT96MIN
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
D7
A5
B3
E5
E1
G4
H4
J5
K3
M2
N3
P2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
1
VDDIOMP
VDDIOMP
E9
G8
SSTD0_MISO1_PC0
SSTD1_MOSI1_PC1
SSTD2_SPCK1_PC2
ETX0_NPCS10_PC3
ETX1_NPCS11_PC4
MSIRQ3_NPCS12_PC5
SMOE_NPCS13_PC6
SSTD0_TWD0_PC7
SSTD1_TWCK0_PC8
SSTD2_URXD1_PC9
ETX0_UTXD1_PC10
ETX1_UCTS1_PC11
NPCS11_URTS1_PC12
SSTD3_USCK1_PC13
A22_URXD2_PC14
A23_UTXD2_PC15
A24_UCTS2_PC16
A25_URTS2_PC17
NPCS12_USCK2_PC18
NPCS13_TIOB2_PC19
SSTD3_TWD1_PC20
NPCS13_TWCK1_PC21
CDOUT1_MCCK_PC22
MSIRQ2_MCCDA_PC23
SMOE_MCDA0_PC24
SMWE_MCDA1_PC25
NCS4_MCDA2_PC26
NCS5_MCDA3_PC27
NCS6_CDIN1_PC28
NCS7_CDOUT1_PC29
CFCE1_DRXD_PC30
CFCE2_DTXD_PC31
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E2
F5
G5
H5
J6
J3
K4
L3
M1
N2
N6
R4
T1
T8
R8
N9
U10
V11
R11
V12
R13
U14
U16
P15
P18
N18
L14
L17
K18
J16
J14
J12
H12
G15
F15
D18
D17
B15
B14
B13
C12
E11
F10
E10
C9
C8
F8
C7
E6
A3
C4
D2
2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
H1
J7
J2
J1
K9
K7
K5
K1
K2
K6
K8
L5
L1
L2
L4
L7
M3
L8
M4
M5
M6
N1
M7
N4
N5
P1
P3
P4
P5
R1
R2
R3
Date
PRJ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
DDP S5
DDM S5
HDPA S5
HDMA S5
HDPB S5
HDMB S5
Monday, November 05, 2007
B
DWG NO
Rev
Sheet
<Doc>
2
3
2
1
of
S25
5
MTDI S1,5
MTMS S1,5
3V3
MTCK S1,5
MNTRST S1,5
MTDO S1
NRST S3,4,5
NWR0 S1,5
NWR1 S3,5
NWR3 S3,5
NCS0 S3
SDCS_NCS1 S3
NCS2 S5
SMCS_NCS3 S5
CFOE_NOE_NRD S3,5
SDWE S3
SDA10 S3
SDCKE S3
SDCK S3
RAS S3
CAS S3
Via G. V. Galati, 91 - 00155 Rome - ITALY
D940HF CPU MODULE
-
3V3
A1
A18
V1
V18
U6
V4
M8
U9
T11
U1
R16
R17
M15
C18
C17
B18
A14
C3
B1
P8
N8
T7
R7
V7
U7
J18
E15
E17
F13
E16
E14
J17
C6
D6
G7
F7
A6
B7
E7
B6
B4
A7
C5
B5
D5
A4
B2
C2
C1
D4
D3
D1
E4
E3
F6
G6
F3
H8
F2
F1
G3
H7
G1
G2
H6
H3
J8
H2
A[0..21] S3,5
D[0..31] S3,5
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
Atmel Roma
D940HF
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDP
DDM
HDPA
HDMA
HDPB
HDMB
TST
MTDI
MTMS
MTCK
MNTRST
MTDO
NRST
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
NCS0
SDCS_NCS1
NCS2
NANDCS_NCS3
CFOE_NRD
SDWE
SDA10
SDCKE
SDCK
RAS
CAS
NBS0_A0
NWR2_NBS2_A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BA0_A16
BA1_A17
A18
A19
A20
A21
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
C10
D11
G11
A13
A15
C16
F14
G16
H18
J15
K13
L16
M12
N14
U17
P14
P12
U11
R10
T9
V8
V6
2
DIOPSIS 940HF Evaluation Board User Guide
1
8
A
B
C
D
Schematics
7014A–DSP–03/09
6-3
A
B
C
D
SDWE
SDA10
SDCKE
SDCK
8
S1,2,4,5 PB[0..31]
S1,2,4,5 PA[0..31]
S1 FLVPP
S1 NWP
S2,4,5 NRST
S1 RDYBSY
S2,5 CFOE_NOE_NRD
S1 FLWRITE
S2 NCS0
D[0..31]
EBI FLASH
S2 SDCS_NCS1
S2,5 NWR1
S2,5 NWR3
S2
S2
S2
S2
S2 RAS
S2 CAS
S2,5 D[0..31]
3V3
PB28
PB29
S35
EBI SDRAM INTERFACE
S2,5 A[0..21]
10K
NWP
7
7
R24
3V3
A21
PB28
PA28
PA29
PA15
RDYBSY
R23
10K
A0
NWR1
A14
A16
A17
A13
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
19
7
16
17
8
18
9
U10
16
19
17
18
U8
VSS
VSS
VSS
VCC
VCC
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
6
FLVPP
2 Gbits
38
36
13
37
12
48
47
46
45
40
39
35
34
33
28
27
29
30
31
32
41
42
43
44
256 Mbits
3V3
28
41
54
6
12
46
52
1
14
27
3
9
43
49
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
C93
100nF
D0
D1
D2
D3
D4
D5
D6
D7
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
MT29F2G08AACWP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
WP
R/B
CLE
ALE
RE
WE
CE
SDWE
CAS
RAS
15
39
38
SDCK
NBS0
37
36
40
20
21
SDCKE
BA0
BA1
SDA10
23
24
25
26
29
30
31
32
33
34
22
35
6
C94
100nF
3V3
R25
10K
5
CFOE_NOE_NRD
NRST
FLWRITE
FLVPP
NCS0
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
PB28
PB29
C75
C77
C79
C81
100nF 100nF
100nF 100nF
100nF C80
C76
100nF C78
100nF
3V3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
5
28
12
11
13
26
14
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
OE
RST
WE
VPP
CE
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
U11
3V3
37
47
VCC
VCCQ
GND1
GND2
27
46
4
100nF
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
17
18
16
19
CAS
RAS
SDWE
15
39
38
SDCK
NBS2
37
36
40
20
21
23
24
25
26
29
30
31
32
33
34
22
35
SDCKE
BA0
BA1
SDA10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
AT49BV642_48SO
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
A14
A16
A17
A13
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A1
NWR3
C91 100nF
C89
4
U9
3
CFOE_NOE_NRD
NRST
FLWRITE
FLVPP
NCS0
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
PB28
PB29
28
12
11
13
26
14
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
256 Mbits
OE
RST
WE
VPP
CE
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
U12
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
3
2
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
-
D940HF CPU MODULE
Monday, November 05, 2007
PRJ
Date
B
DWG NO
Rev
Sheet
<Doc>
3
Via G. V. Galati, 91 - 00155 Rome - ITALY
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
Atmel Roma
EXTERNAL MEMORIES
AT49BV642_48SO
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
C92 100nF
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C82
C84
C86
C88
100nF 100nF
100nF 100nF
C83
C85
C87
100nF 100nF
100nF
3V3
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3V3 C90 100nF
28
41
54
6
12
46
52
1
14
27
3
9
43
49
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
37
47
VCC
VCCQ
6-4
GND1
GND2
7014A–DSP–03/09
27
46
8
5
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
8
7
3V3
S1 ETHEXTCKEN
S2,3,5 NRST
S1,2,3,5 PA[0..31]
7
C102
100NF
4
1
GND
OUT
R34
6
50.00 MHz
VALPEY-FISHER
VDD
PA20
PA16
PA17
E/D
Y6
(ETHREFCLK)
S1,2,3,5 PB[0..31]
3V3
PB25
PA19
PA18
PA14
PA13
PA22
PA21
PA23
6
2
3
10K
NRST
3V3
25
26
27
28
29
30
31
32
33
34
35
36
5
C103
10µF
10V
MDIO
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
DVDD
RXEN
MDINTR#
DGND
RXCLK/SCRAMEN/10BTSER
CRS/PHYAD4
COL/RMII
5
24
23
22
21
20
19
18
17
16
15
14
13
DM9161/LQFP48
U13
MDC
DVDD
TXCLK/ISOLATE
TXEN
TXD0
TXD1
TXD2
TXD3
TXER/TXD4
DGND
CABLESTS/LINKSTS
LINK/ACTLED#/OP2
C104
100NF
C105
100NF
AGND_ETH
3V3
4
C106
100NF
C107
100NF
TO BE
PLACED NEAR
pin 47-48
12
11
10
9
8
7
6
5
4
3
2
1
SPEED
FDX_COL
LINK_ACT
3
AGND_ETH
C95
10µF
10V
3
C98
100NF
Near Pin9
C101
100NF
L5
1
Date
B
DWG NO
Rev
Sheet
4
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
D940HF CPU MODULE
Monday, November 05, 2007
PRJ
<Doc>
Via G. V. Galati, 91 - 00155 Rome - ITALY
TX AND RX
RESISTANCES/CAPS NEAR
DM9161 PINS
AVDD_ETH
ETHERNET INTERFACE
-
RXIm S5
RXIp S5
TXOm S5
TXOp S5
Atmel Roma
R33
49.9/1%
R0603
AT572D940
Roma
C99
100NF
C100
100NF
R30
49.9/1%
R0603
AGND_ETH
AGND_ETH
R32
49.9/1%
R0603
RXIm
RXIp
TXOm
TXOp
R29
49.9/1%
R0603
2
Ferrite
Near Pin 1 and 2
C96
10µF
10V
C97
100NF
AVDD_ETH_RX
SPEED S5
FDX_COL S5
R28
10K
LINK_ACT S5
(AVDD for RX)
RXIm
RXIp
TXOm
TXOp
R27
10K
R26
10K
3V3
3V3
(AVDD for TX)
CAPS TO BE
PLACED
NEAR THE
DVDD PINS
SPEEDLED#/OP1
FDX/COLLED#/OP0
PWRDWN
AVDD
TXTX+
AGND
AGND
RXRX+
AVDD
AVDD
LINKSTS S1
4
R31
6.80K/1%
R0603
RXDV/TESTMODE
RXER/RXD4/RPTR
DVDD
RESET#
DVDD
XT2
XT1
DGND
NC
AGND
BGRESG
BGRES
DIOPSIS 940HF Evaluation Board User Guide
37
38
39
40
41
42
43
44
45
46
47
48
D
8
5
A
B
C
D
Schematics
7014A–DSP–03/09
6-5
7014A–DSP–03/09
6-6
A
B
C
D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
S2,3 A[0..21]
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
8
PA[0..31] S1,2,3,4
8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D[0..31] S2,3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB[0..31] S1,2,3,4
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
HDMB
HDPB
HDMA
HDPA
DDP
DDM
S4 RXIm
S4 RXIp
S4 TXOm
S4 TXOp
S4 SPEED
S4 FDX_COL
S4 LINK_ACT
S1 SD_WP
S1 SD_DET
S2
S2
S2
S2
S2
S2
S1,2 MTMS
S1,2 MNTRST
S1,2 MTDI
S1,2 MTCK
S1 X1_MTDO
S1 X1_RTCK
S1,2 TMS
S1,2 NTRST
S1,2 TDI
S1,2 TCK
S1 X1_TDO
S2,3,4 NRST
7
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S1,2
S2
S2
S2
PA2R
PA11R
PB3R
PB5R
PB9R
PB11R
PB15R
PB17R
PB21R
PB23R
PC2R
PC8R
PC21R
PC22R
S1 CTS2
S1 RTS2
S1 SCLK2
S1 TXD2
S1 RXD2
S1 CTS1
S1 RTS1
S1 SCLK1
S1 CFRST2
S1 CFCD1
S1 CFCD2
S1 CFIRQ1
S1 CFIRQ2
S1 CANRX0
S2 NCS2
S2 SMCS_NCS3
S2,3 CFOE_NOE_NRD
S1,2 NWR0
S2,3 NWR1
S2,3 NWR3
PC[0..31] S1,2
7
6
6
AVDD_ETH
TXOp
TXOm
FDX_COL
LINK_ACT
SPEED
DDP
DDM
SD_WP
PC24
PC27
PC26
SD_DET
PB0
PB5R
PB4
PC7
PA0
PA3
PA5
PB25
PB24
PA26
PA6
PB1
RTS2
TXD2
PC30
NRST
RTS1
PC10
NRST
PA10
PA8
NRST
TMS
X1_TDO
NTRST
X1
1
3
5
7
9
NRST
11
X1_RTCK
13
TDI
15
TCK
17
19
PA8
21
PA11R
23
PA9
25
PA7
27
29
PC10
31
SCLK1
33
CTS1
35
PC9
37
39
PC31
41
SCLK2
43
CTS2
45
RXD2
47
49
PA5
51
PB7
53
PC19
55
PA10
57
59
PA1
61
PA2R
63
PA4
65
PA6
67
69
PB1
71
PB3R
73
PB2
75
PC8R
77
79
HDPA
81
HDMA
83
HDPB
85
HDMB
87
89
PC23
91
PC22R
93
PC25
95
97
99
101
103
105
PB30
107
109
PB27
111
113 CANRX0
115
RXIp
117
RXIm
119
HEADER 60X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
5
CAPS MUST BE PLACED NEAR CONNECTORS
C108
10µF
10V
3V3
5
AGND_ETH
4
C109
10µF
10V
4
3V3
X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
HEADER 60X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
A1
42
A3
44
A5
46
A7
48
50
A10
52
A12
54
A14
56
A16
58
60
A18
62
A20
64
PB28
66
NWR1
68
70
D1
72
D3
74
D5
76
D7
78
80
D9
82
D11
84
D13
86
D15
88
90
NWR0
92
CFOE_NOE_NRD 94
PA27
96
SMCS_NCS3 98
100
CFOE_NOE_NRD 102
PA31
104
NWR3
106
CFIRQ1
108
110
CFCD1
112
CFCD2
114
CFIRQ2
116
PB31
118
120
3
C110
10µF
10V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
-
MTDI
MTCK
A1
D24
D26
D28
D30
D16
D18
D20
D22
PB19
PB21R
PB20
PC21R
PB13
PB15R
PB14
PC8R
PB7
PB9R
PB8
PC21R
PC1
PC2R
PC4
PC6
PC29
PC28
D940HF CPU MODULE
Monday, November 05, 2007
PRJ
Date
Rev
B
DWG NO
Sheet
<Doc>
5
Via G. V. Galati, 91 - 00155 Rome - ITALY
HEADER 60X2
X3
X CONNECTORS
Atmel Roma
NWR3
MTMS
X1_MTDO
MNTRST
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
PA11 CFRST1
CFRST2
NWR1
NWR0
PA30
D25
D27
D29
D31
PA26 CFCS0
NCS2
PB18
PB23R
PB22
PC20
PB12
PB17R
PB16
PC7
PB6
PB11R
PB10
PC20
PC0
PC3
PC5
PA12
D17
D19
D21
D23
Roma
3V3
2
D8
D10
D12
D14
D0
D2
D4
D6
A17
A19
A21
PA25
A0
A2
A4
A6
A8
A9
A11
A13
A15
MODULE CONNECTORS
3
5
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
Schematics
6.2
DBM Board Schematics
The DBM board schematics are composed of the following eleven sheets:
!
Sheet 1: POWER AND RESET
!
Sheet 2: AD1939 AUDIO CODECS
!
Sheet 3: AUDIO ANALOG OUTPUTS A1
!
Sheet 4: AUDIO ANALOG OUTPUTS A2
!
Sheet 5: AUDIO ANALOG IN FILTERS A1
!
Sheet 6: AUDIO ANALOG IN FILTERS A2
!
Sheet 7: JTAGS
!
Sheet 8: CAN RTC SD
!
Sheet 9: USB, ETH AND SERIAL INTERFACES
!
Sheet 10: HEADERS AND USER’S INTERFACES
!
Sheet 11: X CONNECTORS
DIOPSIS 940HF Evaluation Board User Guide
6-7
7014A–DSP–03/09
A
B
C
J1
+
8
S4
1µF
C13
RB
7
VDD_OP
30.1K
R9
3
RF
C14
3
80.6K
C18
MOUNTED
ONLY FOR
BIAS USE
1µF
GND
OUT
3V3
S1
6
C8
R4
L3
AGND
ESR 0.2
+ C12
100 uF
C9
R3
0.25
600 OHM
TO OP-AMP
L4
Ferrite
FERRITE TO BE
MOUNTED ONLY IF
AVDD_OP = 3.3 V
FB1
3V3
L1
Ferrite
AVDD_ETH
600 OHM
5
FERRITE TO BE
MOUNTED ONLY IF
AVDD_OP = 4.5 V
C19 100nF
4
5V
C17
10µF 10V
C16 100nF
C15
10µF 10V
3V3A_OUT
FB2
FROM CODEC
AVDD_3V3
L2
3V3
Ferrite
1
SW1
1K
3
4
RST
DS1818
GND
VCC
U2
C4
0.1UF
1
U4
4
2
FZT953
3
RESET BUTTON
NRESET
3V3
1
DS2
DS1
BERG2
J4
2
2
-
D940HF BACK MODULE
Monday, October 29, 2007
PRJ
Date
B
DWG NO
Rev
Sheet
<Doc>
1
Via G. V. Galati, 91 - 00155 Rome - ITALY
DS3
POWER LED
R7
120
POWER AND RESET
Atmel Roma
3V3
NRESET S2,7,10,11
J3
HEADER_1
1
3V3
3V3
2
1
of
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
1
R2 120
R1 120
1
GROUND HOOKS
HEADER_1
J2
STATUS LED
CPU MODULE LED
REMOTE RESET CONNECTOR
Roma
R6
1K
S11 SCLK0
S11 CPULED
ON CHIP 5.5K
PULL-UP RESISTOR
3
2
3
SW_PUSHBUTTON-SPST-2/SM
3
2
C3
10µF
10V
3V3
AVDD_OP = 3.3 V
GENERATED BY AD1939
INTERNAL CIRCUIT WITH
FZT953 SUPPORT
100nF
C11
C2
0.1UF
S2 VDRIVES
R10
AGND_ETH
C1
10µF
10V
ETH POWER PLANE
DECOUPLING
CAPACITORS
4
TO CODECS
AVDD_OP
3.3V DIGITAL OUTPUT
+ C6
100 uF
ESR 0.2
PREC. RESISTOR FOR
CURR. MEASUREMENT
SHAPE 2512
5
COPPER HEATSINK
AREA UNDERNEATH
THE VOLTAGE
REGULATORS
15PF
51K
Ferrite
MOUNTED
ONLY FOR
BIAS USE
1µF
3
4
FEEDBACK
connection as
short as possible
1 x 2 CM MAX
TPS75801
EN
FB
IN
U1
FEEDBACK
connection as
short as possible
VDD_OP
13 pF
1
5
2
6
VOLTAGE
REGULATOR
T0 - 263
PACKAGE
30.1K
R5
4.5V OPTION: RF=80.6KOHm
3.3V OPTION: RF=51KOHm
R8
GND
OUT
TPS75801
EN
FB
IN
U3
S3
1
5
2
4
CAP FOR
SOFT START
10 NF MAX
1000pF
C10
NPO
3
1µF
C7
4.5V / 3.3V OUTPUT
S2
5V
CERAMIC CAP AS
CLOSE AS POSSIBLE
TO VCC
CAP FOR
SOFT START
10 NF MAX
1000pF
C20
NPO
3
CR1
5V
5V
CERAMIC CAP AS
CLOSE AS POSSIBLE
TO VCC
C5
330 uF
1
2
2
REGULATED
5V ONLY
1
5V
7
1
2
D
1
2
1
2
1
6-8
2
7014A–DSP–03/09
1
8
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
D
8
S10,11 NPCS02
S10,11 NPCS01
AGND
AVDD_3V3
S9
R16
15K
3V3
AGND
AVDD_3V3
S11 TK0
S11 TF0
S5
TF0
TK0
7
S1,7,10,11 NRESET
S8,10,11 SCK0
S8,10,11 MOSI0
7
S6
S6
S6
S6
S6
S6
S6
S6
3V3
3V3
15K
15K
15K
S11 TD0
15K
15K
15K
ADC3LN
ADC3LP
ADC3RN
ADC3RP
ADC4LN
ADC4LP
ADC4RN
ADC4RP
R13
R14
R15
R18
R19
R20
100NF CAPS
PLACED NEAR
DVDD AND AVDD
AGND
ADC1LN
ADC1LP
ADC1RN
ADC1RP
ADC2LN
ADC2LP
ADC2RN
ADC2RP
AGND
100NF CAPS
PLACED NEAR
DVDD AND AVDD
NRESET
MOSI0
SCK0
S5
S5
S5
S5
S5
S5
S5
S5
54
53
56
55
58
57
60
59
TK0
TF0
6
MCLKI
NRESET
SCK0
MOSI0
5
45
51
62
17
32
49
50
63
64
19
18
15
21
22
1
34
30
35
20
2
14
24
23
54
53
56
55
58
57
60
59
5
45
51
62
17
32
49
50
63
64
19
18
15
21
22
1
34
30
35
20
MCLKI
2
14
VSENSE 24
VSUPPLY 23
6
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD
NC
NC
NC
NC
DSDATA2
DSDATA3
DSDATA4
DBCLK
DLRCLK
U5
AD1939YSTZ
AGND
AGND
AGND
AGND
DGND
DGND
ABCLK
ALRCLK
ASDATA2
COUT/SDA
VDRIVE
OR1N
OR1P
OR2N
OR2P
OR3N
OR3P
OR4N
OR4P
OL1N
OL1P
OL2N
OL2P
OL3N
OL3P
OL4N
OL4P
ASDATA1
CM
FILTR
LF
MCLKO/XO
FIRST
U6
AD1939YSTZ
AGND
AGND
AGND
AGND
DGND
DGND
ABCLK
ALRCLK
ASDATA2
COUT/SDA
VDRIVE
OR1N
OR1P
OR2N
OR2P
OR3N
OR3P
OR4N
OR4P
OL1N
OL1P
OL2N
OL2P
OL3N
OL3P
OL4N
OL4P
ASDATA1
CM
FILTR
LF
MCLKO/XO
SECOND
AGND
CCLK/SCL
CIN/ADR0
CLATCH/ADR1*
DSDATA1
MCLKI/XI
PD/RST
VSENSE
VSUPPLY
ADC1LN
ADC1LP
ADC1RN
ADC1RP
ADC2LN
ADC2LP
ADC2RN
ADC2RP
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD
NC
NC
NC
NC
DSDATA2
DSDATA3
DSDATA4
DBCLK
DLRCLK
AGND
CCLK/SCL
CIN/ADR0
CLATCH/ADR1*
DSDATA1
MCLKI/XI
PD/RST
VSENSE
VSUPPLY
ADC1LN
ADC1LP
ADC1RN
ADC1RP
ADC2LN
ADC2LP
ADC2RN
ADC2RP
4
44
46
48
16
33
28
29
26
31
25
39
38
43
42
9
8
13
12
37
36
41
40
7
6
11
10
27
52
47
61
3
5
4
44
46
48
16
33
28
29
26
31
25
39
38
43
42
9
8
13
12
37
36
41
40
7
6
11
10
27
52
47
61
3
5
VDRIVE
S3
S3
S3
S3
S4
S4
S4
S4
S3
S3
S3
S3
S4
S4
S4
S4
MISO0
RK0
RF0
RD_1OUT
FILTR1
LF
C21
100nF
R21
15K
4
RK0 S11
RF0 S11
C37
10µF
10V
AGND
CM1
FILTR1 S6
R17
750
C36
100nF
0.33 uF
C38
10000PF
C39
AGND
LF1
C34
100nF
C35
10µF
10V
AGND
RF0
MISO0
RK0
C24
10µF
10V
AGND
CM
FILTR S5
R12
750
C23
100nF
0.33 uF
C25
10000PF
C26
C22
10µF
10V
MISO0 S8,10,11
RD_1OUT
OR1N
OR1P
OR2N
OR2P
OR3N
OR3P
OR4N
OR4P
OL1N
OL1P
OL2N
OL2P
OL3N
OL3P
OL4N
OL4P
FILTR
RD0 S11
4
AVDD_3V3
TO BE PLACED
AS CLOSE AS
POSSIBLE TO
FILTR AND CM
AVDD_3V3
3
TO BE PLACED
AS CLOSE AS
POSSIBLE TO
FILTR AND CM
3
3V3
4
1
OUT
GND
3
2
VSENSE
VSUPPLY
VDRIVE
12.288MHz
VALPEY-FISHER
VDD
E/D
Y1
3
3
S11
3
S10
3
S8
Date
PRJ
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
2
Via G. V. Galati, 91 - 00155 Rome - ITALY
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
-
AD1939 AUDIO CODECS
Atmel Roma
5V
TF1 S10,11
VDRIVES S1
3V3A_OUT
- CLOSE ALL 2-3 PINS WHEN 4.5 V OPTION
- CLOSE ALL 1-2 PINS WHEN 3.3 V OPTION
VDRIVE, VSUPPLY AND VSENSE:
C27
100nF
S7
MCLKI
S6
2
2
1
R11
15K
C28
3V3
C29
100nF
C40
100nF
C30
100nF
C41
100nF
C31
100nF
C42
100nF
C43
100nF
C32
100nF
C44
100nF
100nF
C33
100nF
C45
100nF
2
1
2
1
2
DIOPSIS 940HF Evaluation Board User Guide
1
8
11
A
B
C
D
Schematics
7014A–DSP–03/09
6-9
7014A–DSP–03/09
6-10
A
B
C
D
S2 OR1P
S2 OR1N
S2 OL1P
S2 OL1N
8
8
R52
2.74K/1%
R49
NPO
C69
680pF
NPO
C65
330PF
R43
R40
5.49K/1%
AGND
C73
10µF
10V
5.49K/1%
R48
AGND
11K/1%
R42
R33
NPO
C54
680pF
NPO
C50
330PF
R27
AGND
1.65K/1%
C56
220PF
NPO
C46
100PF
7
C71
220PF
C63
NPO
100PF
AGND
1.65K/1%
3.32K/1%
3.32K/1%
R36
2.74K/1%
AGND
C59
10µF
10V
5.49K/1%
R32
AGND
11K/1%
R26
R22
5.49K/1%
7
6
10V
10µF
604/1%
C66
2200pF
C61
R38
6
AGND
NPO
C48
10µF
10V
1
2
3
4
5
49.9K/1%
R46
AGND
R24
604/1%
J5
STJACK3.5
5
2200pF
49.9K/1%
R30
NPO
C51
5
AGND
100nF
C60
AVDD_OP
AGND
1
2
3
4
5
6
7
AD8608_TSSOP
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
U7
14
13
12
11
10
9
8
4
4
S2 OR2P
S2 OR2N
AGND
S2 OL2P
S2 OL2N
AGND
R35
NPO
C55
680pF
NPO
C52
330PF
R29
3
R53
2.74K/1%
R51
NPO
C70
680pF
NPO
C68
330PF
R45
R41
5.49K/1%
R37
2.74K/1%
AGND
C74
10µF
10V
5.49K/1%
R50
AGND
11K/1%
R44
10V
10µF
C58
5.49K/1%
R34
AGND
11K/1%
R28
R23
5.49K/1%
3
AGND
1.65K/1%
3.32K/1%
C57
220PF
604/1%
R39
-
AGND
NPO
1
2
3
4
5
J6
STJACK3.5
49.9K/1%
R31
2200pF
AGND
Date
PRJ
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
3
Via G. V. Galati, 91 - 00155 Rome - ITALY
49.9K/1%
R47
AGND
C53
NPO
AUDIO ANALOG OUTPUTS A1
Atmel Roma
C67
2200pF
10V
10µF
C62
C49
10µF
10V
R25
604/1%
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
C72
220PF
C64
NPO
100PF
AGND
1.65K/1%
3.32K/1%
NPO
C47
100PF
2
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
D
S2 OR3P
S2 OR3N
S2 OL3P
S2 OL3N
8
8
R84
2.74K/1%
R81
NPO
C98
680pF
NPO
C96
330PF
R75
R72
5.49K/1%
AGND
C102
10µF
10V
5.49K/1%
R80
AGND
11K/1%
R74
R65
NPO
C83
680pF
NPO
C79
330PF
R59
AGND
1.65K/1%
C85
220PF
NPO
C75
100PF
7
C100
220PF
C92
NPO
100PF
AGND
1.65K/1%
3.32K/1%
3.32K/1%
R68
2.74K/1%
AGND
C88
10µF
10V
5.49K/1%
R64
AGND
11K/1%
R58
R54
5.49K/1%
7
10V
10µF
604/1%
6
C94
2200pF
C90
R70
6
AGND
NPO
C77
10µF
10V
1
2
3
4
5
49.9K/1%
R78
AGND
R56
604/1%
J7
STJACK3.5
5
2200pF
49.9K/1%
R62
NPO
C80
5
AGND
100nF
C89
AVDD_OP
AGND
1
2
3
4
5
6
7
AD8608_TSSOP
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
U8
14
13
12
11
10
9
8
4
4
S2 OR4P
S2 OR4N
AGND
S2 OL4P
S2 OL4N
AGND
R67
NPO
C84
680pF
NPO
C81
330PF
R61
3
R85
2.74K/1%
R83
NPO
C99
680pF
NPO
C97
330PF
R77
R73
5.49K/1%
R69
2.74K/1%
AGND
C103
10µF
10V
5.49K/1%
R82
AGND
11K/1%
R76
10V
10µF
C87
5.49K/1%
R66
AGND
11K/1%
R60
R55
5.49K/1%
3
AGND
1.65K/1%
3.32K/1%
C86
220PF
Roma
604/1%
R71
-
AGND
NPO
1
2
3
4
5
J8
STJACK3.5
49.9K/1%
R63
2200pF
AGND
Date
PRJ
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
4
Via G. V. Galati, 91 - 00155 Rome - ITALY
49.9K/1%
R79
AGND
C82
NPO
AUDIO ANALOG OUTPUTS A2
Atmel Roma
C95
2200pF
10V
10µF
C91
C78
10µF
10V
R57
604/1%
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
C101
220PF
C93
NPO
100PF
AGND
1.65K/1%
3.32K/1%
NPO
C76
100PF
2
11
A
B
C
D
Schematics
7014A–DSP–03/09
6-11
7014A–DSP–03/09
6-12
A
B
C
D
8
8
J10
STJACK3.5
J9
STJACK3.5
1
2
3
4
5
1
2
3
4
5
7
7
L8
Ferrite
AGND
L7
Ferrite
L6
Ferrite
AGND
L5
Ferrite
10µF 10V
C127
49.9K/1%
R111
AGND
49.9K/1%
R108
10µF 10V
C118
10µF 10V
C114
49.9K/1%
R95
AGND
49.9K/1%
R92
10µF 10V
C105
6.8K/1%
R115
NPO
C124
100PF
NPO
C123
100PF
6.8K/1%
6
120PF
C128
R112 5.76K/1%
FILTR
120PF
C120
R105 5.76K/1%
120PF
R104
C115
5.76K/1%
120PF
C107
5.76K/1%
R99
R96
FILTR
S2 FILTR
R89
6.8K/1%
NPO
C111
100PF
NPO
C110
100PF
6.8K/1%
R88
6
1
2
3
4
5
6
7
U9
C108
AGND
5.76K/1%
AGND
14
13
12
11
10
9
8
5
R113 5.76K/1%
AD8608_TSSOP
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
U10
C121
R106 5.76K/1%
R97
AD8608_TSSOP
14
13
12
11
10
9
8
5.76K/1%
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
100nF
AVDD_OP
1
2
3
4
5
6
7
100nF
AVDD_OP
R90
5
FILTR
FILTR
FILTR
FILTR
5.76K/1%
AGND
5.76K/1%
750K/1%
R116 750K/1%
R114 5.76K/1%
AGND
R107 5.76K/1%
R103 750K/1%
R100 750K/1%
R98
R91
R87
R117
AGND
R110
R109
4
237/1%
237/1%
237/1%
237/1%
R102
AGND
237/1%
237/1%
237/1%
237/1%
R101
AGND
R94
R93
AGND
R86
4
C129
NPO
1000pF
C125
NPO
1000pF
C122
NPO
1000pF
C117
NPO
1000pF
C116
NPO
1000pF
C112
NPO
1000pF
C109
NPO
1000pF
C104
NPO
1000pF
ADC2RN S2
NPO
C126
100PF
ADC2RP S2
ADC2LP S2
NPO
C119
100PF
ADC2LN S2
ADC1RN S2
NPO
C113
100PF
ADC1RP S2
ADC1LP S2
NPO
C106
100PF
ADC1LN S2
3
3
Via G. V. Galati, 91 - 00155 Rome - ITALY
Date
PRJ
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
5
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
-
1
AUDIO ANALOG IN FILTERS A1
Atmel Roma
2
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
D
8
8
J12
STJACK3.5
J11
STJACK3.5
1
2
3
4
5
1
2
3
4
5
7
7
L12
Ferrite
AGND
L11
Ferrite
L10
Ferrite
AGND
L9
Ferrite
10µF 10V
C153
49.9K/1%
R143
AGND
49.9K/1%
R140
10µF 10V
C143
10µF 10V
C140
49.9K/1%
R127
AGND
49.9K/1%
R124
10µF 10V
C130
6.8K/1%
R147
NPO
C150
100PF
NPO
C149
100PF
6.8K/1%
6
120PF
C154
R144 5.76K/1%
FILTR1
120PF
C146
R137 5.76K/1%
120PF
R136
C141
R131
R128 5.76K/1%
FILTR1
S2 FILTR1
120PF
C132
R121 5.76K/1%
6.8K/1%
NPO
C137
100PF
NPO
C136
100PF
6.8K/1%
R120
6
1
2
3
4
5
6
7
U11
C134
AGND
14
13
12
11
10
9
8
AGND
14
13
12
11
10
9
8
5
R145 5.76K/1%
AD8608_TSSOP
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
U12
C147
R138 5.76K/1%
R129 5.76K/1%
AD8608_TSSOP
OUTA OUTD
INAINDINA+
IND+
V+
VINB+
INC+
INBINCOUTB OUTC
100nF
AVDD_OP
1
2
3
4
5
6
7
100nF
AVDD_OP
R122 5.76K/1%
5
AGND
AGND
R148 750K/1%
R146 5.76K/1%
FILTR1
FILTR1
R139 5.76K/1%
R135 750K/1%
R132 750K/1%
R130 5.76K/1%
FILTR1
FILTR1
R123 5.76K/1%
R119 750K/1%
R149
AGND
R142
R141
4
237/1%
237/1%
237/1%
237/1%
R134
AGND
237/1%
237/1%
237/1%
237/1%
R133
AGND
R126
R125
AGND
R118
4
C155
NPO
1000pF
C151
NPO
1000pF
C148
NPO
1000pF
C144
NPO
1000pF
C142
NPO
1000pF
C138
NPO
1000pF
C135
NPO
1000pF
C131
NPO
1000pF
ADC4RN S2
NPO
C152
100PF
ADC4RP S2
ADC4LP S2
NPO
C145
100PF
ADC4LN S2
ADC3RN S2
NPO
C139
100PF
ADC3RP S2
ADC3LP S2
NPO
C133
100PF
ADC3LN S2
3
3
Via G. V. Galati, 91 - 00155 Rome - ITALY
Date
PRJ
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
6
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
-
1
AUDIO ANALOG IN FILTERS A2
Atmel Roma
2
11
A
B
C
D
Schematics
7014A–DSP–03/09
6-13
A
B
8
S11 ANTRST
S11 ATDI
S11 ATMS
S11 ATCK
S11 RTCK
S11 ATDO
S1,2,10,11 NRESET
7
R158
15K
C
S14
S12
6
S16
6
ICE_ANTRST
ATDI
ATMS
ATCK
ICE_ARTCK
ATDO
ICE_ANSRST
S15
ARM ICE INTERFACE
R159
15K
R150
R151
R152
R153
15K
15K
15K
15K
7
1
3
5
7
9
11
13
15
17
19
J13
2
4
6
8
10
12
14
16
18
20
3V3
5
5
S11 MTDO
S11 MNTRST
S11 MTDI
S11 MTMS
S11 MTCK
NRESET
S13
4
MTDO
S26
ICE_MNTRST
MTDI
MTMS
MTCK
mAgic DSP INTERFACE
4
R160
15K
6-14
R154
R155
R156
R157
7014A–DSP–03/09
MNSRST
15K
15K
15K
15K
D
8
1
3
5
7
9
11
13
15
17
19
J14
3
3
2
4
6
8
10
12
14
16
18
20
3V3
Date
PRJ
Friday, October 26, 2007
Rev
B
DWG NO
Sheet
<Doc>
7
Via G. V. Galati, 91 - 00155 Rome - ITALY
D940HF BACK MODULE
-
1
of
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
2
1
AT572D940
Roma
JTAGS
Atmel Roma
2
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
D
8
S2,10,11 SCK0
S2,10,11 MISO0
S2,10,11 MOSI0
S10,11 NPCS03
S10,11 IRQ1
S10,11 CANTX1
S10,11 CANTX0
J16
1
S21
2
7
NC1
NC2
D
U14
3V3
R168
Y2
32.768 kHz
5
8
1
3V3
NC1
NC2
D
C157 100nF
5
8
1
U13
C156 100nF
7
3
VCC
CANH0
CANL0
CANRXOUT0
7
6
4
4
7
6
15K
3V3
IRQ1
15K
S22
DS1306E
VCC2 VCC1
Vbat
NC
X1
32KHz
NC
VCCIF
X2
SDO
NC
SDI
INT0
SCLK
INT1
NC
1Hz
CE
GND SMOD
R167
6
S19
R163
120
S17
R161
120
U15
15K
1
2
3
4
5
6
7
8
9
10
S20
S18
6
R166
CANRXOUT1
CANH1
CANL1
SN65HVD232
R
CAN
CAN
SN65HVD232
R
CAN
CAN
GND
2
3
VCC
GND
2
1
DIOPSIS 940HF Evaluation Board User Guide
4
8
20
19
18
17
16
15
14
13
12
11
NPCS03S
MISO0
MOSI0
SCK0
3V3
5
CANRX1 S10,11
CANL1 S10
CANH1 S10
CANRX0 S10,11
CANL0 S10
CANH0 S10
5
4
TII0 S10,11
4
S11 SDDET
S11 SDWP
S11 MCCDA
S11 MCDA3
S11 MCDA2
S11 MCCK
S11 MCDA1
S11 MCDA0
3
3
3V3
15K
R165
Date
PRJ
Friday, October 26, 2007
D940HF BACK MODULE
Rev
B
DWG NO
Sheet
<Doc>
8
Via G. V. Galati, 91 - 00155 Rome - ITALY
11 12
CAN RTC SD
-
3V3
FPS009
Atmel Roma
10
1
of
2
1
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AT572D940
15K
3V3
8
7
6
5
4
3
2
1
9
J15
SD CARD / MMC CARD
DATAFLASH CARD
INTERFACE
R164
100nF
C158
15K
Roma
MCCDA
MCDA3
MCDA2
MCCK
MCDA1
MCDA0
R162
3V3
2
11
A
B
C
D
Schematics
7014A–DSP–03/09
6-15
A
B
C
0.1UF
C165
8
0.1UF
C160
0.1UF
3V3
C159
0.1UF
S11 DTXD
S11 TXD0
S11 RTS0
C166
S11 RXm
S11 RXp
23
15
2
6
11
24
1
3
4
5
7
8
10
18
17
16
0.1UF
S11 TXm
S11 TXp
C167
RSRXD
RSRX0
RSCTS0
MAX3387E
VCC
VL
V+
V-
FORCEON
FORCEOFF
C1+
C1C2+
C2-
T1IN
T2IN
T3IN
R1IN
R2IN
R3IN
U16
9
21
20
19
14
13
12
100nF
100nF
7
AGND_ETH
C175
5
4
1nF
S11 LEDSPEED
S11 LEDLINK
J0026D21BNL
8 RD-
CHASSIS_ETH
RXm
75 75
75
6
75
8
7
5
4
6
S11 LEDCOL
RX-
3
RX+
7 RD+
RXp
6 CT
2
1
TX-
TX+
2 TD-
J20
CHASSIS_ETH
TXm
3 CT
1 TD+
R169
USART0 PORT
ETHERNET INTERFACE
DRXD S11
RXD0 S11
CTS0 S11
TXp
RSTXD
RSTX0
RSRTS0
C174
AVDD_ETH
INVALID
T1OUT
T2OUT
T3OUT
R1OUT
R2OUT
R3OUT
13
9
D
C176
C171
CHASSIS_UART
1
6
2
7
3
8
4
9
5
5
DS4
FULL DUPLEX
AGND_ETH
0.1UF/2KV
0.1UF/2KV
MALE RIGHT ANGLED
J19
CHASSIS_UART
1
6
2
7
3
8
4
9
5
CHASSIS_ETH
RXD
RTS
TXD
CTS
5
MALE RIGHT ANGLED
J17
0.0 Ohm
TXD
RXD
SERIAL DEBUG PORT
14
10
10
6
11
7
12
11
6-16
10
7014A–DSP–03/09
11
8
1K
1K
R182
R183
4
1K
R181
S11 DDP
S11 DDM
3V3
S11 HDMB
S11 HDPB
S11 HDMA
S11 HDPA
4
3
5V
27 OHM
27 OHM
R176
15K
27 OHM
27 OHM
R172
15K
C172
15PF
USB DEVICE INTERFACE
R174
R175
R170
R171
USB HOST INTERFACE
3
47PF
C169
47PF
C162
27 OHM
27 OHM
-
1 2
B
A
5
6
4
1
CHASSIS_USB
J21
100nF
C170
100nF
C164
Via G. V. Galati, 91 - 00155 Rome - ITALY
CHASSIS_USB
0.0 Ohm
3
2
3 4
B1
B2
B3
B4
CHASSIS_USB
CHASSIS_USB
A1
A2
A3
A4
F2
500 mA
D940HF BACK MODULE
Monday, October 29, 2007
PRJ
Date
Rev
B
DWG NO
Sheet
<Doc>
9
USB, ETH AND SERIAL INTERF.
Atmel Roma
R180
C163
100nF
J18
CCUSBA-32002-30X
F1
500 mA
1
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
AT572D940
Roma
C173
15PF
R179
R178
R177 C168
15K
47PF
R173 C161
15K
47PF
S23
5V POWER ALTERNATIVE
2
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
A
B
C
D
S11 SCLK2
S11 CTS2
S11 RXD2
S11 SCLK1
S11 CTS1
8
3V3
HRXD1
3V3
3V3
J26
R184
HEADER12
1
3
5
7
9
11
15K
2
4
6
8
10
12
7
1
SW2 4
IRQ1 S8,11
2
3
SW_PUSHBUTTON-SPST-2/SM
IRQ1
IRQ1 PUSH BUTTON
3V3
S8 CANL0
NRESET S1,2,7,11 S8,11 CANRX0
RTS2 S11
S8,11 CANRX1
TXD2 S11
S8 CANL1
3V3
HRXD1
2
4
6
8
10
12
6
S11 RXD1
2
S25
HEADER12
1
3
5
7
9
11
J27
2
4
6
8
10
12
CAN0/1
S11 TIOA0
S11 TIOA1
S11 TIOB2
S11 TII1
1
3
5
7
9
11
USART2
3V3
NRESET S1,2,7,11
RTS1 S11
TXD1 S11
3V3
J23
TIMER
HEADER12
2
4
6
8
10
12
6
HEADER12
1
3
5
7
9
11
J22
USART1
7
3
DIOPSIS 940HF Evaluation Board User Guide
1
5
3V3
3V3
3V3
5
S8,11
S11
S11
S11
R185
120
VPlus
S11 NPCS12
S11 MOSI1
S11 SCK1
S2,8,11 MOSI0
S2,8,11 SCK0
S11 IRQ0
S2,11 NPCS02
IRQ1
3V3
3V3
4
HEADER12
1
3
5
7
9
11
5V
1
J31
2
4
6N139T&R
5
6
7
8
2
3V3
HEADER_2X2
S24
1
3
4
J28
SPI1
HEADER12
1
3
5
7
9
11
J24
SPI0
U17
VMinus
3
1
4
2
OPTOISOLATOR CIRCUIT
CANH0 S8
CANTX0 S8,11
CANTX1 S8,11
CANH1 S8
TII0
TIOA2
TIOB1
TIOB0
3
8
D1
1N914
2
4
6
8
10
12
2
4
6
8
10
12
3V3
3V3
3
R186
237/1%
MISO1
NPCS10
NPCS11
NPCS13
MISO0
NPCS00
NPCS01
NPCS03
3
S11
S11
S11
S11
3V3
3V3
S2,8,11
S11
S2,11
S8,11
3V3
3V3
HEADER12
1
3
5
7
9
11
2
4
6
8
10
12
R188
2
4
6
8
10
12
J30
-
R190
2
4
6
8
10
12
TWD1
RD3 S11
RK3 S11
RF3 S11
TWD1 S11
RD2 S11
RK2 S11
RF2 S11
TWD0 S11
RD1 S11
RK1 S11
RF1 S11
Via G. V. Galati, 91 - 00155 Rome - ITALY
1K
3V3
1K
3V3
3V3
TWD1
1
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
10 of
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
2
1
Date
PRJ
HEADERS AND USER'S INTERF.
Atmel Roma
3V3
HEADER12
1
3
5
7
9
11
SSC3/TWI1
3V3
HEADER12
1
3
5
7
9
11
J29
SSC2/TWI0
TWCK1
TWCK1
AT572D940
Roma
1K
TD3
TK3
TF3
TWCK1
R189
S11
S11
S11
S11
1K
TD2
TK2
TF2
TWCK0
R187
S11
S11
S11
S11
S11 TD1
S11 TK1
S2,11 TF1
3V3
J25
SSC1/TWI1
2
11
A
B
C
D
Schematics
7014A–DSP–03/09
6-17
7014A–DSP–03/09
6-18
A
B
C
D
SCLK2
CTS2
RXD2
RTS2
TXD2
S10
S10
S10
S10
S10
MOSI0
MISO0
NPCS00
NPCS01
NPCS02
NPCS03
SCK0
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
8
S10 TD3
S10 TK3
S10 TF3
S10 RD3
S10 RK3
S10 RF3
S10 TD2
S10 TK2
S10 TF2
S10 RD2
S10 RK2
S10 RF2
S10 TD1
S10 TK1
S2,10 TF1
S10 RD1
S10 RK1
S10 RF1
S2 TD0
S2 TK0
S2 TF0
S2 RD0
S2 RK0
S2 RF0
S10 TWCK1
S10 TWD1
S10 TWCK0
S10 TWD0
S10 IRQ0
S8,10 IRQ1
S10 MOSI1
S10 MISO1
S10 NPCS10
S10 NPCS11
S10 NPCS12
S10 NPCS13
S10 SCK1
S2,8,10
S2,8,10
S10
S2,10
S2,10
S8,10
S2,8,10
S10
S10
S10
S10
S10
S10
S8,10 TII0
S10 TII1
S9 DRXD
S9 DTXD
SCLK1
CTS1
RXD1
RTS1
TXD1
S10
S10
S10
S10
S10
S1 SCLK0
S9 CTS0
S9 RXD0
S9 RTS0
S9 TXD0
S7 RTCK
S7 ATDI
S7 ATCK
S7 ATMS
S7 ANTRST
S7 ATDO
S1,2,7,10 NRESET
8
7
7
TXp
TXm
RXp
RXm
LEDSPEED
LEDCOL
LEDLINK
CANRX0
CANTX0
CANRX1
CANTX1
MCCDA
MCCK
MCDA0
MCDA1
MCDA2
MCDA3
SDWP
SDDET
HDPA
HDMA
HDPB
HDMB
DDP
DDM
S1 CPULED
S9
S9
S9
S9
S9
S9
S9
S8,10
S8,10
S8,10
S8,10
S8
S8
S8
S8
S8
S8
S8
S8
S9
S9
S9
S9
S9
S9
S7 MTDI
S7 MTCK
S7 MTMS
S7 MNTRST
S7 MTDO
6
6
AGND_ETH
RXp
RXm
CANTX0
CANRX0
CPULED
MCCDA
MCCK
MCDA1
HDPA
HDMA
HDPB
HDMB
TD0
TK0
TF0
TWCK0
MOSI0
SCK0
NPCS01
NPCS03
TIOA0
TIOA1
TIOB2
TII1
DTXD
SCLK2
CTS2
RXD2
SCLK1
CTS1
RXD1
SCLK0
CTS0
RXD0
NRESET
RTCK
ATDI
ATCK
5
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
60x2 RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
X1
X1 CONNECTOR
TXp
TXm
LEDCOL
LEDLINK
LEDSPEED
DDP
DDM
SDWP
MCDA0
MCDA3
MCDA2
SDDET
RD0
RK0
RF0
TWD0
MISO0
NPCS00
NPCS02
IRQ0
TII0
TIOA2
TIOB1
TIOB0
RTS2
TXD2
DRXD
RTS1
TXD1
RTS0
TXD0
ATMS
ATDO
ANTRST
4
AVDD_ETH
3V3
MODULE X CONNECTORS
4
3
3
MTDI
MTCK
TD3
TK3
TF3
TD2
TK2
TF2
TD1
TK1
TF1
TWCK1
MOSI1
SCK1
NPCS11
NPCS13
CANTX1
CANRX1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
Atmel Roma
3V3
-
D940HF BACK MODULE
Friday, October 26, 2007
B
DWG NO
Rev
Sheet
<Doc>
11
of
2
1
This agreement is our property. Registration and publication without our written authorization shall expose offender to legal proceedings
Date
PRJ
1
Via G. V. Galati, 91 - 00155 Rome - ITALY
X CONNECTORS
MTMS
MTDO
MNTRST
RD3
RK3
RF3
RD2
RK2
RF2
RD1
RK1
RF1
TWD1
MISO1
NPCS10
NPCS12
IRQ1
AT572D940
Roma
60x2 RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
X3
X3 CONNECTOR
2
11
A
B
C
D
Schematics
DIOPSIS 940HF Evaluation Board User Guide
Section 7
Parts Lists
Tables Table 7-1 and Table 7-2 report only the parts lists of the DCM and DBM main devices.
7.1
DCM Parts List
Table 7-1 reports the parts list of the DCM board:
Table 7-1. DCM Parts List
Reference
Q.ty
Part Number
Description
Producer
U1
1
NCP565D2TG
Voltage Regulator 3.3V - 1.2V
ON-Semi
U2
1
MAX4372TEUK-T
Current Sense OP AMP
Maxim
U3
1
AD7457BRT
AD Converter
Analog
Devices
U4
1
SN74LVC1G32DBVR
Positive OR-Gate
TI
U5
1
ADR121AUJZ-R2
Voltage Reference (2.5V)
Analog
Devices
U6
1
AT572D940 (D940HF)
Dual Core DSP mAgic + ARM926™
Atmel
U7
1
SN74AVCH2T45DCUR
Voltage Transceiver (Optional)
TI
U8, U9
2
K4S561632H-UC76T
SDRAM 16Mx16
Samsung
U10
1
MT29F2G08AACWP
NAND Flash 256Mx8
Micron
U11, U12
2
AT49BV642D-70TU
Parallel Flash 4Mx16
Atmel
U13
1
DM9161E
Ethernet PHY
Davicom
SW1
1
SDA04H0SBD
DIP Switch 4 Positions
ITT
X1, X2, X3
3
61083-121402LF
Connector 60x2 (Male)
FCI
Y1
1
ABM3-12.000MHZ-B2-T
12 MHz Quartz
Abracon
Y2
1
FC-255 32.7680K-A3
32.768 KHz Quartz
Epson
Y3
1
ASFL1-12.000MHZ-EK-T
12 MHz Oscillator (Optional)
Abracon
Y4
1
ECS-327SMO-TR
32.768 MHz Oscillator (Optional)
ECS
Y5
1
ASFL1-96.000MHZ-EK-T
96 MHz Oscillator (Optional)
Abracon
DIOPSIS 940HF Evaluation Board User Guide
7-1
7014A–DSP–03/09
Parts Lists
7.2
DBM Parts List
Table 7-2 reports the parts list of the DBM board:
Table 7-2. DBM Parts List
7-2
7014A–DSP–03/09
Reference
Q.ty
Part Number
Description
Producer
U1, U3
2
TPS75801KTTT
Voltage Regulator 5V - 3.3V or 4.5V
TI
U2
1
DS1818R-10+T&R
Power-On-Reset
Dallas
U4
1
FZT953TA
PNP Power Transistor
Zetex
U5, U6
2
AD1939YSTZ
4ADC/8DAC 24-Bit CODEC
Analog
Devices
U7, U8, U9,
U10, U11,
U12
6
AD8608ARUZ
Quad Operational Amplifier
Analog
Devices
U13, U14
2
SN65HVD232D
3.3V CAN Transceiver
TI
U15
1
DS1306EN+
Serial Alarm Real Time Clock
Dallas
U16
1
MAX3387ECUG
RS-232 Transceiver
Maxim
U17
1
HCPL-0700-000E
Optocoupler
Avago
Y1
1
ASFL1-12.288MHZ-EC-T
3V RS-232 Transceiver (Optional)
Abracon
Y2
1
FC-255 32.7680K-A3
32.768 KHz Quartz
Epson
X1, X3
2
61082-121402LF
Connector 60x2 (Female)
FCI
SW1, SW2
2
B3S1002P
Push Button
Omron
J1
1
RAPC722
Power Supply Connector
SwitchCraft
J5, J6, J7,
J8, J9, J10,
J11, J12
8
SJ-3505
3.5 mm Audio Stereo Connector
CUI
J13, J14
2
9185206324
20-Pin JTAG Connector
Harting
J15
1
SD-RSMT-2-MQ
SD Memory Connector
3M
J16
1
3000
12 mm SMD Battery Holder
Keystone
J17, J19
2
182-009-113R531
DB9 RS-232 Connector
NorComp
J18
1
896-43-008-90-000000
Dual USB Host Connector
Mill Max
J20
1
J0026D21BNL
ETH Port 10/100B-TX Connector
Pulse
J21
1
897-43-004-90-000000
USB Device Connector
Mill Max
DIOPSIS 940HF Evaluation Board User Guide
Section 8
Revision History
8.1
Revision History
Doc. Rev.
Date
7014A
03/09
Comments
• Initial document release
DIOPSIS 940HF Evaluation Board User Guide
8-1
7014A–DSP–03/09
Revision History
8-2
7014A–DSP–03/09
DIOPSIS 940HF Evaluation Board User Guide
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7014A–DSP–03/09