Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 1/10
Solution of Homework#06
(1) Draw block diagram to show how to use 3-to-8 lines decoders to produce the
following:
(All decoders have one active-low ENABLE input, active-high binary code inputs,
and active-low outputs. You can use additional components if required)
(a) A 4-to-16 line decoder
(b) A 6-to-64 line decoder
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 2/10
(2) Show how to build each of the following single- or multiple-output logic functions
using one or more 74x138 binary decoders and NAND gates.
(Hint: Each realization should be equivalent to a sum of minterms.)
(a) F = ΣX,Y,Z(2,4,7)
(b) F= ∏A,B,C(3,4,5,6,7)
(c) F = ΣA,B,C,D(2,4,6,14)
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 3/10
(d) F = ΣW,X,Y(1,3,5,6) and G = ΣW,X,Y(2,3,4,7)
(e) F = ΣA,B,C(0,4,6) and G = ΣC,D,E(1,2)
(3) Using MSI 74x49 BCD to seven-segment decoder and additional hardware to
build a new seven-segment decoder such that the digits 6 and 9 have tails as shown
below.
Seven-segment display
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 4/10
The truth table of modified BCD-to-seven-segment decoder is shown below
Function
or
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI
D
C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
Inputs
B
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
BI_L
na
nb
Nc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Outputs
nd ne
1
0
1
1
0
1
1
0
1
1
1
1
0
1
1
0
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
nf
ng
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
(4) Suppose you would like to use seven-segment display to show characters A, B, C,
D, E and F. So you have to design the code converter circuit to convert binary code
inputs to seven-segment code outputs. If the circuit has an active-high “lamp test”
input which force all LEDs on, and the active-low “blank input” input which force all
LEDs off except “lamp test” is asserted. Show the truth table, simplified AND-OR
logic diagram, and seven-segment display of each character.
A=
B=
Panupong Sornkhom
C=
D=
E=
Department of Electrical and
Computer Engineering
F=
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 5/10
The truth table is shown below
Function
or
Character
A
B
C
D
E
F
BI
LT
C
B
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
Inputs
A LT
0
1
0
1
0
1
0
1
X
X
0
0
0
0
0
0
0
0
0
1
BI_L
na
nb
Nc
1
1
1
1
1
1
1
1
0
X
1
1
1
1
1
1
d
d
0
1
1
1
0
1
0
0
d
d
0
1
1
1
0
1
0
0
D
D
0
1
Outputs
nd ne
0
1
1
1
1
0
D
D
0
1
1
1
1
1
1
1
d
d
0
1
nf
ng
1
1
1
1
1
1
d
d
0
1
1
1
1
0
1
1
d
d
0
1
Each output is in form of LT+BI·m where m is a logic function of
minterm.
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 6/10
(5) Draw the logic diagram for a 8-to-3 encoder using just three 4-input NAND gates.
What are the active levels of the inputs and outputs in your design?
Inputs are active low and outputs are active high.
(6) A customized priority encoder is defined in the table below; show the simplified
NAND-NAND circuit corresponding to such priority encoder.
EN
0
1
1
1
1
Panupong Sornkhom
Inputs
RI2
RI1
X
X
1
X
0
1
0
0
0
0
RI0
X
X
X
1
0
Y1
0
1
0
1
0
Department of Electrical and
Computer Engineering
Outputs
Y0
0
0
1
1
0
RO
0
1
1
1
0
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 7/10
(7) Write the minimal sum expression of 8-to-1 multiplexer with one enable input EN,
eight data inputs D7-D0, three selecting inputs S2-S0, and one output Y. (all inputs
and outputs are active-high.)
The truth table of 8-to-1 multiplexer is shown below
Inputs
Outputs
EN
S2
S1
S0
Y
0
X
X
X
0
1
0
0
0
D0
1
0
0
1
D1
1
0
1
0
D2
1
0
1
1
D3
1
1
0
0
D4
1
1
0
1
D5
1
1
1
0
D6
1
1
1
1
D7
From the truth table
Y = EN·S2′·S1′·S0′·D0 + EN·S2′·S1′·S0·D1 + EN·S2′·S1·S0′·D2 + EN·S2′·S1·S0·D3
+ EN·S2·S1′·S0′·D4 + EN·S2·S1′·S0·D5 + EN·S2·S1·S0′·D6 + EN·S2·S1·S0·D7
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 8/10
(8) Use 4-to-1 multiplexer to implement the following:
(All multiplexer have one active-low ENABLE input, active-high data inputs, activehigh selector inputs, and active-high data output. You can use additional components
if required)
(a) 16-to-1 multiplexer
(b) 32-to-1 multiplexer
Panupong Sornkhom
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 9/10
(9) Show how to build each of the following logic functions using 4-to-1 multiplexer
and additional gates.
(a) F = ΣX,Y,Z(2,4,7)
YZ
X
Minterm
F
D
00
0
1
0
1
0
1
0
1
0
4
1
5
2
6
3
7
0
1
0
0
1
0
0
1
X
01
10
11
0
X′
X
(b) F= ∏A,B,C(3,4,5,6,7)
BC
A
Minterm
F
D
00
0
1
0
1
0
1
0
1
0
4
1
5
2
6
3
7
0
1
0
1
0
1
1
1
A
01
10
11
A
A
1
(c) F = ΣA,B,C,D(2,4,6,14)
CD
AB
Minterm
F
D
00
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
A′·B
01
10
11
Panupong Sornkhom
0
A′+B
0
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University
Solution of
Homework#06
Digital Circuit and Logic Design 1
2005/2
Page 10/10
(d) Odd parity generator for 4 information bits
F = ΣA,B,C,D(0,3,5,6,9,10,12,15)
CD
AB
Minterm
F
D
00
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
A′·B′ +
A·B
=(A⊕B)′
01
10
11
A′·B +
A·B′
=A⊕B
A′·B +
A·B′
=A⊕B
A′·B′ +
A·B
=(A⊕B)′
(10) Implement 1-to-8 demultiplexer which all pins are active-high; using only one
74x139 IC and additional gates, show the logic diagram in bubble-to-bubble logic
design form.
Data
A
Y0
1/2 74x139
1
2
3
a1
a2
a3
G
A
B
B
Y0
Y1
Y2
5
Y3
8
b1
b2
b3
b4
Y1
6
Y2
7
Y3
Y4
C
Y5
1/2 74x139
1
2
3
a1
a2
a3
G
A
B
Y0
Y1
Y2
5
Y3
8
b1
b2
b3
b4
Panupong Sornkhom
6
Y6
Y7
7
Department of Electrical and
Computer Engineering
Faculty of Engineering,
Naresuan University