Martin Pearson
1
, Ian Gilhespy
1
, Kevin Gurney
2
, Chris Melhuish
1
,
Benjamin Mitchinson
2
, Mokhtar Nibouche
1
, and Anthony Pipe
1
2
1
Intelligent Autonomous Systems laboratory,
University of the West of England
Adaptive Behaviour Research Group, University of Sheffield
Abstract.
A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project, to investigate and implement biologically plausible models of the rodent vibrissae based somatosensory system to control a robot. An emphasis has been made on hard real-time performance of the processor, as it is to be used as part of a feedback control system. This has led to a revision of some of the established modelling protocols used in other hardware spiking neural network processors. The underlying neuron model has the ability to model synaptic noise and inter-neural propagation delays to provide a greater degree of biological plausibility. The processor has been demonstrated modelling real neural circuitry in real-time, independent of the underlying neural network activity.
The hardware processor detailed in this paper can model large networks of
Leaky-Integrate-and-Fire (LIF) neural processing nodes (described in numerous
sources, e.g., [1], [2]) which are themselves based on the observed phenomenolog-
ical function of biological neurons. Additional biologically plausible features of the model used here include synaptic and membrane threshold noise, inter-neural propagation delays, and individual membrane potential and post synaptic current decay constants. The hard-real-time constraints that are encountered in the field of embedded computing is an area which has been applied to artificial neu-
ral networks before [3]. However, to the best of our knowledge, this has not been
used in relation to ‘Spiking’ artificial Neural Network (SNN) implementations.
SNNs differ from more conventional rate-coded artificial neural networks in that the information passed between neurons is expressed as temporally separated discrete events, or spikes. SNNs and Pulse Coded Neural Networks (PC-
NNs) [4] can generate behaviours and reproduce coding schemes closely analogous to biological neural systems [5]. They are consequently used extensively
by computational neuroscientists in experiments to model and obtain insights into the operational functionality of the brain. Typically these models are sim-
ulated using software simulators, such as [6], compiled to conventional Personal
W. Duch et al. (Eds.): ICANN 2005, LNCS 3697, pp. 1021–1026, 2005.
c Springer-Verlag Berlin Heidelberg 2005

1022 M. Pearson et al.
Computers (PC) or parallel High Performance Computing (HPC) systems such
as Beowulf clusters [7]. These simulators utilise the inherent characteristics of
biologically plausible neural networks (low average network activity and sparse
inter-neural connectivity [2]) to maximise the utility of the processing space and
minimise simulation time. This approach is also adopted by dedicated biologi-
cally plausible hardware neural network accelerators, for example, [8], [9]. To test
neural network models for robustness in real-world control environments, such as mobile robotics, the underlying network processing platform must guarantee hard-real-time performance. The computationally efficient, activity dependant approach to network modelling, as described above, can not guarantee this performance at all levels of network activity. Therefore, a new SNN processing architecture, which trades some network complexity for a guaranteed temporal performance at all levels of SNN activity, is preferential for the stable on-line control of, for example, a mobile robot.
The neuron model used in this processor is a single point (or single compartmen-
tal) model which exhibits class I excitability [10]. The weight of each synapse can
be subjected to multiplicative Rayleigh distributed noise. Gaussian distributed noise can also be injected additively to the magnitude of the membrane threshold potential. The noise distributions used here were chosen to best fit the model output to empirical biological data. A variable inter-neural delay is associated with each synapse which is used to model spatially distributed networks. Both the absolute and the relative refractory periods of each neuron are also modelled.
The use of floating point arithmetic to represent and manipulate these parameters is not available to FPGA without incurring a substantial cost in silicon real estate. For this reason, fixed point, 16-bit integers have been used to approximate the more accurate representation of these floating point values.
The architecture of this design is best described as a Single Instruction path,
Multiple Data path (SIMD) array processor, Fig. 1. It consists of an array of
Processing Elements (PE) operating concurrently on the same instruction, issued from a central sequencer, using locally stored data. The input stimulus to the processor is ported via 2 input modules which can read in data asynchronously. Similarly there are also 2 output modules. The neurons and synapses are implemented in what we have called Neural Processing Elements (NPE).
The SIMD neural processor, detailed in this report, has 10 NPEs, each of which emulates 120 virtual neurons and 912 synapses. The update period of the processor is set at 500
µ
S which is regulated by a real time counter in the sequencer module.

A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor 1023
Command in
Bus
Command out
Bus
Sequencer
Next_state
Bus
Current_state
Bus npe0 npe1 npe2 npe3 npe4 npe5 npe6 npe7 npe8 npe9
Fig. 1.
Block diagram of SIMD neural processor topology
The Sequencer maintains the real time performance and coordinates the activity of all the concurrently operating PEs of the processor. This coordination is performed using a 2 bit control channel and a 16 bit data bus between each of the elements.
The input module has a 64-bit input port (multiplexed onto 384 input channels) which can be connected either to physical pins or an appropriate internal interface using the logic array of the host FPGA. Handshaking lines facilitate asynchronous operation and allow communications across different clock domains. The 384 input channels are passed onto the internal 16 bit data bus of the module and consequently stored in the current state memory.
The output module has a similar architecture and operation to the input module but with an additional block of RAM containing a list of the network outputs.
The Neural Processing Element contains a hardware implementation of a
neuron and a single synapse, Fig. 2. The contextual information of 120 ‘vir-
tual’ neurons and 912 synapses are stored locally in 4 banks of RAM. The context for each neuron and synapse are sequentially multiplexed onto the hardware at super-real-time. A copy of the state of the entire network is stored locally in each NPE (as in the output module) which serves as the input stimulus for the virtual neurons/synapses. The updated state of each of the neurons in the NPE are stored in the local next state memory space and is subsequently broadcast to the other PEs.

1024 M. Pearson et al.
Neuron Model
Output
Threshold
>=
Reset
Potential
Membrane
Potential
Integrator
Sigma
Gaussian
Noise
Decay Constant
Synapse Model
Decay constant
Post Synaptic current integrator
To Neuron model Axonal delay buffer
Raleighian
Noise
Sigma
Weight
Input
Fig. 2.
Block diagram of individual neuron and a single synapse
An existing model of part of the Basal Ganglia [11] was used to test the perfor-
mance of the system. The parameters, generated from a floating point software simulator, were translated into fixed point integers. Tests were conducted, using a C++ coded hardware simulator, to assess the degradation in the network performance compared to the original floating point model. These parameters were then passed into the physical synthesis process of the FPGA design flow and the subsequent bit stream was used to configure the device. The target FPGA was a Xilinx Virtex-II (XC2V1000-4), 1 million gate equivalent, clocked at 50MHz and situated on a Celoxica RC200 development board. The raster plot shown in
the top panel of figure 3, is from 1200 hardware implemented neurons over a 400
millisecond time period (800 operational epochs) buffered from the FPGA via an RS232 serial port. The histogram, shown in the lower panel, was generated from the spike event data taken from the raster plot and clearly indicates the periods of peak neural activity during this trial.
In a previous study it was found that floating point SNN simulator software compiled and executed on a Pentium 4 based PC
1
could maintain real-time performance whilst modelling a network of 7000 neurons with an average network activity of 50 spike events per neuron per second (50Hz) and an average divergence of 16 synapses per neuron. This equates to a total of 350,000 spike events per second or 175 per update period (500 µ S), above which this processing paradigm will require more than 500 µ S to update the state space of the network.
To assess whether a neural network can be modelled in real time a metric which establishes a measure of peak activity, size of the network itself and the required update period was derived. This was referred to as the activity quota of the network; peak number of spike events per neuron per update period. Therefore, a
1
3GHz processor, utilising Microsoft Windows XP operating system.

A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor 1025 network of 7000 neurons generating a constant spike activity of 175 spike events per update period can be categorised as requiring an activity quota of 0.025
from the underlying processing modality to remain operating in real-time. In
figure 3, the histogram shows that the network used in this test, of 1200 neu-
rons, has instances of network activity in excess of 30 spike events per update period. This network therefore requires an activity quota greater than 0.025 to remain operating in real-time. Were the network size to be increased to 7000,
and the activity quota remained high as shown in Fig. 3, this network could not
be modelled in real-time by the PC. The processor described in this paper has been designed to maintain real-time performance up to a network activity quota of 1, i.e., it is activity independent.
Raster plot
1200
1000
800
600
400
200
0
0 100 200 300 400
Histogram
500 600 700 800
40
30
20
10
0
0
Activity
Quota
=0.025
100 200 300 400 500 600
Operational epoch index (network update period)
700 800
Fig. 3.
Raster plot and corresponding activity histogram of 1200 neurons modelling the Basal Ganglia over a 400mS period
The architecture has been designed to accommodate a substantial size increase in the near future. Further, the hardware has been designed from the outset to cater easily for cascading processor cores, either on the same FPGA or via physical pins to separate devices. Thus, very large networks could be generated.
In fact, a matrix of 6 interconnected processor cores could simulate a network of almost 7000 neurons in hard real-time independent of network activity.
The work reported on in this paper has demonstrated that a large SNN model, based closely on the observed behaviour of biological neurons, can be simulated in real-time using a single FPGA. The emphasis on hard real-time

1026 M. Pearson et al.
performance has resulted in a re-evaluation of some of the existing optimisation techniques which take advantage of the temporal and spatial characteristics of biologically plausible SNNs to provide hardware acceleration for off-line modelling.
This work forms part of and is supported by EPSRC Grant No. GR/S19639/01
“whiskerbot project”. Acknowledgement is given to all members of the project.
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