Topics
Shifters
Adders and ALUs
Combinational shifters
Useful for arithmetic operations, bit field
extraction, etc.
Latch-based shift register can shift only one
bit per clock cycle
A multiple-shift shifter requires additional
connectivity
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Modern VLSI Design 3e: Chapter 6
Barrel shifter
Can perform n-bit shifts in a single cycle
Efficient layout
Does require transmission gates and long
wires
Barrel shifter structure
Accepts 2n data inputs and n control signals,
producing n data outputs
n bits
n bits
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Modern VLSI Design 3e: Chapter 6
Modern VLSI Design 3e: Chapter 6
Barrel shifter layout
n bits
data 2
output
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Modern VLSI Design 3e: Chapter 6
data 1
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Barrel shifter cell
Two-dimensional array
– 2n X n
Input data travels diagonally upward
– Output wires travel horizontally
Control signals run vertically
– Exactly one control signal is set to 1, turning on
all transmission gates in that column
Modern VLSI Design 3e: Chapter 6
Copyright  1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 6
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Barrel shifter in action
Analysis
Large number of cells
– But each cell is small
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Modern VLSI Design 3e: Chapter 6
Delay is large, considering long wires and
transmission gates
Modern VLSI Design 3e: Chapter 6
Adders
Adder delay is dominated by carry chain
Carry chain analysis must consider
transistor, wiring delay
Modern VLSI favors adder designs which
have compact carry chains
Copyright  1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 6
Full adder
First compute carry propagate, generate:
Ripple-carry adder
Delay of ripple-carry adder goes through all
carry bits
– n-bit adder built from full adders
Modern VLSI Design 3e: Chapter 6
Can recursively expand carry formula:
– ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)
– ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2)
Compute sum and carry from P and G:
– si = ci XOR Pi XOR Gi
– ci+1 = Gi + Pici
Modern VLSI Design 3e: Chapter 6
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Carry-lookahead expansion
– Pi = a i + bi
– Gi = a i b i
Computes one-bit sum, carry:
– si = ai XOR bi XOR ci
– ci+1 = aibi + aici + bici
Carry-lookahead adder
Copyright  1998, 2002 Prentice Hall PTR
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Expanded formula does not depend on
intermediate carries
Allows carry for each bit to be computed
independently
Modern VLSI Design 3e: Chapter 6
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Depth-4 carry-lookahead
Carry-lookahead analysis
Deepest carry expansion requires gates with
large fan-in
– Large and slow
Carry-lookahead unit requires complex
wiring between adders and lookahead unit
Layout is even more complex with multiple
levels of lookahead
Modern VLSI Design 3e: Chapter 6
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Carry-skip adder
Modern VLSI Design 3e: Chapter 6
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Two-bit carry-skip structure
Looks for cases in which carry out of a set
of bits is identical to carry in
Typically organized into m-bit stages
If ai ≠ bi for every bit in stage, then bypass
gate sends stage’s carry input directly to
carry output.
Modern VLSI Design 3e: Chapter 6
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Modern VLSI Design 3e: Chapter 6
Carry-select adder
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Carry-select structure
Computes two results in parallel, each for
different carry input assumptions
Uses actual carry in to select correct result
Reduces delay to multiplexer
Modern VLSI Design 3e: Chapter 6
Copyright  1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 6
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Manchester carry chain
Manchester carry chain circuit
Precharged carry chain which uses P and G
signals
Propagate signal connects adjacent carry
bits
Generate signal discharges carry bit
Worst-case discharge path goes through
entire carry chain
Copyright  1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 6
Modern VLSI Design 3e: Chapter 6
Serial adder
May be used in signal-processing arithmetic
where fast computation is important but
latency is unimportant
Data format (LSB first):
0
1
1
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Serial adder structure
LSB control signal clears the carry shift
register:
0
LSB
Modern VLSI Design 3e: Chapter 6
Copyright  1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 6
Copyright  1998, 2002 Prentice Hall PTR