Topics
FPGA Design
EECE 277
“I don’t know their names. Can I give you their numbers?”
– Freddy Mitchell
WR for the Philadelphia Eagles
Interconnect and Logic Elements
• Administrative stuff
– Homework Assignment #2 (due Wednesday, February 2)
– Laboratory Assignment #1 (due Friday, February 4)
Dr. William H. Robinson
January 31, 2005
• FPGA review
• Interconnect issues
• Logic element issues
http://eecs.vanderbilt.edu/courses/eece277/
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Guest Lecture
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Laboratory Assignment #1
• Quartus II Software
• Dr. Robinson will be on travel
– Any installation issues?
– Friday, January 28, 2005
• UP2 Design Laboratory Kits
– Any configuration issues?
• Presentations on current FPGA research
– Jason Scott
• Laboratory Report
• Embedded System Design Tools and Xilinx FPGAs
– Follow guidelines from handout
– Philippe Adell
• Implementing a Rad-Hard digital power controller with an FPGA
• Potential Lab Session
– Tuesday, cancelled
– Wednesday during normal class time
Potential Final Project Ideas!!!
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FPGA Fabric (Architecture)
FPGA Fabric Questions
• Logic
• Given limited area budget
– How many logic elements?
– How much interconnect?
– How many I/O blocks?
• Interconnect
• I/O pins
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
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Logic Element Questions
Copyright  2004 Prentice Hall PTR
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Interconnect Questions
• How many wires in each channel?
• How many inputs?
• Uniform distribution of wiring?
• How many functions?
– All functions of n inputs or eliminate some
combinations?
– What inputs go to what pieces of the function?
• How should wires be segmented?
• How rich is interconnect between
channels?
• Any specialized logic?
– Adder, etc.
• How long is the average wire?
• What register features?
FPGA-Based System Design: Chapter 3
FPGA-Based System Design: Chapter 3
• How much buffering do we add to wires?
Copyright  2004 Prentice Hall PTR
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FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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I/O Block Questions
Programming Technologies
• What types are available?
• How many pins?
Technology
– Maximum number of pins determined by package
type.
• Are pins programmed individually or in
groups?
• Can all pins perform all functions?
Copyright  2004 Prentice Hall PTR
Fusible-link
SPLDs
Antifuse
FPGAs
EPROM
SPLDs and CPLDs
E PROM/
FLASH
SPLDs and CPLDs
(some FPGAs)
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• How many logic families do we support?
FPGA-Based System Design: Chapter 3
SRAM
FPGAs (some CPLDs)
SRAM
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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SRAM-Based FPGAs
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Terminology
• Configuration:
• Program logic functions, interconnect
using SRAM
– Bits that determine logic function + interconnect
• CLB:
• Advantages:
– Combinational Logic Block = Logic Element (LE)
– Re-programmable
– Dynamically reconfigurable
– Uses standard processes
• LUT:
– Lookup table = SRAM used for truth table
• I/O block (IOB):
• Disadvantages:
– I/O pin + associated logic and electronics
– SRAM burns power
– Possible to steal, disrupt configuration bits
FPGA-Based System Design: Chapter 3
Predominantly
associated with ...
Symbol
Copyright  2004 Prentice Hall PTR
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FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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Example: FPGA Configuration
Example: FPGA Configuration
• Your FPGA has 9 logic elements (LE) each with four
inputs and one output
• How many configuration
bits are required?
Routing channel
Routing channel
• There are four vertical and four horizontal routing
channels with four wires per channel
• Each wire in the routing channel can be connected to
every input of the LE on its right and the output of the LE
on its left
LE
LE
LE
• 580 configuration bits
LE
LE
LE
LE
LE
LE
– LE SRAMs:
16 x 9 = 144
– I/O connections of LEs:
20 x 9 = 180
– Routing channel intersections:
16 x 16 = 256
• When two routing channels intersect, all possible
connections between the intersecting wires can be made
• How many configuration bits are required?
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Configuration
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Programmable Interconnection Point
• Must set control bits for
x1 0
0
0
x2
1
– LE
– Interconnect
– I/O blocks
• Usually configured off-line
Vf
f1
1
VA
1
0
0
SRAM
SRAM
SRAM
– Separate burn-in step (antifuse)
– At power-up (SRAM)
(to other wires)
Figure 3.68. Pass-transistor switches in FPGAs.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
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Programmable vs. Fixed Interconnect
Interconnect Strategies
• Switch adds delay
• Some wires will not be utilized
• Transistor off-state is worse in advanced
technologies
• Congestion will not be same throughout chip
• Types of wires
– Short wires: local LE connections
– Global wires: long-distance, buffered communication
– Special wires: clocks, etc.
• FPGA interconnect has extra length
– Equals added capacitance
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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Paths in Interconnect
LE
Wiring channel
LE
LE
LE
Wiring channel
Wiring channel
LE
LE
LE
LE
LE
LE
FPGA-Based System Design: Chapter 3
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• Connections from wiring channels to LEs
• Connections between wires in the wiring
channels
Vertical wiring channel
LE
Copyright  2004 Prentice Hall PTR
Interconnect Architecture
• Connection may be long and complex
Horizontal
wiring
channel
FPGA-Based System Design: Chapter 3
LE
LE
LE
LE
Copyright  2004 Prentice Hall PTR
LE
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FPGA-Based System Design: Chapter 3
LE
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Interconnect Richness
Segmented Wiring
• Within a channel:
LE
– How many wires
– Length of segments
– Connections from LE to channel
LE
LE
LE
Length 1
• Between channels:
Length 2
– Number of connections between channels
– Channel structure
Length 3
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
channel
channel
LE
channel
FPGA-Based System Design: Chapter 3
channel
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LE
channel
channel
SW
channel
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Interconnect paths
channel
Channel Intersections (Switchbox)
Copyright  2004 Prentice Hall PTR
SW
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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Logic Element (LE) Output Drivers
Interconnect Circuits
• Why so many types of
interconnect?
• Must drive load
– Wire
– Destination LE
– Provide a choice of delay
alternatives.
• Different types of wiring present different
loads
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
• Sources of delay
– Wires
– Programming points
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Styles of Programmable
Interconnection Points
FPGA-Based System Design: Chapter 3
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Copyright  2004 Prentice Hall PTR
Using a Pass Transistor
• Small area.
SRAM
cell
• Resistive switch.
SRAM
cell
...
• Delay grows as the
square of the number of
switches.
...
Pass transistor
FPGA-Based System Design: Chapter 3
SRAM
cell
SRAM
cell
...
...
Three-state
Copyright  2004 Prentice Hall PTR
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FPGA-Based System Design: Chapter 3
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FPGA Fabric (Architecture)
Using a Three-State Buffer
• Larger area.
• Logic
• Regenerative driver.
• Interconnect
+
FPGA-Based System Design: Chapter 3
• I/O pins
Copyright  2004 Prentice Hall PTR
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Evaluation of SRAM-based LUT
Copyright  2005 McGraw-Hill
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Summary
• N-input LUT can handle function of 2n input
combinations
• Regular placement of logic elements leads to
regular structure of interconnect
• All logic functions take the same amount of space
• All functions have the same delay
• Delays are affected by path length and the
switching points
• SRAM is larger than static gate equivalent of
function
• Logic elements are used to implement
functions
• Burns power at idle
FPGA-Based System Design: Chapter 3
Fundamentals of Digital Logic: Chapter 3
Copyright  2004 Prentice Hall PTR
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